; -------------------------------------------------------------------------------- ; @Title: iMX61 On-Chip Peripherals ; @Props: Released ; @Author: KNO, STR, MAJ, KKW ; @Changelog: 2015-07-29 ; @Manufacturer: NXP ; @Doc: IMX6SXRM.pdf ; @Chip: Cortex-A9;Cortex-M4 ; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perimx6slx.per 17736 2024-04-08 09:26:07Z kwisniewski $ ; Known problems: In some modules (SPDIF and ROMC) there are differences in addresses from memory map and registers descriptions. ; Base addresses for some modules are missing. ;Register MLB_MLBPC2 is described in documentation using 0x0218C00D, in perfile following register is using address 0x0218C010 (same address is used in imx6sx) width 0xb sif ((corename()=="CORTEXA9")||(corename()=="CORTEXA9MPCORE")) tree "Core Registers (Cortex-A9MPCore)" width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x0++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" textline " " bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x200++0x0 line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register" rgroup.long c15:0x300++0x0 line.long 0x0 "TLBTR,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries" bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128" textline " " bitfld.long 0x0 0. " nU ,Unified or Separate TLBs" "Unified,Separate" rgroup.long c15:0x500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 8.--11. " ClusterID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "0,1,2,3" rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..." bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported" bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Not supported,Supported,?..." rgroup.long c15:0x0020++0x00 line.long 0x00 "ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..." tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " PARON ,Parity On" "Disabled,Enabled" bitfld.long 0x00 8. " ALIOW ,Enable allocation in one cache way only" "Disabled,Enabled" bitfld.long 0x00 7. " EXCL ,Exclusive cache Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SMP ,Signals if the Cortex-A9 processor is taking part in coherency or not" "0,1" bitfld.long 0x00 3. " FOZ ,Full Of Zero mode Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DP1 ,L1 Dside prefetch Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PH2 ,L2 prefetch hint Enable" "Disabled,Enabled" bitfld.long 0x00 0. " FW ,Cache and TLB maintenance broadcast" "Disabled,Enabled" group.long c15:0x201++0x0 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x11++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 6. " nET ,Not early termination" "Not early,Early" bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" textline " " bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group.long c15:0x111++0x0 line.long 0x0 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted" bitfld.long 0x00 16. " PLE ,NS accesses to the Preload Engine resources control" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register" "No,Yes" bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted" group.long c15:0x0311++0x00 line.long 0x00 "VCR,Virtualization Control Register" bitfld.long 0x00 8. " AMO ,Abort Mask Override" "0,1" bitfld.long 0x00 7. " IMO ,IRQ Mask Override" "0,1" bitfld.long 0x00 6. " IFO ,FIQ Mask Override" "0,1" group.long c15:0xf++0x0 line.long 0x00 "PCR,Power Control Register" bitfld.long 0x00 8.--10. " MCL ,Max Clock Latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EDCG ,Enable Dynamic Clock Gating" "Disabled,Enabled" textline " " group.long c15:0x000c++0x00 line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address" group.long c15:0x10c++0x00 line.long 0x0 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address" rgroup.long c15:0x1C++0x0 line.long 0x0 "ISR,Interrupt status Register" bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending" bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending" bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending" group.long c15:0x11c++0x0 line.long 0x00 "VIR,Virtualization Interrupt Register" bitfld.long 0x00 8. " VA ,Virtual Abort" "0,1" bitfld.long 0x00 7. " VI ,Virtual IRQ" "0,1" bitfld.long 0x00 6. " VF ,Virtual FIQ" "0,1" tree.end width 0x0d tree "Memory Management Unit" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" textline " " group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address" bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" textline " " bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address" bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" textline " " bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable" bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable" bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000" textline " " group.long c15:0x3--0x3 line.long 0x0 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" hexmask.long 0x00 0.--31. 1. " DFA ,Data Fault Address" group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " SD ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" hexmask.long 0x00 0.--31. 1. " IFA ,Instruction Fault Address" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" hexmask.long 0x00 0.--31. 1. " DAFS ,Data Auxiliary Fault Status" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,AuxiliaryInstruction Fault Status Register" hexmask.long 0x00 0.--31. 1. " IAFS ,Instruction Auxiliary Fault Status" textline " " group.long c15:0xa++0x0 line.long 0x0 "TLBLR,TLB Lockdown Register" bitfld.long 0x0 28.--29. " VICTIM ,Victim Value Increments after Each Tabel Walk" "0,1,2,3" bitfld.long 0x0 0. " P ,Lockdown by Victim or Set Associative Region of TLB" "Associative,Lockdown" group.long c15:0x0047++0x00 line.long 0x00 "PAR,PA Register" hexmask.long 0x00 12.--31. 0x1000 " PA ,Physical Adress" bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable" textline " " bitfld.long 0x00 9. " NS ,Non-secure" "Not secured,Secured" bitfld.long 0x00 7. " SH ,Shareable attribute" "Non-shareable,Shareable" textline " " bitfld.long 0x00 4.--6. " Inner ,Signals region inner attributes" "Noncacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back allocate,Write-through,Write-back" bitfld.long 0x00 2.--3. " Outer ,Signals region outer attributes for normal memory type" "Noncacheable,Write-back allocate,Write-through,Write-back" textline " " bitfld.long 0x00 1. " SS ,Supersection Enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " F ,Translation Successful" "Successful,No successful" textline " " group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attribute 7" "Outer,Inner" bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attribute 6" "Outer,Inner" textline " " bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attribute 5" "Outer,Inner" bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attribute 4" "Outer,Inner" textline " " bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attribute 3" "Outer,Inner" bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attribute 2" "Outer,Inner" textline " " bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attribute 1" "Outer,Inner" bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attribute 0" "Outer,Inner" textline " " bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " group.long c15:0x400f++0x0 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long 0x00 0.--31. 1. " CBA ,Configuration Base Address" textline " " rgroup.long c15:0x000d++0x00 line.long 0x00 "FCSEIDR,FCSE PID Register" hexmask.long.byte 0x00 25.--31. 0x02 " PID ,Process for Fast Context Switch Identification and Specification" group.long c15:0x10d++0x0 line.long 0x0 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID" hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID" group.long c15:0x020d++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRURW ,User Read/Write Thread ID" group.long c15:0x030d++0x00 line.long 0x00 "TPIDRURO,User Read-only Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRURO ,User Read-only Thread ID" group.long c15:0x040d++0x00 line.long 0x00 "TPIDRPRW,Privileged Only Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRPRW ,Privileged Only Thread ID" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 18.--20. " CType7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 15.--17. " CType6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 12.--14. " CType5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 9.--11. " CType4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 6.--8. " CType3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 3.--5. " CType2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 0.--2. " CType1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words" group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction" tree.end width 12. tree "System Performance Monitor" group.long c15:0xC9++0x0 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled" group.long c15:0x1C9++0x0 line.long 0x0 "PMCNTENSET,Count Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x2C9++0x0 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x3C9++0x0 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. " P4 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4C9++0x0 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 5. " P5 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 4. " P4 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" textline " " eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x5C9++0x0 line.long 0x0 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--5. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,CNT4,CNT5,?..." group.long c15:0xD9++0x0 line.long 0x00 "PMCCNTR,Cycle Count Register" hexmask.long 0x00 0.--31. 1. " CCNT ,Cycle Count" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Select Register" hexmask.long.byte 0x00 0.--7. 1. " EVCNT ,Event to count" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" hexmask.long 0x00 0.--31. 1. " PMNX ,Event Count" group.long c15:0xE9++0x0 line.long 0x0 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled" group.long c15:0x1E9++0x0 line.long 0x0 "PMINTENSET,Interrupt Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2E9++0x0 line.long 0x0 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" tree.end width 8. tree "Preload Engine" rgroup.long c15:0x000b++0x00 line.long 0x00 "PLEIDR,PLE ID Register" bitfld.long 0x00 16.--20. " FIFOS ,PLE FIFO size" "Not present,Reserved,Reserved,Reserved,4,Reserved,Reserved,Reserved,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,?..." bitfld.long 0x00 0. " PEP ,Preload Engine presence" "Not present,Present" rgroup.long c15:0x020b++0x00 line.long 0x00 "PLEASR,PLE Activity Status Register" bitfld.long 0x00 0. " R ,PLE Channel running" "Not running,Running" rgroup.long c15:0x040b++0x00 line.long 0x00 "PLEFSR,PLE FIFO Status Register" bitfld.long 0x00 0.--4. " AE ,Number of available entries in the PLE FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x001b++0x00 line.long 0x00 "PLEUAR,Preload Engine User Accessibility Register" bitfld.long 0x00 0. " U ,User accessibility" "Not permited,Permited" group.long c15:0x011b++0x00 line.long 0x00 "PLEPCR,Preload Engine Parameters Control Register" hexmask.long.word 0x00 16.--29. 1. " BSM ,Block size mask" hexmask.long.byte 0x00 8.--15. 1. " BNM ,Block number mask" hexmask.long.byte 0x00 0.--7. 1. " WS ,PLE wait states" tree.end tree "NEON" rgroup.long c15:0x000f++0x00 line.long 0x00 "NEON,NEON busy Register" bitfld.long 0x00 0. " Busy ,NEON busy" "Not busy,Busy" tree.end width 0xb width 9. tree "Debug Registers" tree "Jazelle Register" group.long c14:0x7000++0x0 line.long 0x00 "JIDR,Jazelle ID Register" bitfld.long 0x00 28.--31. " ARCH ,Architecture code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DESIGN ,Implementor code of the designer of the subarchitecture" textline " " hexmask.long.byte 0x00 12.--19. 1. " SAMAJ ,The subarchitecture code" bitfld.long 0x00 8.--11. " SAMIN ,The subarchitecture minor code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6. " TRTBFR ,Format of the Jazelle Configurable Opcode Translation Table Register" "0,1" bitfld.long 0x00 0.--5. " TRTBSZ ,Size of the Jazelle Configurable Opcode Translation Table Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long c14:0x7001++0x0 line.long 0x00 "JOSCR,Jazelle OS Control Register" bitfld.long 0x00 1. " CV ,Configuration Valid" "Not valid,Valid" bitfld.long 0x00 0. " CD ,Configuration Disabled" "No,Yes" group.long c14:0x7002++0x0 line.long 0x00 "JMCR,Jazelle Main Configuration Register" bitfld.long 0x00 31. " nAR ,Not Array Operations" "Disabled,Enabled" bitfld.long 0x00 30. " FP ,Floating-point opcodes handler" "VM implementation,VFP instructions" bitfld.long 0x00 29. " AP ,Array Pointer" "Handler,Pointer" textline " " bitfld.long 0x00 28. " OP ,Object Pointer" "Handler,Pointer" bitfld.long 0x00 27. " IS ,Index Size" "8 bits,16 bits" bitfld.long 0x00 26. " SP ,Static Pointer" "Handler,Pointer" textline " " bitfld.long 0x00 0. " JE ,Jazelle Enable" "Disabled,Enabled" group.long c14:0x7003++0x0 line.long 0x00 "JPR,Jazelle Parameters Register" bitfld.long 0x00 17.--21. " BSH ,Bounds SHift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " sADO ,Signed Array Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " ARO ,Array Reference Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " STO ,STatic Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ODO ,Object Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long c14:0x7004++0x0 line.long 0x00 "JCOTTRR,Jazelle Configurable Opcode Translation Table Register" bitfld.long 0x00 10.--15. " OPCODE ,Bottom bits of the configurable opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " OPERATION ,Code for the operation" "0,1,2,3,4,5,6,7,8,9,?..." tree.end width 11. tree "Processor Identifier Registers" rgroup c14:0x340--0x340 line.long 0x00 "CPUID,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup c14:0x341--0x341 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DMinLine ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." textline " " bitfld.long 0x00 14.--15. " L1_Ipolicy ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " IMinLine ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup c14:0x343--0x343 line.long 0x00 "TLBTYPE,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILsize ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLsize ,Specifies the number of unified or data TLB lockable entries" textline " " bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128" bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate" rgroup c14:0x348--0x348 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..." rgroup c14:0x349--0x349 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..." rgroup c14:0x34a--0x34a line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..." rgroup c14:0x34c--0x34c line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..." textline " " bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..." rgroup c14:0x34d--0x34d line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup c14:0x34e--0x34e line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." rgroup c14:0x34f--0x34f line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup c14:0x350--0x350 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..." rgroup c14:0x351--0x351 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..." rgroup c14:0x352--0x352 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..." rgroup c14:0x353--0x353 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..." rgroup c14:0x354--0x354 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..." tree.end tree "Coresight Management Registers" width 0xC textline " " group c14:0x3c0--0x3c0 line.long 0x0 "ITCTRL,Integration Mode Control Register" bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group c14:0x3e8--0x3e8 line.long 0x0 "CLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set" group c14:0x3e9--0x3e9 line.long 0x0 "CLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared" wgroup c14:0x3ec--0x3ec line.long 0x0 "LAR,Lock Access Register" hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key" rgroup c14:0x3ed--0x3ed line.long 0x0 "LSR,Lock Status Register" bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed" bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored" textline " " bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required" width 0xc rgroup c14:0x3ee--0x3ee line.long 0x0 "AUTHSTATUS,Authentication Status Register" bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented" bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented" bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented" bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented" bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled" width 0xc rgroup c14:0x3f2--0x3f2 line.long 0x0 "DEVID,Device Identifier" bitfld.long 0x00 0.--3. " PCSAMPLE ,Level of Program Counter sampling support (DBGPCSR and DBGCIDSR)" "Not implemented,DBGPCSR,Both,?..." rgroup c14:0x3f3--0x3f3 line.long 0x0 "DEVTYPE,Device Type" hexmask.long.byte 0x0 4.--7. 1. " STPC ,Sub Type: Processor Core" hexmask.long.byte 0x0 0.--3. 1. " MCDL ,Main Class: Debug Logic" rgroup c14:0x3f8--0x3f8 line.long 0x0 "PID0,Peripherial ID0" hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]" rgroup c14:0x3f9--0x3f9 line.long 0x0 "PID1,Peripherial ID1" hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]" hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]" rgroup c14:0x3fa--0x3fa line.long 0x0 "PID2,Peripherial ID2" hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " JEPCD ,JEP 106 ID code" "Not used,Used" textline " " hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]" rgroup c14:0x3fb--0x3fb line.long 0x0 "PID3,Peripherial ID3" hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd" hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified" rgroup c14:0x3f4--0x3f4 line.long 0x0 "PID4,Peripherial ID4" bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" rgroup c14:0x3fc--0x3fc line.long 0x0 "COMPONENTID0,Component ID0" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3fd--0x3fd line.long 0x0 "COMPONENTID1,Component ID1" hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)" hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble" rgroup c14:0x3fe--0x3fe line.long 0x0 "COMPONENTID2,Component ID2" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3ff--0x3ff line.long 0x0 "COMPONENTID3,Component ID3" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" tree.end textline " " width 0x7 rgroup c14:0x000--0x000 line.long 0x0 "DIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x0 16.--19. " Version ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,ARMv7 no ext.,?..." textline " " bitfld.long 0x0 15. " DEVID_IMP ,Debug Device ID Register DBGDEVID implemented" "Not implemented,Implemented" bitfld.long 0x0 14. " NSUHD_IMP ,Secure User halting debug implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 13. " PCSR_IMP ,Program Counter Sampling Register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " SE_IMP ,Security Extensions implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 4.--7. " Variant ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " Revision ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x7 group c14:0x22--0x22 line.long 0x0 "DSCR,Debug Status and Control Register" bitfld.long 0x0 30. " DTRRXfull ,The DTRRX Full Flag" "Empty,Full" bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full" textline " " bitfld.long 0x00 27. " DTRRXfull_l ,The DTRRX Full Flag 1" "Empty,Full" bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full" textline " " bitfld.long 0x0 25. " PIPEADV ,Sticky Pipeline Advance" "No effect,Instruction retired" bitfld.long 0x0 24. " INSTRCOMPL_L ,Latched Instruction Complete" "Executing,Not executing" textline " " bitfld.long 0x0 20.--21. " EXTDCCMODE ,External DCC access mode" "Non-blocking,Stall,Fast,?..." bitfld.long 0x0 19. " ADADISCARD ,Asynchronous Data Aborts Discarded" "Not discarded,Discarded" textline " " bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured" bitfld.long 0x0 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disabled" "No,Yes" textline " " bitfld.long 0x0 16. " SPIDDIS ,Secure Privileged Invasive Debug Disabled" "No,Yes" bitfld.long 0x0 15. " MDBGEN ,Monitor Debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled" bitfld.long 0x0 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " UDCCDIS ,User mode access to Comms Channel disable" "No,Yes" bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "No,Yes" textline " " bitfld.long 0x0 10. " DbgAck ,Force Debug Acknowledge" "Not forced,Forced" bitfld.long 0x0 8. " UND_l ,Sticky Undefined Instruction" "No exception,Exception" textline " " bitfld.long 0x0 7. " ADABORT_l ,Sticky Asynchronous Data Abort" "Not aborted,Aborted" bitfld.long 0x0 6. " SDABORT_l ,Sticky Synchronous Data Abort" "Not aborted,Aborted" textline " " bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Halt request,Breakpoint,Asynchronous Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited" textline " " bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state" width 0x7 if (((data.long(c14:0x00))&0x01000)==0x00000) group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled" bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" else group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled" bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled" bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" endif ;rgroup c14:0x1++0x1 ; line.long 0x0 "DRAR,Debug ROM Address Register" ; hexmask.long 0x0 12.--31. 0x1000 " DBROMPA ,Debug bus ROM physical address" ; bitfld.long 0x0 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid" ; line.long 0x4 "DSAR,Debug Self Address Offset Register" ; hexmask.long 0x4 12.--31. 0x1000 " DBSAOV ,Debug bus self-address offset value" ; bitfld.long 0x4 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid" ;hgroup c14:0x50++0x0 ; hide.long 0x0 "DTR,Data Transfer Register" ; in width 0x7 hgroup c14:0x020--0x020 hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register" in group c14:0x023--0x023 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" wgroup c14:0x21++0x00 line.long 0x00 "ITR,Instruction Transfer Register" hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute" wgroup c14:0x24++0x00 line.long 0x00 "DRCR,Debug Run Control Register" bitfld.long 0x00 4. " CBIUR , Cancel Bus Interface Unit Requests" "Not canceled,Canceled" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared" bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested" rgroup c14:0xc4++0x00 line.long 0x00 "PRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 2. " HNDLR ,Hold non-debug logic reset" "No reset,Reset" bitfld.long 0x00 1. " WRR ,Warm reset request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high" hgroup c14:0xc5++0x00 hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register" in tree.end width 6. tree "Breakpoint Registers" group c14:0x40++0x00 line.long 0x00 "BVR0,Breakpoint Value Register 0" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group c14:0x50++0x00 line.long 0x00 "BCR0,Breakpoint Control Register 0" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x41++0x00 line.long 0x00 "BVR1,Breakpoint Value Register 1" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group c14:0x51++0x00 line.long 0x00 "BCR1,Breakpoint Control Register 1" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x42++0x00 line.long 0x00 "BVR2,Breakpoint Value Register 2" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group c14:0x52++0x00 line.long 0x00 "BCR2,Breakpoint Control Register 2" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x43++0x00 line.long 0x00 "BVR3,Breakpoint Value Register 3" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group c14:0x53++0x00 line.long 0x00 "BCR3,Breakpoint Control Register 3" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x44++0x00 line.long 0x00 "BVR4,Breakpoint Value Register 4" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group c14:0x54++0x00 line.long 0x00 "BCR4,Breakpoint Control Register 4" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x45++0x00 line.long 0x00 "BVR5,Breakpoint Value Register 5" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group c14:0x55++0x00 line.long 0x00 "BCR5,Breakpoint Control Register 5" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end width 6. tree "Watchpoint Control Registers" group c14:0x60++0x00 line.long 0x00 "WVR0,Watchpoint Value Register 0" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group c14:0x70--0x70 line.long 0x0 "WCR0,Watchpoint Control Register 0" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x61++0x00 line.long 0x00 "WVR1,Watchpoint Value Register 1" hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1" group c14:0x71--0x71 line.long 0x0 "WCR1,Watchpoint Control Register 1" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x62++0x00 line.long 0x00 "WVR2,Watchpoint Value Register 2" hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2" group c14:0x72--0x72 line.long 0x0 "WCR2,Watchpoint Control Register 2" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x63++0x00 line.long 0x00 "WVR3,Watchpoint Value Register 3" hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3" group c14:0x73--0x73 line.long 0x0 "WCR3,Watchpoint Control Register 3" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x006--0x006 line.long 0x0 "WFAR,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction" tree.end width 0xb width 9. base ad:(d.l(c15:0x400f)) tree "Snoop Control Unit (SCU)" group.long 0x00++0x03 line.long 0x00 "SCUCR,SCU Control Register" bitfld.long 0x00 6. " ICSE ,IC standby enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCUSE ,SCU standby enable" "Disabled,Enabled" bitfld.long 0x00 4. " FADTP0E ,Force all Device to port0 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SCUSLE ,SCU Speculative linefills enable" "Disabled,Enabled" bitfld.long 0x00 2. " SCURPE ,SCU RAMs Parity enable" "Disabled,Enabled" bitfld.long 0x00 1. " AFE ,Address filtering enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SCUE ,SCU enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SCUCON,SCU Configuration Register" bitfld.long 0x00 14.--15. " RAM3 ,Cortex-A9 CPU3 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 12.--13. " RAM2 ,Cortex-A9 CPU2 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 10.--11. " RAM1 ,Cortex-A9 CPU1 Tag RAM Size" "16KB,32KB,64KB,?..." textline " " bitfld.long 0x00 8.--9. " RAM0 ,Cortex-A9 CPU0 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 7. " MOD3 ,CPU3 Mode" "AMP,SMP" bitfld.long 0x00 6. " MOD2 ,CPU2 Mode" "AMP,SMP" textline " " bitfld.long 0x00 5. " MOD1 ,CPU1 Mode" "AMP,SMP" bitfld.long 0x00 4. " MOD0 ,CPU0 Mode" "AMP,SMP" bitfld.long 0x00 0.--1. " NUM ,CPU Number" "CPU0,CPU0-CPU1,CPU0-CPU2,CPU0-CPU3" group.long 0x08++0x03 line.long 0x00 "SCUSTAT,SCU CPU Power Status Register" bitfld.long 0x00 24.--25. " STAT3 ,CPU3 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 16.--17. " STAT2 ,CPU2 Status" "Normal,Reserved,Dormant,Powered-off" textline " " bitfld.long 0x00 8.--9. " STAT1 ,CPU1 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 0.--1. " STAT0 ,CPU0 Status" "Normal,Reserved,Dormant,Powered-off" wgroup.long 0x0c++0x03 line.long 0x00 "INV,SCU Invalidate All Register" bitfld.long 0x00 12.--15. " WAY3 ,Cortex-A9 CPU3 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " WAY2 ,Cortex-A9 CPU2 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " WAY1 ,Cortex-A9 CPU1 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " WAY0 ,Cortex-A9 CPU0 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x03 line.long 0x00 "FSAR,Filtering Start Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FSA ,Filtering start address" group.long 0x44++0x03 line.long 0x00 "FEAR,Filtering End Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FEA ,Filtering end address" group.long 0x50++0x03 line.long 0x00 "SAC,SCU Access Control Register" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" group.long 0x54++0x03 line.long 0x00 "SSAC,SCU Secure Access Control Register" bitfld.long 0x00 11. " GCPU3 ,Global timer for CPU3" "Secure only,Secure/Non-secure" bitfld.long 0x00 10. " GCPU2 ,Global timer for CPU2" "Secure only,Secure/Non-secure" bitfld.long 0x00 9. " GCPU1 ,Global timer for CPU1" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 8. " GCPU0 ,Global timer for CPU0" "Secure only,Secure/Non-secure" bitfld.long 0x00 7. " TCPU3 ,Private timer for CPU3 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 6. " TCPU2 ,Private timer for CPU2 Access" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 5. " TCPU1 ,Private timer for CPU1 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 4. " TCPU0 ,Private timer for CPU0 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" tree.end width 0xb width 8. tree "Timer and Watchdog Blocks" base ad:(d.l(c15:0x400f))+0x600 group.long 0x00++0xb "Timer" line.long 0x00 "TLR,Timer Load Register" line.long 0x04 "TCR,Timer Counter Register" line.long 0x08 "TCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " AREL ,Auto reload" "Single shot,Auto-reload" bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "TISR,Timer Interrupt Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x20++0x13 "Watchdog" line.long 0x00 "WLR,Watchdog Load Register" line.long 0x04 "WCR,Watchdog Counter Register" line.long 0x08 "WCONR,Watchdog Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " WDM ,WD Mode" "Timer,Watchdog" bitfld.long 0x08 2. " ITEN ,IT Enable" "Disabled,Enabled" bitfld.long 0x08 1. " AREL ,Auto-Reload" "Single shot,Auto-reload" textline " " bitfld.long 0x08 0. " WEN ,Watchdog Enable" "Disabled,Enabled" line.long 0x0c "WISR,Watchdog Interrupt Status Register" eventfld.long 0x0C 0. " EFLAG ,Event Flag" "0,1" line.long 0x10 "WRSR,Watchdog Reset Sent Register" eventfld.long 0x10 0. " RFLAG ,Reset Flag" "No effect,Reset" wgroup.long 0x34++0x3 line.long 0x00 "WDR,Watchdog Disable Register" base ad:(d.l(c15:0x400f))+0x200 group.long 0x00++0xb "Global Timer" line.long 0x00 "GTLCR,Lower 32-bit Timer Counter Register" line.long 0x04 "GTUCR,Upper 32-bit Timer Counter Register" line.long 0x08 "GTCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "GTSR,Timer Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x10++0xb line.long 0x00 "GTLCOMR,Lower 32-bit Comparator Register" line.long 0x04 "GTUCOMR,Upper 32-bit Comparator Register" line.long 0x08 "GTINCR,Auto-increment Register for Comparator" tree.end width 11. tree.open "Interrupt Controller (PL-390)" width 17. base AD:0xa01000 tree "Distributor Interface" if (((d.l(AD:0xa01000+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif if (((d.l(AD:0xa01000+0x04))&0x400)==0x400) rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" else rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" endif rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..." hexmask.long.word 0x00 12.--23. 1. " REV_NUM ,Returns the revision number of the GIC" textline " " hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure) width 17. tree "Group/Security Registers" group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x01) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x02) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x03) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x04) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x05) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x06) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x07) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x08) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x09) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0A) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0B) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0C) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0D) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0E) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0F) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x10) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x11) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x12) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x13) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x14) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x15) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x16) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x17) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x18) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x0E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x19) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1A) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1B) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1C) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x0F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1D) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1E) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)==0x1F) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1" else hgroup.long 0x00FC++0x03 hide.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end endif width 24. tree "Set/Clear Enable Registers" group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)==0x1F) group.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled" else hgroup.long 0x017C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 22. tree "Set/Clear Pending Registers" group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Disabled,Enabled" if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Disabled,Enabled" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Disabled,Enabled" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Disabled,Enabled" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Disabled,Enabled" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Disabled,Enabled" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Disabled,Enabled" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Disabled,Enabled" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Disabled,Enabled" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Disabled,Enabled" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Disabled,Enabled" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Disabled,Enabled" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Disabled,Enabled" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Disabled,Enabled" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Disabled,Enabled" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Disabled,Enabled" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Disabled,Enabled" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Disabled,Enabled" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Disabled,Enabled" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Disabled,Enabled" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Disabled,Enabled" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Disabled,Enabled" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Disabled,Enabled" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Disabled,Enabled" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Disabled,Enabled" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Disabled,Enabled" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Disabled,Enabled" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Disabled,Enabled" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Disabled,Enabled" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Disabled,Enabled" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Disabled,Enabled" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)==0x1F) group.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Disabled,Enabled" else hgroup.long 0x027C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 24. tree "Set/Clear Active Registers" rgroup.long 0x0300++0x03 line.long 0x0 "GICD_ICDABR0,Active Status Register 0" bitfld.long 0x00 31. " ASB31 ,Active Status Bit 31" "Not active,Active" bitfld.long 0x00 30. " ASB30 ,Active Status Bit 30" "Not active,Active" bitfld.long 0x00 29. " ASB29 ,Active Status Bit 29" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB28 ,Active Status Bit 28" "Not active,Active" bitfld.long 0x00 27. " ASB27 ,Active Status Bit 27" "Not active,Active" bitfld.long 0x00 26. " ASB26 ,Active Status Bit 26" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB25 ,Active Status Bit 25" "Not active,Active" bitfld.long 0x00 24. " ASB24 ,Active Status Bit 24" "Not active,Active" bitfld.long 0x00 23. " ASB23 ,Active Status Bit 23" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB22 ,Active Status Bit 22" "Not active,Active" bitfld.long 0x00 21. " ASB21 ,Active Status Bit 21" "Not active,Active" bitfld.long 0x00 20. " ASB20 ,Active Status Bit 20" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB19 ,Active Status Bit 19" "Not active,Active" bitfld.long 0x00 18. " ASB18 ,Active Status Bit 18" "Not active,Active" bitfld.long 0x00 17. " ASB17 ,Active Status Bit 17" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB16 ,Active Status Bit 16" "Not active,Active" bitfld.long 0x00 15. " ASB15 ,Active Status Bit 15" "Not active,Active" bitfld.long 0x00 14. " ASB14 ,Active Status Bit 14" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB13 ,Active Status Bit 13" "Not active,Active" bitfld.long 0x00 12. " ASB12 ,Active Status Bit 12" "Not active,Active" bitfld.long 0x00 11. " ASB11 ,Active Status Bit 11" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB10 ,Active Status Bit 10" "Not active,Active" bitfld.long 0x00 9. " ASB9 ,Active Status Bit 9" "Not active,Active" bitfld.long 0x00 8. " ASB8 ,Active Status Bit 8" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB7 ,Active Status Bit 7" "Not active,Active" bitfld.long 0x00 6. " ASB6 ,Active Status Bit 6" "Not active,Active" bitfld.long 0x00 5. " ASB5 ,Active Status Bit 5" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB4 ,Active Status Bit 4" "Not active,Active" bitfld.long 0x00 3. " ASB3 ,Active Status Bit 3" "Not active,Active" bitfld.long 0x00 2. " ASB2 ,Active Status Bit 2" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB1 ,Active Status Bit 1" "Not active,Active" bitfld.long 0x00 0. " ASB0 ,Active Status Bit 0" "Not active,Active" if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" bitfld.long 0x00 31. " ASB63 ,Active Status Bit 63" "Not active,Active" bitfld.long 0x00 30. " ASB62 ,Active Status Bit 62" "Not active,Active" bitfld.long 0x00 29. " ASB61 ,Active Status Bit 61" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB60 ,Active Status Bit 60" "Not active,Active" bitfld.long 0x00 27. " ASB59 ,Active Status Bit 59" "Not active,Active" bitfld.long 0x00 26. " ASB58 ,Active Status Bit 58" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB57 ,Active Status Bit 57" "Not active,Active" bitfld.long 0x00 24. " ASB56 ,Active Status Bit 56" "Not active,Active" bitfld.long 0x00 23. " ASB55 ,Active Status Bit 55" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB54 ,Active Status Bit 54" "Not active,Active" bitfld.long 0x00 21. " ASB53 ,Active Status Bit 53" "Not active,Active" bitfld.long 0x00 20. " ASB52 ,Active Status Bit 52" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB51 ,Active Status Bit 51" "Not active,Active" bitfld.long 0x00 18. " ASB50 ,Active Status Bit 50" "Not active,Active" bitfld.long 0x00 17. " ASB49 ,Active Status Bit 49" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB48 ,Active Status Bit 48" "Not active,Active" bitfld.long 0x00 15. " ASB47 ,Active Status Bit 47" "Not active,Active" bitfld.long 0x00 14. " ASB46 ,Active Status Bit 46" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB45 ,Active Status Bit 45" "Not active,Active" bitfld.long 0x00 12. " ASB44 ,Active Status Bit 44" "Not active,Active" bitfld.long 0x00 11. " ASB43 ,Active Status Bit 43" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB42 ,Active Status Bit 42" "Not active,Active" bitfld.long 0x00 9. " ASB41 ,Active Status Bit 41" "Not active,Active" bitfld.long 0x00 8. " ASB40 ,Active Status Bit 40" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB39 ,Active Status Bit 39" "Not active,Active" bitfld.long 0x00 6. " ASB38 ,Active Status Bit 38" "Not active,Active" bitfld.long 0x00 5. " ASB37 ,Active Status Bit 37" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB36 ,Active Status Bit 36" "Not active,Active" bitfld.long 0x00 3. " ASB35 ,Active Status Bit 35" "Not active,Active" bitfld.long 0x00 2. " ASB34 ,Active Status Bit 34" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB33 ,Active Status Bit 33" "Not active,Active" bitfld.long 0x00 0. " ASB32 ,Active Status Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_ICDABR1,Active Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" bitfld.long 0x00 31. " ASB95 ,Active Status Bit 95" "Not active,Active" bitfld.long 0x00 30. " ASB94 ,Active Status Bit 94" "Not active,Active" bitfld.long 0x00 29. " ASB93 ,Active Status Bit 93" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB92 ,Active Status Bit 92" "Not active,Active" bitfld.long 0x00 27. " ASB91 ,Active Status Bit 91" "Not active,Active" bitfld.long 0x00 26. " ASB90 ,Active Status Bit 90" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB89 ,Active Status Bit 89" "Not active,Active" bitfld.long 0x00 24. " ASB88 ,Active Status Bit 88" "Not active,Active" bitfld.long 0x00 23. " ASB87 ,Active Status Bit 87" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB86 ,Active Status Bit 86" "Not active,Active" bitfld.long 0x00 21. " ASB85 ,Active Status Bit 85" "Not active,Active" bitfld.long 0x00 20. " ASB84 ,Active Status Bit 84" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB83 ,Active Status Bit 83" "Not active,Active" bitfld.long 0x00 18. " ASB82 ,Active Status Bit 82" "Not active,Active" bitfld.long 0x00 17. " ASB81 ,Active Status Bit 81" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB80 ,Active Status Bit 80" "Not active,Active" bitfld.long 0x00 15. " ASB79 ,Active Status Bit 79" "Not active,Active" bitfld.long 0x00 14. " ASB78 ,Active Status Bit 78" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB77 ,Active Status Bit 77" "Not active,Active" bitfld.long 0x00 12. " ASB76 ,Active Status Bit 76" "Not active,Active" bitfld.long 0x00 11. " ASB75 ,Active Status Bit 75" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB74 ,Active Status Bit 74" "Not active,Active" bitfld.long 0x00 9. " ASB73 ,Active Status Bit 73" "Not active,Active" bitfld.long 0x00 8. " ASB72 ,Active Status Bit 72" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB71 ,Active Status Bit 71" "Not active,Active" bitfld.long 0x00 6. " ASB70 ,Active Status Bit 70" "Not active,Active" bitfld.long 0x00 5. " ASB69 ,Active Status Bit 69" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB68 ,Active Status Bit 68" "Not active,Active" bitfld.long 0x00 3. " ASB67 ,Active Status Bit 67" "Not active,Active" bitfld.long 0x00 2. " ASB66 ,Active Status Bit 66" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB65 ,Active Status Bit 65" "Not active,Active" bitfld.long 0x00 0. " ASB64 ,Active Status Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_ICDABR2,Active Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x03) rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" bitfld.long 0x00 31. " ASB127 ,Active Status Bit 127" "Not active,Active" bitfld.long 0x00 30. " ASB126 ,Active Status Bit 126" "Not active,Active" bitfld.long 0x00 29. " ASB125 ,Active Status Bit 125" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB124 ,Active Status Bit 124" "Not active,Active" bitfld.long 0x00 27. " ASB123 ,Active Status Bit 123" "Not active,Active" bitfld.long 0x00 26. " ASB122 ,Active Status Bit 122" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB121 ,Active Status Bit 121" "Not active,Active" bitfld.long 0x00 24. " ASB120 ,Active Status Bit 120" "Not active,Active" bitfld.long 0x00 23. " ASB119 ,Active Status Bit 119" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB118 ,Active Status Bit 118" "Not active,Active" bitfld.long 0x00 21. " ASB117 ,Active Status Bit 117" "Not active,Active" bitfld.long 0x00 20. " ASB116 ,Active Status Bit 116" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB115 ,Active Status Bit 115" "Not active,Active" bitfld.long 0x00 18. " ASB114 ,Active Status Bit 114" "Not active,Active" bitfld.long 0x00 17. " ASB113 ,Active Status Bit 113" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB112 ,Active Status Bit 112" "Not active,Active" bitfld.long 0x00 15. " ASB111 ,Active Status Bit 111" "Not active,Active" bitfld.long 0x00 14. " ASB110 ,Active Status Bit 110" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB109 ,Active Status Bit 109" "Not active,Active" bitfld.long 0x00 12. " ASB108 ,Active Status Bit 108" "Not active,Active" bitfld.long 0x00 11. " ASB107 ,Active Status Bit 107" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB106 ,Active Status Bit 106" "Not active,Active" bitfld.long 0x00 9. " ASB105 ,Active Status Bit 105" "Not active,Active" bitfld.long 0x00 8. " ASB104 ,Active Status Bit 104" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB103 ,Active Status Bit 103" "Not active,Active" bitfld.long 0x00 6. " ASB102 ,Active Status Bit 102" "Not active,Active" bitfld.long 0x00 5. " ASB101 ,Active Status Bit 101" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB100 ,Active Status Bit 100" "Not active,Active" bitfld.long 0x00 3. " ASB99 ,Active Status Bit 99" "Not active,Active" bitfld.long 0x00 2. " ASB98 ,Active Status Bit 98" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB97 ,Active Status Bit 97" "Not active,Active" bitfld.long 0x00 0. " ASB96 ,Active Status Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_ICDABR3,Active Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" bitfld.long 0x00 31. " ASB159 ,Active Status Bit 159" "Not active,Active" bitfld.long 0x00 30. " ASB158 ,Active Status Bit 158" "Not active,Active" bitfld.long 0x00 29. " ASB157 ,Active Status Bit 157" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB156 ,Active Status Bit 156" "Not active,Active" bitfld.long 0x00 27. " ASB155 ,Active Status Bit 155" "Not active,Active" bitfld.long 0x00 26. " ASB154 ,Active Status Bit 154" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB153 ,Active Status Bit 153" "Not active,Active" bitfld.long 0x00 24. " ASB152 ,Active Status Bit 152" "Not active,Active" bitfld.long 0x00 23. " ASB151 ,Active Status Bit 151" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB150 ,Active Status Bit 150" "Not active,Active" bitfld.long 0x00 21. " ASB149 ,Active Status Bit 149" "Not active,Active" bitfld.long 0x00 20. " ASB148 ,Active Status Bit 148" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB147 ,Active Status Bit 147" "Not active,Active" bitfld.long 0x00 18. " ASB146 ,Active Status Bit 146" "Not active,Active" bitfld.long 0x00 17. " ASB145 ,Active Status Bit 145" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB144 ,Active Status Bit 144" "Not active,Active" bitfld.long 0x00 15. " ASB143 ,Active Status Bit 143" "Not active,Active" bitfld.long 0x00 14. " ASB142 ,Active Status Bit 142" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB141 ,Active Status Bit 141" "Not active,Active" bitfld.long 0x00 12. " ASB140 ,Active Status Bit 140" "Not active,Active" bitfld.long 0x00 11. " ASB139 ,Active Status Bit 139" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB138 ,Active Status Bit 138" "Not active,Active" bitfld.long 0x00 9. " ASB137 ,Active Status Bit 137" "Not active,Active" bitfld.long 0x00 8. " ASB136 ,Active Status Bit 136" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB135 ,Active Status Bit 135" "Not active,Active" bitfld.long 0x00 6. " ASB134 ,Active Status Bit 134" "Not active,Active" bitfld.long 0x00 5. " ASB133 ,Active Status Bit 133" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB132 ,Active Status Bit 132" "Not active,Active" bitfld.long 0x00 3. " ASB131 ,Active Status Bit 131" "Not active,Active" bitfld.long 0x00 2. " ASB130 ,Active Status Bit 130" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB129 ,Active Status Bit 129" "Not active,Active" bitfld.long 0x00 0. " ASB128 ,Active Status Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_ICDABR4,Active Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" bitfld.long 0x00 31. " ASB191 ,Active Status Bit 191" "Not active,Active" bitfld.long 0x00 30. " ASB190 ,Active Status Bit 190" "Not active,Active" bitfld.long 0x00 29. " ASB189 ,Active Status Bit 189" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB188 ,Active Status Bit 188" "Not active,Active" bitfld.long 0x00 27. " ASB187 ,Active Status Bit 187" "Not active,Active" bitfld.long 0x00 26. " ASB186 ,Active Status Bit 186" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB185 ,Active Status Bit 185" "Not active,Active" bitfld.long 0x00 24. " ASB184 ,Active Status Bit 184" "Not active,Active" bitfld.long 0x00 23. " ASB183 ,Active Status Bit 183" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB182 ,Active Status Bit 182" "Not active,Active" bitfld.long 0x00 21. " ASB181 ,Active Status Bit 181" "Not active,Active" bitfld.long 0x00 20. " ASB180 ,Active Status Bit 180" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB179 ,Active Status Bit 179" "Not active,Active" bitfld.long 0x00 18. " ASB178 ,Active Status Bit 178" "Not active,Active" bitfld.long 0x00 17. " ASB177 ,Active Status Bit 177" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB176 ,Active Status Bit 176" "Not active,Active" bitfld.long 0x00 15. " ASB175 ,Active Status Bit 175" "Not active,Active" bitfld.long 0x00 14. " ASB174 ,Active Status Bit 174" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB173 ,Active Status Bit 173" "Not active,Active" bitfld.long 0x00 12. " ASB172 ,Active Status Bit 172" "Not active,Active" bitfld.long 0x00 11. " ASB171 ,Active Status Bit 171" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB170 ,Active Status Bit 170" "Not active,Active" bitfld.long 0x00 9. " ASB169 ,Active Status Bit 169" "Not active,Active" bitfld.long 0x00 8. " ASB168 ,Active Status Bit 168" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB167 ,Active Status Bit 167" "Not active,Active" bitfld.long 0x00 6. " ASB166 ,Active Status Bit 166" "Not active,Active" bitfld.long 0x00 5. " ASB165 ,Active Status Bit 165" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB164 ,Active Status Bit 164" "Not active,Active" bitfld.long 0x00 3. " ASB163 ,Active Status Bit 163" "Not active,Active" bitfld.long 0x00 2. " ASB162 ,Active Status Bit 162" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB161 ,Active Status Bit 161" "Not active,Active" bitfld.long 0x00 0. " ASB160 ,Active Status Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_ICDABR5,Active Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" bitfld.long 0x00 31. " ASB223 ,Active Status Bit 223" "Not active,Active" bitfld.long 0x00 30. " ASB222 ,Active Status Bit 222" "Not active,Active" bitfld.long 0x00 29. " ASB221 ,Active Status Bit 221" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB220 ,Active Status Bit 220" "Not active,Active" bitfld.long 0x00 27. " ASB219 ,Active Status Bit 219" "Not active,Active" bitfld.long 0x00 26. " ASB218 ,Active Status Bit 218" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB217 ,Active Status Bit 217" "Not active,Active" bitfld.long 0x00 24. " ASB216 ,Active Status Bit 216" "Not active,Active" bitfld.long 0x00 23. " ASB215 ,Active Status Bit 215" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB214 ,Active Status Bit 214" "Not active,Active" bitfld.long 0x00 21. " ASB213 ,Active Status Bit 213" "Not active,Active" bitfld.long 0x00 20. " ASB212 ,Active Status Bit 212" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB211 ,Active Status Bit 211" "Not active,Active" bitfld.long 0x00 18. " ASB210 ,Active Status Bit 210" "Not active,Active" bitfld.long 0x00 17. " ASB209 ,Active Status Bit 209" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB208 ,Active Status Bit 208" "Not active,Active" bitfld.long 0x00 15. " ASB207 ,Active Status Bit 207" "Not active,Active" bitfld.long 0x00 14. " ASB206 ,Active Status Bit 206" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB205 ,Active Status Bit 205" "Not active,Active" bitfld.long 0x00 12. " ASB204 ,Active Status Bit 204" "Not active,Active" bitfld.long 0x00 11. " ASB203 ,Active Status Bit 203" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB202 ,Active Status Bit 202" "Not active,Active" bitfld.long 0x00 9. " ASB201 ,Active Status Bit 201" "Not active,Active" bitfld.long 0x00 8. " ASB200 ,Active Status Bit 200" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB199 ,Active Status Bit 199" "Not active,Active" bitfld.long 0x00 6. " ASB198 ,Active Status Bit 198" "Not active,Active" bitfld.long 0x00 5. " ASB197 ,Active Status Bit 197" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB196 ,Active Status Bit 196" "Not active,Active" bitfld.long 0x00 3. " ASB195 ,Active Status Bit 195" "Not active,Active" bitfld.long 0x00 2. " ASB194 ,Active Status Bit 194" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB193 ,Active Status Bit 193" "Not active,Active" bitfld.long 0x00 0. " ASB192 ,Active Status Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_ICDABR6,Active Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x07) rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" bitfld.long 0x00 31. " ASB255 ,Active Status Bit 255" "Not active,Active" bitfld.long 0x00 30. " ASB254 ,Active Status Bit 254" "Not active,Active" bitfld.long 0x00 29. " ASB253 ,Active Status Bit 253" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB252 ,Active Status Bit 252" "Not active,Active" bitfld.long 0x00 27. " ASB251 ,Active Status Bit 251" "Not active,Active" bitfld.long 0x00 26. " ASB250 ,Active Status Bit 250" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB249 ,Active Status Bit 249" "Not active,Active" bitfld.long 0x00 24. " ASB248 ,Active Status Bit 248" "Not active,Active" bitfld.long 0x00 23. " ASB247 ,Active Status Bit 247" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB246 ,Active Status Bit 246" "Not active,Active" bitfld.long 0x00 21. " ASB245 ,Active Status Bit 245" "Not active,Active" bitfld.long 0x00 20. " ASB244 ,Active Status Bit 244" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB243 ,Active Status Bit 243" "Not active,Active" bitfld.long 0x00 18. " ASB242 ,Active Status Bit 242" "Not active,Active" bitfld.long 0x00 17. " ASB241 ,Active Status Bit 241" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB240 ,Active Status Bit 240" "Not active,Active" bitfld.long 0x00 15. " ASB239 ,Active Status Bit 239" "Not active,Active" bitfld.long 0x00 14. " ASB238 ,Active Status Bit 238" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB237 ,Active Status Bit 237" "Not active,Active" bitfld.long 0x00 12. " ASB236 ,Active Status Bit 236" "Not active,Active" bitfld.long 0x00 11. " ASB235 ,Active Status Bit 235" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB234 ,Active Status Bit 234" "Not active,Active" bitfld.long 0x00 9. " ASB233 ,Active Status Bit 233" "Not active,Active" bitfld.long 0x00 8. " ASB232 ,Active Status Bit 232" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB231 ,Active Status Bit 231" "Not active,Active" bitfld.long 0x00 6. " ASB230 ,Active Status Bit 230" "Not active,Active" bitfld.long 0x00 5. " ASB229 ,Active Status Bit 229" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB228 ,Active Status Bit 228" "Not active,Active" bitfld.long 0x00 3. " ASB227 ,Active Status Bit 227" "Not active,Active" bitfld.long 0x00 2. " ASB226 ,Active Status Bit 226" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB225 ,Active Status Bit 225" "Not active,Active" bitfld.long 0x00 0. " ASB224 ,Active Status Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_ICDABR7,Active Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" bitfld.long 0x00 31. " ASB287 ,Active Status Bit 287" "Not active,Active" bitfld.long 0x00 30. " ASB286 ,Active Status Bit 286" "Not active,Active" bitfld.long 0x00 29. " ASB285 ,Active Status Bit 285" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB284 ,Active Status Bit 284" "Not active,Active" bitfld.long 0x00 27. " ASB283 ,Active Status Bit 283" "Not active,Active" bitfld.long 0x00 26. " ASB282 ,Active Status Bit 282" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB281 ,Active Status Bit 281" "Not active,Active" bitfld.long 0x00 24. " ASB280 ,Active Status Bit 280" "Not active,Active" bitfld.long 0x00 23. " ASB279 ,Active Status Bit 279" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB278 ,Active Status Bit 278" "Not active,Active" bitfld.long 0x00 21. " ASB277 ,Active Status Bit 277" "Not active,Active" bitfld.long 0x00 20. " ASB276 ,Active Status Bit 276" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB275 ,Active Status Bit 275" "Not active,Active" bitfld.long 0x00 18. " ASB274 ,Active Status Bit 274" "Not active,Active" bitfld.long 0x00 17. " ASB273 ,Active Status Bit 273" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB272 ,Active Status Bit 272" "Not active,Active" bitfld.long 0x00 15. " ASB271 ,Active Status Bit 271" "Not active,Active" bitfld.long 0x00 14. " ASB270 ,Active Status Bit 270" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB269 ,Active Status Bit 269" "Not active,Active" bitfld.long 0x00 12. " ASB268 ,Active Status Bit 268" "Not active,Active" bitfld.long 0x00 11. " ASB267 ,Active Status Bit 267" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB266 ,Active Status Bit 266" "Not active,Active" bitfld.long 0x00 9. " ASB265 ,Active Status Bit 265" "Not active,Active" bitfld.long 0x00 8. " ASB264 ,Active Status Bit 264" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB263 ,Active Status Bit 263" "Not active,Active" bitfld.long 0x00 6. " ASB262 ,Active Status Bit 262" "Not active,Active" bitfld.long 0x00 5. " ASB261 ,Active Status Bit 261" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB260 ,Active Status Bit 260" "Not active,Active" bitfld.long 0x00 3. " ASB259 ,Active Status Bit 259" "Not active,Active" bitfld.long 0x00 2. " ASB258 ,Active Status Bit 258" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB257 ,Active Status Bit 257" "Not active,Active" bitfld.long 0x00 0. " ASB256 ,Active Status Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_ICDABR8,Active Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" bitfld.long 0x00 31. " ASB319 ,Active Status Bit 319" "Not active,Active" bitfld.long 0x00 30. " ASB318 ,Active Status Bit 318" "Not active,Active" bitfld.long 0x00 29. " ASB317 ,Active Status Bit 317" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB316 ,Active Status Bit 316" "Not active,Active" bitfld.long 0x00 27. " ASB315 ,Active Status Bit 315" "Not active,Active" bitfld.long 0x00 26. " ASB314 ,Active Status Bit 314" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB313 ,Active Status Bit 313" "Not active,Active" bitfld.long 0x00 24. " ASB312 ,Active Status Bit 312" "Not active,Active" bitfld.long 0x00 23. " ASB311 ,Active Status Bit 311" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB310 ,Active Status Bit 310" "Not active,Active" bitfld.long 0x00 21. " ASB309 ,Active Status Bit 309" "Not active,Active" bitfld.long 0x00 20. " ASB308 ,Active Status Bit 308" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB307 ,Active Status Bit 307" "Not active,Active" bitfld.long 0x00 18. " ASB306 ,Active Status Bit 306" "Not active,Active" bitfld.long 0x00 17. " ASB305 ,Active Status Bit 305" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB304 ,Active Status Bit 304" "Not active,Active" bitfld.long 0x00 15. " ASB303 ,Active Status Bit 303" "Not active,Active" bitfld.long 0x00 14. " ASB302 ,Active Status Bit 302" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB301 ,Active Status Bit 301" "Not active,Active" bitfld.long 0x00 12. " ASB300 ,Active Status Bit 300" "Not active,Active" bitfld.long 0x00 11. " ASB299 ,Active Status Bit 299" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB298 ,Active Status Bit 298" "Not active,Active" bitfld.long 0x00 9. " ASB297 ,Active Status Bit 297" "Not active,Active" bitfld.long 0x00 8. " ASB296 ,Active Status Bit 296" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB295 ,Active Status Bit 295" "Not active,Active" bitfld.long 0x00 6. " ASB294 ,Active Status Bit 294" "Not active,Active" bitfld.long 0x00 5. " ASB293 ,Active Status Bit 293" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB292 ,Active Status Bit 292" "Not active,Active" bitfld.long 0x00 3. " ASB291 ,Active Status Bit 291" "Not active,Active" bitfld.long 0x00 2. " ASB290 ,Active Status Bit 290" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB289 ,Active Status Bit 289" "Not active,Active" bitfld.long 0x00 0. " ASB288 ,Active Status Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_ICDABR9,Active Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" bitfld.long 0x00 31. " ASB351 ,Active Status Bit 351" "Not active,Active" bitfld.long 0x00 30. " ASB350 ,Active Status Bit 350" "Not active,Active" bitfld.long 0x00 29. " ASB349 ,Active Status Bit 349" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB348 ,Active Status Bit 348" "Not active,Active" bitfld.long 0x00 27. " ASB347 ,Active Status Bit 347" "Not active,Active" bitfld.long 0x00 26. " ASB346 ,Active Status Bit 346" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB345 ,Active Status Bit 345" "Not active,Active" bitfld.long 0x00 24. " ASB344 ,Active Status Bit 344" "Not active,Active" bitfld.long 0x00 23. " ASB343 ,Active Status Bit 343" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB342 ,Active Status Bit 342" "Not active,Active" bitfld.long 0x00 21. " ASB341 ,Active Status Bit 341" "Not active,Active" bitfld.long 0x00 20. " ASB340 ,Active Status Bit 340" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB339 ,Active Status Bit 339" "Not active,Active" bitfld.long 0x00 18. " ASB338 ,Active Status Bit 338" "Not active,Active" bitfld.long 0x00 17. " ASB337 ,Active Status Bit 337" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB336 ,Active Status Bit 336" "Not active,Active" bitfld.long 0x00 15. " ASB335 ,Active Status Bit 335" "Not active,Active" bitfld.long 0x00 14. " ASB334 ,Active Status Bit 334" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB333 ,Active Status Bit 333" "Not active,Active" bitfld.long 0x00 12. " ASB332 ,Active Status Bit 332" "Not active,Active" bitfld.long 0x00 11. " ASB331 ,Active Status Bit 331" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB330 ,Active Status Bit 330" "Not active,Active" bitfld.long 0x00 9. " ASB329 ,Active Status Bit 329" "Not active,Active" bitfld.long 0x00 8. " ASB328 ,Active Status Bit 328" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB327 ,Active Status Bit 327" "Not active,Active" bitfld.long 0x00 6. " ASB326 ,Active Status Bit 326" "Not active,Active" bitfld.long 0x00 5. " ASB325 ,Active Status Bit 325" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB324 ,Active Status Bit 324" "Not active,Active" bitfld.long 0x00 3. " ASB323 ,Active Status Bit 323" "Not active,Active" bitfld.long 0x00 2. " ASB322 ,Active Status Bit 322" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB321 ,Active Status Bit 321" "Not active,Active" bitfld.long 0x00 0. " ASB320 ,Active Status Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_ICDABR10,Active Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" bitfld.long 0x00 31. " ASB383 ,Active Status Bit 383" "Not active,Active" bitfld.long 0x00 30. " ASB382 ,Active Status Bit 382" "Not active,Active" bitfld.long 0x00 29. " ASB381 ,Active Status Bit 381" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB380 ,Active Status Bit 380" "Not active,Active" bitfld.long 0x00 27. " ASB379 ,Active Status Bit 379" "Not active,Active" bitfld.long 0x00 26. " ASB378 ,Active Status Bit 378" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB377 ,Active Status Bit 377" "Not active,Active" bitfld.long 0x00 24. " ASB376 ,Active Status Bit 376" "Not active,Active" bitfld.long 0x00 23. " ASB375 ,Active Status Bit 375" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB374 ,Active Status Bit 374" "Not active,Active" bitfld.long 0x00 21. " ASB373 ,Active Status Bit 373" "Not active,Active" bitfld.long 0x00 20. " ASB372 ,Active Status Bit 372" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB371 ,Active Status Bit 371" "Not active,Active" bitfld.long 0x00 18. " ASB370 ,Active Status Bit 370" "Not active,Active" bitfld.long 0x00 17. " ASB369 ,Active Status Bit 369" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB368 ,Active Status Bit 368" "Not active,Active" bitfld.long 0x00 15. " ASB367 ,Active Status Bit 367" "Not active,Active" bitfld.long 0x00 14. " ASB366 ,Active Status Bit 366" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB365 ,Active Status Bit 365" "Not active,Active" bitfld.long 0x00 12. " ASB364 ,Active Status Bit 364" "Not active,Active" bitfld.long 0x00 11. " ASB363 ,Active Status Bit 363" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB362 ,Active Status Bit 362" "Not active,Active" bitfld.long 0x00 9. " ASB361 ,Active Status Bit 361" "Not active,Active" bitfld.long 0x00 8. " ASB360 ,Active Status Bit 360" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB359 ,Active Status Bit 359" "Not active,Active" bitfld.long 0x00 6. " ASB358 ,Active Status Bit 358" "Not active,Active" bitfld.long 0x00 5. " ASB357 ,Active Status Bit 357" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB356 ,Active Status Bit 356" "Not active,Active" bitfld.long 0x00 3. " ASB355 ,Active Status Bit 355" "Not active,Active" bitfld.long 0x00 2. " ASB354 ,Active Status Bit 354" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB353 ,Active Status Bit 353" "Not active,Active" bitfld.long 0x00 0. " ASB352 ,Active Status Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_ICDABR11,Active Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" bitfld.long 0x00 31. " ASB415 ,Active Status Bit 415" "Not active,Active" bitfld.long 0x00 30. " ASB414 ,Active Status Bit 414" "Not active,Active" bitfld.long 0x00 29. " ASB413 ,Active Status Bit 413" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB412 ,Active Status Bit 412" "Not active,Active" bitfld.long 0x00 27. " ASB411 ,Active Status Bit 411" "Not active,Active" bitfld.long 0x00 26. " ASB410 ,Active Status Bit 410" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB409 ,Active Status Bit 409" "Not active,Active" bitfld.long 0x00 24. " ASB408 ,Active Status Bit 408" "Not active,Active" bitfld.long 0x00 23. " ASB407 ,Active Status Bit 407" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB406 ,Active Status Bit 406" "Not active,Active" bitfld.long 0x00 21. " ASB405 ,Active Status Bit 405" "Not active,Active" bitfld.long 0x00 20. " ASB404 ,Active Status Bit 404" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB403 ,Active Status Bit 403" "Not active,Active" bitfld.long 0x00 18. " ASB402 ,Active Status Bit 402" "Not active,Active" bitfld.long 0x00 17. " ASB401 ,Active Status Bit 401" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB400 ,Active Status Bit 400" "Not active,Active" bitfld.long 0x00 15. " ASB399 ,Active Status Bit 399" "Not active,Active" bitfld.long 0x00 14. " ASB398 ,Active Status Bit 398" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB397 ,Active Status Bit 397" "Not active,Active" bitfld.long 0x00 12. " ASB396 ,Active Status Bit 396" "Not active,Active" bitfld.long 0x00 11. " ASB395 ,Active Status Bit 395" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB394 ,Active Status Bit 394" "Not active,Active" bitfld.long 0x00 9. " ASB393 ,Active Status Bit 393" "Not active,Active" bitfld.long 0x00 8. " ASB392 ,Active Status Bit 392" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB391 ,Active Status Bit 391" "Not active,Active" bitfld.long 0x00 6. " ASB390 ,Active Status Bit 390" "Not active,Active" bitfld.long 0x00 5. " ASB389 ,Active Status Bit 389" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB388 ,Active Status Bit 388" "Not active,Active" bitfld.long 0x00 3. " ASB387 ,Active Status Bit 387" "Not active,Active" bitfld.long 0x00 2. " ASB386 ,Active Status Bit 386" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB385 ,Active Status Bit 385" "Not active,Active" bitfld.long 0x00 0. " ASB384 ,Active Status Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_ICDABR12,Active Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" bitfld.long 0x00 31. " ASB447 ,Active Status Bit 447" "Not active,Active" bitfld.long 0x00 30. " ASB446 ,Active Status Bit 446" "Not active,Active" bitfld.long 0x00 29. " ASB445 ,Active Status Bit 445" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB444 ,Active Status Bit 444" "Not active,Active" bitfld.long 0x00 27. " ASB443 ,Active Status Bit 443" "Not active,Active" bitfld.long 0x00 26. " ASB442 ,Active Status Bit 442" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB441 ,Active Status Bit 441" "Not active,Active" bitfld.long 0x00 24. " ASB440 ,Active Status Bit 440" "Not active,Active" bitfld.long 0x00 23. " ASB439 ,Active Status Bit 439" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB438 ,Active Status Bit 438" "Not active,Active" bitfld.long 0x00 21. " ASB437 ,Active Status Bit 437" "Not active,Active" bitfld.long 0x00 20. " ASB436 ,Active Status Bit 436" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB435 ,Active Status Bit 435" "Not active,Active" bitfld.long 0x00 18. " ASB434 ,Active Status Bit 434" "Not active,Active" bitfld.long 0x00 17. " ASB433 ,Active Status Bit 433" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB432 ,Active Status Bit 432" "Not active,Active" bitfld.long 0x00 15. " ASB431 ,Active Status Bit 431" "Not active,Active" bitfld.long 0x00 14. " ASB430 ,Active Status Bit 430" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB429 ,Active Status Bit 429" "Not active,Active" bitfld.long 0x00 12. " ASB428 ,Active Status Bit 428" "Not active,Active" bitfld.long 0x00 11. " ASB427 ,Active Status Bit 427" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB426 ,Active Status Bit 426" "Not active,Active" bitfld.long 0x00 9. " ASB425 ,Active Status Bit 425" "Not active,Active" bitfld.long 0x00 8. " ASB424 ,Active Status Bit 424" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB423 ,Active Status Bit 423" "Not active,Active" bitfld.long 0x00 6. " ASB422 ,Active Status Bit 422" "Not active,Active" bitfld.long 0x00 5. " ASB421 ,Active Status Bit 421" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB420 ,Active Status Bit 420" "Not active,Active" bitfld.long 0x00 3. " ASB419 ,Active Status Bit 419" "Not active,Active" bitfld.long 0x00 2. " ASB418 ,Active Status Bit 418" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB417 ,Active Status Bit 417" "Not active,Active" bitfld.long 0x00 0. " ASB416 ,Active Status Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_ICDABR13,Active Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" bitfld.long 0x00 31. " ASB479 ,Active Status Bit 479" "Not active,Active" bitfld.long 0x00 30. " ASB478 ,Active Status Bit 478" "Not active,Active" bitfld.long 0x00 29. " ASB477 ,Active Status Bit 477" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB476 ,Active Status Bit 476" "Not active,Active" bitfld.long 0x00 27. " ASB475 ,Active Status Bit 475" "Not active,Active" bitfld.long 0x00 26. " ASB474 ,Active Status Bit 474" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB473 ,Active Status Bit 473" "Not active,Active" bitfld.long 0x00 24. " ASB472 ,Active Status Bit 472" "Not active,Active" bitfld.long 0x00 23. " ASB471 ,Active Status Bit 471" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB470 ,Active Status Bit 470" "Not active,Active" bitfld.long 0x00 21. " ASB469 ,Active Status Bit 469" "Not active,Active" bitfld.long 0x00 20. " ASB468 ,Active Status Bit 468" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB467 ,Active Status Bit 467" "Not active,Active" bitfld.long 0x00 18. " ASB466 ,Active Status Bit 466" "Not active,Active" bitfld.long 0x00 17. " ASB465 ,Active Status Bit 465" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB464 ,Active Status Bit 464" "Not active,Active" bitfld.long 0x00 15. " ASB463 ,Active Status Bit 463" "Not active,Active" bitfld.long 0x00 14. " ASB462 ,Active Status Bit 462" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB461 ,Active Status Bit 461" "Not active,Active" bitfld.long 0x00 12. " ASB460 ,Active Status Bit 460" "Not active,Active" bitfld.long 0x00 11. " ASB459 ,Active Status Bit 459" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB458 ,Active Status Bit 458" "Not active,Active" bitfld.long 0x00 9. " ASB457 ,Active Status Bit 457" "Not active,Active" bitfld.long 0x00 8. " ASB456 ,Active Status Bit 456" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB455 ,Active Status Bit 455" "Not active,Active" bitfld.long 0x00 6. " ASB454 ,Active Status Bit 454" "Not active,Active" bitfld.long 0x00 5. " ASB453 ,Active Status Bit 453" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB452 ,Active Status Bit 452" "Not active,Active" bitfld.long 0x00 3. " ASB451 ,Active Status Bit 451" "Not active,Active" bitfld.long 0x00 2. " ASB450 ,Active Status Bit 450" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB449 ,Active Status Bit 449" "Not active,Active" bitfld.long 0x00 0. " ASB448 ,Active Status Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_ICDABR14,Active Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" bitfld.long 0x00 31. " ASB511 ,Active Status Bit 511" "Not active,Active" bitfld.long 0x00 30. " ASB510 ,Active Status Bit 510" "Not active,Active" bitfld.long 0x00 29. " ASB509 ,Active Status Bit 509" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB508 ,Active Status Bit 508" "Not active,Active" bitfld.long 0x00 27. " ASB507 ,Active Status Bit 507" "Not active,Active" bitfld.long 0x00 26. " ASB506 ,Active Status Bit 506" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB505 ,Active Status Bit 505" "Not active,Active" bitfld.long 0x00 24. " ASB504 ,Active Status Bit 504" "Not active,Active" bitfld.long 0x00 23. " ASB503 ,Active Status Bit 503" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB502 ,Active Status Bit 502" "Not active,Active" bitfld.long 0x00 21. " ASB501 ,Active Status Bit 501" "Not active,Active" bitfld.long 0x00 20. " ASB500 ,Active Status Bit 500" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB499 ,Active Status Bit 499" "Not active,Active" bitfld.long 0x00 18. " ASB498 ,Active Status Bit 498" "Not active,Active" bitfld.long 0x00 17. " ASB497 ,Active Status Bit 497" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB496 ,Active Status Bit 496" "Not active,Active" bitfld.long 0x00 15. " ASB495 ,Active Status Bit 495" "Not active,Active" bitfld.long 0x00 14. " ASB494 ,Active Status Bit 494" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB493 ,Active Status Bit 493" "Not active,Active" bitfld.long 0x00 12. " ASB492 ,Active Status Bit 492" "Not active,Active" bitfld.long 0x00 11. " ASB491 ,Active Status Bit 491" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB490 ,Active Status Bit 490" "Not active,Active" bitfld.long 0x00 9. " ASB489 ,Active Status Bit 489" "Not active,Active" bitfld.long 0x00 8. " ASB488 ,Active Status Bit 488" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB487 ,Active Status Bit 487" "Not active,Active" bitfld.long 0x00 6. " ASB486 ,Active Status Bit 486" "Not active,Active" bitfld.long 0x00 5. " ASB485 ,Active Status Bit 485" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB484 ,Active Status Bit 484" "Not active,Active" bitfld.long 0x00 3. " ASB483 ,Active Status Bit 483" "Not active,Active" bitfld.long 0x00 2. " ASB482 ,Active Status Bit 482" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB481 ,Active Status Bit 481" "Not active,Active" bitfld.long 0x00 0. " ASB480 ,Active Status Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_ICDABR15,Active Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" bitfld.long 0x00 31. " ASB543 ,Active Status Bit 543" "Not active,Active" bitfld.long 0x00 30. " ASB542 ,Active Status Bit 542" "Not active,Active" bitfld.long 0x00 29. " ASB541 ,Active Status Bit 541" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB540 ,Active Status Bit 540" "Not active,Active" bitfld.long 0x00 27. " ASB539 ,Active Status Bit 539" "Not active,Active" bitfld.long 0x00 26. " ASB538 ,Active Status Bit 538" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB537 ,Active Status Bit 537" "Not active,Active" bitfld.long 0x00 24. " ASB536 ,Active Status Bit 536" "Not active,Active" bitfld.long 0x00 23. " ASB535 ,Active Status Bit 535" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB534 ,Active Status Bit 534" "Not active,Active" bitfld.long 0x00 21. " ASB533 ,Active Status Bit 533" "Not active,Active" bitfld.long 0x00 20. " ASB532 ,Active Status Bit 532" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB531 ,Active Status Bit 531" "Not active,Active" bitfld.long 0x00 18. " ASB530 ,Active Status Bit 530" "Not active,Active" bitfld.long 0x00 17. " ASB529 ,Active Status Bit 529" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB528 ,Active Status Bit 528" "Not active,Active" bitfld.long 0x00 15. " ASB527 ,Active Status Bit 527" "Not active,Active" bitfld.long 0x00 14. " ASB526 ,Active Status Bit 526" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB525 ,Active Status Bit 525" "Not active,Active" bitfld.long 0x00 12. " ASB524 ,Active Status Bit 524" "Not active,Active" bitfld.long 0x00 11. " ASB523 ,Active Status Bit 523" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB522 ,Active Status Bit 522" "Not active,Active" bitfld.long 0x00 9. " ASB521 ,Active Status Bit 521" "Not active,Active" bitfld.long 0x00 8. " ASB520 ,Active Status Bit 520" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB519 ,Active Status Bit 519" "Not active,Active" bitfld.long 0x00 6. " ASB518 ,Active Status Bit 518" "Not active,Active" bitfld.long 0x00 5. " ASB517 ,Active Status Bit 517" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB516 ,Active Status Bit 516" "Not active,Active" bitfld.long 0x00 3. " ASB515 ,Active Status Bit 515" "Not active,Active" bitfld.long 0x00 2. " ASB514 ,Active Status Bit 514" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB513 ,Active Status Bit 513" "Not active,Active" bitfld.long 0x00 0. " ASB512 ,Active Status Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_ICDABR16,Active Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" bitfld.long 0x00 31. " ASB575 ,Active Status Bit 575" "Not active,Active" bitfld.long 0x00 30. " ASB574 ,Active Status Bit 574" "Not active,Active" bitfld.long 0x00 29. " ASB573 ,Active Status Bit 573" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB572 ,Active Status Bit 572" "Not active,Active" bitfld.long 0x00 27. " ASB571 ,Active Status Bit 571" "Not active,Active" bitfld.long 0x00 26. " ASB570 ,Active Status Bit 570" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB569 ,Active Status Bit 569" "Not active,Active" bitfld.long 0x00 24. " ASB568 ,Active Status Bit 568" "Not active,Active" bitfld.long 0x00 23. " ASB567 ,Active Status Bit 567" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB566 ,Active Status Bit 566" "Not active,Active" bitfld.long 0x00 21. " ASB565 ,Active Status Bit 565" "Not active,Active" bitfld.long 0x00 20. " ASB564 ,Active Status Bit 564" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB563 ,Active Status Bit 563" "Not active,Active" bitfld.long 0x00 18. " ASB562 ,Active Status Bit 562" "Not active,Active" bitfld.long 0x00 17. " ASB561 ,Active Status Bit 561" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB560 ,Active Status Bit 560" "Not active,Active" bitfld.long 0x00 15. " ASB559 ,Active Status Bit 559" "Not active,Active" bitfld.long 0x00 14. " ASB558 ,Active Status Bit 558" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB557 ,Active Status Bit 557" "Not active,Active" bitfld.long 0x00 12. " ASB556 ,Active Status Bit 556" "Not active,Active" bitfld.long 0x00 11. " ASB555 ,Active Status Bit 555" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB554 ,Active Status Bit 554" "Not active,Active" bitfld.long 0x00 9. " ASB553 ,Active Status Bit 553" "Not active,Active" bitfld.long 0x00 8. " ASB552 ,Active Status Bit 552" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB551 ,Active Status Bit 551" "Not active,Active" bitfld.long 0x00 6. " ASB550 ,Active Status Bit 550" "Not active,Active" bitfld.long 0x00 5. " ASB549 ,Active Status Bit 549" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB548 ,Active Status Bit 548" "Not active,Active" bitfld.long 0x00 3. " ASB547 ,Active Status Bit 547" "Not active,Active" bitfld.long 0x00 2. " ASB546 ,Active Status Bit 546" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB545 ,Active Status Bit 545" "Not active,Active" bitfld.long 0x00 0. " ASB544 ,Active Status Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_ICDABR17,Active Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" bitfld.long 0x00 31. " ASB607 ,Active Status Bit 607" "Not active,Active" bitfld.long 0x00 30. " ASB606 ,Active Status Bit 606" "Not active,Active" bitfld.long 0x00 29. " ASB605 ,Active Status Bit 605" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB604 ,Active Status Bit 604" "Not active,Active" bitfld.long 0x00 27. " ASB603 ,Active Status Bit 603" "Not active,Active" bitfld.long 0x00 26. " ASB602 ,Active Status Bit 602" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB601 ,Active Status Bit 601" "Not active,Active" bitfld.long 0x00 24. " ASB600 ,Active Status Bit 600" "Not active,Active" bitfld.long 0x00 23. " ASB599 ,Active Status Bit 599" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB598 ,Active Status Bit 598" "Not active,Active" bitfld.long 0x00 21. " ASB597 ,Active Status Bit 597" "Not active,Active" bitfld.long 0x00 20. " ASB596 ,Active Status Bit 596" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB595 ,Active Status Bit 595" "Not active,Active" bitfld.long 0x00 18. " ASB594 ,Active Status Bit 594" "Not active,Active" bitfld.long 0x00 17. " ASB593 ,Active Status Bit 593" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB592 ,Active Status Bit 592" "Not active,Active" bitfld.long 0x00 15. " ASB591 ,Active Status Bit 591" "Not active,Active" bitfld.long 0x00 14. " ASB590 ,Active Status Bit 590" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB589 ,Active Status Bit 589" "Not active,Active" bitfld.long 0x00 12. " ASB588 ,Active Status Bit 588" "Not active,Active" bitfld.long 0x00 11. " ASB587 ,Active Status Bit 587" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB586 ,Active Status Bit 586" "Not active,Active" bitfld.long 0x00 9. " ASB585 ,Active Status Bit 585" "Not active,Active" bitfld.long 0x00 8. " ASB584 ,Active Status Bit 584" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB583 ,Active Status Bit 583" "Not active,Active" bitfld.long 0x00 6. " ASB582 ,Active Status Bit 582" "Not active,Active" bitfld.long 0x00 5. " ASB581 ,Active Status Bit 581" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB580 ,Active Status Bit 580" "Not active,Active" bitfld.long 0x00 3. " ASB579 ,Active Status Bit 579" "Not active,Active" bitfld.long 0x00 2. " ASB578 ,Active Status Bit 578" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB577 ,Active Status Bit 577" "Not active,Active" bitfld.long 0x00 0. " ASB576 ,Active Status Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_ICDABR18,Active Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x13) rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" bitfld.long 0x00 31. " ASB639 ,Active Status Bit 639" "Not active,Active" bitfld.long 0x00 30. " ASB638 ,Active Status Bit 638" "Not active,Active" bitfld.long 0x00 29. " ASB637 ,Active Status Bit 637" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB636 ,Active Status Bit 636" "Not active,Active" bitfld.long 0x00 27. " ASB635 ,Active Status Bit 635" "Not active,Active" bitfld.long 0x00 26. " ASB634 ,Active Status Bit 634" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB633 ,Active Status Bit 633" "Not active,Active" bitfld.long 0x00 24. " ASB632 ,Active Status Bit 632" "Not active,Active" bitfld.long 0x00 23. " ASB631 ,Active Status Bit 631" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB630 ,Active Status Bit 630" "Not active,Active" bitfld.long 0x00 21. " ASB629 ,Active Status Bit 629" "Not active,Active" bitfld.long 0x00 20. " ASB628 ,Active Status Bit 628" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB627 ,Active Status Bit 627" "Not active,Active" bitfld.long 0x00 18. " ASB626 ,Active Status Bit 626" "Not active,Active" bitfld.long 0x00 17. " ASB625 ,Active Status Bit 625" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB624 ,Active Status Bit 624" "Not active,Active" bitfld.long 0x00 15. " ASB623 ,Active Status Bit 623" "Not active,Active" bitfld.long 0x00 14. " ASB622 ,Active Status Bit 622" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB621 ,Active Status Bit 621" "Not active,Active" bitfld.long 0x00 12. " ASB620 ,Active Status Bit 620" "Not active,Active" bitfld.long 0x00 11. " ASB619 ,Active Status Bit 619" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB618 ,Active Status Bit 618" "Not active,Active" bitfld.long 0x00 9. " ASB617 ,Active Status Bit 617" "Not active,Active" bitfld.long 0x00 8. " ASB616 ,Active Status Bit 616" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB615 ,Active Status Bit 615" "Not active,Active" bitfld.long 0x00 6. " ASB614 ,Active Status Bit 614" "Not active,Active" bitfld.long 0x00 5. " ASB613 ,Active Status Bit 613" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB612 ,Active Status Bit 612" "Not active,Active" bitfld.long 0x00 3. " ASB611 ,Active Status Bit 611" "Not active,Active" bitfld.long 0x00 2. " ASB610 ,Active Status Bit 610" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB609 ,Active Status Bit 609" "Not active,Active" bitfld.long 0x00 0. " ASB608 ,Active Status Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_ICDABR19,Active Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" bitfld.long 0x00 31. " ASB671 ,Active Status Bit 671" "Not active,Active" bitfld.long 0x00 30. " ASB670 ,Active Status Bit 670" "Not active,Active" bitfld.long 0x00 29. " ASB669 ,Active Status Bit 669" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB668 ,Active Status Bit 668" "Not active,Active" bitfld.long 0x00 27. " ASB667 ,Active Status Bit 667" "Not active,Active" bitfld.long 0x00 26. " ASB666 ,Active Status Bit 666" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB665 ,Active Status Bit 665" "Not active,Active" bitfld.long 0x00 24. " ASB664 ,Active Status Bit 664" "Not active,Active" bitfld.long 0x00 23. " ASB663 ,Active Status Bit 663" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB662 ,Active Status Bit 662" "Not active,Active" bitfld.long 0x00 21. " ASB661 ,Active Status Bit 661" "Not active,Active" bitfld.long 0x00 20. " ASB660 ,Active Status Bit 660" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB659 ,Active Status Bit 659" "Not active,Active" bitfld.long 0x00 18. " ASB658 ,Active Status Bit 658" "Not active,Active" bitfld.long 0x00 17. " ASB657 ,Active Status Bit 657" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB656 ,Active Status Bit 656" "Not active,Active" bitfld.long 0x00 15. " ASB655 ,Active Status Bit 655" "Not active,Active" bitfld.long 0x00 14. " ASB654 ,Active Status Bit 654" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB653 ,Active Status Bit 653" "Not active,Active" bitfld.long 0x00 12. " ASB652 ,Active Status Bit 652" "Not active,Active" bitfld.long 0x00 11. " ASB651 ,Active Status Bit 651" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB650 ,Active Status Bit 650" "Not active,Active" bitfld.long 0x00 9. " ASB649 ,Active Status Bit 649" "Not active,Active" bitfld.long 0x00 8. " ASB648 ,Active Status Bit 648" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB647 ,Active Status Bit 647" "Not active,Active" bitfld.long 0x00 6. " ASB646 ,Active Status Bit 646" "Not active,Active" bitfld.long 0x00 5. " ASB645 ,Active Status Bit 645" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB644 ,Active Status Bit 644" "Not active,Active" bitfld.long 0x00 3. " ASB643 ,Active Status Bit 643" "Not active,Active" bitfld.long 0x00 2. " ASB642 ,Active Status Bit 642" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB641 ,Active Status Bit 641" "Not active,Active" bitfld.long 0x00 0. " ASB640 ,Active Status Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_ICDABR20,Active Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" bitfld.long 0x00 31. " ASB703 ,Active Status Bit 703" "Not active,Active" bitfld.long 0x00 30. " ASB702 ,Active Status Bit 702" "Not active,Active" bitfld.long 0x00 29. " ASB701 ,Active Status Bit 701" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB700 ,Active Status Bit 700" "Not active,Active" bitfld.long 0x00 27. " ASB699 ,Active Status Bit 699" "Not active,Active" bitfld.long 0x00 26. " ASB698 ,Active Status Bit 698" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB697 ,Active Status Bit 697" "Not active,Active" bitfld.long 0x00 24. " ASB696 ,Active Status Bit 696" "Not active,Active" bitfld.long 0x00 23. " ASB695 ,Active Status Bit 695" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB694 ,Active Status Bit 694" "Not active,Active" bitfld.long 0x00 21. " ASB693 ,Active Status Bit 693" "Not active,Active" bitfld.long 0x00 20. " ASB692 ,Active Status Bit 692" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB691 ,Active Status Bit 691" "Not active,Active" bitfld.long 0x00 18. " ASB690 ,Active Status Bit 690" "Not active,Active" bitfld.long 0x00 17. " ASB689 ,Active Status Bit 689" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB688 ,Active Status Bit 688" "Not active,Active" bitfld.long 0x00 15. " ASB687 ,Active Status Bit 687" "Not active,Active" bitfld.long 0x00 14. " ASB686 ,Active Status Bit 686" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB685 ,Active Status Bit 685" "Not active,Active" bitfld.long 0x00 12. " ASB684 ,Active Status Bit 684" "Not active,Active" bitfld.long 0x00 11. " ASB683 ,Active Status Bit 683" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB682 ,Active Status Bit 682" "Not active,Active" bitfld.long 0x00 9. " ASB681 ,Active Status Bit 681" "Not active,Active" bitfld.long 0x00 8. " ASB680 ,Active Status Bit 680" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB679 ,Active Status Bit 679" "Not active,Active" bitfld.long 0x00 6. " ASB678 ,Active Status Bit 678" "Not active,Active" bitfld.long 0x00 5. " ASB677 ,Active Status Bit 677" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB676 ,Active Status Bit 676" "Not active,Active" bitfld.long 0x00 3. " ASB675 ,Active Status Bit 675" "Not active,Active" bitfld.long 0x00 2. " ASB674 ,Active Status Bit 674" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB673 ,Active Status Bit 673" "Not active,Active" bitfld.long 0x00 0. " ASB672 ,Active Status Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_ICDABR21,Active Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" bitfld.long 0x00 31. " ASB735 ,Active Status Bit 735" "Not active,Active" bitfld.long 0x00 30. " ASB734 ,Active Status Bit 734" "Not active,Active" bitfld.long 0x00 29. " ASB733 ,Active Status Bit 733" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB732 ,Active Status Bit 732" "Not active,Active" bitfld.long 0x00 27. " ASB731 ,Active Status Bit 731" "Not active,Active" bitfld.long 0x00 26. " ASB730 ,Active Status Bit 730" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB729 ,Active Status Bit 729" "Not active,Active" bitfld.long 0x00 24. " ASB728 ,Active Status Bit 728" "Not active,Active" bitfld.long 0x00 23. " ASB727 ,Active Status Bit 727" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB726 ,Active Status Bit 726" "Not active,Active" bitfld.long 0x00 21. " ASB725 ,Active Status Bit 725" "Not active,Active" bitfld.long 0x00 20. " ASB724 ,Active Status Bit 724" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB723 ,Active Status Bit 723" "Not active,Active" bitfld.long 0x00 18. " ASB722 ,Active Status Bit 722" "Not active,Active" bitfld.long 0x00 17. " ASB721 ,Active Status Bit 721" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB720 ,Active Status Bit 720" "Not active,Active" bitfld.long 0x00 15. " ASB719 ,Active Status Bit 719" "Not active,Active" bitfld.long 0x00 14. " ASB718 ,Active Status Bit 718" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB717 ,Active Status Bit 717" "Not active,Active" bitfld.long 0x00 12. " ASB716 ,Active Status Bit 716" "Not active,Active" bitfld.long 0x00 11. " ASB715 ,Active Status Bit 715" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB714 ,Active Status Bit 714" "Not active,Active" bitfld.long 0x00 9. " ASB713 ,Active Status Bit 713" "Not active,Active" bitfld.long 0x00 8. " ASB712 ,Active Status Bit 712" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB711 ,Active Status Bit 711" "Not active,Active" bitfld.long 0x00 6. " ASB710 ,Active Status Bit 710" "Not active,Active" bitfld.long 0x00 5. " ASB709 ,Active Status Bit 709" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB708 ,Active Status Bit 708" "Not active,Active" bitfld.long 0x00 3. " ASB707 ,Active Status Bit 707" "Not active,Active" bitfld.long 0x00 2. " ASB706 ,Active Status Bit 706" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB705 ,Active Status Bit 705" "Not active,Active" bitfld.long 0x00 0. " ASB704 ,Active Status Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_ICDABR22,Active Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x17) rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" bitfld.long 0x00 31. " ASB767 ,Active Status Bit 767" "Not active,Active" bitfld.long 0x00 30. " ASB766 ,Active Status Bit 766" "Not active,Active" bitfld.long 0x00 29. " ASB765 ,Active Status Bit 765" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB764 ,Active Status Bit 764" "Not active,Active" bitfld.long 0x00 27. " ASB763 ,Active Status Bit 763" "Not active,Active" bitfld.long 0x00 26. " ASB762 ,Active Status Bit 762" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB761 ,Active Status Bit 761" "Not active,Active" bitfld.long 0x00 24. " ASB760 ,Active Status Bit 760" "Not active,Active" bitfld.long 0x00 23. " ASB759 ,Active Status Bit 759" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB758 ,Active Status Bit 758" "Not active,Active" bitfld.long 0x00 21. " ASB757 ,Active Status Bit 757" "Not active,Active" bitfld.long 0x00 20. " ASB756 ,Active Status Bit 756" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB755 ,Active Status Bit 755" "Not active,Active" bitfld.long 0x00 18. " ASB754 ,Active Status Bit 754" "Not active,Active" bitfld.long 0x00 17. " ASB753 ,Active Status Bit 753" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB752 ,Active Status Bit 752" "Not active,Active" bitfld.long 0x00 15. " ASB751 ,Active Status Bit 751" "Not active,Active" bitfld.long 0x00 14. " ASB750 ,Active Status Bit 750" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB749 ,Active Status Bit 749" "Not active,Active" bitfld.long 0x00 12. " ASB748 ,Active Status Bit 748" "Not active,Active" bitfld.long 0x00 11. " ASB747 ,Active Status Bit 747" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB746 ,Active Status Bit 746" "Not active,Active" bitfld.long 0x00 9. " ASB745 ,Active Status Bit 745" "Not active,Active" bitfld.long 0x00 8. " ASB744 ,Active Status Bit 744" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB743 ,Active Status Bit 743" "Not active,Active" bitfld.long 0x00 6. " ASB742 ,Active Status Bit 742" "Not active,Active" bitfld.long 0x00 5. " ASB741 ,Active Status Bit 741" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB740 ,Active Status Bit 740" "Not active,Active" bitfld.long 0x00 3. " ASB739 ,Active Status Bit 739" "Not active,Active" bitfld.long 0x00 2. " ASB738 ,Active Status Bit 738" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB737 ,Active Status Bit 737" "Not active,Active" bitfld.long 0x00 0. " ASB736 ,Active Status Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_ICDABR23,Active Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x18) rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" bitfld.long 0x00 31. " ASB799 ,Active Status Bit 799" "Not active,Active" bitfld.long 0x00 30. " ASB798 ,Active Status Bit 798" "Not active,Active" bitfld.long 0x00 29. " ASB797 ,Active Status Bit 797" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB796 ,Active Status Bit 796" "Not active,Active" bitfld.long 0x00 27. " ASB795 ,Active Status Bit 795" "Not active,Active" bitfld.long 0x00 26. " ASB794 ,Active Status Bit 794" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB793 ,Active Status Bit 793" "Not active,Active" bitfld.long 0x00 24. " ASB792 ,Active Status Bit 792" "Not active,Active" bitfld.long 0x00 23. " ASB791 ,Active Status Bit 791" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB790 ,Active Status Bit 790" "Not active,Active" bitfld.long 0x00 21. " ASB789 ,Active Status Bit 789" "Not active,Active" bitfld.long 0x00 20. " ASB788 ,Active Status Bit 788" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB787 ,Active Status Bit 787" "Not active,Active" bitfld.long 0x00 18. " ASB786 ,Active Status Bit 786" "Not active,Active" bitfld.long 0x00 17. " ASB785 ,Active Status Bit 785" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB784 ,Active Status Bit 784" "Not active,Active" bitfld.long 0x00 15. " ASB783 ,Active Status Bit 783" "Not active,Active" bitfld.long 0x00 14. " ASB782 ,Active Status Bit 782" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB781 ,Active Status Bit 781" "Not active,Active" bitfld.long 0x00 12. " ASB780 ,Active Status Bit 780" "Not active,Active" bitfld.long 0x00 11. " ASB779 ,Active Status Bit 779" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB778 ,Active Status Bit 778" "Not active,Active" bitfld.long 0x00 9. " ASB777 ,Active Status Bit 777" "Not active,Active" bitfld.long 0x00 8. " ASB776 ,Active Status Bit 776" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB775 ,Active Status Bit 775" "Not active,Active" bitfld.long 0x00 6. " ASB774 ,Active Status Bit 774" "Not active,Active" bitfld.long 0x00 5. " ASB773 ,Active Status Bit 773" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB772 ,Active Status Bit 772" "Not active,Active" bitfld.long 0x00 3. " ASB771 ,Active Status Bit 771" "Not active,Active" bitfld.long 0x00 2. " ASB770 ,Active Status Bit 770" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB769 ,Active Status Bit 769" "Not active,Active" bitfld.long 0x00 0. " ASB768 ,Active Status Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_ICDABR24,Active Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" bitfld.long 0x00 31. " ASB831 ,Active Status Bit 831" "Not active,Active" bitfld.long 0x00 30. " ASB830 ,Active Status Bit 830" "Not active,Active" bitfld.long 0x00 29. " ASB829 ,Active Status Bit 829" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB828 ,Active Status Bit 828" "Not active,Active" bitfld.long 0x00 27. " ASB827 ,Active Status Bit 827" "Not active,Active" bitfld.long 0x00 26. " ASB826 ,Active Status Bit 826" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB825 ,Active Status Bit 825" "Not active,Active" bitfld.long 0x00 24. " ASB824 ,Active Status Bit 824" "Not active,Active" bitfld.long 0x00 23. " ASB823 ,Active Status Bit 823" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB822 ,Active Status Bit 822" "Not active,Active" bitfld.long 0x00 21. " ASB821 ,Active Status Bit 821" "Not active,Active" bitfld.long 0x00 20. " ASB820 ,Active Status Bit 820" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB819 ,Active Status Bit 819" "Not active,Active" bitfld.long 0x00 18. " ASB818 ,Active Status Bit 818" "Not active,Active" bitfld.long 0x00 17. " ASB817 ,Active Status Bit 817" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB816 ,Active Status Bit 816" "Not active,Active" bitfld.long 0x00 15. " ASB815 ,Active Status Bit 815" "Not active,Active" bitfld.long 0x00 14. " ASB814 ,Active Status Bit 814" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB813 ,Active Status Bit 813" "Not active,Active" bitfld.long 0x00 12. " ASB812 ,Active Status Bit 812" "Not active,Active" bitfld.long 0x00 11. " ASB811 ,Active Status Bit 811" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB810 ,Active Status Bit 810" "Not active,Active" bitfld.long 0x00 9. " ASB809 ,Active Status Bit 809" "Not active,Active" bitfld.long 0x00 8. " ASB808 ,Active Status Bit 808" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB807 ,Active Status Bit 807" "Not active,Active" bitfld.long 0x00 6. " ASB806 ,Active Status Bit 806" "Not active,Active" bitfld.long 0x00 5. " ASB805 ,Active Status Bit 805" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB804 ,Active Status Bit 804" "Not active,Active" bitfld.long 0x00 3. " ASB803 ,Active Status Bit 803" "Not active,Active" bitfld.long 0x00 2. " ASB802 ,Active Status Bit 802" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB801 ,Active Status Bit 801" "Not active,Active" bitfld.long 0x00 0. " ASB800 ,Active Status Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_ICDABR25,Active Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" bitfld.long 0x00 31. " ASB863 ,Active Status Bit 863" "Not active,Active" bitfld.long 0x00 30. " ASB862 ,Active Status Bit 862" "Not active,Active" bitfld.long 0x00 29. " ASB861 ,Active Status Bit 861" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB860 ,Active Status Bit 860" "Not active,Active" bitfld.long 0x00 27. " ASB859 ,Active Status Bit 859" "Not active,Active" bitfld.long 0x00 26. " ASB858 ,Active Status Bit 858" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB857 ,Active Status Bit 857" "Not active,Active" bitfld.long 0x00 24. " ASB856 ,Active Status Bit 856" "Not active,Active" bitfld.long 0x00 23. " ASB855 ,Active Status Bit 855" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB854 ,Active Status Bit 854" "Not active,Active" bitfld.long 0x00 21. " ASB853 ,Active Status Bit 853" "Not active,Active" bitfld.long 0x00 20. " ASB852 ,Active Status Bit 852" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB851 ,Active Status Bit 851" "Not active,Active" bitfld.long 0x00 18. " ASB850 ,Active Status Bit 850" "Not active,Active" bitfld.long 0x00 17. " ASB849 ,Active Status Bit 849" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB848 ,Active Status Bit 848" "Not active,Active" bitfld.long 0x00 15. " ASB847 ,Active Status Bit 847" "Not active,Active" bitfld.long 0x00 14. " ASB846 ,Active Status Bit 846" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB845 ,Active Status Bit 845" "Not active,Active" bitfld.long 0x00 12. " ASB844 ,Active Status Bit 844" "Not active,Active" bitfld.long 0x00 11. " ASB843 ,Active Status Bit 843" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB842 ,Active Status Bit 842" "Not active,Active" bitfld.long 0x00 9. " ASB841 ,Active Status Bit 841" "Not active,Active" bitfld.long 0x00 8. " ASB840 ,Active Status Bit 840" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB839 ,Active Status Bit 839" "Not active,Active" bitfld.long 0x00 6. " ASB838 ,Active Status Bit 838" "Not active,Active" bitfld.long 0x00 5. " ASB837 ,Active Status Bit 837" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB836 ,Active Status Bit 836" "Not active,Active" bitfld.long 0x00 3. " ASB835 ,Active Status Bit 835" "Not active,Active" bitfld.long 0x00 2. " ASB834 ,Active Status Bit 834" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB833 ,Active Status Bit 833" "Not active,Active" bitfld.long 0x00 0. " ASB832 ,Active Status Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_ICDABR26,Active Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" bitfld.long 0x00 31. " ASB895 ,Active Status Bit 895" "Not active,Active" bitfld.long 0x00 30. " ASB894 ,Active Status Bit 894" "Not active,Active" bitfld.long 0x00 29. " ASB893 ,Active Status Bit 893" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB892 ,Active Status Bit 892" "Not active,Active" bitfld.long 0x00 27. " ASB891 ,Active Status Bit 891" "Not active,Active" bitfld.long 0x00 26. " ASB890 ,Active Status Bit 890" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB889 ,Active Status Bit 889" "Not active,Active" bitfld.long 0x00 24. " ASB888 ,Active Status Bit 888" "Not active,Active" bitfld.long 0x00 23. " ASB887 ,Active Status Bit 887" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB886 ,Active Status Bit 886" "Not active,Active" bitfld.long 0x00 21. " ASB885 ,Active Status Bit 885" "Not active,Active" bitfld.long 0x00 20. " ASB884 ,Active Status Bit 884" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB883 ,Active Status Bit 883" "Not active,Active" bitfld.long 0x00 18. " ASB882 ,Active Status Bit 882" "Not active,Active" bitfld.long 0x00 17. " ASB881 ,Active Status Bit 881" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB880 ,Active Status Bit 880" "Not active,Active" bitfld.long 0x00 15. " ASB879 ,Active Status Bit 879" "Not active,Active" bitfld.long 0x00 14. " ASB878 ,Active Status Bit 878" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB877 ,Active Status Bit 877" "Not active,Active" bitfld.long 0x00 12. " ASB876 ,Active Status Bit 876" "Not active,Active" bitfld.long 0x00 11. " ASB875 ,Active Status Bit 875" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB874 ,Active Status Bit 874" "Not active,Active" bitfld.long 0x00 9. " ASB873 ,Active Status Bit 873" "Not active,Active" bitfld.long 0x00 8. " ASB872 ,Active Status Bit 872" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB871 ,Active Status Bit 871" "Not active,Active" bitfld.long 0x00 6. " ASB870 ,Active Status Bit 870" "Not active,Active" bitfld.long 0x00 5. " ASB869 ,Active Status Bit 869" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB868 ,Active Status Bit 868" "Not active,Active" bitfld.long 0x00 3. " ASB867 ,Active Status Bit 867" "Not active,Active" bitfld.long 0x00 2. " ASB866 ,Active Status Bit 866" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB865 ,Active Status Bit 865" "Not active,Active" bitfld.long 0x00 0. " ASB864 ,Active Status Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_ICDABR27,Active Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" bitfld.long 0x00 31. " ASB927 ,Active Status Bit 927" "Not active,Active" bitfld.long 0x00 30. " ASB926 ,Active Status Bit 926" "Not active,Active" bitfld.long 0x00 29. " ASB925 ,Active Status Bit 925" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB924 ,Active Status Bit 924" "Not active,Active" bitfld.long 0x00 27. " ASB923 ,Active Status Bit 923" "Not active,Active" bitfld.long 0x00 26. " ASB922 ,Active Status Bit 922" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB921 ,Active Status Bit 921" "Not active,Active" bitfld.long 0x00 24. " ASB920 ,Active Status Bit 920" "Not active,Active" bitfld.long 0x00 23. " ASB919 ,Active Status Bit 919" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB918 ,Active Status Bit 918" "Not active,Active" bitfld.long 0x00 21. " ASB917 ,Active Status Bit 917" "Not active,Active" bitfld.long 0x00 20. " ASB916 ,Active Status Bit 916" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB915 ,Active Status Bit 915" "Not active,Active" bitfld.long 0x00 18. " ASB914 ,Active Status Bit 914" "Not active,Active" bitfld.long 0x00 17. " ASB913 ,Active Status Bit 913" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB912 ,Active Status Bit 912" "Not active,Active" bitfld.long 0x00 15. " ASB911 ,Active Status Bit 911" "Not active,Active" bitfld.long 0x00 14. " ASB910 ,Active Status Bit 910" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB909 ,Active Status Bit 909" "Not active,Active" bitfld.long 0x00 12. " ASB908 ,Active Status Bit 908" "Not active,Active" bitfld.long 0x00 11. " ASB907 ,Active Status Bit 907" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB906 ,Active Status Bit 906" "Not active,Active" bitfld.long 0x00 9. " ASB905 ,Active Status Bit 905" "Not active,Active" bitfld.long 0x00 8. " ASB904 ,Active Status Bit 904" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB903 ,Active Status Bit 903" "Not active,Active" bitfld.long 0x00 6. " ASB902 ,Active Status Bit 902" "Not active,Active" bitfld.long 0x00 5. " ASB901 ,Active Status Bit 901" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB900 ,Active Status Bit 900" "Not active,Active" bitfld.long 0x00 3. " ASB899 ,Active Status Bit 899" "Not active,Active" bitfld.long 0x00 2. " ASB898 ,Active Status Bit 898" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB897 ,Active Status Bit 897" "Not active,Active" bitfld.long 0x00 0. " ASB896 ,Active Status Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_ICDABR28,Active Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" bitfld.long 0x00 31. " ASB959 ,Active Status Bit 959" "Not active,Active" bitfld.long 0x00 30. " ASB958 ,Active Status Bit 958" "Not active,Active" bitfld.long 0x00 29. " ASB957 ,Active Status Bit 957" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB956 ,Active Status Bit 956" "Not active,Active" bitfld.long 0x00 27. " ASB955 ,Active Status Bit 955" "Not active,Active" bitfld.long 0x00 26. " ASB954 ,Active Status Bit 954" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB953 ,Active Status Bit 953" "Not active,Active" bitfld.long 0x00 24. " ASB952 ,Active Status Bit 952" "Not active,Active" bitfld.long 0x00 23. " ASB951 ,Active Status Bit 951" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB950 ,Active Status Bit 950" "Not active,Active" bitfld.long 0x00 21. " ASB949 ,Active Status Bit 949" "Not active,Active" bitfld.long 0x00 20. " ASB948 ,Active Status Bit 948" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB947 ,Active Status Bit 947" "Not active,Active" bitfld.long 0x00 18. " ASB946 ,Active Status Bit 946" "Not active,Active" bitfld.long 0x00 17. " ASB945 ,Active Status Bit 945" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB944 ,Active Status Bit 944" "Not active,Active" bitfld.long 0x00 15. " ASB943 ,Active Status Bit 943" "Not active,Active" bitfld.long 0x00 14. " ASB942 ,Active Status Bit 942" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB941 ,Active Status Bit 941" "Not active,Active" bitfld.long 0x00 12. " ASB940 ,Active Status Bit 940" "Not active,Active" bitfld.long 0x00 11. " ASB939 ,Active Status Bit 939" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB938 ,Active Status Bit 938" "Not active,Active" bitfld.long 0x00 9. " ASB937 ,Active Status Bit 937" "Not active,Active" bitfld.long 0x00 8. " ASB936 ,Active Status Bit 936" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB935 ,Active Status Bit 935" "Not active,Active" bitfld.long 0x00 6. " ASB934 ,Active Status Bit 934" "Not active,Active" bitfld.long 0x00 5. " ASB933 ,Active Status Bit 933" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB932 ,Active Status Bit 932" "Not active,Active" bitfld.long 0x00 3. " ASB931 ,Active Status Bit 931" "Not active,Active" bitfld.long 0x00 2. " ASB930 ,Active Status Bit 930" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB929 ,Active Status Bit 929" "Not active,Active" bitfld.long 0x00 0. " ASB928 ,Active Status Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_ICDABR29,Active Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" bitfld.long 0x00 31. " ASB991 ,Active Status Bit 991" "Not active,Active" bitfld.long 0x00 30. " ASB990 ,Active Status Bit 990" "Not active,Active" bitfld.long 0x00 29. " ASB989 ,Active Status Bit 989" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB988 ,Active Status Bit 988" "Not active,Active" bitfld.long 0x00 27. " ASB987 ,Active Status Bit 987" "Not active,Active" bitfld.long 0x00 26. " ASB986 ,Active Status Bit 986" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB985 ,Active Status Bit 985" "Not active,Active" bitfld.long 0x00 24. " ASB984 ,Active Status Bit 984" "Not active,Active" bitfld.long 0x00 23. " ASB983 ,Active Status Bit 983" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB982 ,Active Status Bit 982" "Not active,Active" bitfld.long 0x00 21. " ASB981 ,Active Status Bit 981" "Not active,Active" bitfld.long 0x00 20. " ASB980 ,Active Status Bit 980" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB979 ,Active Status Bit 979" "Not active,Active" bitfld.long 0x00 18. " ASB978 ,Active Status Bit 978" "Not active,Active" bitfld.long 0x00 17. " ASB977 ,Active Status Bit 977" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB976 ,Active Status Bit 976" "Not active,Active" bitfld.long 0x00 15. " ASB975 ,Active Status Bit 975" "Not active,Active" bitfld.long 0x00 14. " ASB974 ,Active Status Bit 974" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB973 ,Active Status Bit 973" "Not active,Active" bitfld.long 0x00 12. " ASB972 ,Active Status Bit 972" "Not active,Active" bitfld.long 0x00 11. " ASB971 ,Active Status Bit 971" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB970 ,Active Status Bit 970" "Not active,Active" bitfld.long 0x00 9. " ASB969 ,Active Status Bit 969" "Not active,Active" bitfld.long 0x00 8. " ASB968 ,Active Status Bit 968" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB967 ,Active Status Bit 967" "Not active,Active" bitfld.long 0x00 6. " ASB966 ,Active Status Bit 966" "Not active,Active" bitfld.long 0x00 5. " ASB965 ,Active Status Bit 965" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB964 ,Active Status Bit 964" "Not active,Active" bitfld.long 0x00 3. " ASB963 ,Active Status Bit 963" "Not active,Active" bitfld.long 0x00 2. " ASB962 ,Active Status Bit 962" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB961 ,Active Status Bit 961" "Not active,Active" bitfld.long 0x00 0. " ASB960 ,Active Status Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_ICDABR30,Active Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)==0x1F) rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active" bitfld.long 0x00 26. " ASB1018 ,Active Status Bit 1018" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active" bitfld.long 0x00 24. " ASB1016 ,Active Status Bit 1016" "Not active,Active" bitfld.long 0x00 23. " ASB1015 ,Active Status Bit 1015" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active" bitfld.long 0x00 21. " ASB1013 ,Active Status Bit 1013" "Not active,Active" bitfld.long 0x00 20. " ASB1012 ,Active Status Bit 1012" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active" bitfld.long 0x00 18. " ASB1010 ,Active Status Bit 1010" "Not active,Active" bitfld.long 0x00 17. " ASB1009 ,Active Status Bit 1009" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active" bitfld.long 0x00 15. " ASB1007 ,Active Status Bit 1007" "Not active,Active" bitfld.long 0x00 14. " ASB1006 ,Active Status Bit 1006" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active" bitfld.long 0x00 12. " ASB1004 ,Active Status Bit 1004" "Not active,Active" bitfld.long 0x00 11. " ASB1003 ,Active Status Bit 1003" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active" bitfld.long 0x00 9. " ASB1001 ,Active Status Bit 1001" "Not active,Active" bitfld.long 0x00 8. " ASB1000 ,Active Status Bit 1000" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB999 ,Active Status Bit 999" "Not active,Active" bitfld.long 0x00 6. " ASB998 ,Active Status Bit 998" "Not active,Active" bitfld.long 0x00 5. " ASB997 ,Active Status Bit 997" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB996 ,Active Status Bit 996" "Not active,Active" bitfld.long 0x00 3. " ASB995 ,Active Status Bit 995" "Not active,Active" bitfld.long 0x00 2. " ASB994 ,Active Status Bit 994" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB993 ,Active Status Bit 993" "Not active,Active" bitfld.long 0x00 0. " ASB992 ,Active Status Bit 992" "Not active,Active" else hgroup.long 0x037C++0x03 hide.long 0x0 "GICD_ICDABR31,Active Status Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 20. tree "Priority Registers" group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1F) group.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 " group.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 " group.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000" group.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004" group.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008" group.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012" group.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016" else hgroup.long 0x7E0++0x03 hide.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hgroup.long 0x7E4++0x03 hide.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hgroup.long 0x7E8++0x03 hide.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hgroup.long 0x7EC++0x03 hide.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hgroup.long 0x7F0++0x03 hide.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hgroup.long 0x7F4++0x03 hide.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hgroup.long 0x7F8++0x03 hide.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" endif tree.end width 19. tree "Processor Targets Registers" if (((d.l(AD:0xa01000+0x04))&0x000000E0)>0x1) rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 " if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1F) group.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 " group.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 " group.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000" group.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004" group.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008" group.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012" group.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016" else hgroup.long 0xBE0++0x03 hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hgroup.long 0xBE4++0x03 hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hgroup.long 0xBE8++0x03 hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hgroup.long 0xBEC++0x03 hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hgroup.long 0xBF0++0x03 hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hgroup.long 0xBF4++0x03 hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hgroup.long 0xBF8++0x03 hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hgroup.long 0xBE0++0x03 hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hgroup.long 0xBE4++0x03 hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hgroup.long 0xBE8++0x03 hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hgroup.long 0xBEC++0x03 hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hgroup.long 0xBF0++0x03 hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hgroup.long 0xBF4++0x03 hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hgroup.long 0xBF8++0x03 hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif tree.end width 14. tree "Configuration Registers" hgroup.long 0xC00++0x03 hide.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" textline " " rgroup.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1F) group.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCF8++0x03 hide.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" hgroup.long 0xCFC++0x03 hide.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" endif tree.end width 12. tree "Peripheral Interrupt Status Registers" rgroup.long 0x0D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI_C[15] ,Returns the status of the ppi_c[15] inputs on the Distributor" "Low,High" bitfld.long 0x00 14. " PPI_C[14] ,Returns the status of the ppi_c[14] inputs on the Distributor" "Low,High" bitfld.long 0x00 13. " PPI_C[13] ,Returns the status of the ppi_c[13] inputs on the Distributor" "Low,High" bitfld.long 0x00 12. " PPI_C[12] ,Returns the status of the ppi_c[12] inputs on the Distributor" "Low,High" textline " " bitfld.long 0x00 11. " PPI_C[11] ,Returns the status of the ppi_c[11] inputs on the Distributor" "Low,High" bitfld.long 0x00 10. " PPI_C[10] ,Returns the status of the ppi_c[10] inputs on the Distributor" "Low,High" bitfld.long 0x00 9. " PPI_C[9] ,Returns the status of the ppi_c[9] inputs on the Distributor" "Low,High" bitfld.long 0x00 8. " PPI_C[8] ,Returns the status of the ppi_c[8] inputs on the Distributor" "Low,High" textline " " bitfld.long 0x00 7. " PPI_C[7] ,Returns the status of the ppi_c[7] inputs on the Distributor" "Low,High" bitfld.long 0x00 6. " PPI_C[6] ,Returns the status of the ppi_c[6] inputs on the Distributor" "Low,High" bitfld.long 0x00 5. " PPI_C[5] ,Returns the status of the ppi_c[5] inputs on the Distributor" "Low,High" bitfld.long 0x00 4. " PPI_C[4] ,Returns the status of the ppi_c[4] inputs on the Distributor" "Low,High" textline " " bitfld.long 0x00 3. " PPI_C[3] ,Returns the status of the ppi_c[3] inputs on the Distributor" "Low,High" bitfld.long 0x00 2. " PPI_C[2] ,Returns the status of the ppi_c[2] inputs on the Distributor" "Low,High" bitfld.long 0x00 1. " PPI_C[1] ,Returns the status of the ppi_c[1] inputs on the Distributor" "Low,High" bitfld.long 0x00 0. " PPI_C[0] ,Returns the status of the ppi_c[0] inputs on the Distributor" "Low,High" textline " " width 22. if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High" bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High" bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High" textline " " bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High" bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High" bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High" textline " " bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High" bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High" bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High" textline " " bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High" bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High" bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High" textline " " bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High" bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High" bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High" textline " " bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High" bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High" bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High" textline " " bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High" bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High" bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High" textline " " bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High" bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High" bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High" textline " " bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High" bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High" bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High" textline " " bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High" bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High" bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High" textline " " bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High" bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High" bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High" bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High" bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High" bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High" bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High" bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High" bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High" bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High" bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High" bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High" bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High" bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High" bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High" bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High" bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High" bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High" bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High" bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High" bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High" bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High" bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x03) rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High" bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High" bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High" bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High" bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High" bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High" bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High" bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High" bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High" bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High" bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High" bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High" bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High" bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High" bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High" bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High" bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High" bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High" bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High" bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High" bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High" bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High" bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High" bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High" bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High" bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High" bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High" bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High" bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High" bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High" bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High" bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High" bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High" bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High" bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High" bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High" bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High" bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High" bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High" bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High" bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High" bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High" bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High" bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High" bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High" bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High" bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High" bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High" bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High" bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High" bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High" bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High" bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High" bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High" bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High" bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High" bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High" bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High" bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High" bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High" bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High" bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High" bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High" bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High" bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High" bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High" bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High" bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High" bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High" bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High" bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High" bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High" bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High" bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High" bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High" bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High" bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High" bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High" bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High" bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High" bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High" bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High" bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High" bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High" bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x07) rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High" bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High" bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High" bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High" bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High" bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High" bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High" bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High" bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High" bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High" bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High" bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High" bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High" bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High" bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High" bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High" bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High" bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High" bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High" bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High" bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High" bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High" bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High" bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High" bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High" bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High" bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High" bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High" bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High" bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High" bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High" bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High" bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High" bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High" bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High" bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High" bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High" bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High" bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High" bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High" bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High" bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High" bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High" bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High" bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High" bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High" bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High" bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High" bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High" bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High" bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High" bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High" bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High" bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High" bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High" bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High" bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High" bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High" bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High" bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High" bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High" bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High" bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High" bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High" bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High" bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High" bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High" bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High" bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High" bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High" bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High" bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High" bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High" bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High" bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High" bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High" bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High" bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High" bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High" bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High" bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High" bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High" bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High" bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High" bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High" bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High" bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High" bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High" bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High" bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High" bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High" bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High" bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High" bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High" bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High" bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High" bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High" bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High" bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High" bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High" bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High" bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High" bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High" bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High" bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High" bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High" bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High" bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High" bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High" bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High" bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High" bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High" bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High" bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High" bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High" bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High" bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High" bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High" bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High" bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High" bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High" bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High" bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High" bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High" bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High" bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High" bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High" bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High" bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High" bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High" bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High" bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High" bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High" bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High" bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High" bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High" bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High" bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High" bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High" bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High" bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High" bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High" bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High" bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High" bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High" bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High" bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High" bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High" bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High" bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High" bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High" bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High" bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High" bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High" bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High" bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High" bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High" bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High" bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High" bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High" bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High" bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High" bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High" bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High" bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High" bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High" bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High" bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High" bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High" bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High" bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High" bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High" bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High" bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High" bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High" bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High" bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High" bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High" bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High" bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High" bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High" bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High" bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High" bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High" bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High" bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High" bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High" bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High" bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High" bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High" bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High" bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High" bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High" bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High" bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High" bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High" bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High" bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High" bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High" bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High" bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High" bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High" bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High" bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High" bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High" bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High" bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High" bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High" bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High" bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High" bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High" bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High" bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High" bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High" bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High" bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High" bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High" bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High" bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High" bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High" bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High" bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High" bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High" bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High" bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High" bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High" bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High" bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High" bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High" bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High" bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High" bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High" bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High" bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High" bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High" bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High" bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High" bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High" bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High" bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High" bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High" bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High" bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High" bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High" bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High" bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High" bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High" bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High" bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High" bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High" bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High" bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High" bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x13) rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High" bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High" bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High" bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High" bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High" bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High" bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High" bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High" bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High" bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High" bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High" bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High" bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High" bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High" bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High" bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High" bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High" bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High" bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High" bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High" bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High" bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High" bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High" bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High" bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High" bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High" bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High" bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High" bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High" bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High" bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High" bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High" bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High" bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High" bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High" bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High" bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High" bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High" bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High" bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High" bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High" bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High" bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High" bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High" bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High" bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High" bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High" bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High" bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High" bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High" bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High" bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High" bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High" bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High" bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High" bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High" bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High" bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High" bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High" bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High" bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High" bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High" bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High" bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High" bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High" bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High" bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High" bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High" bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High" bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High" bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High" bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High" bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High" bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High" bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High" bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High" bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High" bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High" bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High" bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High" bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High" bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High" bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High" bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High" bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x17) rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High" bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High" bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High" bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High" bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High" bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High" bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High" bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High" bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High" bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High" bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High" bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High" bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High" bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High" bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High" bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High" bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High" bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High" bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High" bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High" bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High" bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x18) rgroup.long 0x060++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High" bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High" bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High" bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High" bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High" bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High" bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High" bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High" bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High" bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High" bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High" bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High" bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High" bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High" bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High" bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High" bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High" bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High" bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High" bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High" bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High" bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High" bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High" bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High" bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High" bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High" bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High" bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High" bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High" bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High" bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High" bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High" bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High" bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High" bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High" bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High" bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High" bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High" bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High" bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High" bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High" bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High" bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High" bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High" bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High" bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High" bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High" bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High" bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High" bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High" bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High" bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High" bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High" bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High" bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High" bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High" bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High" bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High" bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High" bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High" bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High" bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High" bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High" bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High" bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High" bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High" bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High" bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High" bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High" bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High" bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High" bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High" bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High" bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High" bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High" bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High" bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High" bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High" bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High" bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High" bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High" bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High" bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High" bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High" bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High" bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High" bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High" bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High" bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High" bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High" bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High" bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High" bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High" bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High" bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High" bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High" bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High" bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High" bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High" bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High" bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High" bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High" bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High" bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High" bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High" bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High" bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High" bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High" bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High" bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High" bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High" bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High" bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High" bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High" bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High" bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High" bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High" bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High" bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High" bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High" bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High" bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High" bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High" bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High" bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High" bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High" bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High" bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High" bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High" bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High" bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High" bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High" bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High" bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High" bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High" bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High" bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High" bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High" bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High" bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High" bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High" bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High" bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High" bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High" bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High" bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High" bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High" bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0xa01000+0x04))&0x0000001F)>=0x1F) rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High" bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High" bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High" bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High" bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High" bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High" bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High" bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High" bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High" bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High" bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High" bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High" bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High" bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High" bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High" bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High" bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High" bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High" bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High" else hgroup.long 0x0D7C++0x03 hide.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 25. tree "Software Generated Interrupt" if (((d.l(AD:0xa01000+0x04))&0x400)==0x400) wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.byte 0x0FE0++0x00 line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.byte 0x00 0.--7. 1. " PART_NUMBER_0 ,Returns 0x90" rgroup.byte 0x0FE4++0x00 line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.byte 0x00 4.--7. " JEP106_ID_3_0 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PART_NUMBER_1 ,Returns 0x3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FE8++0x00 line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.byte 0x00 4.--7. " ARCHITECTURE ,Identifies the architecture version of the GIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 3. " JEDEC_USED ,This indicates that the GIC uses a manufacturers identity code that was allocated by JEDEC according to JEP106" "Low,High" bitfld.byte 0x00 0.--2. " JEP106_ID_CODE ,JEP106 identity code field" "0,1,2,3,4,5,6,7" rgroup.byte 0x0FEC++0x00 line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.byte 0x00 4.--7. " REVAND ,The top-level RTL provides four AND gates that are tied-off to provide an output value of 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " MOD_NUMBER ,The customer can update this field if they modify the RTL of the GIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD0++0x00 line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.byte 0x00 4.--7. " 4KB_COUNT ,The number of 4KB address blocks you require to access the registers expressed in powers of 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " JEP106_C_CODE ,The JEP106 continuation code value represents how many 0x7F continuation characters occur in the manufacturers identity code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD4++0x00 line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register" bitfld.byte 0x00 5.--7. " PPI_NUMBER_0 ,The LSBs of the number of PPIs that the GIC provides" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--4. " SGI_NUMBER ,The number of SGIs that the GIC provides" "None,INTID0,INTID[1:0],INTID[2:0],INTID[3:0],INTID[4:0],INTID[5:0],INTID[6:0],INTID[7:0],INTID[8:0],INTID[9:0],INTID[10:0],INTID[11:0],INTID[12:0],INTID[13:0],INTID[14:0],INTID[15:0],?..." rgroup.byte 0x0FD8++0x00 line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register" bitfld.byte 0x00 2.--7. " SPI_NUMBER_0 ,The LSBs of the number of SPIs that the GIC provides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.byte 0x00 0.--1. " PPI_NUMBER_1 ,The MSBs of the number of PPIs that the GIC provides" "0,1,2,3" rgroup.byte 0x0FDC++0x00 line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register" bitfld.byte 0x00 7. " TZ ,Identifies the number of security states that the GIC supports" "S,NS&S" bitfld.byte 0x00 4.--6. " PRIORITY ,The number of priority levels that the GIC provides" "16,32,64,128,256,?..." bitfld.byte 0x00 0.--3. " SPI_NUMBER_1 ,The MSBs of the number of SPIs that the GIC provides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FC0++0x00 line.byte 0x00 "GICD_PIDR8,Peripheral ID8 Register" bitfld.byte 0x00 7. " IDENTIFIER ,Identifies the AMBA interface that this register belongs to" "Distributor,CPU Interface" bitfld.byte 0x00 5.--6. " IF_TYPE ,Identifies the AMBA protocol that the GIC supports" "AXI,AHB-Lite,?..." bitfld.byte 0x00 2.--4. " CPU_IF ,Identifies the number of CPU Interfaces that the GIC contains" "1,2,3,4,5,6,7,8" textline " " bitfld.byte 0x00 1. " FIQ_LEGACY ,Identifies if the GIC provides a legacy FIQ input signal for each CPU Interface" "Not supported,Supported" bitfld.byte 0x00 0. " IRQ_LEGACY ,Identifies if the GIC provides a legacy IRQ input signal for each CPU Interface" "Not supported,Supported" tree.end tree.end base AD:0xa00100 width 17. tree "CPU Interface" if (((d.l(AD:0xa01000+0x04))&0x400)==0x0) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 0. " ENABLE ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " textline " " else group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)" bitfld.long 0x00 0. " ENABLE ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " textline " " endif group.long 0x0004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" if (((d.l(AD:0xa01000+0x04))&0x400)==0x400) group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif hgroup.long 0x000C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" if (((d.l(AD:0xa01000+0x04))&0x400)==0x400) group.long 0x001C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else hgroup.long 0x001C++0x03 hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register" endif rgroup.long 0x00FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" tree.end width 0x0B tree.end tree.end else tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif config 16. 8. tree.open "ADC (Analog-to-Digital Converter)" tree "ADC 1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02280000 width 11. group.long 0x00++0x07 line.long 0x00 "ADC1_HC0,Control register for hardware trigger 0" bitfld.long 0x00 7. " AIEN ,Conversion Complete Interrupt Enable/Disable Control" "Disabled,Enabled" bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "Ext_Ch_0,Ext_Ch_1,Ext_Ch_2,Ext_Ch_3,Ext_Ch_4,Ext_Ch_5,Ext_Ch_6,Ext_Ch_7,Ext_Ch_8,Ext_Ch_9,Ext_Ch_10,Ext_Ch_11,Ext_Ch_12,Ext_Ch_13,Ext_Ch_14,Ext_Ch_15,Ext_Sat_0,Ext_Sat_1,Ext_Sat_2,Ext_Sat_3,Ext_Sat_4,Ext_Sat_5,Ext_Sat_6,Ext_Sat_7,,VREFSH,,,,,,Disabled" line.long 0x04 "ADC1_HC1,Control register for hardware trigger 1" bitfld.long 0x04 7. " AIEN ,Conversion Complete Interrupt Enable/Disable Control" "Disabled,Enabled" bitfld.long 0x04 0.--4. " ADCH ,Input Channel Select" "Ext_Ch_0,Ext_Ch_1,Ext_Ch_2,Ext_Ch_3,Ext_Ch_4,Ext_Ch_5,Ext_Ch_6,Ext_Ch_7,Ext_Ch_8,Ext_Ch_9,Ext_Ch_10,Ext_Ch_11,Ext_Ch_12,Ext_Ch_13,Ext_Ch_14,Ext_Ch_15,Ext_Sat_0,Ext_Sat_1,Ext_Sat_2,Ext_Sat_3,Ext_Sat_4,Ext_Sat_5,Ext_Sat_6,Ext_Sat_7,,VREFSH,,,,,,Disabled" rgroup.long 0x08++0x03 line.long 0x00 "ADC1_HS,Status register for HW triggers" bitfld.long 0x00 1. " COCO1 ,HC1 Conversion Complete Flag" "Not completed,Completed" bitfld.long 0x00 0. " COCO0 ,HC0 Conversion Complete Flag" "Not completed,Completed" if (((per.l(ad:0x02280000+0x14))&0x0C)==0x00) group.long 0x0C++0x07 line.long 0x00 "ADC1_R0,Data result register for HW trigger 0" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC1_R1,Data result register for HW trigger 1" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Result of ADC conversion" elif (((per.l(ad:0x02280000+0x14))&0x0C)==0x04) group.long 0x0C++0x07 line.long 0x00 "ADC1_R0,Data result register for HW trigger 0" hexmask.long.word 0x00 0.--9. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC1_R1,Data result register for HW trigger 1" hexmask.long.word 0x04 0.--9. 1. " DATA ,Result of ADC conversion" elif (((per.l(ad:0x02280000+0x14))&0x0C)==0x08) group.long 0x0C++0x07 line.long 0x00 "ADC1_R0,Data result register for HW trigger 0" hexmask.long.word 0x00 0.--11. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC1_R1,Data result register for HW trigger 1" hexmask.long.word 0x04 0.--11. 1. " DATA ,Result of ADC conversion" else hgroup.long 0x0C++0x07 hide.long 0x00 "ADC1_R0,Data result register for HW trigger 0" hide.long 0x04 "ADC1_R1,Data result register for HW trigger 1" endif if ((per.l(ad:0x02280000+0x14)&0x10)==0x00000010) group.long 0x14++0x03 line.long 0x00 "ADC1_CFG,Configuration register" bitfld.long 0x00 16. " OVWREN ,Data Overwrite Enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " AVGS ,Amount of ADC conversions that will be averaged to create the ADC average result" "4 samples,8 samples,16 samples,32 samples" bitfld.long 0x00 13. " ADTRG ,Conversion Trigger Select" "Software,Hardware" textline " " bitfld.long 0x00 11.--12. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,,," bitfld.long 0x00 10. " ADHSC ,High Speed Configuration" "Normal,High speed" bitfld.long 0x00 8.--9. " ADSTS ,Sample time duration" "12,16,20,24" textline " " bitfld.long 0x00 7. " ADLPC ,Low-Power Configuration" "Not Low-Power,Low-Power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divider Select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long" textline " " bitfld.long 0x00 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit," bitfld.long 0x00 0.--1. " ADICLK ,Input clock source to generate the internal clock ADCK" "IPG,IPG/2,ALTCLK,ADACK" else group.long 0x14++0x03 line.long 0x00 "ADC1_CFG,Configuration register" bitfld.long 0x00 16. " OVWREN ,Data Overwrite Enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " AVGS ,Amount of ADC conversions that will be averaged to create the ADC average result." "4 samples,8 samples,16 samples,32 samples" bitfld.long 0x00 13. " ADTRG ,Conversion Trigger Select" "Software,Hardware" textline " " bitfld.long 0x00 11.--12. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,,," bitfld.long 0x00 10. " ADHSC ,High Speed Configuration" "Normal,High speed" bitfld.long 0x00 8.--9. " ADSTS ,Sample time duration" "2,4,6,8" textline " " bitfld.long 0x00 7. " ADLPC ,Low-Power Configuration" "Not Low-Power,Low-Power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divider Select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long" textline " " bitfld.long 0x00 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit," bitfld.long 0x00 0.--1. " ADICLK ,Input clock source to generate the internal clock ADCK" "IPG,IPG/2,ALTCLK,ADACK" endif textline " " if (((per.l(ad:0x02280000+0x18))&0x00000010)==0x00000010) group.long 0x18++0x03 line.long 0x00 "ADC1_GC,General control register" bitfld.long 0x00 7. " CAL ,Calibration sequence" "Completed/Not started,In progress" bitfld.long 0x00 6. " ADCO ,Continuous Conversion Enable" "Single,Continuous" bitfld.long 0x00 5. " AVGE ,Hardware average function of the ADC" "Disabled,Enabled" bitfld.long 0x00 4. " ACFE ,Compare Function Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ACFGT ,Compare Function Greater Than Enable" "Less/Not Inclusive,Greater or equal/Inclusive" bitfld.long 0x00 2. " ACREN ,Compare Function Range Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DMAEN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "ADC1_GC,General control register" bitfld.long 0x00 7. " CAL ,Calibration sequence" "Completed/Not started,In progress" bitfld.long 0x00 6. " ADCO ,Continuous Conversion Enable" "Single,Continuous" bitfld.long 0x00 5. " AVGE ,Hardware average function of the ADC" "Disabled,Enabled" bitfld.long 0x00 4. " ACFE ,Compare Function Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ACREN ,Compare Function Range Enable" "Unaffected,Unaffected" bitfld.long 0x00 1. " DMAEN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" endif group.long 0x1C++0x03 line.long 0x00 "ADC1_GS,General status register" eventfld.long 0x00 2. " AWKST ,Asynchronous wakeup interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 1. " CALF ,Calibration Failed Flag" "Completed,Failed" rbitfld.long 0x00 0. " ADACT ,Conversion Active" "Not in progress,In progress" if ((((per.l(ad:0x02280000+0x18))&0x10)==0x10)&&(((per.l(ad:0x02280000+0x14))&0x0C)==0x00)) group.long 0x20++0x03 line.long 0x00 "ADC1_CV,Compare value register" hexmask.long.byte 0x00 16.--23. 1. " CV2 ,Compare Value 2" hexmask.long.byte 0x00 0.--7. 1. " CV1 ,Compare Value 1" elif ((((per.l(ad:0x02280000+0x18))&0x10)==0x10)&&(((per.l(ad:0x02280000+0x14))&0x0C)==0x04)) group.long 0x20++0x03 line.long 0x00 "ADC1_CV,Compare value register" hexmask.long.word 0x00 16.--25. 1. " CV2 ,Compare Value 2" hexmask.long.word 0x00 0.--9. 1. " CV1 ,Compare Value 1" elif ((((per.l(ad:0x02280000+0x18))&0x10)==0x10)&&(((per.l(ad:0x02280000+0x14))&0x0C)==0x08)) group.long 0x20++0x03 line.long 0x00 "ADC1_CV,Compare value register" hexmask.long.word 0x00 16.--27. 1. " CV2 ,Compare Value 2" hexmask.long.word 0x00 0.--11. 1. " CV1 ,Compare Value 1" else hgroup.long 0x20++0x03 hide.long 0x00 "ADC1_CV,Compare value register" endif group.long 0x24++0x07 line.long 0x00 "ADC1_OFS,Offset correction value register" bitfld.long 0x00 12. " OFFSET ,Sign bit" "+,-" hexmask.long.word 0x00 0.--11. 1. ",Offset value" line.long 0x04 "ADC1_CAL,Calibration value register" bitfld.long 0x04 0.--3. " CAL_CODE ,Calibration Result Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0xB else base ad:0x42280000 width 11. group.long 0x00++0x07 line.long 0x00 "ADC1_HC0,Control register for hardware trigger 0" bitfld.long 0x00 7. " AIEN ,Conversion Complete Interrupt Enable/Disable Control" "Disabled,Enabled" bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "Ext_Ch_0,Ext_Ch_1,Ext_Ch_2,Ext_Ch_3,Ext_Ch_4,Ext_Ch_5,Ext_Ch_6,Ext_Ch_7,Ext_Ch_8,Ext_Ch_9,Ext_Ch_10,Ext_Ch_11,Ext_Ch_12,Ext_Ch_13,Ext_Ch_14,Ext_Ch_15,Ext_Sat_0,Ext_Sat_1,Ext_Sat_2,Ext_Sat_3,Ext_Sat_4,Ext_Sat_5,Ext_Sat_6,Ext_Sat_7,,VREFSH,,,,,,Disabled" line.long 0x04 "ADC1_HC1,Control register for hardware trigger 1" bitfld.long 0x04 7. " AIEN ,Conversion Complete Interrupt Enable/Disable Control" "Disabled,Enabled" bitfld.long 0x04 0.--4. " ADCH ,Input Channel Select" "Ext_Ch_0,Ext_Ch_1,Ext_Ch_2,Ext_Ch_3,Ext_Ch_4,Ext_Ch_5,Ext_Ch_6,Ext_Ch_7,Ext_Ch_8,Ext_Ch_9,Ext_Ch_10,Ext_Ch_11,Ext_Ch_12,Ext_Ch_13,Ext_Ch_14,Ext_Ch_15,Ext_Sat_0,Ext_Sat_1,Ext_Sat_2,Ext_Sat_3,Ext_Sat_4,Ext_Sat_5,Ext_Sat_6,Ext_Sat_7,,VREFSH,,,,,,Disabled" rgroup.long 0x08++0x03 line.long 0x00 "ADC1_HS,Status register for HW triggers" bitfld.long 0x00 1. " COCO1 ,HC1 Conversion Complete Flag" "Not completed,Completed" bitfld.long 0x00 0. " COCO0 ,HC0 Conversion Complete Flag" "Not completed,Completed" if (((per.l(ad:0x42280000+0x14))&0x0C)==0x00) group.long 0x0C++0x07 line.long 0x00 "ADC1_R0,Data result register for HW trigger 0" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC1_R1,Data result register for HW trigger 1" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Result of ADC conversion" elif (((per.l(ad:0x42280000+0x14))&0x0C)==0x04) group.long 0x0C++0x07 line.long 0x00 "ADC1_R0,Data result register for HW trigger 0" hexmask.long.word 0x00 0.--9. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC1_R1,Data result register for HW trigger 1" hexmask.long.word 0x04 0.--9. 1. " DATA ,Result of ADC conversion" elif (((per.l(ad:0x42280000+0x14))&0x0C)==0x08) group.long 0x0C++0x07 line.long 0x00 "ADC1_R0,Data result register for HW trigger 0" hexmask.long.word 0x00 0.--11. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC1_R1,Data result register for HW trigger 1" hexmask.long.word 0x04 0.--11. 1. " DATA ,Result of ADC conversion" else hgroup.long 0x0C++0x07 hide.long 0x00 "ADC1_R0,Data result register for HW trigger 0" hide.long 0x04 "ADC1_R1,Data result register for HW trigger 1" endif if ((per.l(ad:0x42280000+0x14)&0x10)==0x00000010) group.long 0x14++0x03 line.long 0x00 "ADC1_CFG,Configuration register" bitfld.long 0x00 16. " OVWREN ,Data Overwrite Enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " AVGS ,Amount of ADC conversions that will be averaged to create the ADC average result" "4 samples,8 samples,16 samples,32 samples" bitfld.long 0x00 13. " ADTRG ,Conversion Trigger Select" "Software,Hardware" textline " " bitfld.long 0x00 11.--12. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,,," bitfld.long 0x00 10. " ADHSC ,High Speed Configuration" "Normal,High speed" bitfld.long 0x00 8.--9. " ADSTS ,Sample time duration" "12,16,20,24" textline " " bitfld.long 0x00 7. " ADLPC ,Low-Power Configuration" "Not Low-Power,Low-Power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divider Select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long" textline " " bitfld.long 0x00 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit," bitfld.long 0x00 0.--1. " ADICLK ,Input clock source to generate the internal clock ADCK" "IPG,IPG/2,ALTCLK,ADACK" else group.long 0x14++0x03 line.long 0x00 "ADC1_CFG,Configuration register" bitfld.long 0x00 16. " OVWREN ,Data Overwrite Enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " AVGS ,Amount of ADC conversions that will be averaged to create the ADC average result." "4 samples,8 samples,16 samples,32 samples" bitfld.long 0x00 13. " ADTRG ,Conversion Trigger Select" "Software,Hardware" textline " " bitfld.long 0x00 11.--12. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,,," bitfld.long 0x00 10. " ADHSC ,High Speed Configuration" "Normal,High speed" bitfld.long 0x00 8.--9. " ADSTS ,Sample time duration" "2,4,6,8" textline " " bitfld.long 0x00 7. " ADLPC ,Low-Power Configuration" "Not Low-Power,Low-Power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divider Select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long" textline " " bitfld.long 0x00 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit," bitfld.long 0x00 0.--1. " ADICLK ,Input clock source to generate the internal clock ADCK" "IPG,IPG/2,ALTCLK,ADACK" endif textline " " if (((per.l(ad:0x42280000+0x18))&0x00000010)==0x00000010) group.long 0x18++0x03 line.long 0x00 "ADC1_GC,General control register" bitfld.long 0x00 7. " CAL ,Calibration sequence" "Completed/Not started,In progress" bitfld.long 0x00 6. " ADCO ,Continuous Conversion Enable" "Single,Continuous" bitfld.long 0x00 5. " AVGE ,Hardware average function of the ADC" "Disabled,Enabled" bitfld.long 0x00 4. " ACFE ,Compare Function Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ACFGT ,Compare Function Greater Than Enable" "Less/Not Inclusive,Greater or equal/Inclusive" bitfld.long 0x00 2. " ACREN ,Compare Function Range Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DMAEN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "ADC1_GC,General control register" bitfld.long 0x00 7. " CAL ,Calibration sequence" "Completed/Not started,In progress" bitfld.long 0x00 6. " ADCO ,Continuous Conversion Enable" "Single,Continuous" bitfld.long 0x00 5. " AVGE ,Hardware average function of the ADC" "Disabled,Enabled" bitfld.long 0x00 4. " ACFE ,Compare Function Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ACREN ,Compare Function Range Enable" "Unaffected,Unaffected" bitfld.long 0x00 1. " DMAEN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" endif group.long 0x1C++0x03 line.long 0x00 "ADC1_GS,General status register" eventfld.long 0x00 2. " AWKST ,Asynchronous wakeup interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 1. " CALF ,Calibration Failed Flag" "Completed,Failed" rbitfld.long 0x00 0. " ADACT ,Conversion Active" "Not in progress,In progress" if ((((per.l(ad:0x42280000+0x18))&0x10)==0x10)&&(((per.l(ad:0x42280000+0x14))&0x0C)==0x00)) group.long 0x20++0x03 line.long 0x00 "ADC1_CV,Compare value register" hexmask.long.byte 0x00 16.--23. 1. " CV2 ,Compare Value 2" hexmask.long.byte 0x00 0.--7. 1. " CV1 ,Compare Value 1" elif ((((per.l(ad:0x42280000+0x18))&0x10)==0x10)&&(((per.l(ad:0x42280000+0x14))&0x0C)==0x04)) group.long 0x20++0x03 line.long 0x00 "ADC1_CV,Compare value register" hexmask.long.word 0x00 16.--25. 1. " CV2 ,Compare Value 2" hexmask.long.word 0x00 0.--9. 1. " CV1 ,Compare Value 1" elif ((((per.l(ad:0x42280000+0x18))&0x10)==0x10)&&(((per.l(ad:0x42280000+0x14))&0x0C)==0x08)) group.long 0x20++0x03 line.long 0x00 "ADC1_CV,Compare value register" hexmask.long.word 0x00 16.--27. 1. " CV2 ,Compare Value 2" hexmask.long.word 0x00 0.--11. 1. " CV1 ,Compare Value 1" else hgroup.long 0x20++0x03 hide.long 0x00 "ADC1_CV,Compare value register" endif group.long 0x24++0x07 line.long 0x00 "ADC1_OFS,Offset correction value register" bitfld.long 0x00 12. " OFFSET ,Sign bit" "+,-" hexmask.long.word 0x00 0.--11. 1. ",Offset value" line.long 0x04 "ADC1_CAL,Calibration value register" bitfld.long 0x04 0.--3. " CAL_CODE ,Calibration Result Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0xB endif tree.end tree "ADC 2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02284000 width 11. group.long 0x00++0x07 line.long 0x00 "ADC2_HC0,Control register for hardware trigger 0" bitfld.long 0x00 7. " AIEN ,Conversion Complete Interrupt Enable/Disable Control" "Disabled,Enabled" bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "Ext_Ch_0,Ext_Ch_1,Ext_Ch_2,Ext_Ch_3,Ext_Ch_4,Ext_Ch_5,Ext_Ch_6,Ext_Ch_7,Ext_Ch_8,Ext_Ch_9,Ext_Ch_10,Ext_Ch_11,Ext_Ch_12,Ext_Ch_13,Ext_Ch_14,Ext_Ch_15,Ext_Sat_0,Ext_Sat_1,Ext_Sat_2,Ext_Sat_3,Ext_Sat_4,Ext_Sat_5,Ext_Sat_6,Ext_Sat_7,,VREFSH,,,,,,Disabled" line.long 0x04 "ADC2_HC1,Control register for hardware trigger 1" bitfld.long 0x04 7. " AIEN ,Conversion Complete Interrupt Enable/Disable Control" "Disabled,Enabled" bitfld.long 0x04 0.--4. " ADCH ,Input Channel Select" "Ext_Ch_0,Ext_Ch_1,Ext_Ch_2,Ext_Ch_3,Ext_Ch_4,Ext_Ch_5,Ext_Ch_6,Ext_Ch_7,Ext_Ch_8,Ext_Ch_9,Ext_Ch_10,Ext_Ch_11,Ext_Ch_12,Ext_Ch_13,Ext_Ch_14,Ext_Ch_15,Ext_Sat_0,Ext_Sat_1,Ext_Sat_2,Ext_Sat_3,Ext_Sat_4,Ext_Sat_5,Ext_Sat_6,Ext_Sat_7,,VREFSH,,,,,,Disabled" rgroup.long 0x08++0x03 line.long 0x00 "ADC2_HS,Status register for HW triggers" bitfld.long 0x00 1. " COCO1 ,HC1 Conversion Complete Flag" "Not completed,Completed" bitfld.long 0x00 0. " COCO0 ,HC0 Conversion Complete Flag" "Not completed,Completed" if (((per.l(ad:0x02284000+0x14))&0x0C)==0x00) group.long 0x0C++0x07 line.long 0x00 "ADC2_R0,Data result register for HW trigger 0" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC2_R1,Data result register for HW trigger 1" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Result of ADC conversion" elif (((per.l(ad:0x02284000+0x14))&0x0C)==0x04) group.long 0x0C++0x07 line.long 0x00 "ADC2_R0,Data result register for HW trigger 0" hexmask.long.word 0x00 0.--9. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC2_R1,Data result register for HW trigger 1" hexmask.long.word 0x04 0.--9. 1. " DATA ,Result of ADC conversion" elif (((per.l(ad:0x02284000+0x14))&0x0C)==0x08) group.long 0x0C++0x07 line.long 0x00 "ADC2_R0,Data result register for HW trigger 0" hexmask.long.word 0x00 0.--11. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC2_R1,Data result register for HW trigger 1" hexmask.long.word 0x04 0.--11. 1. " DATA ,Result of ADC conversion" else hgroup.long 0x0C++0x07 hide.long 0x00 "ADC2_R0,Data result register for HW trigger 0" hide.long 0x04 "ADC2_R1,Data result register for HW trigger 1" endif if ((per.l(ad:0x02284000+0x14)&0x10)==0x00000010) group.long 0x14++0x03 line.long 0x00 "ADC2_CFG,Configuration register" bitfld.long 0x00 16. " OVWREN ,Data Overwrite Enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " AVGS ,Amount of ADC conversions that will be averaged to create the ADC average result" "4 samples,8 samples,16 samples,32 samples" bitfld.long 0x00 13. " ADTRG ,Conversion Trigger Select" "Software,Hardware" textline " " bitfld.long 0x00 11.--12. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,,," bitfld.long 0x00 10. " ADHSC ,High Speed Configuration" "Normal,High speed" bitfld.long 0x00 8.--9. " ADSTS ,Sample time duration" "12,16,20,24" textline " " bitfld.long 0x00 7. " ADLPC ,Low-Power Configuration" "Not Low-Power,Low-Power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divider Select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long" textline " " bitfld.long 0x00 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit," bitfld.long 0x00 0.--1. " ADICLK ,Input clock source to generate the internal clock ADCK" "IPG,IPG/2,ALTCLK,ADACK" else group.long 0x14++0x03 line.long 0x00 "ADC2_CFG,Configuration register" bitfld.long 0x00 16. " OVWREN ,Data Overwrite Enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " AVGS ,Amount of ADC conversions that will be averaged to create the ADC average result." "4 samples,8 samples,16 samples,32 samples" bitfld.long 0x00 13. " ADTRG ,Conversion Trigger Select" "Software,Hardware" textline " " bitfld.long 0x00 11.--12. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,,," bitfld.long 0x00 10. " ADHSC ,High Speed Configuration" "Normal,High speed" bitfld.long 0x00 8.--9. " ADSTS ,Sample time duration" "2,4,6,8" textline " " bitfld.long 0x00 7. " ADLPC ,Low-Power Configuration" "Not Low-Power,Low-Power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divider Select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long" textline " " bitfld.long 0x00 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit," bitfld.long 0x00 0.--1. " ADICLK ,Input clock source to generate the internal clock ADCK" "IPG,IPG/2,ALTCLK,ADACK" endif textline " " if (((per.l(ad:0x02284000+0x18))&0x00000010)==0x00000010) group.long 0x18++0x03 line.long 0x00 "ADC2_GC,General control register" bitfld.long 0x00 7. " CAL ,Calibration sequence" "Completed/Not started,In progress" bitfld.long 0x00 6. " ADCO ,Continuous Conversion Enable" "Single,Continuous" bitfld.long 0x00 5. " AVGE ,Hardware average function of the ADC" "Disabled,Enabled" bitfld.long 0x00 4. " ACFE ,Compare Function Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ACFGT ,Compare Function Greater Than Enable" "Less/Not Inclusive,Greater or equal/Inclusive" bitfld.long 0x00 2. " ACREN ,Compare Function Range Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DMAEN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "ADC2_GC,General control register" bitfld.long 0x00 7. " CAL ,Calibration sequence" "Completed/Not started,In progress" bitfld.long 0x00 6. " ADCO ,Continuous Conversion Enable" "Single,Continuous" bitfld.long 0x00 5. " AVGE ,Hardware average function of the ADC" "Disabled,Enabled" bitfld.long 0x00 4. " ACFE ,Compare Function Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ACREN ,Compare Function Range Enable" "Unaffected,Unaffected" bitfld.long 0x00 1. " DMAEN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" endif group.long 0x1C++0x03 line.long 0x00 "ADC2_GS,General status register" eventfld.long 0x00 2. " AWKST ,Asynchronous wakeup interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 1. " CALF ,Calibration Failed Flag" "Completed,Failed" rbitfld.long 0x00 0. " ADACT ,Conversion Active" "Not in progress,In progress" if ((((per.l(ad:0x02284000+0x18))&0x10)==0x10)&&(((per.l(ad:0x02284000+0x14))&0x0C)==0x00)) group.long 0x20++0x03 line.long 0x00 "ADC2_CV,Compare value register" hexmask.long.byte 0x00 16.--23. 1. " CV2 ,Compare Value 2" hexmask.long.byte 0x00 0.--7. 1. " CV1 ,Compare Value 1" elif ((((per.l(ad:0x02284000+0x18))&0x10)==0x10)&&(((per.l(ad:0x02284000+0x14))&0x0C)==0x04)) group.long 0x20++0x03 line.long 0x00 "ADC2_CV,Compare value register" hexmask.long.word 0x00 16.--25. 1. " CV2 ,Compare Value 2" hexmask.long.word 0x00 0.--9. 1. " CV1 ,Compare Value 1" elif ((((per.l(ad:0x02284000+0x18))&0x10)==0x10)&&(((per.l(ad:0x02284000+0x14))&0x0C)==0x08)) group.long 0x20++0x03 line.long 0x00 "ADC2_CV,Compare value register" hexmask.long.word 0x00 16.--27. 1. " CV2 ,Compare Value 2" hexmask.long.word 0x00 0.--11. 1. " CV1 ,Compare Value 1" else hgroup.long 0x20++0x03 hide.long 0x00 "ADC2_CV,Compare value register" endif group.long 0x24++0x07 line.long 0x00 "ADC2_OFS,Offset correction value register" bitfld.long 0x00 12. " OFFSET ,Sign bit" "+,-" hexmask.long.word 0x00 0.--11. 1. ",Offset value" line.long 0x04 "ADC2_CAL,Calibration value register" bitfld.long 0x04 0.--3. " CAL_CODE ,Calibration Result Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0xB else base ad:0x42284000 width 11. group.long 0x00++0x07 line.long 0x00 "ADC2_HC0,Control register for hardware trigger 0" bitfld.long 0x00 7. " AIEN ,Conversion Complete Interrupt Enable/Disable Control" "Disabled,Enabled" bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "Ext_Ch_0,Ext_Ch_1,Ext_Ch_2,Ext_Ch_3,Ext_Ch_4,Ext_Ch_5,Ext_Ch_6,Ext_Ch_7,Ext_Ch_8,Ext_Ch_9,Ext_Ch_10,Ext_Ch_11,Ext_Ch_12,Ext_Ch_13,Ext_Ch_14,Ext_Ch_15,Ext_Sat_0,Ext_Sat_1,Ext_Sat_2,Ext_Sat_3,Ext_Sat_4,Ext_Sat_5,Ext_Sat_6,Ext_Sat_7,,VREFSH,,,,,,Disabled" line.long 0x04 "ADC2_HC1,Control register for hardware trigger 1" bitfld.long 0x04 7. " AIEN ,Conversion Complete Interrupt Enable/Disable Control" "Disabled,Enabled" bitfld.long 0x04 0.--4. " ADCH ,Input Channel Select" "Ext_Ch_0,Ext_Ch_1,Ext_Ch_2,Ext_Ch_3,Ext_Ch_4,Ext_Ch_5,Ext_Ch_6,Ext_Ch_7,Ext_Ch_8,Ext_Ch_9,Ext_Ch_10,Ext_Ch_11,Ext_Ch_12,Ext_Ch_13,Ext_Ch_14,Ext_Ch_15,Ext_Sat_0,Ext_Sat_1,Ext_Sat_2,Ext_Sat_3,Ext_Sat_4,Ext_Sat_5,Ext_Sat_6,Ext_Sat_7,,VREFSH,,,,,,Disabled" rgroup.long 0x08++0x03 line.long 0x00 "ADC2_HS,Status register for HW triggers" bitfld.long 0x00 1. " COCO1 ,HC1 Conversion Complete Flag" "Not completed,Completed" bitfld.long 0x00 0. " COCO0 ,HC0 Conversion Complete Flag" "Not completed,Completed" if (((per.l(ad:0x42284000+0x14))&0x0C)==0x00) group.long 0x0C++0x07 line.long 0x00 "ADC2_R0,Data result register for HW trigger 0" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC2_R1,Data result register for HW trigger 1" hexmask.long.byte 0x04 0.--7. 1. " DATA ,Result of ADC conversion" elif (((per.l(ad:0x42284000+0x14))&0x0C)==0x04) group.long 0x0C++0x07 line.long 0x00 "ADC2_R0,Data result register for HW trigger 0" hexmask.long.word 0x00 0.--9. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC2_R1,Data result register for HW trigger 1" hexmask.long.word 0x04 0.--9. 1. " DATA ,Result of ADC conversion" elif (((per.l(ad:0x42284000+0x14))&0x0C)==0x08) group.long 0x0C++0x07 line.long 0x00 "ADC2_R0,Data result register for HW trigger 0" hexmask.long.word 0x00 0.--11. 1. " DATA ,Result of ADC conversion" line.long 0x04 "ADC2_R1,Data result register for HW trigger 1" hexmask.long.word 0x04 0.--11. 1. " DATA ,Result of ADC conversion" else hgroup.long 0x0C++0x07 hide.long 0x00 "ADC2_R0,Data result register for HW trigger 0" hide.long 0x04 "ADC2_R1,Data result register for HW trigger 1" endif if ((per.l(ad:0x42284000+0x14)&0x10)==0x00000010) group.long 0x14++0x03 line.long 0x00 "ADC2_CFG,Configuration register" bitfld.long 0x00 16. " OVWREN ,Data Overwrite Enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " AVGS ,Amount of ADC conversions that will be averaged to create the ADC average result" "4 samples,8 samples,16 samples,32 samples" bitfld.long 0x00 13. " ADTRG ,Conversion Trigger Select" "Software,Hardware" textline " " bitfld.long 0x00 11.--12. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,,," bitfld.long 0x00 10. " ADHSC ,High Speed Configuration" "Normal,High speed" bitfld.long 0x00 8.--9. " ADSTS ,Sample time duration" "12,16,20,24" textline " " bitfld.long 0x00 7. " ADLPC ,Low-Power Configuration" "Not Low-Power,Low-Power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divider Select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long" textline " " bitfld.long 0x00 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit," bitfld.long 0x00 0.--1. " ADICLK ,Input clock source to generate the internal clock ADCK" "IPG,IPG/2,ALTCLK,ADACK" else group.long 0x14++0x03 line.long 0x00 "ADC2_CFG,Configuration register" bitfld.long 0x00 16. " OVWREN ,Data Overwrite Enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " AVGS ,Amount of ADC conversions that will be averaged to create the ADC average result." "4 samples,8 samples,16 samples,32 samples" bitfld.long 0x00 13. " ADTRG ,Conversion Trigger Select" "Software,Hardware" textline " " bitfld.long 0x00 11.--12. " REFSEL ,Voltage Reference Selection" "VREFH/VREFL,,," bitfld.long 0x00 10. " ADHSC ,High Speed Configuration" "Normal,High speed" bitfld.long 0x00 8.--9. " ADSTS ,Sample time duration" "2,4,6,8" textline " " bitfld.long 0x00 7. " ADLPC ,Low-Power Configuration" "Not Low-Power,Low-Power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divider Select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long" textline " " bitfld.long 0x00 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit," bitfld.long 0x00 0.--1. " ADICLK ,Input clock source to generate the internal clock ADCK" "IPG,IPG/2,ALTCLK,ADACK" endif textline " " if (((per.l(ad:0x42284000+0x18))&0x00000010)==0x00000010) group.long 0x18++0x03 line.long 0x00 "ADC2_GC,General control register" bitfld.long 0x00 7. " CAL ,Calibration sequence" "Completed/Not started,In progress" bitfld.long 0x00 6. " ADCO ,Continuous Conversion Enable" "Single,Continuous" bitfld.long 0x00 5. " AVGE ,Hardware average function of the ADC" "Disabled,Enabled" bitfld.long 0x00 4. " ACFE ,Compare Function Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ACFGT ,Compare Function Greater Than Enable" "Less/Not Inclusive,Greater or equal/Inclusive" bitfld.long 0x00 2. " ACREN ,Compare Function Range Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DMAEN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "ADC2_GC,General control register" bitfld.long 0x00 7. " CAL ,Calibration sequence" "Completed/Not started,In progress" bitfld.long 0x00 6. " ADCO ,Continuous Conversion Enable" "Single,Continuous" bitfld.long 0x00 5. " AVGE ,Hardware average function of the ADC" "Disabled,Enabled" bitfld.long 0x00 4. " ACFE ,Compare Function Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ACREN ,Compare Function Range Enable" "Unaffected,Unaffected" bitfld.long 0x00 1. " DMAEN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" endif group.long 0x1C++0x03 line.long 0x00 "ADC2_GS,General status register" eventfld.long 0x00 2. " AWKST ,Asynchronous wakeup interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 1. " CALF ,Calibration Failed Flag" "Completed,Failed" rbitfld.long 0x00 0. " ADACT ,Conversion Active" "Not in progress,In progress" if ((((per.l(ad:0x42284000+0x18))&0x10)==0x10)&&(((per.l(ad:0x42284000+0x14))&0x0C)==0x00)) group.long 0x20++0x03 line.long 0x00 "ADC2_CV,Compare value register" hexmask.long.byte 0x00 16.--23. 1. " CV2 ,Compare Value 2" hexmask.long.byte 0x00 0.--7. 1. " CV1 ,Compare Value 1" elif ((((per.l(ad:0x42284000+0x18))&0x10)==0x10)&&(((per.l(ad:0x42284000+0x14))&0x0C)==0x04)) group.long 0x20++0x03 line.long 0x00 "ADC2_CV,Compare value register" hexmask.long.word 0x00 16.--25. 1. " CV2 ,Compare Value 2" hexmask.long.word 0x00 0.--9. 1. " CV1 ,Compare Value 1" elif ((((per.l(ad:0x42284000+0x18))&0x10)==0x10)&&(((per.l(ad:0x42284000+0x14))&0x0C)==0x08)) group.long 0x20++0x03 line.long 0x00 "ADC2_CV,Compare value register" hexmask.long.word 0x00 16.--27. 1. " CV2 ,Compare Value 2" hexmask.long.word 0x00 0.--11. 1. " CV1 ,Compare Value 1" else hgroup.long 0x20++0x03 hide.long 0x00 "ADC2_CV,Compare value register" endif group.long 0x24++0x07 line.long 0x00 "ADC2_OFS,Offset correction value register" bitfld.long 0x00 12. " OFFSET ,Sign bit" "+,-" hexmask.long.word 0x00 0.--11. 1. ",Offset value" line.long 0x04 "ADC2_CAL,Calibration value register" bitfld.long 0x04 0.--3. " CAL_CODE ,Calibration Result Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0xB endif tree.end tree.end tree.open "AIPSTZ (AHB to IP Bridge)" tree "AIPS-1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0207C000 else base ad:0x4207C000 endif width 7. group.long 0x00++0x3 line.long 0x00 "MPR,Master Privilege Register" bitfld.long 0x00 31. " MBW[0] ,Master 0 buffer write accesses" "Disabled,Enabled" bitfld.long 0x00 30. " MTR[0] ,Master 0 trusted for read accesses" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW[0] ,Master 0 trusted for write accesses" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL[0] ,Force accesses from master 0 to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MBW[1] ,ARM A9 CORE master buffer writes" "Disabled,Enabled" bitfld.long 0x00 26. " MTR[1] ,ARM A9 CORE master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 25. " MTW[1] ,ARM A9 CORE master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL[1] ,Force accesses from ARM A9 CORE master to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MBW[2] ,CAAM master buffer writes" "Disabled,Enabled" bitfld.long 0x00 22. " MTR[2] ,CAAM master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW[2] ,CAAM master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 20. " MPL[2] ,Force accesses from CAAM master to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MBW[3] ,SDMA master buffer writes" "Disabled,Enabled" bitfld.long 0x00 18. " MTR[3] ,SDMA master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 17. " MTW[3] ,SDMA master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MPL[3] ,Force accesses from SDMA master to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MBW[5] ,ARM M4 CORE master buffer writes" "Disabled,Enabled" bitfld.long 0x00 10. " MTR[5] ,ARM M4 CORE master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 9. " MTW[5] ,ARM M4 CORE master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 8. " MPL[5] ,Force accesses from ARM M4 CORE master to user-mode" "Forced,Not forced" textline "" group.long 0x40++0x13 line.long 0x00 "OPACR0,Off-Platform Peripheral Access Control Register 0" bitfld.long 0x00 31. " BW0 ,Off-platform Peripheral Access Control 0 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 30. " SP0 ,Off-platform Peripheral Access Control 0 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Off-platform Peripheral Access Control 0 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Off-platform Peripheral Access Control 0 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " BW1 ,Off-platform Peripheral Access Control 1 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 26. " SP1 ,Off-platform Peripheral Access Control 1 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Off-platform Peripheral Access Control 1 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Off-platform Peripheral Access Control 1 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " BW2 ,Off-platform Peripheral Access Control 2 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 22. " SP2 ,Off-platform Peripheral Access Control 2 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Off-platform Peripheral Access Control 2 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Off-platform Peripheral Access Control 2 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BW3 ,Off-platform Peripheral Access Control 3 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 18. " SP3 ,Off-platform Peripheral Access Control 3 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Off-platform Peripheral Access Control 3 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Off-platform Peripheral Access Control 3 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " BW4 ,Off-platform Peripheral Access Control 4 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 14. " SP4 ,Off-platform Peripheral Access Control 4 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Off-platform Peripheral Access Control 4 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Off-platform Peripheral Access Control 4 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " BW5 ,Off-platform Peripheral Access Control 5 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 10. " SP5 ,Off-platform Peripheral Access Control 5 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Off-platform Peripheral Access Control 5 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Off-platform Peripheral Access Control 5 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BW6 ,Off-platform Peripheral Access Control 6 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 6. " SP6 ,Off-platform Peripheral Access Control 6 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Off-platform Peripheral Access Control 6 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Off-platform Peripheral Access Control 6 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BW7 ,Off-platform Peripheral Access Control 7 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 2. " SP7 ,Off-platform Peripheral Access Control 7 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Off-platform Peripheral Access Control 7 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Off-platform Peripheral Access Control 7 - Trusted Protect" "Disabled,Enabled" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Register 1" bitfld.long 0x04 31. " BW8 ,Off-platform Peripheral Access Control 8 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 30. " SP8 ,Off-platform Peripheral Access Control 8 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 29. " WP8 ,Off-platform Peripheral Access Control 8 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 28. " TP8 ,Off-platform Peripheral Access Control 8 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " BW9 ,Off-platform Peripheral Access Control 9 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 26. " SP9 ,Off-platform Peripheral Access Control 9 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 25. " WP9 ,Off-platform Peripheral Access Control 9 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 24. " TP9 ,Off-platform Peripheral Access Control 9 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " BW10 ,Off-platform Peripheral Access Control 10 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 22. " SP10 ,Off-platform Peripheral Access Control 10 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 21. " WP10 ,Off-platform Peripheral Access Control 10 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 20. " TP10 ,Off-platform Peripheral Access Control 10 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " BW11 ,Off-platform Peripheral Access Control 11 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 18. " SP11 ,Off-platform Peripheral Access Control 11 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 17. " WP11 ,Off-platform Peripheral Access Control 11 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 16. " TP11 ,Off-platform Peripheral Access Control 11 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " BW12 ,Off-platform Peripheral Access Control 12 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 14. " SP12 ,Off-platform Peripheral Access Control 12 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 13. " WP12 ,Off-platform Peripheral Access Control 12 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 12. " TP12 ,Off-platform Peripheral Access Control 12 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " BW13 ,Off-platform Peripheral Access Control 13 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 10. " SP13 ,Off-platform Peripheral Access Control 13 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 9. " WP13 ,Off-platform Peripheral Access Control 13 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 8. " TP13 ,Off-platform Peripheral Access Control 13 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " BW14 ,Off-platform Peripheral Access Control 14 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 6. " SP14 ,Off-platform Peripheral Access Control 14 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 5. " WP14 ,Off-platform Peripheral Access Control 14 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 4. " TP14 ,Off-platform Peripheral Access Control 14 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " BW15 ,Off-platform Peripheral Access Control 15 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 2. " SP15 ,Off-platform Peripheral Access Control 15 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 1. " WP15 ,Off-platform Peripheral Access Control 15 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 0. " TP15 ,Off-platform Peripheral Access Control 15 - Trusted Protect" "Disabled,Enabled" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Register 2" bitfld.long 0x08 31. " BW16 ,Off-platform Peripheral Access Control 16 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 30. " SP16 ,Off-platform Peripheral Access Control 16 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 29. " WP16 ,Off-platform Peripheral Access Control 16 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 28. " TP16 ,Off-platform Peripheral Access Control 16 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 27. " BW17 ,Off-platform Peripheral Access Control 17 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 26. " SP17 ,Off-platform Peripheral Access Control 17 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 25. " WP17 ,Off-platform Peripheral Access Control 17 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 24. " TP17 ,Off-platform Peripheral Access Control 17 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 23. " BW18 ,Off-platform Peripheral Access Control 18 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 22. " SP18 ,Off-platform Peripheral Access Control 18 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 21. " WP18 ,Off-platform Peripheral Access Control 18 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 20. " TP18 ,Off-platform Peripheral Access Control 18 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " BW19 ,Off-platform Peripheral Access Control 19 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 18. " SP19 ,Off-platform Peripheral Access Control 19 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 17. " WP19 ,Off-platform Peripheral Access Control 19 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 16. " TP19 ,Off-platform Peripheral Access Control 19 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 15. " BW20 ,Off-platform Peripheral Access Control 20 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 14. " SP20 ,Off-platform Peripheral Access Control 20 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 13. " WP20 ,Off-platform Peripheral Access Control 20 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 12. " TP20 ,Off-platform Peripheral Access Control 20 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " BW21 ,Off-platform Peripheral Access Control 21 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 10. " SP21 ,Off-platform Peripheral Access Control 21 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 9. " WP21 ,Off-platform Peripheral Access Control 21 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 8. " TP21 ,Off-platform Peripheral Access Control 21 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " BW22 ,Off-platform Peripheral Access Control 22 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 6. " SP22 ,Off-platform Peripheral Access Control 22 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 5. " WP22 ,Off-platform Peripheral Access Control 22 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 4. " TP22 ,Off-platform Peripheral Access Control 22 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " BW23 ,Off-platform Peripheral Access Control 23 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 2. " SP23 ,Off-platform Peripheral Access Control 23 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 1. " WP23 ,Off-platform Peripheral Access Control 23 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 0. " TP23 ,Off-platform Peripheral Access Control 23 - Trusted Protect" "Disabled,Enabled" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Register 3" bitfld.long 0x0C 31. " BW24 ,Off-platform Peripheral Access Control 24 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 30. " SP24 ,Off-platform Peripheral Access Control 24 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 29. " WP24 ,Off-platform Peripheral Access Control 24 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 28. " TP24 ,Off-platform Peripheral Access Control 24 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 27. " BW25 ,Off-platform Peripheral Access Control 25 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 26. " SP25 ,Off-platform Peripheral Access Control 25 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 25. " WP25 ,Off-platform Peripheral Access Control 25 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 24. " TP25 ,Off-platform Peripheral Access Control 25 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 23. " BW26 ,Off-platform Peripheral Access Control 26 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 22. " SP26 ,Off-platform Peripheral Access Control 26 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 21. " WP26 ,Off-platform Peripheral Access Control 26 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 20. " TP26 ,Off-platform Peripheral Access Control 26 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 19. " BW27 ,Off-platform Peripheral Access Control 27 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 18. " SP27 ,Off-platform Peripheral Access Control 27 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 17. " WP27 ,Off-platform Peripheral Access Control 27 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 16. " TP27 ,Off-platform Peripheral Access Control 27 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 15. " BW28 ,Off-platform Peripheral Access Control 28 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 14. " SP28 ,Off-platform Peripheral Access Control 28 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 13. " WP28 ,Off-platform Peripheral Access Control 28 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 12. " TP28 ,Off-platform Peripheral Access Control 28 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 11. " BW29 ,Off-platform Peripheral Access Control 29 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 10. " SP29 ,Off-platform Peripheral Access Control 29 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 9. " WP29 ,Off-platform Peripheral Access Control 29 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 8. " TP29 ,Off-platform Peripheral Access Control 29 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 7. " BW30 ,Off-platform Peripheral Access Control 30 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 6. " SP30 ,Off-platform Peripheral Access Control 30 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 5. " WP30 ,Off-platform Peripheral Access Control 30 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 4. " TP30 ,Off-platform Peripheral Access Control 30 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 3. " BW31 ,Off-platform Peripheral Access Control 31 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 2. " SP31 ,Off-platform Peripheral Access Control 31 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 1. " WP31 ,Off-platform Peripheral Access Control 31 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 0. " TP31 ,Off-platform Peripheral Access Control 31 - Trusted Protect" "Disabled,Enabled" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Register 4" bitfld.long 0x10 31. " BW32 ,Off-platform Peripheral Access Control 32 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x10 30. " SP32 ,Off-platform Peripheral Access Control 32 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x10 29. " WP32 ,Off-platform Peripheral Access Control 32 - Write Protect" "Disabled,Enabled" bitfld.long 0x10 28. " TP32 ,Off-platform Peripheral Access Control 32 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " BW33 ,Off-platform Peripheral Access Control 33 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x10 26. " SP33 ,Off-platform Peripheral Access Control 33 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x10 25. " WP33 ,Off-platform Peripheral Access Control 33 - Write Protect" "Disabled,Enabled" bitfld.long 0x10 24. " TP33 ,Off-platform Peripheral Access Control 33 - Trusted Protect" "Disabled,Enabled" width 0xB tree.end tree "AIPS-2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0217C000 else base ad:0x4217C000 endif width 7. group.long 0x00++0x3 line.long 0x00 "MPR,Master Privilege Register" bitfld.long 0x00 31. " MBW[0] ,Master 0 buffer write accesses" "Disabled,Enabled" bitfld.long 0x00 30. " MTR[0] ,Master 0 trusted for read accesses" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW[0] ,Master 0 trusted for write accesses" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL[0] ,Force accesses from master 0 to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MBW[1] ,ARM A9 CORE master buffer writes" "Disabled,Enabled" bitfld.long 0x00 26. " MTR[1] ,ARM A9 CORE master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 25. " MTW[1] ,ARM A9 CORE master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL[1] ,Force accesses from ARM A9 CORE master to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MBW[2] ,CAAM master buffer writes" "Disabled,Enabled" bitfld.long 0x00 22. " MTR[2] ,CAAM master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW[2] ,CAAM master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 20. " MPL[2] ,Force accesses from CAAM master to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MBW[3] ,SDMA master buffer writes" "Disabled,Enabled" bitfld.long 0x00 18. " MTR[3] ,SDMA master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 17. " MTW[3] ,SDMA master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MPL[3] ,Force accesses from SDMA master to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MBW[5] ,ARM M4 CORE master buffer writes" "Disabled,Enabled" bitfld.long 0x00 10. " MTR[5] ,ARM M4 CORE master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 9. " MTW[5] ,ARM M4 CORE master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 8. " MPL[5] ,Force accesses from ARM M4 CORE master to user-mode" "Forced,Not forced" textline "" group.long 0x40++0x13 line.long 0x00 "OPACR0,Off-Platform Peripheral Access Control Register 0" bitfld.long 0x00 31. " BW0 ,Off-platform Peripheral Access Control 0 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 30. " SP0 ,Off-platform Peripheral Access Control 0 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Off-platform Peripheral Access Control 0 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Off-platform Peripheral Access Control 0 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " BW1 ,Off-platform Peripheral Access Control 1 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 26. " SP1 ,Off-platform Peripheral Access Control 1 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Off-platform Peripheral Access Control 1 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Off-platform Peripheral Access Control 1 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " BW2 ,Off-platform Peripheral Access Control 2 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 22. " SP2 ,Off-platform Peripheral Access Control 2 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Off-platform Peripheral Access Control 2 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Off-platform Peripheral Access Control 2 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BW3 ,Off-platform Peripheral Access Control 3 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 18. " SP3 ,Off-platform Peripheral Access Control 3 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Off-platform Peripheral Access Control 3 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Off-platform Peripheral Access Control 3 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " BW4 ,Off-platform Peripheral Access Control 4 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 14. " SP4 ,Off-platform Peripheral Access Control 4 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Off-platform Peripheral Access Control 4 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Off-platform Peripheral Access Control 4 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " BW5 ,Off-platform Peripheral Access Control 5 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 10. " SP5 ,Off-platform Peripheral Access Control 5 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Off-platform Peripheral Access Control 5 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Off-platform Peripheral Access Control 5 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BW6 ,Off-platform Peripheral Access Control 6 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 6. " SP6 ,Off-platform Peripheral Access Control 6 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Off-platform Peripheral Access Control 6 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Off-platform Peripheral Access Control 6 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BW7 ,Off-platform Peripheral Access Control 7 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 2. " SP7 ,Off-platform Peripheral Access Control 7 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Off-platform Peripheral Access Control 7 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Off-platform Peripheral Access Control 7 - Trusted Protect" "Disabled,Enabled" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Register 1" bitfld.long 0x04 31. " BW8 ,Off-platform Peripheral Access Control 8 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 30. " SP8 ,Off-platform Peripheral Access Control 8 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 29. " WP8 ,Off-platform Peripheral Access Control 8 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 28. " TP8 ,Off-platform Peripheral Access Control 8 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " BW9 ,Off-platform Peripheral Access Control 9 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 26. " SP9 ,Off-platform Peripheral Access Control 9 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 25. " WP9 ,Off-platform Peripheral Access Control 9 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 24. " TP9 ,Off-platform Peripheral Access Control 9 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " BW10 ,Off-platform Peripheral Access Control 10 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 22. " SP10 ,Off-platform Peripheral Access Control 10 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 21. " WP10 ,Off-platform Peripheral Access Control 10 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 20. " TP10 ,Off-platform Peripheral Access Control 10 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " BW11 ,Off-platform Peripheral Access Control 11 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 18. " SP11 ,Off-platform Peripheral Access Control 11 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 17. " WP11 ,Off-platform Peripheral Access Control 11 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 16. " TP11 ,Off-platform Peripheral Access Control 11 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " BW12 ,Off-platform Peripheral Access Control 12 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 14. " SP12 ,Off-platform Peripheral Access Control 12 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 13. " WP12 ,Off-platform Peripheral Access Control 12 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 12. " TP12 ,Off-platform Peripheral Access Control 12 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " BW13 ,Off-platform Peripheral Access Control 13 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 10. " SP13 ,Off-platform Peripheral Access Control 13 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 9. " WP13 ,Off-platform Peripheral Access Control 13 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 8. " TP13 ,Off-platform Peripheral Access Control 13 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " BW14 ,Off-platform Peripheral Access Control 14 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 6. " SP14 ,Off-platform Peripheral Access Control 14 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 5. " WP14 ,Off-platform Peripheral Access Control 14 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 4. " TP14 ,Off-platform Peripheral Access Control 14 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " BW15 ,Off-platform Peripheral Access Control 15 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 2. " SP15 ,Off-platform Peripheral Access Control 15 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 1. " WP15 ,Off-platform Peripheral Access Control 15 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 0. " TP15 ,Off-platform Peripheral Access Control 15 - Trusted Protect" "Disabled,Enabled" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Register 2" bitfld.long 0x08 31. " BW16 ,Off-platform Peripheral Access Control 16 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 30. " SP16 ,Off-platform Peripheral Access Control 16 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 29. " WP16 ,Off-platform Peripheral Access Control 16 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 28. " TP16 ,Off-platform Peripheral Access Control 16 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 27. " BW17 ,Off-platform Peripheral Access Control 17 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 26. " SP17 ,Off-platform Peripheral Access Control 17 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 25. " WP17 ,Off-platform Peripheral Access Control 17 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 24. " TP17 ,Off-platform Peripheral Access Control 17 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 23. " BW18 ,Off-platform Peripheral Access Control 18 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 22. " SP18 ,Off-platform Peripheral Access Control 18 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 21. " WP18 ,Off-platform Peripheral Access Control 18 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 20. " TP18 ,Off-platform Peripheral Access Control 18 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " BW19 ,Off-platform Peripheral Access Control 19 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 18. " SP19 ,Off-platform Peripheral Access Control 19 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 17. " WP19 ,Off-platform Peripheral Access Control 19 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 16. " TP19 ,Off-platform Peripheral Access Control 19 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 15. " BW20 ,Off-platform Peripheral Access Control 20 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 14. " SP20 ,Off-platform Peripheral Access Control 20 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 13. " WP20 ,Off-platform Peripheral Access Control 20 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 12. " TP20 ,Off-platform Peripheral Access Control 20 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " BW21 ,Off-platform Peripheral Access Control 21 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 10. " SP21 ,Off-platform Peripheral Access Control 21 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 9. " WP21 ,Off-platform Peripheral Access Control 21 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 8. " TP21 ,Off-platform Peripheral Access Control 21 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " BW22 ,Off-platform Peripheral Access Control 22 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 6. " SP22 ,Off-platform Peripheral Access Control 22 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 5. " WP22 ,Off-platform Peripheral Access Control 22 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 4. " TP22 ,Off-platform Peripheral Access Control 22 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " BW23 ,Off-platform Peripheral Access Control 23 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 2. " SP23 ,Off-platform Peripheral Access Control 23 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 1. " WP23 ,Off-platform Peripheral Access Control 23 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 0. " TP23 ,Off-platform Peripheral Access Control 23 - Trusted Protect" "Disabled,Enabled" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Register 3" bitfld.long 0x0C 31. " BW24 ,Off-platform Peripheral Access Control 24 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 30. " SP24 ,Off-platform Peripheral Access Control 24 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 29. " WP24 ,Off-platform Peripheral Access Control 24 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 28. " TP24 ,Off-platform Peripheral Access Control 24 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 27. " BW25 ,Off-platform Peripheral Access Control 25 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 26. " SP25 ,Off-platform Peripheral Access Control 25 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 25. " WP25 ,Off-platform Peripheral Access Control 25 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 24. " TP25 ,Off-platform Peripheral Access Control 25 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 23. " BW26 ,Off-platform Peripheral Access Control 26 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 22. " SP26 ,Off-platform Peripheral Access Control 26 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 21. " WP26 ,Off-platform Peripheral Access Control 26 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 20. " TP26 ,Off-platform Peripheral Access Control 26 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 19. " BW27 ,Off-platform Peripheral Access Control 27 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 18. " SP27 ,Off-platform Peripheral Access Control 27 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 17. " WP27 ,Off-platform Peripheral Access Control 27 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 16. " TP27 ,Off-platform Peripheral Access Control 27 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 15. " BW28 ,Off-platform Peripheral Access Control 28 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 14. " SP28 ,Off-platform Peripheral Access Control 28 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 13. " WP28 ,Off-platform Peripheral Access Control 28 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 12. " TP28 ,Off-platform Peripheral Access Control 28 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 11. " BW29 ,Off-platform Peripheral Access Control 29 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 10. " SP29 ,Off-platform Peripheral Access Control 29 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 9. " WP29 ,Off-platform Peripheral Access Control 29 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 8. " TP29 ,Off-platform Peripheral Access Control 29 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 7. " BW30 ,Off-platform Peripheral Access Control 30 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 6. " SP30 ,Off-platform Peripheral Access Control 30 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 5. " WP30 ,Off-platform Peripheral Access Control 30 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 4. " TP30 ,Off-platform Peripheral Access Control 30 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 3. " BW31 ,Off-platform Peripheral Access Control 31 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 2. " SP31 ,Off-platform Peripheral Access Control 31 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 1. " WP31 ,Off-platform Peripheral Access Control 31 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 0. " TP31 ,Off-platform Peripheral Access Control 31 - Trusted Protect" "Disabled,Enabled" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Register 4" bitfld.long 0x10 31. " BW32 ,Off-platform Peripheral Access Control 32 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x10 30. " SP32 ,Off-platform Peripheral Access Control 32 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x10 29. " WP32 ,Off-platform Peripheral Access Control 32 - Write Protect" "Disabled,Enabled" bitfld.long 0x10 28. " TP32 ,Off-platform Peripheral Access Control 32 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " BW33 ,Off-platform Peripheral Access Control 33 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x10 26. " SP33 ,Off-platform Peripheral Access Control 33 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x10 25. " WP33 ,Off-platform Peripheral Access Control 33 - Write Protect" "Disabled,Enabled" bitfld.long 0x10 24. " TP33 ,Off-platform Peripheral Access Control 33 - Trusted Protect" "Disabled,Enabled" width 0xB tree.end tree "AIPS-3" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0227C000 else base ad:0x4227C000 endif width 7. group.long 0x00++0x3 line.long 0x00 "MPR,Master Privilege Register" bitfld.long 0x00 31. " MBW[0] ,Master 0 buffer write accesses" "Disabled,Enabled" bitfld.long 0x00 30. " MTR[0] ,Master 0 trusted for read accesses" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW[0] ,Master 0 trusted for write accesses" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL[0] ,Force accesses from master 0 to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 27. " MBW[1] ,ARM A9 CORE master buffer writes" "Disabled,Enabled" bitfld.long 0x00 26. " MTR[1] ,ARM A9 CORE master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 25. " MTW[1] ,ARM A9 CORE master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL[1] ,Force accesses from ARM A9 CORE master to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 23. " MBW[2] ,CAAM master buffer writes" "Disabled,Enabled" bitfld.long 0x00 22. " MTR[2] ,CAAM master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW[2] ,CAAM master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 20. " MPL[2] ,Force accesses from CAAM master to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 19. " MBW[3] ,SDMA master buffer writes" "Disabled,Enabled" bitfld.long 0x00 18. " MTR[3] ,SDMA master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 17. " MTW[3] ,SDMA master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MPL[3] ,Force accesses from SDMA master to user-mode" "Forced,Not forced" textline " " bitfld.long 0x00 11. " MBW[5] ,ARM M4 CORE master buffer writes" "Disabled,Enabled" bitfld.long 0x00 10. " MTR[5] ,ARM M4 CORE master trusted for reads" "Not trusted,Trusted" bitfld.long 0x00 9. " MTW[5] ,ARM M4 CORE master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 8. " MPL[5] ,Force accesses from ARM M4 CORE master to user-mode" "Forced,Not forced" textline "" group.long 0x40++0x13 line.long 0x00 "OPACR0,Off-Platform Peripheral Access Control Register 0" bitfld.long 0x00 31. " BW0 ,Off-platform Peripheral Access Control 0 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 30. " SP0 ,Off-platform Peripheral Access Control 0 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Off-platform Peripheral Access Control 0 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Off-platform Peripheral Access Control 0 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " BW1 ,Off-platform Peripheral Access Control 1 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 26. " SP1 ,Off-platform Peripheral Access Control 1 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Off-platform Peripheral Access Control 1 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Off-platform Peripheral Access Control 1 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " BW2 ,Off-platform Peripheral Access Control 2 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 22. " SP2 ,Off-platform Peripheral Access Control 2 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Off-platform Peripheral Access Control 2 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Off-platform Peripheral Access Control 2 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BW3 ,Off-platform Peripheral Access Control 3 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 18. " SP3 ,Off-platform Peripheral Access Control 3 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Off-platform Peripheral Access Control 3 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Off-platform Peripheral Access Control 3 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " BW4 ,Off-platform Peripheral Access Control 4 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 14. " SP4 ,Off-platform Peripheral Access Control 4 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Off-platform Peripheral Access Control 4 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Off-platform Peripheral Access Control 4 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " BW5 ,Off-platform Peripheral Access Control 5 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 10. " SP5 ,Off-platform Peripheral Access Control 5 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Off-platform Peripheral Access Control 5 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Off-platform Peripheral Access Control 5 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BW6 ,Off-platform Peripheral Access Control 6 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 6. " SP6 ,Off-platform Peripheral Access Control 6 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Off-platform Peripheral Access Control 6 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Off-platform Peripheral Access Control 6 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BW7 ,Off-platform Peripheral Access Control 7 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x00 2. " SP7 ,Off-platform Peripheral Access Control 7 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Off-platform Peripheral Access Control 7 - Write Protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Off-platform Peripheral Access Control 7 - Trusted Protect" "Disabled,Enabled" line.long 0x04 "OPACR1,Off-Platform Peripheral Access Control Register 1" bitfld.long 0x04 31. " BW8 ,Off-platform Peripheral Access Control 8 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 30. " SP8 ,Off-platform Peripheral Access Control 8 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 29. " WP8 ,Off-platform Peripheral Access Control 8 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 28. " TP8 ,Off-platform Peripheral Access Control 8 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " BW9 ,Off-platform Peripheral Access Control 9 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 26. " SP9 ,Off-platform Peripheral Access Control 9 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 25. " WP9 ,Off-platform Peripheral Access Control 9 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 24. " TP9 ,Off-platform Peripheral Access Control 9 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " BW10 ,Off-platform Peripheral Access Control 10 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 22. " SP10 ,Off-platform Peripheral Access Control 10 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 21. " WP10 ,Off-platform Peripheral Access Control 10 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 20. " TP10 ,Off-platform Peripheral Access Control 10 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " BW11 ,Off-platform Peripheral Access Control 11 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 18. " SP11 ,Off-platform Peripheral Access Control 11 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 17. " WP11 ,Off-platform Peripheral Access Control 11 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 16. " TP11 ,Off-platform Peripheral Access Control 11 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " BW12 ,Off-platform Peripheral Access Control 12 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 14. " SP12 ,Off-platform Peripheral Access Control 12 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 13. " WP12 ,Off-platform Peripheral Access Control 12 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 12. " TP12 ,Off-platform Peripheral Access Control 12 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " BW13 ,Off-platform Peripheral Access Control 13 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 10. " SP13 ,Off-platform Peripheral Access Control 13 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 9. " WP13 ,Off-platform Peripheral Access Control 13 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 8. " TP13 ,Off-platform Peripheral Access Control 13 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " BW14 ,Off-platform Peripheral Access Control 14 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 6. " SP14 ,Off-platform Peripheral Access Control 14 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 5. " WP14 ,Off-platform Peripheral Access Control 14 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 4. " TP14 ,Off-platform Peripheral Access Control 14 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " BW15 ,Off-platform Peripheral Access Control 15 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x04 2. " SP15 ,Off-platform Peripheral Access Control 15 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x04 1. " WP15 ,Off-platform Peripheral Access Control 15 - Write Protect" "Disabled,Enabled" bitfld.long 0x04 0. " TP15 ,Off-platform Peripheral Access Control 15 - Trusted Protect" "Disabled,Enabled" line.long 0x08 "OPACR2,Off-Platform Peripheral Access Control Register 2" bitfld.long 0x08 31. " BW16 ,Off-platform Peripheral Access Control 16 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 30. " SP16 ,Off-platform Peripheral Access Control 16 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 29. " WP16 ,Off-platform Peripheral Access Control 16 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 28. " TP16 ,Off-platform Peripheral Access Control 16 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 27. " BW17 ,Off-platform Peripheral Access Control 17 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 26. " SP17 ,Off-platform Peripheral Access Control 17 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 25. " WP17 ,Off-platform Peripheral Access Control 17 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 24. " TP17 ,Off-platform Peripheral Access Control 17 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 23. " BW18 ,Off-platform Peripheral Access Control 18 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 22. " SP18 ,Off-platform Peripheral Access Control 18 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 21. " WP18 ,Off-platform Peripheral Access Control 18 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 20. " TP18 ,Off-platform Peripheral Access Control 18 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " BW19 ,Off-platform Peripheral Access Control 19 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 18. " SP19 ,Off-platform Peripheral Access Control 19 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 17. " WP19 ,Off-platform Peripheral Access Control 19 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 16. " TP19 ,Off-platform Peripheral Access Control 19 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 15. " BW20 ,Off-platform Peripheral Access Control 20 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 14. " SP20 ,Off-platform Peripheral Access Control 20 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 13. " WP20 ,Off-platform Peripheral Access Control 20 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 12. " TP20 ,Off-platform Peripheral Access Control 20 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " BW21 ,Off-platform Peripheral Access Control 21 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 10. " SP21 ,Off-platform Peripheral Access Control 21 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 9. " WP21 ,Off-platform Peripheral Access Control 21 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 8. " TP21 ,Off-platform Peripheral Access Control 21 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " BW22 ,Off-platform Peripheral Access Control 22 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 6. " SP22 ,Off-platform Peripheral Access Control 22 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 5. " WP22 ,Off-platform Peripheral Access Control 22 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 4. " TP22 ,Off-platform Peripheral Access Control 22 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " BW23 ,Off-platform Peripheral Access Control 23 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x08 2. " SP23 ,Off-platform Peripheral Access Control 23 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x08 1. " WP23 ,Off-platform Peripheral Access Control 23 - Write Protect" "Disabled,Enabled" bitfld.long 0x08 0. " TP23 ,Off-platform Peripheral Access Control 23 - Trusted Protect" "Disabled,Enabled" line.long 0x0C "OPACR3,Off-Platform Peripheral Access Control Register 3" bitfld.long 0x0C 31. " BW24 ,Off-platform Peripheral Access Control 24 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 30. " SP24 ,Off-platform Peripheral Access Control 24 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 29. " WP24 ,Off-platform Peripheral Access Control 24 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 28. " TP24 ,Off-platform Peripheral Access Control 24 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 27. " BW25 ,Off-platform Peripheral Access Control 25 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 26. " SP25 ,Off-platform Peripheral Access Control 25 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 25. " WP25 ,Off-platform Peripheral Access Control 25 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 24. " TP25 ,Off-platform Peripheral Access Control 25 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 23. " BW26 ,Off-platform Peripheral Access Control 26 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 22. " SP26 ,Off-platform Peripheral Access Control 26 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 21. " WP26 ,Off-platform Peripheral Access Control 26 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 20. " TP26 ,Off-platform Peripheral Access Control 26 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 19. " BW27 ,Off-platform Peripheral Access Control 27 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 18. " SP27 ,Off-platform Peripheral Access Control 27 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 17. " WP27 ,Off-platform Peripheral Access Control 27 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 16. " TP27 ,Off-platform Peripheral Access Control 27 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 15. " BW28 ,Off-platform Peripheral Access Control 28 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 14. " SP28 ,Off-platform Peripheral Access Control 28 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 13. " WP28 ,Off-platform Peripheral Access Control 28 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 12. " TP28 ,Off-platform Peripheral Access Control 28 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 11. " BW29 ,Off-platform Peripheral Access Control 29 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 10. " SP29 ,Off-platform Peripheral Access Control 29 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 9. " WP29 ,Off-platform Peripheral Access Control 29 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 8. " TP29 ,Off-platform Peripheral Access Control 29 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 7. " BW30 ,Off-platform Peripheral Access Control 30 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 6. " SP30 ,Off-platform Peripheral Access Control 30 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 5. " WP30 ,Off-platform Peripheral Access Control 30 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 4. " TP30 ,Off-platform Peripheral Access Control 30 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x0C 3. " BW31 ,Off-platform Peripheral Access Control 31 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x0C 2. " SP31 ,Off-platform Peripheral Access Control 31 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x0C 1. " WP31 ,Off-platform Peripheral Access Control 31 - Write Protect" "Disabled,Enabled" bitfld.long 0x0C 0. " TP31 ,Off-platform Peripheral Access Control 31 - Trusted Protect" "Disabled,Enabled" line.long 0x10 "OPACR4,Off-Platform Peripheral Access Control Register 4" bitfld.long 0x10 31. " BW32 ,Off-platform Peripheral Access Control 32 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x10 30. " SP32 ,Off-platform Peripheral Access Control 32 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x10 29. " WP32 ,Off-platform Peripheral Access Control 32 - Write Protect" "Disabled,Enabled" bitfld.long 0x10 28. " TP32 ,Off-platform Peripheral Access Control 32 - Trusted Protect" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " BW33 ,Off-platform Peripheral Access Control 33 - Writes allowed to be buffered" "Not allowed,Allowed" bitfld.long 0x10 26. " SP33 ,Off-platform Peripheral Access Control 33 - Supervisor Protect" "Disabled,Enabled" bitfld.long 0x10 25. " WP33 ,Off-platform Peripheral Access Control 33 - Write Protect" "Disabled,Enabled" bitfld.long 0x10 24. " TP33 ,Off-platform Peripheral Access Control 33 - Trusted Protect" "Disabled,Enabled" width 0xB tree.end tree.end tree "ASRC (Asynchronous Sample Rate Converter)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02034000 width 15. group.long 0x00++0x07 line.long 0x00 "ASRC_ASRCTR,ASRC Control Register" bitfld.long 0x00 22. " ATSC ,ASRC Pair C Automatic Selection For Processing Options" "Manual,Automatic" bitfld.long 0x00 21. " ATSB ,ASRC Pair B Automatic Selection For Processing Options" "Manual,Automatic" bitfld.long 0x00 20. " ATSA ,ASRC Pair A Automatic Selection For Processing Options" "Manual,Automatic" bitfld.long 0x00 17.--18. " IDRC_USRC ,Ratio for Pair C" ",,ASRC internal,ASRIDRH/LC" textline " " bitfld.long 0x00 15.--16. " IDRB_USRB ,Ratio for Pair B" ",,ASRC internal,ASRIDRH/LB" bitfld.long 0x00 13.--14. " IDRA_USRA ,Ratio for Pair A" ",,ASRC internal,ASRIDRH/LA" bitfld.long 0x00 4. " SRST ,Software Reset" "No effect,Reset" bitfld.long 0x00 3. " ASREC ,ASRC Enable C" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ASREB ,ASRC Enable B" "Disabled,Enabled" bitfld.long 0x00 1. " ASREA ,ASRC Enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC Enable" "Disabled,Enabled" line.long 0x04 "ASRC_ASRIER,ASRC Interrupt Enable Register" bitfld.long 0x04 7. " AFPWE ,FP in Wait State Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 6. " AOLIE ,Overload Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " ADOEC ,Data Output C Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 4. " ADOEB ,Data Output B Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " ADOEA ,Data Output A Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " ADIEC ,Data Input C Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 1. " ADIEB ,Data Input B Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " ADIEA ,Data Input A Interrupt Enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "ASRC_ASRCNCR,ASRC Channel Number Configuration Register" bitfld.long 0x00 8.--11. " ANCC ,Number of C Channels" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 4.--7. " ANCB ,Number of B Channels" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 0.--3. " ANCA ,Number of A Channels" "0,1,2,3,4,5,6,7,8,9,10,?..." group.long 0x10++0x0F line.long 0x00 "ASRC_ASRCFG,ASRC Filter Configuration Status Register" rbitfld.long 0x00 23. " INIRQC ,Initialization for Conversion Pair C is served" "Not served,Served" rbitfld.long 0x00 22. " INIRQB ,Initialization for Conversion Pair B is served" "Not served,Served" rbitfld.long 0x00 21. " INIRQA ,Initialization for Conversion Pair A is served" "Not served,Served" bitfld.long 0x00 20. " NDPRC ,Not Use Default Parameters for RAM-stored Parameters For Conversion Pair C" "Default,Not default" textline " " bitfld.long 0x00 19. " NDPRB ,Not Use Default Parameters for RAM-stored Parameters For Conversion Pair B" "Default,Not default" bitfld.long 0x00 18. " NDPRA ,Not Use Default Parameters for RAM-stored Parameters For Conversion Pair A" "Default,Not default" bitfld.long 0x00 16.--17. " POSTMODC ,Post-Processing Configuration for Conversion Pair C" "Upsampling by 2,Direct Connection,Downsampling by 2," bitfld.long 0x00 14.--15. " PREMODC ,Pre-Processing Configuration for Conversion Pair C" "Upsampling by 2,Direct Connection,Downsampling by 2,Passthrough" textline " " bitfld.long 0x00 12.--13. " POSTMODB ,Post-Processing Configuration for Conversion Pair B" "Upsampling by 2,Direct Connection,Downsampling by 2," bitfld.long 0x00 10.--11. " PREMODB ,Pre-Processing Configuration for Conversion Pair B" "Upsampling by 2,Direct Connection,Downsampling by 2,Passthrough" bitfld.long 0x00 8.--9. " POSTMODA ,Post-Processing Configuration for Conversion Pair A" "Upsampling by 2,Direct Connection,Downsampling by 2," bitfld.long 0x00 6.--7. " PREMODA ,Pre-Processing Configuration for Conversion Pair A" "Upsampling by 2,Direct Connection,Downsampling by 2,Passthrough" line.long 0x04 "ASRC_ASRCSR,ASRC Clock Source Register" bitfld.long 0x04 20.--23. " AOCSC ,Output Clock Source C" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" bitfld.long 0x04 16.--19. " AOCSB ,Output Clock Source B" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" bitfld.long 0x04 12.--15. " AOCSA ,Output Clock Source A" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" bitfld.long 0x04 8.--11. " AICSC ,Input Clock Source C" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" textline " " bitfld.long 0x04 4.--7. " AICSB ,Input Clock Source B" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" bitfld.long 0x04 0.--3. " AICSA ,Input Clock Source A" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" line.long 0x08 "ASRC_ASRCDR1,ASRC Clock Divider Register 1" bitfld.long 0x08 21.--23. " AOCDB ,Output Clock Divider B" "1,2,3,4,5,6,7,8" bitfld.long 0x08 18.--20. " AOCPB ,Output Clock Prescaler B" "1,2,4,8,16,32,64,128" bitfld.long 0x08 15.--17. " AOCDA ,Output Clock Divider A" "1,2,3,4,5,6,7,8" bitfld.long 0x08 12.--14. " AOCPA ,Output Clock Prescaler A" "1,2,4,8,16,32,64,128" textline " " bitfld.long 0x08 9.--11. " AICDB ,Input Clock Divider B" "1,2,3,4,5,6,7,8" bitfld.long 0x08 6.--8. " AICPB ,Input Clock Prescaler B" "1,2,4,8,16,32,64,128" bitfld.long 0x08 3.--5. " AICDA ,Input Clock Divider A" "1,2,3,4,5,6,7,8" bitfld.long 0x08 0.--2. " AICPA ,Input Clock Prescaler A" "1,2,4,8,16,32,64,128" line.long 0x0C "ASRC_ASRCDR2,ASRC Clock Divider Register 2" bitfld.long 0x0C 9.--11. " AOCDC ,Output Clock Divider C" "1,2,3,4,5,6,7,8" bitfld.long 0x0C 6.--8. " AOCPC ,Output Clock Prescaler C" "1,2,4,8,16,32,64,128" bitfld.long 0x0C 3.--5. " AICDC ,Input Clock Divider C" "1,2,3,4,5,6,7,8" bitfld.long 0x0C 0.--2. " AICPC ,Input Clock Prescaler C" "1,2,4,8,16,32,64,128" rgroup.long 0x20++0x03 line.long 0x00 "ASRC_ASRSTR,ASRC Status Register" bitfld.long 0x00 21. " DSLCNT ,DSL Counter Input to FIFO ready" "Not ready,Ready" bitfld.long 0x00 20. " ATQOL ,Task Queue FIFO overload" "No overload,Overload" bitfld.long 0x00 19. " AOOLC ,Pair C Output Task Overload" "No overload,Overload" bitfld.long 0x00 18. " AOOLB ,Pair B Output Task Overload" "No overload,Overload" textline " " bitfld.long 0x00 17. " AOOLA ,Pair A Output Task Overload" "No overload,Overload" bitfld.long 0x00 16. " AIOLC ,Pair C Input Task Overload" "No overload,Overload" bitfld.long 0x00 15. " AIOLB ,Pair B Input Task Overload" "No overload,Overload" bitfld.long 0x00 14. " AIOLA ,Pair A Input Task Overload" "No overload,Overload" textline " " bitfld.long 0x00 13. " AODOC ,Output Data Buffer C has overflowed" "No overflow,Overflow" bitfld.long 0x00 12. " AODOB ,Output Data Buffer B has overflowed" "No overflow,Overflow" bitfld.long 0x00 11. " AODOA ,Output Data Buffer A has overflowed" "No overflow,Overflow" bitfld.long 0x00 10. " AIDUC ,Input Data Buffer C has underflowed" "No underflow,Underflow" textline " " bitfld.long 0x00 9. " AIDUB ,Input Data Buffer B has underflowed" "No underflow,Underflow" bitfld.long 0x00 8. " AIDUA ,Input Data Buffer A has underflowed" "No underflow,Underflow" bitfld.long 0x00 7. " FPWT ,FP is in wait states" "Not in wait,In wait" bitfld.long 0x00 6. " AOLE ,Overload Error Flag" "No error,Error" textline " " bitfld.long 0x00 5. " AODFC ,Relation between data sizes in Output Data Buffer C and threshold" "<=,>" bitfld.long 0x00 4. " AODFB ,Relation between data sizes in Output Data Buffer B and threshold" "<=,>" bitfld.long 0x00 3. " AODFA ,Relation between data sizes in Output Data Buffer A and threshold" "<=,>" bitfld.long 0x00 2. " AIDEC ,Relation between data sizes in Input Data Buffer C and threshold" ">=,<" textline " " bitfld.long 0x00 1. " AIDEB ,Relation between data sizes in Input Data Buffer B and threshold" ">=,<" bitfld.long 0x00 0. " AIDEA ,Relation between data sizes in Input Data Buffer A and threshold" ">=,<" bitfld.long 0x00 0. " AIDEA ,Relation between data sizes in Input Data Buffer A and threshold" ">=,<" textline "" group.long 0x40++0x13 line.long 0x00 "ASRC_ASRPM1,ASRC Parameter Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x44++0x13 line.long 0x00 "ASRC_ASRPM2,ASRC Parameter Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x48++0x13 line.long 0x00 "ASRC_ASRPM3,ASRC Parameter Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x4C++0x13 line.long 0x00 "ASRC_ASRPM4,ASRC Parameter Register 4" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x50++0x13 line.long 0x00 "ASRC_ASRPM5,ASRC Parameter Register 5" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x54++0x03 line.long 0x00 "ASRC_ASRTFR1,ASRC Task Queue FIFO Register 1" hexmask.long.byte 0x00 13.--19. 1. " TF_FILL ,Current number of entries in task queue FIFO" hexmask.long.byte 0x00 6.--12. 1. " TF_BASE ,Base address for task queue FIFO" group.long 0x5C++0x03 line.long 0x00 "ASRC_ASRCCR,ASRC Channel Counter Register" bitfld.long 0x00 20.--23. " ACOC ,The channel counter for Pair C's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 16.--19. " ACOB ,The channel counter for Pair B's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 12.--15. " ACOA ,The channel counter for Pair A's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 8.--11. " ACIC ,The channel counter for Pair C's input FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 4.--7. " ACIB ,The channel counter for Pair B's input FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 0.--3. " ACIA ,The channel counter for Pair A's input FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." wgroup.long 0x60++0x03 line.long 0x00 "ASRC_ASRDIA,ASRC Data Input Register for Pair A" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long 0x64++0x03 line.long 0x00 "ASRC_ASRDOA,ASRC Data Output Register for Pair A" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" wgroup.long 0x68++0x03 line.long 0x00 "ASRC_ASRDIB,ASRC Data Input Register for Pair B" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long 0x6C++0x03 line.long 0x00 "ASRC_ASRDOB,ASRC Data Output Register for Pair B" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" wgroup.long 0x70++0x03 line.long 0x00 "ASRC_ASRDIC,ASRC Data Input Register for Pair C" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long 0x74++0x03 line.long 0x00 "ASRC_ASRDOC,ASRC Data Output Register for Pair C" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" textline "" if (((per.l(ad:0x02034000))&0x6000)==0x6000) group.long 0x80++0x07 line.long 0x00 "ASRC_ASRIDRHA,ASRC Ideal Ratio for Pair A-High Part" hexmask.long.byte 0x00 0.--7. 1. " IDRATIOA[31:24] ,High part of ideal ratio value for pair A" line.long 0x04 "ASRC_ASRIDRLA,ASRC Ideal Ratio for Pair A-Low Part" hexmask.long 0x04 0.--23. 1. " IDRATIOA[23:0] ,Low part of ideal ratio value for pair A" else hgroup.long 0x80++0x07 hide.long 0x00 "ASRC_ASRIDRHA,ASRC Ideal Ratio for Pair A-High Part" hide.long 0x04 "ASRC_ASRIDRLA,ASRC Ideal Ratio for Pair A-Low Part" endif if (((per.l(ad:0x02034000))&0x18000)==0x18000) group.long 0x88++0x07 line.long 0x00 "ASRC_ASRIDRHB,ASRC Ideal Ratio for Pair B-High Part" hexmask.long.byte 0x00 0.--7. 1. " IDRATIOB[31:24] ,High part of ideal ratio value for pair B" line.long 0x04 "ASRC_ASRIDRLB,ASRC Ideal Ratio for Pair B-Low Part" hexmask.long 0x04 0.--23. 1. " IDRATIOB[23:0] ,Low part of ideal ratio value for pair B" else hgroup.long 0x88++0x07 hide.long 0x00 "ASRC_ASRIDRHB,ASRC Ideal Ratio for Pair B-High Part" hide.long 0x04 "ASRC_ASRIDRLB,ASRC Ideal Ratio for Pair B-Low Part" endif if (((per.l(ad:0x02034000))&0x60000)==0x60000) group.long 0x90++0x07 line.long 0x00 "ASRC_ASRIDRHC,ASRC Ideal Ratio for Pair C-High Part" hexmask.long.byte 0x00 0.--7. 1. " IDRATIOC[31:24] ,High part of ideal ratio value for pair C" line.long 0x04 "ASRC_ASRIDRLC,ASRC Ideal Ratio for Pair C-Low Part" hexmask.long 0x04 0.--23. 1. " IDRATIOC[23:0] ,Low part of ideal ratio value for pair C" else hgroup.long 0x90++0x07 hide.long 0x00 "ASRC_ASRIDRHC,ASRC Ideal Ratio for Pair C-High Part" hide.long 0x04 "ASRC_ASRIDRLC,ASRC Ideal Ratio for Pair C-Low Part" endif textline " " group.long 0x98++0x0B line.long 0x00 "ASRC_ASR76K,ASRC 76kHz Period in terms of ASRC processing clock" hexmask.long.tbyte 0x00 0.--16. 1. " ASR76K ,Value for the period of the 76kHz sampling clock" line.long 0x04 "ASRC_ASR56K,ASRC 56kHz Period in terms of ASRC processing clock" hexmask.long.tbyte 0x04 0.--16. 1. " ASRC_ASR56K ,Value for the period of the 56kHz sampling clock" line.long 0x08 "ASRC_ASRMCRA,ASRC Misc Control Register for Pair A" bitfld.long 0x08 23. " ZEROBUFA ,Initialization of pair's A buffer when pair A is enabled - zeroize" "Disabled,Enabled" bitfld.long 0x08 22. " EXTTHRSHA ,Use external thresholds for FIFO control of Pair A" "Default,External" bitfld.long 0x08 21. " BUFSTALLA ,Stall Pair A conversion in case of Buffer Near Empty/Full Condition" "Disabled,Enabled" bitfld.long 0x08 20. " BYPASSPOLYA ,Bypass Polyphase Filtering for Pair A" "Disabled,Enabled" textline " " bitfld.long 0x08 12.--17. " OUTFIFO_THRESHOLDA ,The threshold for Pair A's output FIFO per channel" "0,1,2,3,4,5,%d..." bitfld.long 0x08 11. " RSYNIFA ,Re-sync Input FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x08 10. " RSYNOFA ,Re-sync Output FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x08 0.--5. " INFIFO_THRESHOLDA ,The threshold for Pair A's input FIFO per channel" "0,1,2,3,4,5,%d..." rgroup.long 0xA4++0x03 line.long 0x00 "ASRC_ASRFSTA,ASRC FIFO Status Register for Pair A" bitfld.long 0x00 23. " OAFA ,Output FIFO is near Full for Pair A" "Not near full,Near full" hexmask.long.byte 0x00 12.--18. 0x1000 " OUTFIFO_FILLA ,The fillings for Pair A's output FIFO per channel" bitfld.long 0x00 11. " IAEA ,Input FIFO is near Empty for Pair A" "Not near empty,Near empty" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLA ,The fillings for Pair A's input FIFO per channel" group.long 0xA8++0x03 line.long 0x00 "ASRC_ASRMCRB,ASRC Misc Control Register for Pair B" bitfld.long 0x00 23. " ZEROBUFB ,Initialization of pair's B buffer when pair B is enabled - zeroize" "Disabled,Enabled" bitfld.long 0x00 22. " EXTTHRSHB ,Use external thresholds for FIFO control of Pair B" "Default,External" bitfld.long 0x00 21. " BUFSTALLB ,Stall Pair B conversion in case of Buffer Near Empty/Full Condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYB ,Bypass Polyphase Filtering for Pair B" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDB ,The threshold for Pair B's output FIFO per channel" "0,1,2,3,4,5,%d..." bitfld.long 0x00 11. " RSYNIFB ,Re-sync Input FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x00 10. " RSYNOFB ,Re-sync Output FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDB ,The threshold for Pair B's input FIFO per channel" "0,1,2,3,4,5,%d..." rgroup.long 0xAC++0x03 line.long 0x00 "ASRC_ASRFSTB,ASRC FIFO Status Register for Pair B" bitfld.long 0x00 23. " OAFB ,Output FIFO is near Full for Pair B" "Not near full,Near full" hexmask.long.byte 0x00 12.--18. 0x1000 " OUTFIFO_FILLB ,The fillings for Pair B's output FIFO per channel" bitfld.long 0x00 11. " IAEB ,Input FIFO is near Empty for Pair B" "Not near empty,Near empty" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLB ,The fillings for Pair B's input FIFO per channel" group.long 0xB0++0x03 line.long 0x00 "ASRC_ASRMCRC,ASRC Misc Control Register for Pair C" bitfld.long 0x00 23. " ZEROBUFC ,Initialization of pair's C buffer when pair C is enabled - zeroize" "Disabled,Enabled" bitfld.long 0x00 22. " EXTTHRSHC ,Use external thresholds for FIFO control of Pair C" "Default,External" bitfld.long 0x00 21. " BUFSTALLC ,Stall Pair C conversion in case of Buffer Near Empty/Full Condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYC ,Bypass Polyphase Filtering for Pair C" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDC ,The threshold for Pair C's output FIFO per channel" "0,1,2,3,4,5,%d..." bitfld.long 0x00 11. " RSYNIFC ,Re-sync Input FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x00 10. " RSYNOFC ,Re-sync Output FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDC ,The threshold for Pair C's input FIFO per channel" "0,1,2,3,4,5,%d..." rgroup.long 0xB4++0x03 line.long 0x00 "ASRC_ASRFSTC,ASRC FIFO Status Register for Pair C" bitfld.long 0x00 23. " OAFC ,Output FIFO is near Full for Pair C" "Not near full,Near full" hexmask.long.byte 0x00 12.--18. 0x1000 " OUTFIFO_FILLC ,The fillings for Pair C's output FIFO per channel" bitfld.long 0x00 11. " IAEC ,Input FIFO is near Empty for Pair C" "Not near empty,Near empty" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLC ,The fillings for Pair C's input FIFO per channel" textline "" group.long 0xC0++0x0B line.long 0x00 "ASRC_ASRMCR1A,ASRC Misc Control Register 1 for Pair A" bitfld.long 0x00 9.--11. " IWD ,Data Width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x00 8. " IMSB ,Data Alignment of the input FIFO" "LSB,MSB" bitfld.long 0x00 2. " OMSB ,Data Alignment of the output FIFO" "LSB,MSB" bitfld.long 0x00 1. " OSGN ,Sign Extension Option of the output FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " OW16 ,Bit Width Option of the output FIFO" "24-bit,16-bit" line.long 0x04 "ASRC_ASRMCR1B,ASRC Misc Control Register 1 for Pair B" bitfld.long 0x04 9.--11. " IWD ,Data Width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x04 8. " IMSB ,Data Alignment of the input FIFO" "LSB,MSB" bitfld.long 0x04 2. " OMSB ,Data Alignment of the output FIFO" "MSB aligned,LSB aligned" bitfld.long 0x04 1. " OSGN ,Sign Extension Option of the output FIFO" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " OW16 ,Bit Width Option of the output FIFO" "24-bit,16-bit" line.long 0x08 "ASRC_ASRMCR1C,ASRC Misc Control Register 1 for Pair C" bitfld.long 0x08 9.--11. " IWD ,Data Width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x08 8. " IMSB ,Data Alignment of the input FIFO" "LSB,MSB" bitfld.long 0x08 2. " OMSB ,Data Alignment of the output FIFO" "LSB,MSB" bitfld.long 0x08 1. " OSGN ,Sign Extension Option of the output FIFO" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " OW16 ,Bit Width Option of the output FIFO" "24-bit,16-bit" width 0xB else base ad:0x42034000 width 15. group.long 0x00++0x07 line.long 0x00 "ASRC_ASRCTR,ASRC Control Register" bitfld.long 0x00 22. " ATSC ,ASRC Pair C Automatic Selection For Processing Options" "Manual,Automatic" bitfld.long 0x00 21. " ATSB ,ASRC Pair B Automatic Selection For Processing Options" "Manual,Automatic" bitfld.long 0x00 20. " ATSA ,ASRC Pair A Automatic Selection For Processing Options" "Manual,Automatic" bitfld.long 0x00 17.--18. " IDRC_USRC ,Ratio for Pair C" ",,ASRC internal,ASRIDRH/LC" textline " " bitfld.long 0x00 15.--16. " IDRB_USRB ,Ratio for Pair B" ",,ASRC internal,ASRIDRH/LB" bitfld.long 0x00 13.--14. " IDRA_USRA ,Ratio for Pair A" ",,ASRC internal,ASRIDRH/LA" bitfld.long 0x00 4. " SRST ,Software Reset" "No effect,Reset" bitfld.long 0x00 3. " ASREC ,ASRC Enable C" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ASREB ,ASRC Enable B" "Disabled,Enabled" bitfld.long 0x00 1. " ASREA ,ASRC Enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC Enable" "Disabled,Enabled" line.long 0x04 "ASRC_ASRIER,ASRC Interrupt Enable Register" bitfld.long 0x04 7. " AFPWE ,FP in Wait State Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 6. " AOLIE ,Overload Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " ADOEC ,Data Output C Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 4. " ADOEB ,Data Output B Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " ADOEA ,Data Output A Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " ADIEC ,Data Input C Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 1. " ADIEB ,Data Input B Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " ADIEA ,Data Input A Interrupt Enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "ASRC_ASRCNCR,ASRC Channel Number Configuration Register" bitfld.long 0x00 8.--11. " ANCC ,Number of C Channels" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 4.--7. " ANCB ,Number of B Channels" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 0.--3. " ANCA ,Number of A Channels" "0,1,2,3,4,5,6,7,8,9,10,?..." group.long 0x10++0x0F line.long 0x00 "ASRC_ASRCFG,ASRC Filter Configuration Status Register" rbitfld.long 0x00 23. " INIRQC ,Initialization for Conversion Pair C is served" "Not served,Served" rbitfld.long 0x00 22. " INIRQB ,Initialization for Conversion Pair B is served" "Not served,Served" rbitfld.long 0x00 21. " INIRQA ,Initialization for Conversion Pair A is served" "Not served,Served" bitfld.long 0x00 20. " NDPRC ,Not Use Default Parameters for RAM-stored Parameters For Conversion Pair C" "Default,Not default" textline " " bitfld.long 0x00 19. " NDPRB ,Not Use Default Parameters for RAM-stored Parameters For Conversion Pair B" "Default,Not default" bitfld.long 0x00 18. " NDPRA ,Not Use Default Parameters for RAM-stored Parameters For Conversion Pair A" "Default,Not default" bitfld.long 0x00 16.--17. " POSTMODC ,Post-Processing Configuration for Conversion Pair C" "Upsampling by 2,Direct Connection,Downsampling by 2," bitfld.long 0x00 14.--15. " PREMODC ,Pre-Processing Configuration for Conversion Pair C" "Upsampling by 2,Direct Connection,Downsampling by 2,Passthrough" textline " " bitfld.long 0x00 12.--13. " POSTMODB ,Post-Processing Configuration for Conversion Pair B" "Upsampling by 2,Direct Connection,Downsampling by 2," bitfld.long 0x00 10.--11. " PREMODB ,Pre-Processing Configuration for Conversion Pair B" "Upsampling by 2,Direct Connection,Downsampling by 2,Passthrough" bitfld.long 0x00 8.--9. " POSTMODA ,Post-Processing Configuration for Conversion Pair A" "Upsampling by 2,Direct Connection,Downsampling by 2," bitfld.long 0x00 6.--7. " PREMODA ,Pre-Processing Configuration for Conversion Pair A" "Upsampling by 2,Direct Connection,Downsampling by 2,Passthrough" line.long 0x04 "ASRC_ASRCSR,ASRC Clock Source Register" bitfld.long 0x04 20.--23. " AOCSC ,Output Clock Source C" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" bitfld.long 0x04 16.--19. " AOCSB ,Output Clock Source B" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" bitfld.long 0x04 12.--15. " AOCSA ,Output Clock Source A" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" bitfld.long 0x04 8.--11. " AICSC ,Input Clock Source C" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" textline " " bitfld.long 0x04 4.--7. " AICSB ,Input Clock Source B" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" bitfld.long 0x04 0.--3. " AICSA ,Input Clock Source A" "ESAI RX,SSI-1 RX/SAI1 RX,SSI-2 RX,SSI-3 RX,SAI1 RX/SPDIF RX,MLB,ASRC_EXT_CLK,SAI1 RX,ESAI TX,SSI-1 TX/SAI1 TX,SSI-2 TX,SSI-3 TX,SAI1 TX/SPDIF TX,CCM_CDCDR,SAI1 TX,Disabled" line.long 0x08 "ASRC_ASRCDR1,ASRC Clock Divider Register 1" bitfld.long 0x08 21.--23. " AOCDB ,Output Clock Divider B" "1,2,3,4,5,6,7,8" bitfld.long 0x08 18.--20. " AOCPB ,Output Clock Prescaler B" "1,2,4,8,16,32,64,128" bitfld.long 0x08 15.--17. " AOCDA ,Output Clock Divider A" "1,2,3,4,5,6,7,8" bitfld.long 0x08 12.--14. " AOCPA ,Output Clock Prescaler A" "1,2,4,8,16,32,64,128" textline " " bitfld.long 0x08 9.--11. " AICDB ,Input Clock Divider B" "1,2,3,4,5,6,7,8" bitfld.long 0x08 6.--8. " AICPB ,Input Clock Prescaler B" "1,2,4,8,16,32,64,128" bitfld.long 0x08 3.--5. " AICDA ,Input Clock Divider A" "1,2,3,4,5,6,7,8" bitfld.long 0x08 0.--2. " AICPA ,Input Clock Prescaler A" "1,2,4,8,16,32,64,128" line.long 0x0C "ASRC_ASRCDR2,ASRC Clock Divider Register 2" bitfld.long 0x0C 9.--11. " AOCDC ,Output Clock Divider C" "1,2,3,4,5,6,7,8" bitfld.long 0x0C 6.--8. " AOCPC ,Output Clock Prescaler C" "1,2,4,8,16,32,64,128" bitfld.long 0x0C 3.--5. " AICDC ,Input Clock Divider C" "1,2,3,4,5,6,7,8" bitfld.long 0x0C 0.--2. " AICPC ,Input Clock Prescaler C" "1,2,4,8,16,32,64,128" rgroup.long 0x20++0x03 line.long 0x00 "ASRC_ASRSTR,ASRC Status Register" bitfld.long 0x00 21. " DSLCNT ,DSL Counter Input to FIFO ready" "Not ready,Ready" bitfld.long 0x00 20. " ATQOL ,Task Queue FIFO overload" "No overload,Overload" bitfld.long 0x00 19. " AOOLC ,Pair C Output Task Overload" "No overload,Overload" bitfld.long 0x00 18. " AOOLB ,Pair B Output Task Overload" "No overload,Overload" textline " " bitfld.long 0x00 17. " AOOLA ,Pair A Output Task Overload" "No overload,Overload" bitfld.long 0x00 16. " AIOLC ,Pair C Input Task Overload" "No overload,Overload" bitfld.long 0x00 15. " AIOLB ,Pair B Input Task Overload" "No overload,Overload" bitfld.long 0x00 14. " AIOLA ,Pair A Input Task Overload" "No overload,Overload" textline " " bitfld.long 0x00 13. " AODOC ,Output Data Buffer C has overflowed" "No overflow,Overflow" bitfld.long 0x00 12. " AODOB ,Output Data Buffer B has overflowed" "No overflow,Overflow" bitfld.long 0x00 11. " AODOA ,Output Data Buffer A has overflowed" "No overflow,Overflow" bitfld.long 0x00 10. " AIDUC ,Input Data Buffer C has underflowed" "No underflow,Underflow" textline " " bitfld.long 0x00 9. " AIDUB ,Input Data Buffer B has underflowed" "No underflow,Underflow" bitfld.long 0x00 8. " AIDUA ,Input Data Buffer A has underflowed" "No underflow,Underflow" bitfld.long 0x00 7. " FPWT ,FP is in wait states" "Not in wait,In wait" bitfld.long 0x00 6. " AOLE ,Overload Error Flag" "No error,Error" textline " " bitfld.long 0x00 5. " AODFC ,Relation between data sizes in Output Data Buffer C and threshold" "<=,>" bitfld.long 0x00 4. " AODFB ,Relation between data sizes in Output Data Buffer B and threshold" "<=,>" bitfld.long 0x00 3. " AODFA ,Relation between data sizes in Output Data Buffer A and threshold" "<=,>" bitfld.long 0x00 2. " AIDEC ,Relation between data sizes in Input Data Buffer C and threshold" ">=,<" textline " " bitfld.long 0x00 1. " AIDEB ,Relation between data sizes in Input Data Buffer B and threshold" ">=,<" bitfld.long 0x00 0. " AIDEA ,Relation between data sizes in Input Data Buffer A and threshold" ">=,<" bitfld.long 0x00 0. " AIDEA ,Relation between data sizes in Input Data Buffer A and threshold" ">=,<" textline "" group.long 0x40++0x13 line.long 0x00 "ASRC_ASRPM1,ASRC Parameter Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x44++0x13 line.long 0x00 "ASRC_ASRPM2,ASRC Parameter Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x48++0x13 line.long 0x00 "ASRC_ASRPM3,ASRC Parameter Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x4C++0x13 line.long 0x00 "ASRC_ASRPM4,ASRC Parameter Register 4" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x50++0x13 line.long 0x00 "ASRC_ASRPM5,ASRC Parameter Register 5" hexmask.long.tbyte 0x00 0.--23. 1. " PARAM_VALUE ,Recommend Parameter Value" group.long 0x54++0x03 line.long 0x00 "ASRC_ASRTFR1,ASRC Task Queue FIFO Register 1" hexmask.long.byte 0x00 13.--19. 1. " TF_FILL ,Current number of entries in task queue FIFO" hexmask.long.byte 0x00 6.--12. 1. " TF_BASE ,Base address for task queue FIFO" group.long 0x5C++0x03 line.long 0x00 "ASRC_ASRCCR,ASRC Channel Counter Register" bitfld.long 0x00 20.--23. " ACOC ,The channel counter for Pair C's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 16.--19. " ACOB ,The channel counter for Pair B's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 12.--15. " ACOA ,The channel counter for Pair A's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 8.--11. " ACIC ,The channel counter for Pair C's input FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 4.--7. " ACIB ,The channel counter for Pair B's input FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 0.--3. " ACIA ,The channel counter for Pair A's input FIFO" "0,1,2,3,4,5,6,7,8,9,10,?..." wgroup.long 0x60++0x03 line.long 0x00 "ASRC_ASRDIA,ASRC Data Input Register for Pair A" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long 0x64++0x03 line.long 0x00 "ASRC_ASRDOA,ASRC Data Output Register for Pair A" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" wgroup.long 0x68++0x03 line.long 0x00 "ASRC_ASRDIB,ASRC Data Input Register for Pair B" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long 0x6C++0x03 line.long 0x00 "ASRC_ASRDOB,ASRC Data Output Register for Pair B" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" wgroup.long 0x70++0x03 line.long 0x00 "ASRC_ASRDIC,ASRC Data Input Register for Pair C" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long 0x74++0x03 line.long 0x00 "ASRC_ASRDOC,ASRC Data Output Register for Pair C" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" textline "" if (((per.l(ad:0x42034000))&0x6000)==0x6000) group.long 0x80++0x07 line.long 0x00 "ASRC_ASRIDRHA,ASRC Ideal Ratio for Pair A-High Part" hexmask.long.byte 0x00 0.--7. 1. " IDRATIOA[31:24] ,High part of ideal ratio value for pair A" line.long 0x04 "ASRC_ASRIDRLA,ASRC Ideal Ratio for Pair A-Low Part" hexmask.long 0x04 0.--23. 1. " IDRATIOA[23:0] ,Low part of ideal ratio value for pair A" else hgroup.long 0x80++0x07 hide.long 0x00 "ASRC_ASRIDRHA,ASRC Ideal Ratio for Pair A-High Part" hide.long 0x04 "ASRC_ASRIDRLA,ASRC Ideal Ratio for Pair A-Low Part" endif if (((per.l(ad:0x42034000))&0x18000)==0x18000) group.long 0x88++0x07 line.long 0x00 "ASRC_ASRIDRHB,ASRC Ideal Ratio for Pair B-High Part" hexmask.long.byte 0x00 0.--7. 1. " IDRATIOB[31:24] ,High part of ideal ratio value for pair B" line.long 0x04 "ASRC_ASRIDRLB,ASRC Ideal Ratio for Pair B-Low Part" hexmask.long 0x04 0.--23. 1. " IDRATIOB[23:0] ,Low part of ideal ratio value for pair B" else hgroup.long 0x88++0x07 hide.long 0x00 "ASRC_ASRIDRHB,ASRC Ideal Ratio for Pair B-High Part" hide.long 0x04 "ASRC_ASRIDRLB,ASRC Ideal Ratio for Pair B-Low Part" endif if (((per.l(ad:0x42034000))&0x60000)==0x60000) group.long 0x90++0x07 line.long 0x00 "ASRC_ASRIDRHC,ASRC Ideal Ratio for Pair C-High Part" hexmask.long.byte 0x00 0.--7. 1. " IDRATIOC[31:24] ,High part of ideal ratio value for pair C" line.long 0x04 "ASRC_ASRIDRLC,ASRC Ideal Ratio for Pair C-Low Part" hexmask.long 0x04 0.--23. 1. " IDRATIOC[23:0] ,Low part of ideal ratio value for pair C" else hgroup.long 0x90++0x07 hide.long 0x00 "ASRC_ASRIDRHC,ASRC Ideal Ratio for Pair C-High Part" hide.long 0x04 "ASRC_ASRIDRLC,ASRC Ideal Ratio for Pair C-Low Part" endif textline " " group.long 0x98++0x0B line.long 0x00 "ASRC_ASR76K,ASRC 76kHz Period in terms of ASRC processing clock" hexmask.long.tbyte 0x00 0.--16. 1. " ASR76K ,Value for the period of the 76kHz sampling clock" line.long 0x04 "ASRC_ASR56K,ASRC 56kHz Period in terms of ASRC processing clock" hexmask.long.tbyte 0x04 0.--16. 1. " ASRC_ASR56K ,Value for the period of the 56kHz sampling clock" line.long 0x08 "ASRC_ASRMCRA,ASRC Misc Control Register for Pair A" bitfld.long 0x08 23. " ZEROBUFA ,Initialization of pair's A buffer when pair A is enabled - zeroize" "Disabled,Enabled" bitfld.long 0x08 22. " EXTTHRSHA ,Use external thresholds for FIFO control of Pair A" "Default,External" bitfld.long 0x08 21. " BUFSTALLA ,Stall Pair A conversion in case of Buffer Near Empty/Full Condition" "Disabled,Enabled" bitfld.long 0x08 20. " BYPASSPOLYA ,Bypass Polyphase Filtering for Pair A" "Disabled,Enabled" textline " " bitfld.long 0x08 12.--17. " OUTFIFO_THRESHOLDA ,The threshold for Pair A's output FIFO per channel" "0,1,2,3,4,5,%d..." bitfld.long 0x08 11. " RSYNIFA ,Re-sync Input FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x08 10. " RSYNOFA ,Re-sync Output FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x08 0.--5. " INFIFO_THRESHOLDA ,The threshold for Pair A's input FIFO per channel" "0,1,2,3,4,5,%d..." rgroup.long 0xA4++0x03 line.long 0x00 "ASRC_ASRFSTA,ASRC FIFO Status Register for Pair A" bitfld.long 0x00 23. " OAFA ,Output FIFO is near Full for Pair A" "Not near full,Near full" hexmask.long.byte 0x00 12.--18. 0x1000 " OUTFIFO_FILLA ,The fillings for Pair A's output FIFO per channel" bitfld.long 0x00 11. " IAEA ,Input FIFO is near Empty for Pair A" "Not near empty,Near empty" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLA ,The fillings for Pair A's input FIFO per channel" group.long 0xA8++0x03 line.long 0x00 "ASRC_ASRMCRB,ASRC Misc Control Register for Pair B" bitfld.long 0x00 23. " ZEROBUFB ,Initialization of pair's B buffer when pair B is enabled - zeroize" "Disabled,Enabled" bitfld.long 0x00 22. " EXTTHRSHB ,Use external thresholds for FIFO control of Pair B" "Default,External" bitfld.long 0x00 21. " BUFSTALLB ,Stall Pair B conversion in case of Buffer Near Empty/Full Condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYB ,Bypass Polyphase Filtering for Pair B" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDB ,The threshold for Pair B's output FIFO per channel" "0,1,2,3,4,5,%d..." bitfld.long 0x00 11. " RSYNIFB ,Re-sync Input FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x00 10. " RSYNOFB ,Re-sync Output FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDB ,The threshold for Pair B's input FIFO per channel" "0,1,2,3,4,5,%d..." rgroup.long 0xAC++0x03 line.long 0x00 "ASRC_ASRFSTB,ASRC FIFO Status Register for Pair B" bitfld.long 0x00 23. " OAFB ,Output FIFO is near Full for Pair B" "Not near full,Near full" hexmask.long.byte 0x00 12.--18. 0x1000 " OUTFIFO_FILLB ,The fillings for Pair B's output FIFO per channel" bitfld.long 0x00 11. " IAEB ,Input FIFO is near Empty for Pair B" "Not near empty,Near empty" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLB ,The fillings for Pair B's input FIFO per channel" group.long 0xB0++0x03 line.long 0x00 "ASRC_ASRMCRC,ASRC Misc Control Register for Pair C" bitfld.long 0x00 23. " ZEROBUFC ,Initialization of pair's C buffer when pair C is enabled - zeroize" "Disabled,Enabled" bitfld.long 0x00 22. " EXTTHRSHC ,Use external thresholds for FIFO control of Pair C" "Default,External" bitfld.long 0x00 21. " BUFSTALLC ,Stall Pair C conversion in case of Buffer Near Empty/Full Condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYC ,Bypass Polyphase Filtering for Pair C" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDC ,The threshold for Pair C's output FIFO per channel" "0,1,2,3,4,5,%d..." bitfld.long 0x00 11. " RSYNIFC ,Re-sync Input FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x00 10. " RSYNOFC ,Re-sync Output FIFO Channel Counter" "Disabled,Enabled" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDC ,The threshold for Pair C's input FIFO per channel" "0,1,2,3,4,5,%d..." rgroup.long 0xB4++0x03 line.long 0x00 "ASRC_ASRFSTC,ASRC FIFO Status Register for Pair C" bitfld.long 0x00 23. " OAFC ,Output FIFO is near Full for Pair C" "Not near full,Near full" hexmask.long.byte 0x00 12.--18. 0x1000 " OUTFIFO_FILLC ,The fillings for Pair C's output FIFO per channel" bitfld.long 0x00 11. " IAEC ,Input FIFO is near Empty for Pair C" "Not near empty,Near empty" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLC ,The fillings for Pair C's input FIFO per channel" textline "" group.long 0xC0++0x0B line.long 0x00 "ASRC_ASRMCR1A,ASRC Misc Control Register 1 for Pair A" bitfld.long 0x00 9.--11. " IWD ,Data Width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x00 8. " IMSB ,Data Alignment of the input FIFO" "LSB,MSB" bitfld.long 0x00 2. " OMSB ,Data Alignment of the output FIFO" "LSB,MSB" bitfld.long 0x00 1. " OSGN ,Sign Extension Option of the output FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " OW16 ,Bit Width Option of the output FIFO" "24-bit,16-bit" line.long 0x04 "ASRC_ASRMCR1B,ASRC Misc Control Register 1 for Pair B" bitfld.long 0x04 9.--11. " IWD ,Data Width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x04 8. " IMSB ,Data Alignment of the input FIFO" "LSB,MSB" bitfld.long 0x04 2. " OMSB ,Data Alignment of the output FIFO" "MSB aligned,LSB aligned" bitfld.long 0x04 1. " OSGN ,Sign Extension Option of the output FIFO" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " OW16 ,Bit Width Option of the output FIFO" "24-bit,16-bit" line.long 0x08 "ASRC_ASRMCR1C,ASRC Misc Control Register 1 for Pair C" bitfld.long 0x08 9.--11. " IWD ,Data Width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x08 8. " IMSB ,Data Alignment of the input FIFO" "LSB,MSB" bitfld.long 0x08 2. " OMSB ,Data Alignment of the output FIFO" "LSB,MSB" bitfld.long 0x08 1. " OSGN ,Sign Extension Option of the output FIFO" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " OW16 ,Bit Width Option of the output FIFO" "24-bit,16-bit" width 0xB endif tree.end tree "AUDMUX (Digital Audio Multiplexer)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021D8000 else base ad:0x421D8000 endif width 13. group.long 0x00++0x37 line.long 0x00 "AUDMUX_PTCR1,Port Timing Control Register 1" bitfld.long 0x00 31. " TFS_DIR ,Transmit Frame Sync Direction Control" "Input,Output" bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select [3]" "TXFS,RXFS" bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output" bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TXC,RXC" bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x00 21. " RFS_DIR ,Receive Frame Sync Direction Control" "Input,Output" bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select." "TXFS,RXFS" bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output" bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TXC,RXC" bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous" line.long 0x04 "AUDMUX_PDCR1,Port Data Control Register 1" bitfld.long 0x04 13.--15. " RXDSEL ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "Disabled,Enabled" bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network" textline " " bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded" bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded" bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded" bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded" textline " " bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded" bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded" bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded" bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded" textline " " line.long 0x08 "AUDMUX_PTCR2,Port Timing Control Register 2" bitfld.long 0x08 31. " TFS_DIR ,Transmit Frame Sync Direction Control" "Input,Output" bitfld.long 0x08 30. " TFSEL[3] ,Transmit Frame Sync Select [3]" "TXFS,RXFS" bitfld.long 0x08 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x08 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output" bitfld.long 0x08 25. " TCSEL[3] ,Transmit Clock Select" "TXC,RXC" bitfld.long 0x08 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x08 21. " RFS_DIR ,Receive Frame Sync Direction Control" "Input,Output" bitfld.long 0x08 20. " RFSEL[3] ,Receive Frame Sync Select." "TXFS,RXFS" bitfld.long 0x08 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x08 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output" bitfld.long 0x08 15. " RCSEL[3] ,Receive Clock Select" "TXC,RXC" bitfld.long 0x08 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x08 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous" line.long 0x0C "AUDMUX_PDCR2,Port Data Control Register 2" bitfld.long 0x0C 13.--15. " RXDSEL ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," bitfld.long 0x0C 12. " TXRXEN ,Transmit/Receive Switch Enable" "Disabled,Enabled" bitfld.long 0x0C 8. " MODE ,Mode Select" "Normal,Internal Network" textline " " bitfld.long 0x0C 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded" bitfld.long 0x0C 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded" bitfld.long 0x0C 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded" bitfld.long 0x0C 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded" textline " " bitfld.long 0x0C 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded" bitfld.long 0x0C 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded" bitfld.long 0x0C 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded" bitfld.long 0x0C 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded" textline " " line.long 0x10 "AUDMUX_PTCR3,Port Timing Control Register 3" bitfld.long 0x10 31. " TFS_DIR ,Transmit Frame Sync Direction Control" "Input,Output" bitfld.long 0x10 30. " TFSEL[3] ,Transmit Frame Sync Select [3]" "TXFS,RXFS" bitfld.long 0x10 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x10 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output" bitfld.long 0x10 25. " TCSEL[3] ,Transmit Clock Select" "TXC,RXC" bitfld.long 0x10 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x10 21. " RFS_DIR ,Receive Frame Sync Direction Control" "Input,Output" bitfld.long 0x10 20. " RFSEL[3] ,Receive Frame Sync Select." "TXFS,RXFS" bitfld.long 0x10 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x10 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output" bitfld.long 0x10 15. " RCSEL[3] ,Receive Clock Select" "TXC,RXC" bitfld.long 0x10 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x10 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous" line.long 0x14 "AUDMUX_PDCR3,Port Data Control Register 3" bitfld.long 0x14 13.--15. " RXDSEL ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," bitfld.long 0x14 12. " TXRXEN ,Transmit/Receive Switch Enable" "Disabled,Enabled" bitfld.long 0x14 8. " MODE ,Mode Select" "Normal,Internal Network" textline " " bitfld.long 0x14 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded" bitfld.long 0x14 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded" bitfld.long 0x14 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded" bitfld.long 0x14 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded" textline " " bitfld.long 0x14 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded" bitfld.long 0x14 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded" bitfld.long 0x14 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded" bitfld.long 0x14 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded" textline " " line.long 0x18 "AUDMUX_PTCR4,Port Timing Control Register 4" bitfld.long 0x18 31. " TFS_DIR ,Transmit Frame Sync Direction Control" "Input,Output" bitfld.long 0x18 30. " TFSEL[3] ,Transmit Frame Sync Select [3]" "TXFS,RXFS" bitfld.long 0x18 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x18 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output" bitfld.long 0x18 25. " TCSEL[3] ,Transmit Clock Select" "TXC,RXC" bitfld.long 0x18 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x18 21. " RFS_DIR ,Receive Frame Sync Direction Control" "Input,Output" bitfld.long 0x18 20. " RFSEL[3] ,Receive Frame Sync Select." "TXFS,RXFS" bitfld.long 0x18 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x18 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output" bitfld.long 0x18 15. " RCSEL[3] ,Receive Clock Select" "TXC,RXC" bitfld.long 0x18 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x18 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous" line.long 0x1C "AUDMUX_PDCR4,Port Data Control Register 4" bitfld.long 0x1C 13.--15. " RXDSEL ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," bitfld.long 0x1C 12. " TXRXEN ,Transmit/Receive Switch Enable" "Disabled,Enabled" bitfld.long 0x1C 8. " MODE ,Mode Select" "Normal,Internal Network" textline " " bitfld.long 0x1C 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded" bitfld.long 0x1C 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded" bitfld.long 0x1C 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded" bitfld.long 0x1C 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded" textline " " bitfld.long 0x1C 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded" bitfld.long 0x1C 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded" bitfld.long 0x1C 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded" bitfld.long 0x1C 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded" textline " " line.long 0x20 "AUDMUX_PTCR5,Port Timing Control Register 5" bitfld.long 0x20 31. " TFS_DIR ,Transmit Frame Sync Direction Control" "Input,Output" bitfld.long 0x20 30. " TFSEL[3] ,Transmit Frame Sync Select [3]" "TXFS,RXFS" bitfld.long 0x20 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x20 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output" bitfld.long 0x20 25. " TCSEL[3] ,Transmit Clock Select" "TXC,RXC" bitfld.long 0x20 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x20 21. " RFS_DIR ,Receive Frame Sync Direction Control" "Input,Output" bitfld.long 0x20 20. " RFSEL[3] ,Receive Frame Sync Select." "TXFS,RXFS" bitfld.long 0x20 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x20 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output" bitfld.long 0x20 15. " RCSEL[3] ,Receive Clock Select" "TXC,RXC" bitfld.long 0x20 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x20 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous" line.long 0x24 "AUDMUX_PDCR5,Port Data Control Register 5" bitfld.long 0x24 13.--15. " RXDSEL ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," bitfld.long 0x24 12. " TXRXEN ,Transmit/Receive Switch Enable" "Disabled,Enabled" bitfld.long 0x24 8. " MODE ,Mode Select" "Normal,Internal Network" textline " " bitfld.long 0x24 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded" bitfld.long 0x24 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded" bitfld.long 0x24 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded" bitfld.long 0x24 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded" textline " " bitfld.long 0x24 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded" bitfld.long 0x24 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded" bitfld.long 0x24 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded" bitfld.long 0x24 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded" textline " " line.long 0x28 "AUDMUX_PTCR6,Port Timing Control Register 6" bitfld.long 0x28 31. " TFS_DIR ,Transmit Frame Sync Direction Control" "Input,Output" bitfld.long 0x28 30. " TFSEL[3] ,Transmit Frame Sync Select [3]" "TXFS,RXFS" bitfld.long 0x28 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x28 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output" bitfld.long 0x28 25. " TCSEL[3] ,Transmit Clock Select" "TXC,RXC" bitfld.long 0x28 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x28 21. " RFS_DIR ,Receive Frame Sync Direction Control" "Input,Output" bitfld.long 0x28 20. " RFSEL[3] ,Receive Frame Sync Select." "TXFS,RXFS" bitfld.long 0x28 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x28 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output" bitfld.long 0x28 15. " RCSEL[3] ,Receive Clock Select" "TXC,RXC" bitfld.long 0x28 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x28 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous" line.long 0x2C "AUDMUX_PDCR6,Port Data Control Register 6" bitfld.long 0x2C 13.--15. " RXDSEL ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," bitfld.long 0x2C 12. " TXRXEN ,Transmit/Receive Switch Enable" "Disabled,Enabled" bitfld.long 0x2C 8. " MODE ,Mode Select" "Normal,Internal Network" textline " " bitfld.long 0x2C 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded" bitfld.long 0x2C 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded" bitfld.long 0x2C 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded" bitfld.long 0x2C 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded" textline " " bitfld.long 0x2C 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded" bitfld.long 0x2C 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded" bitfld.long 0x2C 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded" bitfld.long 0x2C 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded" textline "" line.long 0x30 "AUDMUX_PTCR7,Port Timing Control Register 7" bitfld.long 0x30 31. " TFS_DIR ,Transmit Frame Sync Direction Control" "Input,Output" bitfld.long 0x30 30. " TFSEL[3] ,Transmit Frame Sync Select [3]" "TXFS,RXFS" bitfld.long 0x30 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x30 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output" bitfld.long 0x30 25. " TCSEL[3] ,Transmit Clock Select" "TXC,RXC" bitfld.long 0x30 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x30 21. " RFS_DIR ,Receive Frame Sync Direction Control" "Input,Output" bitfld.long 0x30 20. " RFSEL[3] ,Receive Frame Sync Select." "TXFS,RXFS" bitfld.long 0x30 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x30 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output" bitfld.long 0x30 15. " RCSEL[3] ,Receive Clock Select" "TXC,RXC" bitfld.long 0x30 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," textline " " bitfld.long 0x30 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous" line.long 0x34 "AUDMUX_PDCR7,Port Data Control Register 7" bitfld.long 0x34 13.--15. " RXDSEL ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7," bitfld.long 0x34 12. " TXRXEN ,Transmit/Receive Switch Enable" "Disabled,Enabled" bitfld.long 0x34 8. " MODE ,Mode Select" "Normal,Internal Network" textline " " bitfld.long 0x34 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded" bitfld.long 0x34 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded" bitfld.long 0x34 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded" bitfld.long 0x34 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded" textline " " bitfld.long 0x34 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded" bitfld.long 0x34 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded" bitfld.long 0x34 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded" bitfld.long 0x34 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded" width 12. tree.end sif (cpu()=="IMX6SOLOX-CA9") tree "BCH (62-BIT Correcting ECC Accelerator)" base ad:0x01808000 width 19. group.long 0x00++0x0F line.long 0x00 "BCH_CTRL,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x00 31. " SFTRST ,BCH software reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock BCH gates" "Clocked,Not clocked" bitfld.long 0x00 22. " DEBUGSYNDROME ,Debug syndromes enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x00 17. " M2M_ENCODE ,Encode/decode mode for memory-to-memory operations" "0,1" bitfld.long 0x00 16. " M2M_ENABLE ,M2M enable" "Disabled,Enabled" bitfld.long 0x00 10. " DEBUG_STALL_IRQ_EN ,Debug stall mode interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " COMPLETE_IRQ_EN ,Completion of correction interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " DEBUG_STALL_IRQ ,Debug stall Interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " COMPLETE_IRQ ,External interrupt line status" "No interrupt,Interrupt" line.long 0x04 "BCH_CTRL_SET,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x04 31. " SFTRST ,BCH software reset" "No reset,Reset" bitfld.long 0x04 30. " CLKGATE ,Clock BCH gates" "Clocked,Not clocked" bitfld.long 0x04 22. " DEBUGSYNDROME ,Debug syndromes enable" "Disabled,Enabled" bitfld.long 0x04 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x04 17. " M2M_ENCODE ,Encode/decode mode for memory-to-memory operations" "0,1" bitfld.long 0x04 16. " M2M_ENABLE ,M2M enable" "Disabled,Enabled" bitfld.long 0x04 10. " DEBUG_STALL_IRQ_EN ,Debug stall mode interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " COMPLETE_IRQ_EN ,Completion of correction interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt status" "No interrupt,Interrupt" bitfld.long 0x04 2. " DEBUG_STALL_IRQ ,Debug stall Interrupt status" "No interrupt,Interrupt" bitfld.long 0x04 0. " COMPLETE_IRQ ,External interrupt line status" "No interrupt,Interrupt" line.long 0x08 "BCH_CTRL_CLR,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x08 31. " SFTRST ,BCH software reset" "No reset,Reset" bitfld.long 0x08 30. " CLKGATE ,Clock BCH gates" "Clocked,Not clocked" bitfld.long 0x08 22. " DEBUGSYNDROME ,Debug syndromes enable" "Disabled,Enabled" bitfld.long 0x08 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x08 17. " M2M_ENCODE ,Encode/decode mode for memory-to-memory operations" "0,1" bitfld.long 0x08 16. " M2M_ENABLE ,M2M enable" "Disabled,Enabled" bitfld.long 0x08 10. " DEBUG_STALL_IRQ_EN ,Debug stall mode interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " COMPLETE_IRQ_EN ,Completion of correction interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 2. " DEBUG_STALL_IRQ ,Debug stall Interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 0. " COMPLETE_IRQ ,External interrupt line status" "No interrupt,Interrupt" line.long 0x0C "BCH_CTRL_TOG,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x0C 31. " SFTRST ,BCH software reset" "No reset,Reset" bitfld.long 0x0C 30. " CLKGATE ,Clock BCH gates" "Clocked,Not clocked" bitfld.long 0x0C 22. " DEBUGSYNDROME ,Debug syndromes enable" "Disabled,Enabled" bitfld.long 0x0C 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x0C 17. " M2M_ENCODE ,Encode/decode mode for memory-to-memory operations" "0,1" bitfld.long 0x0C 16. " M2M_ENABLE ,M2M enable" "Disabled,Enabled" bitfld.long 0x0C 10. " DEBUG_STALL_IRQ_EN ,Debug stall mode interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 8. " COMPLETE_IRQ_EN ,Completion of correction interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 2. " DEBUG_STALL_IRQ ,Debug stall Interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 0. " COMPLETE_IRQ ,External interrupt line status" "No interrupt,Interrupt" rgroup.long 0x10++0x0F line.long 0x00 "BCH_STATUS0,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x00 20.--31. 1. " HANDLE ,12 bit handle" bitfld.long 0x00 16.--19. " COMPLETED_CE ,Chip enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " STATUS_BLK0 ,BLK0 status" bitfld.long 0x00 4. " ALLONES ,Set all transaction bits to ones" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORRECTED ,At least one correctable error encountered" "No error,Error" bitfld.long 0x00 2. " UNCORRECTABLE ,Uncorrectable error encountered" "No error,Error" line.long 0x04 "BCH_STATUS0_SET,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x04 20.--31. 1. " HANDLE ,12 bit handle" bitfld.long 0x04 16.--19. " COMPLETED_CE ,Chip enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 8.--15. 1. " STATUS_BLK0 ,BLK0 status" bitfld.long 0x04 4. " ALLONES ,Set all transaction bits to ones" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " CORRECTED ,At least one correctable error encountered" "No error,Error" bitfld.long 0x04 2. " UNCORRECTABLE ,Uncorrectable error encountered" "No error,Error" line.long 0x08 "BCH_STATUS0_CLR,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x08 20.--31. 1. " HANDLE ,12 bit handle" bitfld.long 0x08 16.--19. " COMPLETED_CE ,Chip enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 8.--15. 1. " STATUS_BLK0 ,BLK0 status" bitfld.long 0x08 4. " ALLONES ,Set all transaction bits to ones" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " CORRECTED ,At least one correctable error encountered" "No error,Error" bitfld.long 0x08 2. " UNCORRECTABLE ,Uncorrectable error encountered" "No error,Error" line.long 0x0C "BCH_STATUS0_TOG,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x0C 20.--31. 1. " HANDLE ,12 bit handle" bitfld.long 0x0C 16.--19. " COMPLETED_CE ,Chip enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 8.--15. 1. " STATUS_BLK0 ,BLK0 status" bitfld.long 0x0C 4. " ALLONES ,Set all transaction bits to ones" "Disabled,Enabled" textline " " bitfld.long 0x0C 3. " CORRECTED ,At least one correctable error encountered" "No error,Error" bitfld.long 0x0C 2. " UNCORRECTABLE ,Uncorrectable error encountered" "No error,Error" group.long 0x20++0x0F line.long 0x00 "BCH_MODE,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x00 0.--7. 1. " ERASE_THRESHOLD ,Maximum number of zero bits on a flash page" line.long 0x04 "BCH_MODE_SET,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x04 0.--7. 1. " ERASE_THRESHOLD ,Maximum number of zero bits on a flash page" line.long 0x08 "BCH_MODE_CLR,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x08 0.--7. 1. " ERASE_THRESHOLD ,Maximum number of zero bits on a flash page" line.long 0x0C "BCH_MODE_TOG,Hardware ECC Accelerator Mode Register" hexmask.long.byte 0x0C 0.--7. 1. " ERASE_THRESHOLD ,Maximum number of zero bits on a flash page" group.long 0x30++0x0F line.long 0x00 "BCH_ENCODEPTR,Hardware BCH ECC Loopback Encode Buffer Register" line.long 0x04 "BCH_ENCODEPTR_SET,Hardware BCH ECC Loopback Encode Buffer Register" line.long 0x08 "BCH_ENCODEPTR_CLR,Hardware BCH ECC Loopback Encode Buffer Register" line.long 0x0C "BCH_ENCODEPTR_TOG,Hardware BCH ECC Loopback Encode Buffer Register" group.long 0x40++0x0F line.long 0x00 "BCH_DATAPTR,Hardware BCH ECC Loopback Data Buffer Register" line.long 0x04 "BCH_DATAPTR_SET,Hardware BCH ECC Loopback Data Buffer Register" line.long 0x08 "BCH_DATAPTR_CLR,Hardware BCH ECC Loopback Data Buffer Register" line.long 0x0C "BCH_DATAPTR_TOG,Hardware BCH ECC Loopback Data Buffer Register" group.long 0x50++0x0F line.long 0x00 "BCH_METAPTR,Hardware BCH ECC Loopback Metadata Buffer Register" line.long 0x04 "BCH_METAPTR_SET,Hardware BCH ECC Loopback Metadata Buffer Register" line.long 0x08 "BCH_METAPTR_CLR,Hardware BCH ECC Loopback Metadata Buffer Register" line.long 0x0C "BCH_METAPTR_TOG,Hardware BCH ECC Loopback Metadata Buffer Register" textline "" width 22. group.long 0x70++0x0F line.long 0x00 "BCH_LAYOUTSELECT,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x00 30.--31. " CS15_SELECT ,Chip 15 layout select" "0,1,2,3" bitfld.long 0x00 28.--29. " CS14_SELECT ,Chip 14 layout select" "0,1,2,3" bitfld.long 0x00 26.--27. " CS13_SELECT ,Chip 13 layout select" "0,1,2,3" bitfld.long 0x00 24.--25. " CS12_SELECT ,Chip 12 layout select" "0,1,2,3" textline " " bitfld.long 0x00 22.--23. " CS11_SELECT ,Chip 11 layout select" "0,1,2,3" bitfld.long 0x00 20.--21. " CS10_SELECT ,Chip 10 layout select" "0,1,2,3" bitfld.long 0x00 18.--19. " CS9_SELECT ,Chip 9 layout select" "0,1,2,3" bitfld.long 0x00 16.--17. " CS8_SELECT ,Chip 8 layout select" "0,1,2,3" textline " " bitfld.long 0x00 14.--15. " CS7_SELECT ,Chip 7 layout select" "0,1,2,3" bitfld.long 0x00 12.--13. " CS6_SELECT ,Chip 6 layout select" "0,1,2,3" bitfld.long 0x00 10.--11. " CS5_SELECT ,Chip 5 layout select" "0,1,2,3" bitfld.long 0x00 8.--9. " CS4_SELECT ,Chip 4 layout select" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " CS3_SELECT ,Chip 3 layout select" "0,1,2,3" bitfld.long 0x00 4.--5. " CS2_SELECT ,Chip 2 layout select" "0,1,2,3" bitfld.long 0x00 2.--3. " CS1_SELECT ,Chip 1 layout select" "0,1,2,3" bitfld.long 0x00 0.--1. " CS0_SELECT ,Chip 0 layout select" "0,1,2,3" line.long 0x04 "BCH_LAYOUTSELECT_SET,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x04 30.--31. " CS15_SELECT ,Chip 15 layout select" "0,1,2,3" bitfld.long 0x04 28.--29. " CS14_SELECT ,Chip 14 layout select" "0,1,2,3" bitfld.long 0x04 26.--27. " CS13_SELECT ,Chip 13 layout select" "0,1,2,3" bitfld.long 0x04 24.--25. " CS12_SELECT ,Chip 12 layout select" "0,1,2,3" textline " " bitfld.long 0x04 22.--23. " CS11_SELECT ,Chip 11 layout select" "0,1,2,3" bitfld.long 0x04 20.--21. " CS10_SELECT ,Chip 10 layout select" "0,1,2,3" bitfld.long 0x04 18.--19. " CS9_SELECT ,Chip 9 layout select" "0,1,2,3" bitfld.long 0x04 16.--17. " CS8_SELECT ,Chip 8 layout select" "0,1,2,3" textline " " bitfld.long 0x04 14.--15. " CS7_SELECT ,Chip 7 layout select" "0,1,2,3" bitfld.long 0x04 12.--13. " CS6_SELECT ,Chip 6 layout select" "0,1,2,3" bitfld.long 0x04 10.--11. " CS5_SELECT ,Chip 5 layout select" "0,1,2,3" bitfld.long 0x04 8.--9. " CS4_SELECT ,Chip 4 layout select" "0,1,2,3" textline " " bitfld.long 0x04 6.--7. " CS3_SELECT ,Chip 3 layout select" "0,1,2,3" bitfld.long 0x04 4.--5. " CS2_SELECT ,Chip 2 layout select" "0,1,2,3" bitfld.long 0x04 2.--3. " CS1_SELECT ,Chip 1 layout select" "0,1,2,3" bitfld.long 0x04 0.--1. " CS0_SELECT ,Chip 0 layout select" "0,1,2,3" line.long 0x08 "BCH_LAYOUTSELECT_CLR,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x08 30.--31. " CS15_SELECT ,Chip 15 layout select" "0,1,2,3" bitfld.long 0x08 28.--29. " CS14_SELECT ,Chip 14 layout select" "0,1,2,3" bitfld.long 0x08 26.--27. " CS13_SELECT ,Chip 13 layout select" "0,1,2,3" bitfld.long 0x08 24.--25. " CS12_SELECT ,Chip 12 layout select" "0,1,2,3" textline " " bitfld.long 0x08 22.--23. " CS11_SELECT ,Chip 11 layout select" "0,1,2,3" bitfld.long 0x08 20.--21. " CS10_SELECT ,Chip 10 layout select" "0,1,2,3" bitfld.long 0x08 18.--19. " CS9_SELECT ,Chip 9 layout select" "0,1,2,3" bitfld.long 0x08 16.--17. " CS8_SELECT ,Chip 8 layout select" "0,1,2,3" textline " " bitfld.long 0x08 14.--15. " CS7_SELECT ,Chip 7 layout select" "0,1,2,3" bitfld.long 0x08 12.--13. " CS6_SELECT ,Chip 6 layout select" "0,1,2,3" bitfld.long 0x08 10.--11. " CS5_SELECT ,Chip 5 layout select" "0,1,2,3" bitfld.long 0x08 8.--9. " CS4_SELECT ,Chip 4 layout select" "0,1,2,3" textline " " bitfld.long 0x08 6.--7. " CS3_SELECT ,Chip 3 layout select" "0,1,2,3" bitfld.long 0x08 4.--5. " CS2_SELECT ,Chip 2 layout select" "0,1,2,3" bitfld.long 0x08 2.--3. " CS1_SELECT ,Chip 1 layout select" "0,1,2,3" bitfld.long 0x08 0.--1. " CS0_SELECT ,Chip 0 layout select" "0,1,2,3" line.long 0x0C "BCH_LAYOUTSELECT_TOG,Hardware ECC Accelerator Layout Select Register" bitfld.long 0x0C 30.--31. " CS15_SELECT ,Chip 15 layout select" "0,1,2,3" bitfld.long 0x0C 28.--29. " CS14_SELECT ,Chip 14 layout select" "0,1,2,3" bitfld.long 0x0C 26.--27. " CS13_SELECT ,Chip 13 layout select" "0,1,2,3" bitfld.long 0x0C 24.--25. " CS12_SELECT ,Chip 12 layout select" "0,1,2,3" textline " " bitfld.long 0x0C 22.--23. " CS11_SELECT ,Chip 11 layout select" "0,1,2,3" bitfld.long 0x0C 20.--21. " CS10_SELECT ,Chip 10 layout select" "0,1,2,3" bitfld.long 0x0C 18.--19. " CS9_SELECT ,Chip 9 layout select" "0,1,2,3" bitfld.long 0x0C 16.--17. " CS8_SELECT ,Chip 8 layout select" "0,1,2,3" textline " " bitfld.long 0x0C 14.--15. " CS7_SELECT ,Chip 7 layout select" "0,1,2,3" bitfld.long 0x0C 12.--13. " CS6_SELECT ,Chip 6 layout select" "0,1,2,3" bitfld.long 0x0C 10.--11. " CS5_SELECT ,Chip 5 layout select" "0,1,2,3" bitfld.long 0x0C 8.--9. " CS4_SELECT ,Chip 4 layout select" "0,1,2,3" textline " " bitfld.long 0x0C 6.--7. " CS3_SELECT ,Chip 3 layout select" "0,1,2,3" bitfld.long 0x0C 4.--5. " CS2_SELECT ,Chip 2 layout select" "0,1,2,3" bitfld.long 0x0C 2.--3. " CS1_SELECT ,Chip 1 layout select" "0,1,2,3" bitfld.long 0x0C 0.--1. " CS0_SELECT ,Chip 0 layout select" "0,1,2,3" group.long 0x80++0x0F "Flash 0" line.long 0x00 "BCH_FLASH0LAYOUT0,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x00 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x04 "BCH_FLASH0LAYOUT0_SET,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x04 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x08 "BCH_FLASH0LAYOUT0_CLR,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x08 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x0C "BCH_FLASH0LAYOUT0_TOG,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x0C 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Data 0 block size" group.long (0x80+0x10)++0x0F line.long 0x00 "BCH_FLASH0LAYOUT1,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x00 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x04 "BCH_FLASH0LAYOUT1_SET,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x04 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x08 "BCH_FLASH0LAYOUT1_CLR,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x08 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x0C "BCH_FLASH0LAYOUT1_TOG,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x0C 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" group.long 0xA0++0x0F "Flash 1" line.long 0x00 "BCH_FLASH1LAYOUT0,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x00 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x04 "BCH_FLASH1LAYOUT0_SET,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x04 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x08 "BCH_FLASH1LAYOUT0_CLR,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x08 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x0C "BCH_FLASH1LAYOUT0_TOG,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x0C 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Data 0 block size" group.long (0xA0+0x10)++0x0F line.long 0x00 "BCH_FLASH1LAYOUT1,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x00 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x04 "BCH_FLASH1LAYOUT1_SET,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x04 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x08 "BCH_FLASH1LAYOUT1_CLR,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x08 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x0C "BCH_FLASH1LAYOUT1_TOG,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x0C 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" group.long 0xC0++0x0F "Flash 2" line.long 0x00 "BCH_FLASH2LAYOUT0,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x00 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x04 "BCH_FLASH2LAYOUT0_SET,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x04 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x08 "BCH_FLASH2LAYOUT0_CLR,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x08 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x0C "BCH_FLASH2LAYOUT0_TOG,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x0C 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Data 0 block size" group.long (0xC0+0x10)++0x0F line.long 0x00 "BCH_FLASH2LAYOUT1,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x00 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x04 "BCH_FLASH2LAYOUT1_SET,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x04 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x08 "BCH_FLASH2LAYOUT1_CLR,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x08 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x0C "BCH_FLASH2LAYOUT1_TOG,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x0C 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" group.long 0xE0++0x0F "Flash 3" line.long 0x00 "BCH_FLASH3LAYOUT0,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x00 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x04 "BCH_FLASH3LAYOUT0_SET,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x04 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x04 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x04 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x08 "BCH_FLASH3LAYOUT0_CLR,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x08 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x08 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x08 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATA0_SIZE ,Data 0 block size" line.long 0x0C "BCH_FLASH3LAYOUT0_TOG,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page" hexmask.long.byte 0x0C 16.--23. 1. " META_SIZE ,Metadata size" bitfld.long 0x0C 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATA0_SIZE ,Data 0 block size" group.long (0xE0+0x10)++0x0F line.long 0x00 "BCH_FLASH3LAYOUT1,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x00 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x04 "BCH_FLASH3LAYOUT1_SET,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x04 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x04 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x04 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x04 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x08 "BCH_FLASH3LAYOUT1_CLR,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x08 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x08 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x08 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x08 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" line.long 0x0C "BCH_FLASH3LAYOUT1_TOG,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x0C 16.--31. 1. " PAGE_SIZE ,Flash page size" bitfld.long 0x0C 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,ECC34,ECC36,ECC38,ECC40,ECC42,ECC44,ECC46,ECC48,ECC50,ECC52,ECC54,ECC56,ECC58,ECC60,ECC62" bitfld.long 0x0C 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14" hexmask.long.word 0x0C 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks" textline "" group.long 0x100++0x0F line.long 0x00 "BCH_DEBUG0,Hardware BCH ECC Debug Register 0" hexmask.long.word 0x00 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x00 15. " KES_DEBUG_SHIFT_SYND ,KES debug syndrome shift" "Not shifted,Shifted" textline " " bitfld.long 0x00 14. " KES_DEBUG_PAYLOAD_FLAG ,KES debug payload flag" "0,1" bitfld.long 0x00 13. " KES_DEBUG_MODE4K ,KES debug input mode" "0,1" textline " " bitfld.long 0x00 12. " KES_DEBUG_KICK ,KES debug kick" "Not kicked,Kicked" bitfld.long 0x00 11. " KES_STANDALONE ,KES standalone" "Normal,TEST_MODE" textline " " bitfld.long 0x00 10. " KES_DEBUG_STEP ,KES debug step" "Not stepped,Stepped" bitfld.long 0x00 9. " KES_DEBUG_STALL ,KES debug stall" "Normal,Wait" textline " " bitfld.long 0x00 8. " BM_KES_TEST_BYPASS ,BM KES test bypass" "Normal,TEST_MODE" bitfld.long 0x00 0.--5. " DEBUG_REG_SELECT ,Internal register state view value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "BCH_DEBUG0_SET,Hardware BCH ECC Debug Register 0" hexmask.long.word 0x04 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x04 15. " KES_DEBUG_SHIFT_SYND ,KES debug syndrome shift" "Not shifted,Shifted" textline " " bitfld.long 0x04 14. " KES_DEBUG_PAYLOAD_FLAG ,KES debug payload flag" "0,1" bitfld.long 0x04 13. " KES_DEBUG_MODE4K ,KES debug input mode" "0,1" textline " " bitfld.long 0x04 12. " KES_DEBUG_KICK ,KES debug kick" "Not kicked,Kicked" bitfld.long 0x04 11. " KES_STANDALONE ,KES standalone" "Normal,TEST_MODE" textline " " bitfld.long 0x04 10. " KES_DEBUG_STEP ,KES debug step" "Not stepped,Stepped" bitfld.long 0x04 9. " KES_DEBUG_STALL ,KES debug stall" "Normal,Wait" textline " " bitfld.long 0x04 8. " BM_KES_TEST_BYPASS ,BM KES test bypass" "Normal,TEST_MODE" bitfld.long 0x04 0.--5. " DEBUG_REG_SELECT ,Internal register state view value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "BCH_DEBUG0_CLR,Hardware BCH ECC Debug Register 0" hexmask.long.word 0x08 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x08 15. " KES_DEBUG_SHIFT_SYND ,KES debug syndrome shift" "Not shifted,Shifted" textline " " bitfld.long 0x08 14. " KES_DEBUG_PAYLOAD_FLAG ,KES debug payload flag" "0,1" bitfld.long 0x08 13. " KES_DEBUG_MODE4K ,KES debug input mode" "0,1" textline " " bitfld.long 0x08 12. " KES_DEBUG_KICK ,KES debug kick" "Not kicked,Kicked" bitfld.long 0x08 11. " KES_STANDALONE ,KES standalone" "Normal,TEST_MODE" textline " " bitfld.long 0x08 10. " KES_DEBUG_STEP ,KES debug step" "Not stepped,Stepped" bitfld.long 0x08 9. " KES_DEBUG_STALL ,KES debug stall" "Normal,Wait" textline " " bitfld.long 0x08 8. " BM_KES_TEST_BYPASS ,BM KES test bypass" "Normal,TEST_MODE" bitfld.long 0x08 0.--5. " DEBUG_REG_SELECT ,Internal register state view value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "BCH_DEBUG0_TOG,Hardware BCH ECC Debug Register 0" hexmask.long.word 0x0C 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x0C 15. " KES_DEBUG_SHIFT_SYND ,KES debug syndrome shift" "Not shifted,Shifted" textline " " bitfld.long 0x0C 14. " KES_DEBUG_PAYLOAD_FLAG ,KES debug payload flag" "0,1" bitfld.long 0x0C 13. " KES_DEBUG_MODE4K ,KES debug input mode" "0,1" textline " " bitfld.long 0x0C 12. " KES_DEBUG_KICK ,KES debug kick" "Not kicked,Kicked" bitfld.long 0x0C 11. " KES_STANDALONE ,KES standalone" "Normal,TEST_MODE" textline " " bitfld.long 0x0C 10. " KES_DEBUG_STEP ,KES debug step" "Not stepped,Stepped" bitfld.long 0x0C 9. " KES_DEBUG_STALL ,KES debug stall" "Normal,Wait" textline " " bitfld.long 0x0C 8. " BM_KES_TEST_BYPASS ,BM KES test bypass" "Normal,TEST_MODE" bitfld.long 0x0C 0.--5. " DEBUG_REG_SELECT ,Internal register state view value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 23. rgroup.long 0x110++0x6F line.long 0x00 "BCH_DBGKESREAD,KES Debug Read Register" line.long 0x04 "BCH_DBGKESREAD_SET,KES Debug Read Register" line.long 0x08 "BCH_DBGKESREAD_CLR,KES Debug Read Register" line.long 0x0C "BCH_DBGKESREAD_TOG,KES Debug Read Register" line.long 0x10 "BCH_DBGCSFEREAD,Chien Search Debug Read Register" line.long 0x14 "BCH_DBGCSFEREAD_SET,Chien Search Debug Read Register" line.long 0x18 "BCH_DBGCSFEREAD_CLR,Chien Search Debug Read Register" line.long 0x1C "BCH_DBGCSFEREAD_TOG,Chien Search Debug Read Register" line.long 0x20 "BCH_DBGSYNDGENREAD,Syndrome Generator Debug Read Register" line.long 0x24 "BCH_DBGSYNDGENREAD_SET,Syndrome Generator Debug Read Register" line.long 0x28 "BCH_DBGSYNDGENREAD_CLR,Syndrome Generator Debug Read Register" line.long 0x2C "BCH_DBGSYNDGENREAD_TOG,Syndrome Generator Debug Read Register" line.long 0x30 "BCH_DBGAHBMREAD,Bus Master and ECC Controller Debug Read Register" line.long 0x34 "BCH_DBGAHBMREAD_SET,Bus Master and ECC Controller Debug Read Register" line.long 0x38 "BCH_DBGAHBMREAD_CLR,Bus Master and ECC Controller Debug Read Register" line.long 0x3C "BCH_DBGAHBMREAD_TOG,Bus Master and ECC Controller Debug Read Register" line.long 0x40 "HW_BCH_BLOCKNAME,Block Name Register" line.long 0x44 "HW_BCH_BLOCKNAME_SET,Block Name Register" line.long 0x48 "HW_BCH_BLOCKNAME_CLR,Block Name Register" line.long 0x4C "HW_BCH_BLOCKNAME_TOG,Block Name Register" line.long 0x50 "HW_BCH_VERSION,BCH Version Register" hexmask.long.byte 0x50 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x50 16.--23. 1. " MINOR ,MINOR field of the RTL version" hexmask.long.word 0x50 0.--15. 1. " STEP ,Stepping of the RTL version" line.long 0x54 "HW_BCH_VERSION,BCH Version Register" hexmask.long.byte 0x54 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x54 16.--23. 1. " MINOR ,MINOR field of the RTL version" hexmask.long.word 0x54 0.--15. 1. " STEP ,Stepping of the RTL version" line.long 0x58 "HW_BCH_VERSION,BCH Version Register" hexmask.long.byte 0x58 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x58 16.--23. 1. " MINOR ,MINOR field of the RTL version" hexmask.long.word 0x58 0.--15. 1. " STEP ,Stepping of the RTL version" line.long 0x5C "HW_BCH_VERSION,BCH Version Register" hexmask.long.byte 0x5C 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x5C 16.--23. 1. " MINOR ,MINOR field of the RTL version" hexmask.long.word 0x5C 0.--15. 1. " STEP ,Stepping of the RTL version" textline "" line.long 0x60 "BCH_DEBUG1,Hardware BCH ECC Debug Register 1" bitfld.long 0x60 31. " DEBUG1_PREERASECHK ,Blank page enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x60 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" line.long 0x64 "BCH_DEBUG1_SET,Hardware BCH ECC Debug Register 1" bitfld.long 0x64 31. " DEBUG1_PREERASECHK ,Blank page enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x64 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" line.long 0x68 "BCH_DEBUG1_CLR,Hardware BCH ECC Debug Register 1" bitfld.long 0x68 31. " DEBUG1_PREERASECHK ,Blank page enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x68 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" line.long 0x6C "BCH_DEBUG1_TOG,Hardware BCH ECC Debug Register 1" bitfld.long 0x6C 31. " DEBUG1_PREERASECHK ,Blank page enables pre-erase check" "Disabled,Enabled" hexmask.long.word 0x6C 0.--8. 1. " ERASED_ZERO_COUNT ,The zero counts on one page" width 0xb tree.end endif tree "CCM (Clock Controller Module)" tree "CCM registers" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020C4000 else base ad:0x420C4000 endif width 13. group.long 0x00++0x07 line.long 0x00 "CCM_CCR,CCM Control Register" bitfld.long 0x00 27. " RBC_EN ,Enable for REG_BYPASS_COUNTER" "Disabled,Enabled" bitfld.long 0x00 21.--26. " REG_BYPASS_COUNT ,Counter for anatop_reg_bypass signal assertion" "No delay,1 CKIL,2 CKIL,3 CKIL,4 CKIL,5 CKIL,6 CKIL,7 CKIL,8 CKIL,9 CKIL,10 CKIL,11 CKIL,12 CKIL,13 CKIL,14 CKIL,15 CKIL,16 CKIL,17 CKIL,18 CKIL,19 CKIL,20 CKIL,21 CKIL,22 CKIL,23 CKIL,24 CKIL,25 CKIL,26 CKIL,27 CKIL,28 CKIL,29 CKIL,30 CKIL,31 CKIL,32 CKIL,33 CKIL,34 CKIL,35 CKIL,36 CKIL,37 CKIL,38 CKIL,39 CKIL,40 CKIL,41 CKIL,42 CKIL,43 CKIL,44 CKIL,45 CKIL,46 CKIL,47 CKIL,48 CKIL,49 CKIL,50 CKIL,51 CKIL,52 CKIL,53 CKIL,54 CKIL,55 CKIL,56 CKIL,57 CKIL,58 CKIL,59 CKIL,60 CKIL,61 CKIL,62 CKIL,63 CKIL" bitfld.long 0x00 12. " COSC_EN ,On chip oscillator enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " OSCNT ,Oscillator ready counter value" line.long 0x04 "CCM_CCDR,CCM Control Divider Register" bitfld.long 0x04 16. " MMDC_MASK ,Mask handshake with MMDC_CH1 module" "Not masked,Masked" rgroup.long 0x08++0x03 line.long 0x00 "CCM_CSR,CCM Status Register" bitfld.long 0x00 5. " COSC_READY ,Status indication of on board oscillator" "Not ready,Ready" bitfld.long 0x00 0. " REF_EN_B ,Status of the value of REF_EN_B output of CCM" "0,1" group.long 0x0C++0x33 line.long 0x00 "CCM_CCSR,CCM Clock Switcher Register" bitfld.long 0x00 8. " STEP_SEL ,Step frequency when shifting ARM frequency" "OSC_CLK,PLL2 PFD2" bitfld.long 0x00 2. " PLL1_SW_CLK_SEL ,Selects source to generate PLL1_SW_CLK" "PLL1_MAIN_CLK,STEP_CLK" bitfld.long 0x00 0. " PLL3_SW_CLK_SEL ,Source to generate pll3_sw_clk" "PLL3_MAIN_CLK,Pll3 bypass" line.long 0x04 "CCM_CACRR,CCM Arm Clock Root Register" bitfld.long 0x04 0.--2. " ARM_PODF ,Divider for ARM clock root" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "CCM_CBCDR,CCM Bus Clock Divider Register" bitfld.long 0x08 27.--29. " PERIPH_CLK2_PODF ,Divider for periph2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 26. " PERIPH2_CLK_SEL ,Selector for peripheral2 main clock" "PLL2_MAIN_CLK,PERIPH_CLK2_CLK" bitfld.long 0x08 25. " PERIPH_CLK_SEL ,Selector for peripheral main clock" "PLL2_MAIN_CLK,PERIPH_CLK2_CLK" textline " " bitfld.long 0x08 16.--18. " OCRAM_PODF ,Post divider for ocram clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 10.--12. " AHB_PODF ,Divider for ahb podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 8.--9. " IPG_PODF ,Divider for ipg podf" "/1,/2,/3,/4" textline " " bitfld.long 0x08 7. " OCRAM_ALT_CLK_SEL ,OCRAM alternative clock select" "PLL2 PFD2,PLL3 PFD1" bitfld.long 0x08 6. " OCRAM_CLK_SEL ,OCRAM clock source select" "Periph_clk output,AXI alternative clock" bitfld.long 0x08 3.--5. " FABRIC_MMDC__PODF ,Divider for MMDC_CH1_AXI Post divider for fabric/mmdc clock" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x08 0.--2. " PERIPH2_CLK2_PODF ,Divider for PERIPH2_CLK2 podf" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "CCM_CBCMR,CCM Bus Clock Multiplexer Register" bitfld.long 0x0C 29.--31. " GPU_CORE_PODF ,Post divider for gpu_core clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 26.--28. " GPU_AXI_PODF ,Divider for GPU3D_CORE clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 23.--25. " LCDIF1_PODF ,Post-divider for lcdif1 clock" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x0C 21.--22. " PRE_PERIPH2_CLK_SEL ,Selector for PRE_PERIPH2 clock multiplexer" "PLL2,PLL2 PFD2,PLL2 PFD0,PLL4" bitfld.long 0x0C 20. " PERIPH2_CLK2_SEL ,Selector for PERIPH2_CLK2 clock multiplexer" "PLL3_SW_CLK,Oscillator" bitfld.long 0x0C 18.--19. " PRE_PERIPH_CLK_SEL ,Selector for PRE_PERIPH clock multiplexer" "PLL2,PLL2 PFD2,PLL2 PFD0,PLL2 PFD2/2" textline " " bitfld.long 0x0C 12.--13. " PERIPH_CLK2_SEL ,Selector for peripheral CLK2 clock multiplexer" "PLL3_SW_CLK,PLL1_REF_CLK,PLL2_MAIN_CLK," bitfld.long 0x0C 10. " PCIE_AXI_CLK_SEL ,Selector for pcie_axi clock multiplexer" "AXI,AHB" bitfld.long 0x0C 8.--9. " GPU_AXI_SEL ,Selector for gpu_axi clock multiplexer" "PLL2 PFD2,PLL3 PFD0,PLL3 PFD1,PLL2" textline " " bitfld.long 0x0C 4.--5. " GPU_CORE_SEL ,Selector for gpu_core clock multiplexer" "PLL3 PFD1,PLL3 PFD0,PLL2,PLL2 PFD2" line.long 0x10 "CCM_CSCMR1,CCM Serial Clock Multiplexer Register 1" bitfld.long 0x10 29.--30. " ACLK_EMI_SLOW_SEL ,Selector for ACLK_EMI_SLOW root clock multiplexer" "AXI,PLL3_SW_CLK,PLL2 PFD2,PLL3 PFD0" bitfld.long 0x10 26.--28. " QSPI1_PODF ,Divider for QSPI1 clock root" "/1,/2,,,,,,/8" bitfld.long 0x10 23.--25. " ACLK_EMI_SLOW_PODF ,Divider for ACLK_EMI_SLOW clock root" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x10 20.--22. " LCDIF2_PODF ,Post-divider for lcdif2 clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x10 19. " USDHC4_CLK_SEL ,Selector for USDHC4 clock multiplexer" "PLL2 PFD2,PLL2 PFD0" bitfld.long 0x10 18. " USDHC3_CLK_SEL ,Selector for USDHC3 clock multiplexer" "PLL2 PFD2,PLL2 PFD0" textline " " bitfld.long 0x10 17. " USDHC2_CLK_SEL ,Selector for USDHC2 clock multiplexer" "PLL2 PFD2,PLL2 PFD0" bitfld.long 0x10 16. " USDHC1_CLK_SEL ,Selector for USDHC1 clock multiplexer" "PLL2 PFD2,PLL2 PFD0" bitfld.long 0x10 14.--15. " SSI3_CLK_SEL ,Selector for ssi3 clock multiplexer" "PLL3 PFD2,PLL5,PLL4," textline " " bitfld.long 0x10 12.--13. " SSI2_CLK_SEL ,Selector for ssi2 clock multiplexer" "PLL3 PFD2,PLL5,PLL4," bitfld.long 0x10 10.--11. " SSI1_CLK_SEL ,Selector for ssi3 clock multiplexer" "PLL3 PFD2,PLL5,PLL4," bitfld.long 0x10 7.--9. " QSPI1_SEL ,QSPI1 clock select" "PLL3,PLL2 PFD0,PLL2 PFD2,PLL2,PLL3 PFD3,PLL3 PFD2,," textline " " bitfld.long 0x10 6. " PERCLK_CLK_SEL ,Divider for PERCLK podf" "IPG,OSC" bitfld.long 0x10 0.--5. " PERCLK_PODF ,Divider for PERCLK podf" "/1,/2,/3,/4,/5,/6,/7,/8,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," line.long 0x14 "CCM_CSCMR2,CCM Serial Clock Multiplexer Register 2" bitfld.long 0x14 26.--28. " VID_CLK_PODF ,Post-divider for vid clock root" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x14 24.--25. " VID_CLK_PRE_PODF ,Post-divider for vid clock root" "/1,/2,/3,/4" bitfld.long 0x14 21.--23. " VID_CLK_SEL ,Selector for vid clock multiplexer" "PLL3 PFD1,PLL3,PLL3 PFD3,PLL4,PLL5,,," textline " " bitfld.long 0x14 19.--20. " ESAI_CLK_SEL ,Selector for esai clock multiplexer" "PLL4,PLL3 PFD2,PLL5,PLL3_SW_CLK" bitfld.long 0x14 11. " LDB_DI1_IPU_DIV ,Control for divider of LDB clock for IPU di1" "/3.5,/7" bitfld.long 0x14 10. " LDB_DI0_IPU_DIV ,Control for divider of LDB clock for IPU di0" "/3.5,/7" textline " " bitfld.long 0x14 8.--9. " CAN_CLK_SEL ,Selector for FlexCAN clock multiplexer" "PLL3_SW_CLK (60M),OSC,PLL3_SW_CLK (80M),Disabled" bitfld.long 0x14 2.--7. " CAN_CLK_PODF ,Divider for CAN clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x18 "CCM_CSCDR1,CCM Serial Clock Divider Register 1" bitfld.long 0x18 22.--24. " USDHC4_PODF ,Divider for ESDHC4 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 19.--21. " USDHC3_PODF ,Divider for USDHC3 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 16.--18. " USDHC2_PODF ,Divider for USDHC2 clock" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x18 11.--13. " USDHC1_PODF ,Divider for USDHC1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 6. " UART_CLK_SEL ,Selector for the UART clock multiplexor" "PLL3_80M,OSC_CLK" bitfld.long 0x18 0.--5. " UART_CLK_PODF ,Divider for UART clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x1c "CCM_CS1CDR,CCM SSI1 Clock Divider Register" bitfld.long 0x1C 25.--27. " ESAI_CLK_PODF ,Divider for ESAI clock podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x1C 22.--24. " SSI3_CLK_PRED ,Divider for SSI3 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x1C 16.--21. " SSI3_CLK_PODF ,Divider for SSI3 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" textline " " bitfld.long 0x1C 9.--11. " ESAI_CLK_PRED ,Divider for esai clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x1C 6.--8. " SSI1_CLK_PRED ,Divider for SSI1 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x1C 0.--5. " SSI1_CLK_PODF ,Divider for SSI1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x20 "CCM_CS2CDR,CCM SSI2 Clock Divider Register" bitfld.long 0x20 21.--26. " QSPI2_CLK_PODF ,Divider for QSPI2 clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" bitfld.long 0x20 18.--20. " QSPI2_CLK_PRED ,Divider for QSPI2 clock pred divider" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x20 15.--17. " QSPI2_CLK_SEL ,Selector for QSPI2 clock multiplexer" "PLL2 PFD0,PLL2,PLL3_SW_CLK,PLL2 PFD2,PLL3 PFD3,,," textline " " bitfld.long 0x20 12.--14. " LDB_DI1_CLK_SEL ,Selector for ldb_di1 clock multiplexer" "PLL3_SW_CLK,PLL2 PFD0,PLL2 PFD2,PLL2,PLL3 PFD3,PLL3 PFD2,," bitfld.long 0x20 9.--11. " LDB_DI0_CLK_SEL ,Selector for LDB_DI1 clock multiplexer" "PLL5,PLL2 PFD0,PLL2 PFD2,PLL2 PFD3,PLL2 PFD1,PLL3 PFD3,," bitfld.long 0x20 6.--8. " SSI2_CLK_PRED ,Divider for SSI2 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x20 0.--5. " SSI2_CLK_PODF ,Divider for SSI2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "CCM_CDCDR,CCM DI Clock Divider Register" bitfld.long 0x24 25.--27. " SPDIF0_CLK_PRED ,Divider for SPDIF0 clock pred" "/1,/2,/3,,,,,/8" bitfld.long 0x24 22.--24. " SPDIF0_CLK_PODF ,Divider for SPDIF0 clock podf" "/1,,,,,,,/8" bitfld.long 0x24 20.--21. " SPDIF0_CLK_SEL ,Selector for SPDIF0 clock multiplexer" "PLL4,PLL3 PFD2,PLL5,PLL3_SW_CLK" textline " " bitfld.long 0x24 12.--14. " AUDIO_CLK_PRED ,Divider for audio clock pred" "/1,/2,/3,,,,,/8" bitfld.long 0x24 9.--11. " AUDIO_CLK_PODF ,Divider for audio clock podf" "/1,,,,,,,/8" bitfld.long 0x24 7.--8. " SPDIF1_CLK_SEL ,Selector for SPDIF1 clock multiplexer" "PLL4,PLL3 PFD2,PLL5,PLL3" line.long 0x28 "CCM_CHSCCDR,CCM HSC Clock Divider Register" bitfld.long 0x28 15.--17. " ENET_PRE_CLK_SEL ,Selector for ENET root clock pre-multiplexer" "PLL2,PLL3_SW_CLK,PLL5,PLL2 PFD0,PLL2 PFD2,PLL3 PFD2,," bitfld.long 0x28 12.--14. " ENET_PODF ,Divider for ENET clock divider" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x28 9.--11. " ENET_CLK_SEL ,Selector for ENET root clock multiplexer" "Pre-muxed ENET,IPP_DI0_CLK,IPP_DI1_CLK,LDB_DI0_CLK,LDB_DI1_CLK,,," textline " " bitfld.long 0x28 6.--8. " M4_PRE_CLK_SEL ,Selector for M4 root clock pre-multiplexer" "PLL2,PLL3,OSC,PLL2 PFD0,PLL2 PFD2,PLL3 PFD3,," bitfld.long 0x28 3.--5. " M4_PODF ,Divider for M4 clock divider" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x28 0.--2. " M4_CLK_SEL ,Selector for IPU1 DI0 root clock multiplexer" "Pre-muxed M4,IPP_DI0_CLK,IPP_DI1_CLK,LDB_DI0_CLK,LDB_DI1_CLK,,," line.long 0x2C "CCM_CSCDR2,CCM Serial Clock Divider Register 2" bitfld.long 0x2C 19.--24. " ECSPI_CLK_PODF ,Divider for ECSPI clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" bitfld.long 0x2C 18. " ECSPI_CLK_SEL ,Selector for the ECSPI clock multiplexor" "PLL3_60M,OSC" bitfld.long 0x2C 15.--17. " LCDIF_PRE_CLK_SEL ,Selector for IPU1 DI2 root clock pre-multiplexer" "PLL2,PLL3 PFD3,PLL5,PLL2 PFD0,PLL2 PFD1,PLL3 PFD1,," textline " " bitfld.long 0x2C 12.--14. " LCDIF1_PRED ,Pre-divider for lcdif1 clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x2C 9.--11. " LCDIF1_CLK_SEL ,Selector for lcdif1 root clock multiplexer" "Pre-muxed lcdif1,IPP_DI0_CLK,IPP_DI1_CLK,LDB_DI0_CLK,LDB_DI1_CLK,,," bitfld.long 0x2C 6.--8. " LCDIF2_PRE_CLK_SEL ,Selector for lcdif2 root clock pre-multiplexer" "PLL2,PLL3 PFD3,PLL5,PLL2 PFD0,PLL2 PFD3,PLL3 PFD1,," textline " " bitfld.long 0x2C 3.--5. " LCDIF2_PRED ,Pre-divider for lcdif2 clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x2C 0.--2. " LCDIF2_DI0_CLK_SEL ,Selector for lcdif2 root clock multiplexer" "Pre-mux lcdif2,IPP_DI0_CLK,IPP_DI1_CLK,LDB_DI0_CLK,LDB_DI1_CLK,,," line.long 0x30 "CCM_CSCDR3,CCM Serial Clock Divider Register 3" bitfld.long 0x30 16.--18. " DISPLAY_PODF ,Divider for display clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x30 14.--15. " DISPLAY_CLK_SEL ,Selector for display clock multiplexer" "PLL2,PLL2 PFD2,PLL3,PLL3 PFD1" bitfld.long 0x30 11.--13. " CSI_PODF ,Post divider for csi_core clock" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x30 9.--10. " CSI_CLK_SEL ,Selector for IPU1_HSP clock multiplexer" "OSC,PLL2 PFD2,PLL3_120M,PLL3 PFD1" rgroup.long 0x48++0x03 line.long 0x00 "CCM_CDHIPR,CCM Divider Handshake In-Process Register" bitfld.long 0x00 16. " ARM_PODF_BUSY ,Busy indicator for CCM_CACRR[ARM_PODF]" "Not busy,Busy" bitfld.long 0x00 5. " PERIPH_CLK_SEL_BUSY ,Busy indicator for PERIPH_CLK_SEL mux control" "Not busy,Busy" bitfld.long 0x00 3. " PERIPH2_CLK_SEL_BUSY ,Busy indicator PERIPH2_CLK_SEL mux control" "Not busy,Busy" textline " " bitfld.long 0x00 2. " MMDC_PODF_BUSY ,Busy indicator for MMDC_AXI_PODF" "Not busy,Busy" bitfld.long 0x00 1. " AHB_PODF_BUSY ,Busy indicator for AHB_PODF" "Not busy,Busy" bitfld.long 0x00 0. " OCRAM_PODF_BUSY ,Busy indicator for ocram_podf" "Not busy,Busy" group.long 0x54++0x2F line.long 0x00 "CCM_CLPCR,CCM Low Power Control Register" bitfld.long 0x00 27. " MASK_L2CC_IDLE ,Mask L2CC IDLE for entering low power mode" "Not masked,Masked" bitfld.long 0x00 26. " MASK_SCU_IDLE ,Mask SCU IDLE for entering low power mode" "Not masked,Masked" bitfld.long 0x00 22. " MASK_CORE0_WFI ,Mask WFI of core0 for entering low power mode" "Not masked,Masked" textline " " bitfld.long 0x00 21. " BYPASS_MMDC_LPM_HS ,Bypass handshake with mmdc_ch1 on next entrance to low power mode" "Not bypassed,Bypassed" bitfld.long 0x00 11. " COSC_PWRDOWN ,Oscillator Power Down" "Disabled,Enabled" bitfld.long 0x00 9.--10. " STBY_COUNT ,Standby counter definition" "1*pmic+1,3*pmic+1,7*pmic+1,15*pmic+1" textline " " bitfld.long 0x00 8. " VSTBY ,Voltage standby request" "Not requested,Requested" bitfld.long 0x00 7. " DIS_REF_OSC ,External reference oscillator clock disable" "No,Yes" bitfld.long 0x00 6. " SBYOS ,Standby clock oscillator - power down on STOP" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ARM_CLK_DIS_ON_LPM ,ARM clock disable in WAIT mode" "No,Yes" bitfld.long 0x00 0.--1. " LPM ,Setting the Low power mode" "RUN mode,WAIT mode,STOP mode," textline " " line.long 0x04 "CCM_CISR,CCM Interrupt Status Register" eventfld.long 0x04 26. " ARM_PODF_LOADED ,CCM interrupt request 1 generated due to frequency change of ARM_PODF" "No interrupt,Interrupt" eventfld.long 0x04 22. " PERIPH_CLK_SEL_LOADED ,CCM interrupt request 1 generated due to update of PERIPH_CLK_SEL" "No interrupt,Interrupt" eventfld.long 0x04 21. " MMDC_PODF_LOADED ,CCM interrupt request 1 generated due to frequency change of MMDC_PODF_LOADED" "No interrupt,Interrupt" textline " " eventfld.long 0x04 20. " AHB_PODF_LOADED ,CCM interrupt request 1 generated due to frequency change of AHB_PODF" "No interrupt,Interrupt" eventfld.long 0x04 19. " PERIPH2_CLK_SEL_LOADED ,CCM interrupt request 1 generated due to frequency change of PERIPH2_CLK_SEL" "No interrupt,Interrupt" eventfld.long 0x04 17. " OCRAM_PODF_LOADED ,CCM interrupt request 1 generated due to frequency change of ocram_podf" "No interrupt,Interrupt" textline " " eventfld.long 0x04 6. " COSC_READY ,CCM interrupt request 2 generated when on board oscillator ready" "No interrupt,Interrupt" eventfld.long 0x04 0. " LRF_PLL ,CCM interrupt request 2 generated due to lock of all enabled and not bypaseed plls" "No interrupt,Interrupt" line.long 0x08 "CCM_CIMR,CCM Interrupt Mask Register" bitfld.long 0x08 26. " ARM_PODF_LOADED ,Mask interrupt generation due to frequency change of ARM_PODF" "Not masked,Masked" bitfld.long 0x08 22. " MASK_PERIPH_CLK_SEL_LOADED ,Mask interrupt generation due to update of PERIPH_CLK_SEL" "Not masked,Masked" bitfld.long 0x08 21. " MASK_MMDC_PODF_LOADED ,Mask interrupt generation due to frequency change of MASK_MMDC_PODF" "Not masked,Masked" textline " " bitfld.long 0x08 20. " MASK_AHB_PODF_LOADED ,Mask interrupt generation due to frequency change of AHB_PODF" "Not masked,Masked" bitfld.long 0x08 19. " MASK_PERIPH2_CLK_SEL_LOADED ,Mask interrupt generation due to frequency change of PERIPH2_CLK_SEL" "Not masked,Masked" bitfld.long 0x08 17. " MASK_AXI_PODF_LOADED ,Mask interrupt generation due to frequency change of AXI_PODF" "Not masked,Masked" textline " " bitfld.long 0x08 6. " MASK_COSC_READY ,Mask interrupt generation due to on board oscillator ready" "Not masked,Masked" bitfld.long 0x08 0. " MASK_LRF_PLL ,Mask interrupt generation due to lrf of PLLs" "Not masked,Masked" line.long 0x0C "CCM_CCOSR,CCM Clock Output Source Register" bitfld.long 0x0C 24. " CLKO2_EN ,Enable of CCM_CLKO2 clock" "Disabled,Enabled" bitfld.long 0x0C 21.--23. " CLKO2_DIV ,Setting the divider of CCM_CLKO2" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 16.--20. " CKO2_SEL ,Selection of the clock to be generated on CCM_CLKO2" ",MMDC,USDHC4,USDHC1,,WRCK,ECSPI,,USDHC3,PCIE,ARM,CSI_CORE,DISPLAY_AXI,,OSC_CLK,,,USDHC2,SSI1,SSI2,SSI3,GPU_AXI,,CAN,LVDS,QSPI1,ESAI,ACLK_EIM_SLOW,UART_CLK,SPDIF0,AUDIO," textline " " bitfld.long 0x0C 8. " CLK_OUT_SEL ,CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks" "CCM_CLKO1,CCM_CLKO2" bitfld.long 0x0C 7. " CKO1_EN ,Enable of CKO1 clock" "Disabled,Enabled" bitfld.long 0x0C 4.--6. " CKO1_DIV ,Setting the divider of CCM_CLKO1" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x0C 0.--3. " CLKO_SEL ,Selection of the clock to be generated on CCM_CLKO1" ",,,,VID,OCRAM,QSPI2,M4,ENET_AXI,LCDIF2,LCDIF1,AHB,IPG,PERCLK,CKIL_SYNC,PLL4" line.long 0x10 "CCM_CGPR,CCM General Purpose Register" bitfld.long 0x10 17. " INT_MEM_CLK_LPM ,ARM Platform memory clocks enabled if an interrupt is pending when entering low power mode" "Disabled,Enabled" bitfld.long 0x10 16. " FPL ,Engage PLL" "Default,3 CKIL" bitfld.long 0x10 4. " EFUSE_PROG_SUPPLY_GATE ,Gate of program supply for efuse programming" "Gated off,Not gated" textline " " bitfld.long 0x10 2. " MMDC_EXT_CLK_DIS ,Disable external clock driver of MMDC during STOP mode" "No,Yes" bitfld.long 0x10 0. " PMIC_DELAY_SCALER ,Divisor of clock for stby_count" "Not divided,/8" textline "" line.long 0x14 "CCM_CCGR0,CCM Clock Gating Register 0" bitfld.long 0x14 30.--31. " CG15 ,Clock gating for power reduction of aips_tz3 clocks (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x14 26.--27. " CG13 ,Clock gating for power reduction of DCIC2 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x14 24.--25. " CG12 ,Clock gating for power reduction of DCIC 1 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x14 22.--23. " CG11 ,Clock gating for power reduction of CPU debug clocks" "OFF,ON in RUN,,ON" bitfld.long 0x14 20.--21. " CG10 ,Clock gating for power reduction of CAN2_SERIAL clock" "OFF,ON in RUN,,ON" bitfld.long 0x14 18.--19. " CG9 ,Clock gating for power reduction of CAN2 clock" "OFF,ON in RUN,,ON" bitfld.long 0x14 16.--17. " CG8 ,Clock gating for power reduction of CAN1_SERIAL clock" "OFF,ON in RUN,,ON" bitfld.long 0x14 14.--15. " CG7 ,Clock gating for power reduction of CAN1 clock" "OFF,ON in RUN,,ON" textline " " bitfld.long 0x14 12.--13. " CG6 ,Clock gating for power reduction of CAAM_WRAPPER_IPG clock" "OFF,ON in RUN,,ON" bitfld.long 0x14 10.--11. " CG5 ,Clock gating for power reduction of CAAM_WRAPPER_ACLK clock" "OFF,ON in RUN,,ON" bitfld.long 0x14 8.--9. " CG4 ,Clock gating for power reduction of CAAM_SECURE_MEM clock" "OFF,ON in RUN,,ON" bitfld.long 0x14 6.--7. " CG3 ,Clock gating for power reduction of ASRC clock" "OFF,ON in RUN,,ON" bitfld.long 0x14 4.--5. " CG2 ,Clock gating for power reduction of APBHDMA HCLK clock" "OFF,ON in RUN,,ON" bitfld.long 0x14 2.--3. " CG1 ,Clock gating for power reduction of AIPS_TZ2 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x14 0.--1. " CG0 ,Clock gating for power reduction of AIPS_TZ1 clocks" "OFF,ON in RUN,,ON" line.long 0x18 "CCM_CCGR1,CCM Clock Gating Register 1" bitfld.long 0x18 30.--31. " CG13 ,Clock gating for power reduction of CANFD clock" "OFF,ON in RUN,,ON" bitfld.long 0x18 28.--29. " CG13 ,Clock gating for power reduction of OCRAM_S clock" "OFF,ON in RUN,,ON" bitfld.long 0x18 26.--27. " CG13 ,Clock gating for power reduction of GPU clock" "OFF,ON in RUN,,ON" bitfld.long 0x18 22.--23. " CG11 ,Clock gating for power reduction of GPT serial clock" "OFF,ON in RUN,,ON" bitfld.long 0x18 20.--21. " CG10 ,Clock gating for power reduction of GPT bus clock" "OFF,ON in RUN,,ON" bitfld.long 0x18 18.--19. " CG9 ,Clock gating for power reduction of wakeup clock" "OFF,ON in RUN,,ON" bitfld.long 0x18 16.--17. " CG8 ,Clock gating for power reduction of ESAI clocks" "OFF,ON in RUN,,ON" bitfld.long 0x18 14.--15. " CG7 ,Clock gating for power reduction of EPIT2 clocks" "OFF,ON in RUN,,ON" textline " " bitfld.long 0x18 12.--13. " CG6 ,Clock gating for power reduction of EPIT1 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x18 8.--9. " CG4 ,Clock gating for power reduction of ECSPI5 clocks (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x18 6.--7. " CG3 ,Clock gating for power reduction of ECSPI4 clocks (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x18 4.--5. " CG2 ,Clock gating for power reduction of ECSPI3 clocks (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x18 2.--3. " CG1 ,Clock gating for power reduction of ECSPI2 clocks (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x18 0.--1. " CG0 ,Clock gating for power reduction of ECSPI1 clocks (Run/Wait/Stop)" "OFF,ON in RUN,,ON" line.long 0x1C "CCM_CCGR2,CCM Clock Gating Register 2" bitfld.long 0x1C 30.--31. " CG15 ,Clock gating for power reduction of PXP clocks (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x1C 28.--29. " CG14 ,Clock gating for power reduction of LCD clocks (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x1C 22.--23. " CG11 ,Clock gating for power reduction of IPSYNC_IP2APB_TZASC1_IPG clocks (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x1C 20.--21. " CG10 ,Clock gating for power reduction of IPMUX3 clock" "OFF,ON in RUN,,ON" bitfld.long 0x1C 18.--19. " CG9 ,Clock gating for power reduction of IPMUX2 clock" "OFF,ON in RUN,,ON" bitfld.long 0x1C 16.--17. " CG8 ,Clock gating for power reduction of IPMUX1 clock" "OFF,ON in RUN,,ON" bitfld.long 0x1C 14.--15. " CG7 ,Clock gating for power reduction of IOMUX_IPT_CLK_IO clock" "OFF,ON in RUN,,ON" bitfld.long 0x1C 12.--13. " CG6 ,Clock gating for power reduction of OCOTP_CTRL" "OFF,ON in RUN,,ON" textline " " bitfld.long 0x1C 10.--11. " CG5 ,Clock gating for power reduction of I2C3_SERIAL clock" "OFF,ON in RUN,,ON" bitfld.long 0x1C 8.--9. " CG4 ,Clock gating for power reduction of I2C2_SERIAL clock" "OFF,ON in RUN,,ON" bitfld.long 0x1C 6.--7. " CG3 ,Clock gating for power reduction of I2C1_SERIAL clock" "OFF,ON in RUN,,ON" bitfld.long 0x1C 2.--3. " CG1 ,Clock gating for power reduction of CSI clock" "OFF,ON in RUN,,ON" line.long 0x20 "CCM_CCGR3,CCM Clock Gating Register 3" bitfld.long 0x20 28.--29. " CG14 ,Clock gating for power reduction of OCRAM clock" "OFF,ON in RUN,,ON" bitfld.long 0x20 26.--27. " CG13 ,Clock gating for power reduction of MMDC_CORE_IPG_CLK_P1 clock" "OFF,ON in RUN,,ON" bitfld.long 0x20 24.--25. " CG12 ,Clock gating for power reduction of MMDC_CORE_IPG_CLK_P0 clock" "OFF,ON in RUN,,ON" bitfld.long 0x20 20.--21. " CG10 ,Clock gating for power reduction of MMDC_CORE_ACLK_FAST_CORE_P0 clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x20 18.--19. " CG9 ,Clock gating for power reduction of MLB clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x20 14.--15. " CG7 ,Clock gating for power reduction of QSPI1 clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x20 12.--13. " CG6 ,Clock gating for power reduction of LDB_DI0 clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x20 10.--11. " CG5 ,Clock gating for power reduction of LCDIF1 PIX clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" textline " " bitfld.long 0x20 8.--9. " CG4 ,Clock gating for power reduction of LCDIF2 PIX clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x20 6.--7. " CG3 ,Clock gating for power reduction of AXI clock" "OFF,ON in RUN,,ON" bitfld.long 0x20 4.--5. " CG2 ,Clock gating for power reduction of Enet clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x20 2.--3. " CG1 ,Clock gating for power reduction of M4 clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" line.long 0x24 "CCM_CCGR4,CCM Clock Gating Register 4" bitfld.long 0x24 30.--31. " CG15 ,Clock gating for power reduction of RAWNAND_U_GPMI_INPUT_APB clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x24 28.--29. " CG14 ,Clock gating for power reduction of RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x24 26.--27. " CG13 ,Clock gating for power reduction of RAWNAND_U_GPMI_BCH_INPUT_BCH clock (Run/Wait/Stop)" "OFF,ON in RUN,,ON" bitfld.long 0x24 24.--25. " CG12 ,Clock gating for power reduction of RAWNAND_U_BCH_INPUT_APB clock" "OFF,ON in RUN,,ON" bitfld.long 0x24 22.--23. " CG11 ,Clock gating for power reduction of PWM4 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x24 20.--21. " CG10 ,Clock gating for power reduction of PWM3 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x24 18.--19. " CG9 ,Clock gating for power reduction of PWM2 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x24 16.--17. " CG8 ,Clock gating for power reduction of PWM1 clocks" "OFF,ON in RUN,,ON" textline " " bitfld.long 0x24 14.--15. " CG7 ,Clock gating for power reduction of PL301_MX6QPER2_MAINCLK_ENABLE" "OFF,ON in RUN,,ON" bitfld.long 0x24 12.--13. " CG6 ,Clock gating for power reduction of PL301_MX6QPER1_BCH clocks" "OFF,ON in RUN,,ON" bitfld.long 0x24 10.--11. " CG5 ,Clock gating for power reduction of QSPI2 clock" "OFF,ON in RUN,,ON" bitfld.long 0x24 0.--1. " CG0 ,Clock gating for power reduction of PCIE clocks" "OFF,ON in RUN,,ON" line.long 0x28 "CCM_CCGR5,CCM Clock Gating Register 5" bitfld.long 0x28 30.--31. " CG15 ,Clock gating for power reduction of SAI2 clock" "OFF,ON in RUN,,ON" bitfld.long 0x28 28.--29. " CG12 ,Clock gating for power reduction of SAI1 clock" "OFF,ON in RUN,,ON" bitfld.long 0x28 26.--27. " CG13 ,Clock gating for power reduction of UART_SERIAL clock" "OFF,ON in RUN,,ON" bitfld.long 0x28 24.--25. " CG12 ,Clock gating for power reduction of UART clock" "OFF,ON in RUN,,ON" bitfld.long 0x28 22.--23. " CG11 ,Clock gating for power reduction of SSI3 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x28 20.--21. " CG10 ,Clock gating for power reduction of SSI2 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x28 18.--19. " CG9 ,Clock gating for power reduction of SSI1 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x28 14.--15. " CG7 ,Clock gating for power reduction of SPDIF/AUDIO clock" "OFF,ON in RUN,,ON" textline " " bitfld.long 0x28 12.--13. " CG6 ,Clock gating for power reduction of SPBA clock" "OFF,ON in RUN,,ON" bitfld.long 0x28 6.--7. " CG3 ,Clock gating for power reduction of SDMA clock" "OFF,ON in RUN,,ON" bitfld.long 0x28 0.--1. " CG0 ,Clock gating for power reduction of ROM clock" "OFF,ON in RUN,,ON" line.long 0x2C "CCM_CCGR6,CCM Clock Gating Register 6" bitfld.long 0x2C 30.--31. " CG15 ,Clock gating for power reduction of PWM7 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 28.--29. " CG14 ,Clock gating for power reduction of PWM6 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 26.--27. " CG13 ,Clock gating for power reduction of PWM5 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 24.--25. " CG12 ,Clock gating for power reduction of I2C4 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 22.--23. " CG11 ,Clock gating for power reduction of GIS clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 20.--21. " CG10 ,Clock gating for power reduction of VADC clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 18.--19. " CG8 ,Clock gating for power reduction of PWM8 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 10.--11. " CG5 ,Clock gating for power reduction of EIM_SLOW clocks" "OFF,ON in RUN,,ON" textline " " bitfld.long 0x2C 8.--9. " CG4 ,Clock gating for power reduction of USDHC4 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 6.--7. " CG3 ,Clock gating for power reduction of USDHC3 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 4.--5. " CG2 ,Clock gating for power reduction of USDHC2 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 2.--3. " CG1 ,Clock gating for power reduction of USDHC1 clocks" "OFF,ON in RUN,,ON" bitfld.long 0x2C 0.--1. " CG0 ,Clock gating for power reduction of USBOH3 clock" "OFF,ON in RUN,,ON" textline " " group.long 0x88++0x3 line.long 0x00 "CCM_CMEOR,CCM Module Enable Override Register" bitfld.long 0x00 30. " MOD_EN_OV_CAN1_CPI ,Override clock enable signal from can1 clock (not gated based on ENABLE_CLK_CPI)" "Not overridden,Overridden" bitfld.long 0x00 28. " MOD_EN_OV_CAN2_CPI ,Override clock enable signal from CAN2 clock (not gated based on ENABLE_CLK_CPI)" "Not overridden,Overridden" bitfld.long 0x00 10. " MOD_EN_OV_GPU ,Override clock enable signal from GPU" "Not overridden,Overridden" bitfld.long 0x00 7. " MOD_EN_USDHC ,Override clock enable signal from USDHC" "Not overridden,Overridden" textline " " bitfld.long 0x00 6. " MOD_EN_OV_EPIT ,Override clock enable signal from EPIT (not gated based on IPG_ENABLE_CLK)" "Not overridden,Overridden" bitfld.long 0x00 5. " MOD_EN_OV_GPT ,Override clock enable signal from GPT clock (not gated based on IPG_ENABLE_CLK)" "Not overridden,Overridden" width 0xb tree.end tree "CCM Analog Memory registers" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020C8000 else base ad:0x420C8000 endif width 28. group.long 0x00++0x0F line.long 0x00 "CCM_ANALOG_PLL_ARM,Analog ARM PLL control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x00 18. " LVDS_24MHZ_SEL ,Analog Debug Bit" "0,1" bitfld.long 0x00 17. " LVDS_SEL ,Analog Debug Bit" "0,1" textline " " bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK1,," bitfld.long 0x00 13. " ENABLE ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the pll loop divider" line.long 0x04 "CCM_ANALOG_PLL_ARM_SET,Analog ARM PLL control set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x04 18. " LVDS_24MHZ_SEL ,Analog Debug Bit" "0,1" bitfld.long 0x04 17. " LVDS_SEL ,Analog Debug Bit" "0,1" textline " " bitfld.long 0x04 16. " BYPASS ,Bypass the pll" "0,1" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK1,," bitfld.long 0x04 13. " ENABLE ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the pll loop divider" line.long 0x08 "CCM_ANALOG_PLL_ARM_CLR,Analog ARM PLL control clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x08 18. " LVDS_24MHZ_SEL ,Analog Debug Bit" "0,1" bitfld.long 0x08 17. " LVDS_SEL ,Analog Debug Bit" "0,1" textline " " bitfld.long 0x08 16. " BYPASS ,Bypass the pll" "0,1" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK1,," bitfld.long 0x08 13. " ENABLE ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the pll loop divider" line.long 0x0C "CCM_ANALOG_PLL_ARM_TOG,Analog ARM PLL control toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x0C 18. " LVDS_24MHZ_SEL ,Analog Debug Bit" "0,1" bitfld.long 0x0C 17. " LVDS_SEL ,Analog Debug Bit" "0,1" textline " " bitfld.long 0x0C 16. " BYPASS ,Bypass the pll" "0,1" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK1,," bitfld.long 0x0C 13. " ENABLE ,Enable the clock output" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the pll loop divider" textline " " group.long 0x10++0x0F line.long 0x00 "CCM_ANALOG_PLL_USB0,Analog USBPHY0 480MHz PLL Control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" textline " " bitfld.long 0x00 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x00 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x00 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY0" "Off,On" textline " " bitfld.long 0x00 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,," line.long 0x04 "CCM_ANALOG_PLL_USB0_SET,Analog USB0 480MHz PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" textline " " bitfld.long 0x04 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x04 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x04 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY0" "Off,On" textline " " bitfld.long 0x04 0.--1. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22,," line.long 0x08 "CCM_ANALOG_PLL_USB0_CLR,Analog USB0 480MHz PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" textline " " bitfld.long 0x08 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x08 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x08 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY0" "Off,On" textline " " bitfld.long 0x08 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,," line.long 0x0C "CCM_ANALOG_PLL_USB0_TOG,Analog USB0 480MHz PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" textline " " bitfld.long 0x0C 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x0C 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x0C 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY0" "Off,On" textline " " bitfld.long 0x0C 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,," group.long 0x20++0x0F line.long 0x00 "CCM_ANALOG_PLL_USB1,Analog USBPHY1 480MHz PLL Control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" textline " " bitfld.long 0x00 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x00 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x00 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY1" "Off,On" textline " " bitfld.long 0x00 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,," line.long 0x04 "CCM_ANALOG_PLL_USB1_SET,Analog USB1 480MHz PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" textline " " bitfld.long 0x04 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x04 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x04 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY1" "Off,On" textline " " bitfld.long 0x04 0.--1. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22,," line.long 0x08 "CCM_ANALOG_PLL_USB1_CLR,Analog USB1 480MHz PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" textline " " bitfld.long 0x08 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x08 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x08 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY1" "Off,On" textline " " bitfld.long 0x08 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,," line.long 0x0C "CCM_ANALOG_PLL_USB1_TOG,Analog USB1 480MHz PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" textline " " bitfld.long 0x0C 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x0C 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x0C 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY1" "Off,On" textline " " bitfld.long 0x0C 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,," textline "" group.long 0x30++0x13 line.long 0x00 "CCM_ANALOG_PLL_SYS,Analog System PLL Control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x00 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "0,1" textline " " bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" bitfld.long 0x00 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "0,1" textline " " bitfld.long 0x00 0. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22" line.long 0x04 "CCM_ANALOG_PLL_SYS_SET,Analog System PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x04 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "0,1" textline " " bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" bitfld.long 0x04 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "0,1" textline " " bitfld.long 0x04 0. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22" line.long 0x08 "CCM_ANALOG_PLL_SYS_CLR,Analog System PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x08 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "0,1" textline " " bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" bitfld.long 0x08 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "0,1" textline " " bitfld.long 0x08 0. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22" line.long 0x0C "CCM_ANALOG_PLL_SYS_TOG,Analog System PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "0,1" textline " " bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" bitfld.long 0x0C 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "0,1" textline " " bitfld.long 0x0C 0. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22" textline "" group.long 0x40++0x03 line.long 0x00 "CCM_ANALOG_PLL_SYS_SS,528MHz System PLL Spread Spectrum Register" hexmask.long.word 0x00 16.--31. 1. " STOP ,Frequency change = STOP/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz" bitfld.long 0x00 15. " ENABLE ,Spread spectrum modulation enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--14. 1. " STEP ,Frequency change step = STEP/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz" textline "" group.long 0x70++0x0F line.long 0x00 "CCM_ANALOG_PLL_AUDIO,Analog Audio PLL control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x00 19.--20. " POST_DIV_SELECT ,Analog Debug bit" "/4,/2,/1," bitfld.long 0x00 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," bitfld.long 0x00 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x04 "CCM_ANALOG_PLL_AUDIO_SET,Analog Audio PLL control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x04 19.--20. " POST_DIV_SELECT ,Analog Debug bit" "/4,/2,/1," bitfld.long 0x04 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," bitfld.long 0x04 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x08 "CCM_ANALOG_PLL_AUDIO_CLR,Analog Audio PLL control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x08 19.--20. " POST_DIV_SELECT ,Analog Debug bit" "/4,/2,/1," bitfld.long 0x08 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," bitfld.long 0x08 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" textline " " bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x0C "CCM_ANALOG_PLL_AUDIO_TOG,Analog Audio PLL control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x0C 19.--20. " POST_DIV_SELECT ,Analog Debug bit" "/4,/2,/1," bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," bitfld.long 0x0C 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" group.long 0x80++0x03 line.long 0x0 "CCM_ANALOG_PLL_AUDIO_NUM,Numerator of Audio PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " A ,30 bit numerator (A) of fractional loop divider" group.long 0x90++0x03 line.long 0x00 "CCM_ANALOG_PLL_AUDIO_DENOM,Denominator of Audio PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " B ,30 bit Denominator (B) of fractional loop divider" group.long 0xA0++0x0F line.long 0x00 "CCM_ANALOG_PLL_VIDEO,Analog Video PLL control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x00 19.--20. " POST_DIV_SELECT ,These bits implement a divider after the PLL Debug bit" "/4,/2,/1," bitfld.long 0x00 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," bitfld.long 0x00 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x04 "CCM_ANALOG_PLL_VIDEO_SET,Analog Video PLL control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x04 19.--20. " POST_DIV_SELECT ,These bits implement a divider after the PLL Debug bit" "/4,/2,/1," bitfld.long 0x04 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," bitfld.long 0x04 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x08 "CCM_ANALOG_PLL_VIDEO_CLR,Analog Video PLL control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x08 19.--20. " POST_DIV_SELECT ,These bits implement a divider after the PLL Debug bit" "/4,/2,/1," bitfld.long 0x08 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," bitfld.long 0x08 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" textline " " bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x0C "CCM_ANALOG_PLL_VIDEO_TOG,Analog Video PLL control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x0C 19.--20. " POST_DIV_SELECT ,These bits implement a divider after the PLL Debug bit" "/4,/2,/1," bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," bitfld.long 0x0C 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "0,1" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" group.long 0xB0++0x03 line.long 0x00 "CCM_ANALOG_PLL_VIDEO_NUM,Numerator of Video PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " A ,30 bit numerator (A) of fractional loop divider" group.long 0xC0++0x03 line.long 0x00 "CCM_ANALOG_PLL_VIDEO_DENOM,Denominator of Video PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " B ,30 bit Denominator (B) of fractional loop divider" group.long 0xE0++0x002F line.long 0x00 "CCM_ANALOG_PLL_ENET,Analog ENET PLL Control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not Locked,Locked" bitfld.long 0x00 21. " ENET_25M_REF_EN ,Enable the PLL providing ENET 25 MHz reference clock" "Disabled,Enabled" bitfld.long 0x00 20. " ENET2_125M_EN ,Enable the PLL providing the ENET2 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x00 19. " ENABLE_125M ,Enables an offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," textline " " bitfld.long 0x00 13. " ENET1_125M_EN ,Enable the PLL providing the ENET1 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "0,1" bitfld.long 0x00 2.--3. " ENET1_DIV_SELECT ,Controls the frequency of the ethernet1 reference clock" "25MHz,50MHz,100MHz,125MHz" bitfld.long 0x00 0.--1. " ENET0_DIV_SELECT ,Controls the frequency of the ethernet0 reference clock" "25MHz,50MHz,100MHz,125MHz" line.long 0x04 "CCM_ANALOG_PLL_ENET_SET,Analog ENET PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not Locked,Locked" bitfld.long 0x04 21. " ENET_25M_REF_EN ,Enable the PLL providing ENET 25 MHz reference clock" "Disabled,Enabled" bitfld.long 0x04 20. " ENET2_125M_EN ,Enable the PLL providing the ENET2 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x04 19. " ENABLE_125M ,Enables an offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x04 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," textline " " bitfld.long 0x04 13. " ENET1_125M_EN ,Enable the PLL providing the ENET1 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "0,1" bitfld.long 0x04 2.--3. " ENET1_DIV_SELECT ,Controls the frequency of the ethernet1 reference clock" "25MHz,50MHz,100MHz,125MHz" bitfld.long 0x04 0.--1. " ENET0_DIV_SELECT ,Controls the frequency of the ethernet0 reference clock" "25MHz,50MHz,100MHz,125MHz" line.long 0x08 "CCM_ANALOG_PLL_ENET_CLR,Analog ENET PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not Locked,Locked" bitfld.long 0x08 21. " ENET_25M_REF_EN ,Enable the PLL providing ENET 25 MHz reference clock" "Disabled,Enabled" bitfld.long 0x08 20. " ENET2_125M_EN ,Enable the PLL providing the ENET2 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x08 19. " ENABLE_125M ,Enables an offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x08 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," textline " " bitfld.long 0x08 13. " ENET1_125M_EN ,Enable the PLL providing the ENET1 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "0,1" bitfld.long 0x08 2.--3. " ENET1_DIV_SELECT ,Controls the frequency of the ethernet1 reference clock" "25MHz,50MHz,100MHz,125MHz" bitfld.long 0x08 0.--1. " ENET0_DIV_SELECT ,Controls the frequency of the ethernet0 reference clock" "25MHz,50MHz,100MHz,125MHz" line.long 0x0C "CCM_ANALOG_PLL_ENET_TOG,Analog ENET PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not Locked,Locked" bitfld.long 0x0C 21. " ENET_25M_REF_EN ,Enable the PLL providing ENET 25 MHz reference clock" "Disabled,Enabled" bitfld.long 0x0C 20. " ENET2_125M_EN ,Enable the PLL providing the ENET2 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x0C 19. " ENABLE_125M ,Enables an offset in the phase frequency detector" "Disabled,Enabled" textline " " bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "0,1" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,," textline " " bitfld.long 0x0C 13. " ENET1_125M_EN ,Enable the PLL providing the ENET1 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "0,1" bitfld.long 0x0C 2.--3. " ENET1_DIV_SELECT ,Controls the frequency of the ethernet1 reference clock" "25MHz,50MHz,100MHz,125MHz" bitfld.long 0x0C 0.--1. " ENET0_DIV_SELECT ,Controls the frequency of the ethernet0 reference clock" "25MHz,50MHz,100MHz,125MHz" textline "" line.long 0x10 "CCM_ANALOG_PFD_480,480MHz Clock Phase Fractional Divider Control Register" bitfld.long 0x10 31. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x10 30. " PFD3_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x10 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x10 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x10 22. " PFD2_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x10 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x10 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x10 14. " PFD1_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x10 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x10 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x10 6. " PFD0_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x10 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," line.long 0x14 "CCM_ANALOG_PFD_480_SET,480MHz Clock Phase Fractional Divider Control Set Register" bitfld.long 0x14 31. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x14 30. " PFD3_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x14 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x14 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x14 22. " PFD2_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x14 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x14 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x14 14. " PFD1_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x14 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x14 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x14 6. " PFD0_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x14 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," line.long 0x18 "CCM_ANALOG_PFD_480_CLR,480MHz Clock Phase Fractional Divider Control Clear Register" bitfld.long 0x18 31. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x18 30. " PFD3_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x18 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x18 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x18 22. " PFD2_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x18 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x18 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x18 14. " PFD1_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x18 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x18 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x18 6. " PFD0_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x18 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," line.long 0x1C "CCM_ANALOG_PFD_480_TOG,480MHz Clock Phase Fractional Divider Control Toggle Register" bitfld.long 0x1C 31. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x1C 30. " PFD3_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x1C 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x1C 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x1C 22. " PFD2_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x1C 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x1C 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x1C 14. " PFD1_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x1C 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x1C 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x1C 6. " PFD0_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x1C 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," line.long 0x20 "CCM_ANALOG_PFD_528,528MHz Clock Phase Fractional Divider Control Register" bitfld.long 0x20 23. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x20 22. " PFD3_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x20 16.--21. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x20 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x20 22. " PFD2_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x20 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x20 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x20 14. " PFD1_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x20 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x20 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x20 6. " PFD0_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x20 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," line.long 0x24 "CCM_ANALOG_PFD_528_SET,528MHz Clock Phase Fractional Divider Control Set Register" bitfld.long 0x24 23. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x24 22. " PFD3_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x24 16.--21. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x24 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x24 22. " PFD2_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x24 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x24 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x24 14. " PFD1_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x24 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x24 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x24 6. " PFD0_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x24 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," line.long 0x28 "CCM_ANALOG_PFD_528_CLR,528MHz Clock Phase Fractional Divider Control Clear Register" bitfld.long 0x28 23. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x28 22. " PFD3_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x28 16.--21. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x28 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x28 22. " PFD2_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x28 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x28 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x28 14. " PFD1_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x28 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x28 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x28 6. " PFD0_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x28 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," line.long 0x2C "CCM_ANALOG_PFD_528_TOG,528MHz Clock Phase Fractional Divider Control Toggle Register" bitfld.long 0x2C 23. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x2C 22. " PFD3_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x2C 16.--21. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x2C 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x2C 22. " PFD2_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x2C 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x2C 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x2C 14. " PFD1_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x2C 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " bitfld.long 0x2C 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x2C 6. " PFD0_STABLE ,The phase divider clock output" "0,1" bitfld.long 0x2C 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,,,,,,,,,,,,,,,,,,,,,,,,,,,," textline " " group.long 0x150++0x2F line.long 0x00 "CCM_ANALOG_MISC0,Miscellaneous Control Register" bitfld.long 0x00 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x00 30. " XTAL_24M_PWD ,24M crystal oscillator supply" "Powered up,Powered down" bitfld.long 0x00 29. " RTC_XTAL_SOURCE ,Chip source for the RTC clock" "Internal,RTC_XTAL" textline " " bitfld.long 0x00 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x00 25. " CLKGATE_CTRL ,Disabling the clock gate for the xtal 24MHz clock that clocks the digital logic in the analog block" "ALLOW_AUTO_GATE,NO_AUTO_GATE" bitfld.long 0x00 16. " OSC_XTALOK_EN ,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "Disabled,Enabled" textline " " rbitfld.long 0x00 15. " OSC_XTALOK ,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1" bitfld.long 0x00 13.--14. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,-12.5%,-25%,-37.5%" bitfld.long 0x00 12. " RTC_RINGOSC_EN ,Internal ring oscillator that can be used in lieu of an external 32k crystal" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode [XtalOsc/RCOsc/Old BG/New BG]" "All down exc RTC,Certain regulators up,Off/On/On/Off,Off/On/Off/On" bitfld.long 0x00 7. " REFTOP_VBGUP ,Analog bandgap voltage is up and stable" "Unstable,Stable" bitfld.long 0x00 4.--6. " REFTOP_VBGADJ ,Configure the analog behavior in stop mode" "VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" textline " " bitfld.long 0x00 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "Coarse,Bandgap-based" bitfld.long 0x00 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "0,1" line.long 0x04 "CCM_ANALOG_MISC0_SET,Miscellaneous Control Set Register" bitfld.long 0x04 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x04 30. " XTAL_24M_PWD ,24M crystal oscillator supply" "Powered up,Powered down" bitfld.long 0x04 29. " RTC_XTAL_SOURCE ,Chip source for the RTC clock" "Internal ring oscillator,RTC_XTAL" textline " " bitfld.long 0x04 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x04 25. " CLKGATE_CTRL ,Disabling the clock gate for the xtal 24MHz clock that clocks the digital logic in the analog block" "ALLOW_AUTO_GATE,NO_AUTO_GATE" bitfld.long 0x04 16. " OSC_XTALOK_EN ,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "Disabled,Enabled" textline " " rbitfld.long 0x04 15. " OSC_XTALOK ,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1" bitfld.long 0x04 13.--14. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,-12.5%,-25%,-37.5%" bitfld.long 0x04 12. " RTC_RINGOSC_EN ,Internal ring oscillator that can be used in lieu of an external 32k crystal" "Disabled,Enabled" textline " " bitfld.long 0x04 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode [XtalOsc/RCOsc/Old BG/New BG]" "All down exc RTC,Certain regulators up,Off/On/On/Off,Off/On/Off/On" bitfld.long 0x04 7. " REFTOP_VBGUP ,Analog bandgap voltage is up and stable" "Unstable,Stable" bitfld.long 0x04 4.--6. " REFTOP_VBGADJ ,Configure the analog behavior in stop mode" "VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" textline " " bitfld.long 0x04 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "Coarse,Bandgap-based" bitfld.long 0x04 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "0,1" line.long 0x08 "CCM_ANALOG_MISC0_CLR,Miscellaneous Control Clear Register" bitfld.long 0x08 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x08 30. " XTAL_24M_PWD ,24M crystal oscillator supply" "Powered up,Powered down" bitfld.long 0x08 29. " RTC_XTAL_SOURCE ,Chip source for the RTC clock" "Internal ring oscillator,RTC_XTAL" textline " " bitfld.long 0x08 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x08 25. " CLKGATE_CTRL ,Disabling the clock gate for the xtal 24MHz clock that clocks the digital logic in the analog block" "ALLOW_AUTO_GATE,NO_AUTO_GATE" bitfld.long 0x08 16. " OSC_XTALOK_EN ,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "Disabled,Enabled" textline " " rbitfld.long 0x08 15. " OSC_XTALOK ,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1" bitfld.long 0x08 13.--14. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,-12.5%,-25%,-37.5%" bitfld.long 0x08 12. " RTC_RINGOSC_EN ,Internal ring oscillator that can be used in lieu of an external 32k crystal" "Disabled,Enabled" textline " " bitfld.long 0x08 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode [XtalOsc/RCOsc/Old BG/New BG]" "All down exc RTC,Certain regulators up,Off/On/On/Off,Off/On/Off/On" bitfld.long 0x08 7. " REFTOP_VBGUP ,Analog bandgap voltage is up and stable" "Unstable,Stable" bitfld.long 0x08 4.--6. " REFTOP_VBGADJ ,Configure the analog behavior in stop mode" "VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" textline " " bitfld.long 0x08 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "Coarse,Bandgap-based" bitfld.long 0x08 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "0,1" line.long 0x0C "CCM_ANALOG_MISC0_TOG,Miscellaneous Control Toggle Register" bitfld.long 0x0C 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x0C 30. " XTAL_24M_PWD ,24M crystal oscillator supply" "Powered up,Powered down" bitfld.long 0x0C 29. " RTC_XTAL_SOURCE ,Chip source for the RTC clock" "Internal ring oscillator,RTC_XTAL" textline " " bitfld.long 0x0C 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x0C 25. " CLKGATE_CTRL ,Disabling the clock gate for the xtal 24MHz clock that clocks the digital logic in the analog block" "ALLOW_AUTO_GATE,NO_AUTO_GATE" bitfld.long 0x0C 16. " OSC_XTALOK_EN ,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "Disabled,Enabled" textline " " rbitfld.long 0x0C 15. " OSC_XTALOK ,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "0,1" bitfld.long 0x0C 13.--14. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,-12.5%,-25%,-37.5%" bitfld.long 0x0C 12. " RTC_RINGOSC_EN ,Internal ring oscillator that can be used in lieu of an external 32k crystal" "Disabled,Enabled" textline " " bitfld.long 0x0C 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode [XtalOsc/RCOsc/Old BG/New BG]" "All down exc RTC,Certain regulators up,Off/On/On/Off,Off/On/Off/On" bitfld.long 0x0C 7. " REFTOP_VBGUP ,Analog bandgap voltage is up and stable" "Unstable,Stable" bitfld.long 0x0C 4.--6. " REFTOP_VBGADJ ,Configure the analog behavior in stop mode" "VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" textline " " bitfld.long 0x0C 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "Coarse,Bandgap-based" bitfld.long 0x0C 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "0,1" textline " " line.long 0x10 "CCM_ANALOG_MISC1,Miscellaneous Control Register" eventfld.long 0x10 31. " IRQ_DIG_BO ,Any digital regulator brownout interrupt" "Not asserted,Asserted" eventfld.long 0x10 30. " IRQ_ANA_BO ,Any analog regulator brownout interrupt" "Not asserted,Asserted" eventfld.long 0x10 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt for high temperature" "Not asserted,Asserted" eventfld.long 0x10 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt for low temperature" "Not asserted,Asserted" textline " " eventfld.long 0x10 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt for a panic high temperature" "Not asserted,Asserted" bitfld.long 0x10 17. " PFD_528_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x10 16. " PFD_480_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x10 13. " LVDSCLK2_IBEN ,LVDS input buffer for anaclk2/2b" "Disabled,Enabled" textline " " bitfld.long 0x10 12. " LVDSCLK1_IBEN ,LVDS input buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x10 11. " LVDSCLK2_OBEN ,LVDS output buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x10 10. " LVDSCLK1_OBEN ,LVDS output buffer for anaclk1/1b" "Disabled,Enabled" textline " " bitfld.long 0x10 5.--9. " LVDS2_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,MLB_PLL,ETHERNET_REF,PCIE_REF,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x10 0.--4. " LVDS1_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,,,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x14 "CCM_ANALOG_MISC1_SET,Miscellaneous Control Set Register" rbitfld.long 0x14 31. " IRQ_DIG_BO ,Any digital regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x14 30. " IRQ_ANA_BO ,Any analog regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x14 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt for high temperature" "Not asserted,Asserted" rbitfld.long 0x14 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt for low temperature" "Not asserted,Asserted" textline " " rbitfld.long 0x14 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt for a panic high temperature" "Not asserted,Asserted" bitfld.long 0x14 17. " PFD_528_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x14 16. " PFD_480_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x14 13. " LVDSCLK2_IBEN ,LVDS input buffer for anaclk2/2b" "Disabled,Enabled" textline " " bitfld.long 0x14 12. " LVDSCLK1_IBEN ,LVDS input buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x14 11. " LVDSCLK2_OBEN ,LVDS output buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x14 10. " LVDSCLK1_OBEN ,LVDS output buffer for anaclk1/1b" "Disabled,Enabled" textline " " bitfld.long 0x14 5.--9. " LVDS2_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,MLB_PLL,ETHERNET_REF,PCIE_REF,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x14 0.--4. " LVDS1_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,,,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x18 "CCM_ANALOG_MISC1_CLR,Miscellaneous Control Clear Register" rbitfld.long 0x18 31. " IRQ_DIG_BO ,Any digital regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x18 30. " IRQ_ANA_BO ,Any analog regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x18 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt for high temperature" "Not asserted,Asserted" rbitfld.long 0x18 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt for low temperature" "Not asserted,Asserted" textline " " rbitfld.long 0x18 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt for a panic high temperature" "Not asserted,Asserted" bitfld.long 0x18 17. " PFD_528_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x18 16. " PFD_480_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x18 13. " LVDSCLK2_IBEN ,LVDS input buffer for anaclk2/2b" "Disabled,Enabled" textline " " bitfld.long 0x18 12. " LVDSCLK1_IBEN ,LVDS input buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x18 11. " LVDSCLK2_OBEN ,LVDS output buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x18 10. " LVDSCLK1_OBEN ,LVDS output buffer for anaclk1/1b" "Disabled,Enabled" textline " " bitfld.long 0x18 5.--9. " LVDS2_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,MLB_PLL,ETHERNET_REF,PCIE_REF,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x18 0.--4. " LVDS1_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,,,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x1C "CCM_ANALOG_MISC1_TOG,Miscellaneous Control Toggle Register" rbitfld.long 0x1C 31. " IRQ_DIG_BO ,Any digital regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x1C 30. " IRQ_ANA_BO ,Any analog regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x1C 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt for high temperature" "Not asserted,Asserted" rbitfld.long 0x1C 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt for low temperature" "Not asserted,Asserted" textline " " rbitfld.long 0x1C 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt for a panic high temperature" "Not asserted,Asserted" bitfld.long 0x1C 17. " PFD_528_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x1C 16. " PFD_480_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x1C 13. " LVDSCLK2_IBEN ,LVDS input buffer for anaclk2/2b" "Disabled,Enabled" textline " " bitfld.long 0x1C 12. " LVDSCLK1_IBEN ,LVDS input buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x1C 11. " LVDSCLK2_OBEN ,LVDS output buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x1C 10. " LVDSCLK1_OBEN ,LVDS output buffer for anaclk1/1b" "Disabled,Enabled" textline " " bitfld.long 0x1C 5.--9. " LVDS2_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,MLB_PLL,ETHERNET_REF,PCIE_REF,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x1C 0.--4. " LVDS1_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,,,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" textline " " line.long 0x20 "CCM_ANALOG_MISC2,Miscellaneous Control Register" bitfld.long 0x20 30.--31. " VIDEO_DIV ,Post-divider for video" "/1,/2,/1,/4" bitfld.long 0x20 28.--29. " REG2_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x20 26.--27. " REG1_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x20 24.--25. " REG0_STEP_TIME ,Number of clock periods" "64,128,256,512" textline " " bitfld.long 0x20 23. 15. " AUDIO_DIV ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" rbitfld.long 0x20 22. " REG2_OK ,Voltage level relative to the brownout level for the SOC supply" "Greater,Lower/Equal" textline " " bitfld.long 0x20 21. " REG2_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x20 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "0,1" rbitfld.long 0x20 16.--18. " REG2_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" textline " " bitfld.long 0x20 13. " REG1_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x20 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "0,1" rbitfld.long 0x20 8.--10. " REG1_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" textline " " bitfld.long 0x20 7. " PLL3_DISABLE ,PLL3 Disable" "No,Yes" textline " " bitfld.long 0x20 5. " REG0_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x20 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "0,1" rbitfld.long 0x20 0.--2. " REG0_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" line.long 0x24 "CCM_ANALOG_MISC2_SET,Miscellaneous Control Set Register" bitfld.long 0x24 30.--31. " VIDEO_DIV ,Post-divider for video" "/1,/2,/1,/4" bitfld.long 0x24 28.--29. " REG2_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x24 26.--27. " REG1_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x24 24.--25. " REG0_STEP_TIME ,Number of clock periods" "64,128,256,512" textline " " bitfld.long 0x24 23. 15. " AUDIO_DIV ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" rbitfld.long 0x24 22. " REG2_OK ,Voltage level relative to the brownout level for the SOC supply" "Greater,Lower/Equal" textline " " bitfld.long 0x24 21. " REG2_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x24 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "0,1" rbitfld.long 0x24 16.--18. " REG2_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" textline " " bitfld.long 0x24 13. " REG1_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x24 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "0,1" rbitfld.long 0x24 8.--10. " REG1_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" textline " " bitfld.long 0x24 7. " PLL3_DISABLE ,PLL3 Disable" "Enabled,Disabled" textline " " bitfld.long 0x24 5. " REG0_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x24 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "0,1" rbitfld.long 0x24 0.--2. " REG0_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" line.long 0x28 "CCM_ANALOG_MISC2_CLR,Miscellaneous Control Clear Register" bitfld.long 0x28 30.--31. " VIDEO_DIV ,Post-divider for video" "/1,/2,/1,/4" bitfld.long 0x28 28.--29. " REG2_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x28 26.--27. " REG1_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x28 24.--25. " REG0_STEP_TIME ,Number of clock periods" "64,128,256,512" textline " " bitfld.long 0x28 23. 15. " AUDIO_DIV ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" rbitfld.long 0x28 22. " REG2_OK ,Voltage level relative to the brownout level for the SOC supply" "Greater,Lower/Equal" textline " " bitfld.long 0x28 21. " REG2_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x28 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "0,1" rbitfld.long 0x28 16.--18. " REG2_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" textline " " bitfld.long 0x28 13. " REG1_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x28 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "0,1" rbitfld.long 0x28 8.--10. " REG1_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" textline " " bitfld.long 0x28 7. " PLL3_DISABLE ,PLL3 Disable" "Enabled,Disabled" textline " " bitfld.long 0x28 5. " REG0_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x28 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "0,1" rbitfld.long 0x28 0.--2. " REG0_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" line.long 0x2C "CCM_ANALOG_MISC2_TOG,Miscellaneous Control Toggle Register" bitfld.long 0x2C 30.--31. " VIDEO_DIV ,Post-divider for video" "/1,/2,/1,/4" bitfld.long 0x2C 28.--29. " REG2_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x2C 26.--27. " REG1_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x2C 24.--25. " REG0_STEP_TIME ,Number of clock periods" "64,128,256,512" textline " " bitfld.long 0x2C 23. 15. " AUDIO_DIV ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" rbitfld.long 0x2C 22. " REG2_OK ,Voltage level relative to the brownout level for the SOC supply" "Greater,Lower/Equal" textline " " bitfld.long 0x2C 21. " REG2_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x2C 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "0,1" rbitfld.long 0x2C 16.--18. " REG2_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" textline " " bitfld.long 0x2C 13. " REG1_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x2C 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "0,1" rbitfld.long 0x2C 8.--10. " REG1_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" textline " " bitfld.long 0x2C 7. " PLL3_DISABLE ,PLL3 Disable" "Enabled,Disabled" textline " " bitfld.long 0x2C 5. " REG0_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x2C 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "0,1" rbitfld.long 0x2C 0.--2. " REG0_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" width 0xb tree.end tree.end tree.open "CSI (CMOS Sensor Interface)" tree "CSI1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02214000 width 24. if (((per.l(ad:0x02214000))&0x500)==0x000) group.long 0x00++0x03 line.long 0x00 "CSI1_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO Clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO Clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated Clock Mode Enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x02214000))&0x500)==0x100) group.long 0x00++0x03 line.long 0x00 "CSI1_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated Clock Mode Enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x02214000))&0x500)==0x400) group.long 0x00++0x03 line.long 0x00 "CSI1_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO Clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO Clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" else group.long 0x00++0x03 line.long 0x00 "CSI1_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" endif group.long 0x04++0x07 line.long 0x00 "CSI1_CSICR2,CSI Control Register 2" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE_RFF ,Burst Type of DMA Transfer from RxFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 28.--29. " DMA_BURST_TYPE_SFF ,Burst Type of DMA Transfer from STATFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 26. " DRM ,Controls size of statistics grid" "8x6,8x12" bitfld.long 0x00 24.--25. " AFS ,Selects which green pixels are used for auto-focus" "Consecutive,Every third,Every four,Every four" textline " " bitfld.long 0x00 23. " SCE ,Enables or disables the skip count feature" "Disabled,Enabled" bitfld.long 0x00 19.--20. " BTS ,Controls the Bayer pattern starting point" "GR,RG,BG,GB" bitfld.long 0x00 16.--18. " LVRM ,Selects the grid size used for live view resolution" "512x384,448x336,384x288,384x256,320x240,288x216,400x300," textline " " hexmask.long.byte 0x00 8.--15. 1. " VSC ,Number of rows to skip" hexmask.long.byte 0x00 0.--7. 1. " HSC ,Number of pixels to skip" line.long 0x04 "CSI1_CSICR3,CSI Control Register 3" hexmask.long.word 0x04 16.--31. 1. " FRMCNT ,16-bit Frame Counter" bitfld.long 0x04 15. " FRMCNT_RST ,Frame Count Reset" "Not reset,Reset" bitfld.long 0x04 14. " DMA_REFLASH_RFF ,This bit reflash the embedded DMA controller for RxFIFO" "Not reflashing,Reflashed" bitfld.long 0x04 13. " DMA_REFLASH_SFF ,This bit reflash the embedded DMA controller for STATFIFO" "Not reflashing,Reflashed" textline " " bitfld.long 0x04 12. " DMA_REQ_EN_RFF ,DMA Request Enable for RxFIFO" "Disabled,Enabled" bitfld.long 0x04 11. " DMA_REQ_EN_SFF ,DMA Request Enable for STATFIFO" "Disabled,Enabled" bitfld.long 0x04 8.--10. " STATFF_LEVEL ,Number of data words in STATFIFO which generates an interrupt" "4,8,12,16,24,32,48,64" bitfld.long 0x04 7. " HRESP_ERR_EN ,Hresponse error interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 4.--6. " RxFF_LEVEL ,Number of data words after a RxFIFO full interrupt is generated" "4,8,16,24,32,48,64,96" bitfld.long 0x04 3. " TWO_8BIT_SENSOR ,Two 8-bit Sensor Mode" "Only one,Two 8-bit" bitfld.long 0x04 2. " ZERO_PACK_EN ,Dummy Zero Packing Enable" "Disabled,Enabled" bitfld.long 0x04 1. " ECC_INT_EN ,Error Detection Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ECC_AUTO_EN ,Automatic Error Correction Enable" "Disabled,Enabled" hgroup.long 0x0C++0x03 hide.long 0x00 "CSI1_CSISTATFIFO,CSI Statistic FIFO Register" in hgroup.long 0x10++0x03 hide.long 0x04 "CSI1_CSIRFIFO,CSI RX FIFO Register" in group.long 0x14++0x07 line.long 0x00 "CSI1_CSIRXCNT,CSI RX Count Register" hexmask.long.tbyte 0x00 0.--21. 1. " RXCNT ,22-bit counter for RXFIFO" line.long 0x04 "CSI1_CSISR,CSI Status Register" eventfld.long 0x04 28. " BASEADDR_CHHANGE_ERROR ,Switching occurred before DMA completed" "0,1" eventfld.long 0x04 27. " DMA_FIELD0_DONE ,DMA field 0 is complete" "Not completed,Completed" eventfld.long 0x04 26. " DMA_FIELD1_DONE ,DMA field 1 is complete" "Not completed,Completed" eventfld.long 0x04 25. " SF_OR_INT ,STATFIFO Overrun Interrupt Status" "No overflow,Overflow" textline " " eventfld.long 0x04 24. " RF_OR_INT ,RXFIFO Overrun Interrupt Status" "No overflow,Overflow" eventfld.long 0x04 22. " DMA_TSF_DONE_SFF ,DMA Transfer Done from StatFIFO" "Not completed,Completed" bitfld.long 0x04 21. " STATFF_INT ,STATFIFO Full Interrupt Status" "Not full,Full" eventfld.long 0x04 20. " DMA_TSF_DONE_FB2 ,DMA Transfer Done in Frame Buffer2" "Not completed,Completed" textline " " eventfld.long 0x04 19. " DMA_TSF_DONE_FB1 ,DMA Transfer Done in Frame Buffer1" "Not completed,Completed" bitfld.long 0x04 18. " RXFF_INT ,RXFIFO Full Interrupt Status" "Not full,Full" eventfld.long 0x04 17. " EOF_INT ,End of Frame (EOF) Interrupt Status" "Not detected,Detected" eventfld.long 0x04 16. " SOF_INT ,Start of Frame Interrupt Status" "Not detected,Detected" textline " " bitfld.long 0x04 15. " F2_INT ,CCIR Field 2 Interrupt Status" "Not detected,About to start" bitfld.long 0x04 14. " F1_INT ,CCIR Field 1 Interrupt Status" "Not detected,About to start" eventfld.long 0x04 13. " COF_INT ,Change Of Field Interrupt Status" "Not changed,Change detected" textline " " eventfld.long 0x04 7. " HRESP_ERR_INT ,Hresponse Error Interrupt Status" "No error,Error" eventfld.long 0x04 1. " ECC_INT ,CCIR Error Interrupt" "No error,Error" bitfld.long 0x04 0. " DRDY ,Presence of data that is ready for transfer in the RxFIFO" "Not ready,Ready" group.long 0x20++0x2F line.long 0x00 "CSI1_CSIDMASA_STATFIFO,CSI DMA Start Address Register - for STATFIFO" hexmask.long 0x00 2.--31. 0x4 " DMA_START_ADDR_SFF ,Indicates the start address to write data" line.long 0x04 "CSI1_CSIDMATS_STATFIFO,CSI DMA Transfer Size Register - for STATFIFO" line.long 0x08 "CSI1_CSIDMASA_FB1,CSI DMA Start Address Register - for Frame Buffer1" hexmask.long 0x08 2.--31. 0x4 " DMA_START_ADDR_FB1 ,DMA Start Address in Frame Buffer1" line.long 0x0C "CSI1_CSIDMASA_FB2,CSI DMA Transfer Size Register - for Frame Buffer2" hexmask.long 0x0C 2.--31. 0x4 " DMA_START_ADDR_FB2 ,DMA Start Address in Frame Buffer2" line.long 0x10 "CSI1_CSIFBUF_PARA,CSI Frame Buffer Parameter Register" hexmask.long.word 0x10 0.--15. 1. " FBUF_STRIDE ,Indicates the stride of the frame buffer" line.long 0x14 "CSI1_CSIIMAG_PARA,CSI Image Parameter Register" hexmask.long.word 0x14 16.--31. 1. " IMAGE_WIDTH ,Indicates how many pixels in a line of the image from the sensor" hexmask.long.word 0x14 0.--15. 1. " IMAGE_HEIGHT ,Indicates how many pixels in a column of the image from the sensor" group.long 0x48++0x07 line.long 0x00 "CSI1_CSICR18,CSI Control Register 18" bitfld.long 0x00 31. " CSI_ENABLE ,CSI global enable signal" "Disabled,Enabled" bitfld.long 0x00 18.--19. " MASK_OPTION ,Methods of masking the CSI input" "1st frame,CSI_ENABLE = 1,2nd frame,Data comes" bitfld.long 0x00 16.--17. " CSI_LCDIF_BUFFER_LINES ,Number of lines are used in handshake mode with LCDIF" "4,8,16,16" textline " " bitfld.long 0x00 12.--15. " AHB_HPROT ,Hprot value in AHB bus protocol" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. " RGB888A_FORMAT_SEL ,Output is 32-bit format" "8h0_data[23:0],data[23:0]_8h0" bitfld.long 0x00 9. " BASEADDR_CHANGE_ERROR_IE ,Base address change error interrupt enable signal" "0,1" textline " " bitfld.long 0x00 8. " LAST_DMA_REQ_SEL ,Choosing the last DMA request condition" "FIFO_full_level,Hburst_length" bitfld.long 0x00 7. " DMA_FIELD1_DONE_IE ,Field 1 done interrupt enable(in interlace mode)" "Disabled,Enabled" bitfld.long 0x00 6. " FIELD0_DONE_IE ,Field 0 means interrupt enabled (interlace)" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " BASEADDR_SWITCH_SEL ,CSI 2 base addresses switching method" "Vsync,First data" bitfld.long 0x00 4. " BASEADDR_SWITCH_EN ,Switching the base address according to BASEADDR_SWITCH_SEL or atomically by DMA completed" "Atomically,BASEADDR_SWITCH_SEL" bitfld.long 0x00 3. " PARALLEL24_EN ,Parallel input rgb888/yuv444 24bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DEINTERLACE_EN ,Output method When input is TVDECODER or standard CCIR656 video" "Deinterlace disabled,Deinterlace enabled" bitfld.long 0x00 1. " TVDECODER_IN_EN ,Input source" "Other,TV decoder" bitfld.long 0x00 0. " NTSC_EN ,Selection of NTSC/PAL mode (when input is TVDECODER or standard CCIR656)" "PAL,NTSC" line.long 0x04 "CSI1_CSICR19,CSI Control Register 19" hexmask.long.byte 0x04 0.--7. 1. " ,Highest FIFO level achieved by CSI FIFO timely" width 0x0b else base ad:0x42214000 width 24. if (((per.l(ad:0x42214000))&0x500)==0x000) group.long 0x00++0x03 line.long 0x00 "CSI1_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO Clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO Clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated Clock Mode Enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x42214000))&0x500)==0x100) group.long 0x00++0x03 line.long 0x00 "CSI1_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated Clock Mode Enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x42214000))&0x500)==0x400) group.long 0x00++0x03 line.long 0x00 "CSI1_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO Clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO Clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" else group.long 0x00++0x03 line.long 0x00 "CSI1_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" endif group.long 0x04++0x07 line.long 0x00 "CSI1_CSICR2,CSI Control Register 2" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE_RFF ,Burst Type of DMA Transfer from RxFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 28.--29. " DMA_BURST_TYPE_SFF ,Burst Type of DMA Transfer from STATFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 26. " DRM ,Controls size of statistics grid" "8x6,8x12" bitfld.long 0x00 24.--25. " AFS ,Selects which green pixels are used for auto-focus" "Consecutive,Every third,Every four,Every four" textline " " bitfld.long 0x00 23. " SCE ,Enables or disables the skip count feature" "Disabled,Enabled" bitfld.long 0x00 19.--20. " BTS ,Controls the Bayer pattern starting point" "GR,RG,BG,GB" bitfld.long 0x00 16.--18. " LVRM ,Selects the grid size used for live view resolution" "512x384,448x336,384x288,384x256,320x240,288x216,400x300," textline " " hexmask.long.byte 0x00 8.--15. 1. " VSC ,Number of rows to skip" hexmask.long.byte 0x00 0.--7. 1. " HSC ,Number of pixels to skip" line.long 0x04 "CSI1_CSICR3,CSI Control Register 3" hexmask.long.word 0x04 16.--31. 1. " FRMCNT ,16-bit Frame Counter" bitfld.long 0x04 15. " FRMCNT_RST ,Frame Count Reset" "Not reset,Reset" bitfld.long 0x04 14. " DMA_REFLASH_RFF ,This bit reflash the embedded DMA controller for RxFIFO" "Not reflashing,Reflashed" bitfld.long 0x04 13. " DMA_REFLASH_SFF ,This bit reflash the embedded DMA controller for STATFIFO" "Not reflashing,Reflashed" textline " " bitfld.long 0x04 12. " DMA_REQ_EN_RFF ,DMA Request Enable for RxFIFO" "Disabled,Enabled" bitfld.long 0x04 11. " DMA_REQ_EN_SFF ,DMA Request Enable for STATFIFO" "Disabled,Enabled" bitfld.long 0x04 8.--10. " STATFF_LEVEL ,Number of data words in STATFIFO which generates an interrupt" "4,8,12,16,24,32,48,64" bitfld.long 0x04 7. " HRESP_ERR_EN ,Hresponse error interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 4.--6. " RxFF_LEVEL ,Number of data words after a RxFIFO full interrupt is generated" "4,8,16,24,32,48,64,96" bitfld.long 0x04 3. " TWO_8BIT_SENSOR ,Two 8-bit Sensor Mode" "Only one,Two 8-bit" bitfld.long 0x04 2. " ZERO_PACK_EN ,Dummy Zero Packing Enable" "Disabled,Enabled" bitfld.long 0x04 1. " ECC_INT_EN ,Error Detection Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ECC_AUTO_EN ,Automatic Error Correction Enable" "Disabled,Enabled" hgroup.long 0x0C++0x03 hide.long 0x00 "CSI1_CSISTATFIFO,CSI Statistic FIFO Register" in hgroup.long 0x10++0x03 hide.long 0x04 "CSI1_CSIRFIFO,CSI RX FIFO Register" in group.long 0x14++0x07 line.long 0x00 "CSI1_CSIRXCNT,CSI RX Count Register" hexmask.long.tbyte 0x00 0.--21. 1. " RXCNT ,22-bit counter for RXFIFO" line.long 0x04 "CSI1_CSISR,CSI Status Register" eventfld.long 0x04 28. " BASEADDR_CHHANGE_ERROR ,Switching occurred before DMA completed" "0,1" eventfld.long 0x04 27. " DMA_FIELD0_DONE ,DMA field 0 is complete" "Not completed,Completed" eventfld.long 0x04 26. " DMA_FIELD1_DONE ,DMA field 1 is complete" "Not completed,Completed" eventfld.long 0x04 25. " SF_OR_INT ,STATFIFO Overrun Interrupt Status" "No overflow,Overflow" textline " " eventfld.long 0x04 24. " RF_OR_INT ,RXFIFO Overrun Interrupt Status" "No overflow,Overflow" eventfld.long 0x04 22. " DMA_TSF_DONE_SFF ,DMA Transfer Done from StatFIFO" "Not completed,Completed" bitfld.long 0x04 21. " STATFF_INT ,STATFIFO Full Interrupt Status" "Not full,Full" eventfld.long 0x04 20. " DMA_TSF_DONE_FB2 ,DMA Transfer Done in Frame Buffer2" "Not completed,Completed" textline " " eventfld.long 0x04 19. " DMA_TSF_DONE_FB1 ,DMA Transfer Done in Frame Buffer1" "Not completed,Completed" bitfld.long 0x04 18. " RXFF_INT ,RXFIFO Full Interrupt Status" "Not full,Full" eventfld.long 0x04 17. " EOF_INT ,End of Frame (EOF) Interrupt Status" "Not detected,Detected" eventfld.long 0x04 16. " SOF_INT ,Start of Frame Interrupt Status" "Not detected,Detected" textline " " bitfld.long 0x04 15. " F2_INT ,CCIR Field 2 Interrupt Status" "Not detected,About to start" bitfld.long 0x04 14. " F1_INT ,CCIR Field 1 Interrupt Status" "Not detected,About to start" eventfld.long 0x04 13. " COF_INT ,Change Of Field Interrupt Status" "Not changed,Change detected" textline " " eventfld.long 0x04 7. " HRESP_ERR_INT ,Hresponse Error Interrupt Status" "No error,Error" eventfld.long 0x04 1. " ECC_INT ,CCIR Error Interrupt" "No error,Error" bitfld.long 0x04 0. " DRDY ,Presence of data that is ready for transfer in the RxFIFO" "Not ready,Ready" group.long 0x20++0x2F line.long 0x00 "CSI1_CSIDMASA_STATFIFO,CSI DMA Start Address Register - for STATFIFO" hexmask.long 0x00 2.--31. 0x4 " DMA_START_ADDR_SFF ,Indicates the start address to write data" line.long 0x04 "CSI1_CSIDMATS_STATFIFO,CSI DMA Transfer Size Register - for STATFIFO" line.long 0x08 "CSI1_CSIDMASA_FB1,CSI DMA Start Address Register - for Frame Buffer1" hexmask.long 0x08 2.--31. 0x4 " DMA_START_ADDR_FB1 ,DMA Start Address in Frame Buffer1" line.long 0x0C "CSI1_CSIDMASA_FB2,CSI DMA Transfer Size Register - for Frame Buffer2" hexmask.long 0x0C 2.--31. 0x4 " DMA_START_ADDR_FB2 ,DMA Start Address in Frame Buffer2" line.long 0x10 "CSI1_CSIFBUF_PARA,CSI Frame Buffer Parameter Register" hexmask.long.word 0x10 0.--15. 1. " FBUF_STRIDE ,Indicates the stride of the frame buffer" line.long 0x14 "CSI1_CSIIMAG_PARA,CSI Image Parameter Register" hexmask.long.word 0x14 16.--31. 1. " IMAGE_WIDTH ,Indicates how many pixels in a line of the image from the sensor" hexmask.long.word 0x14 0.--15. 1. " IMAGE_HEIGHT ,Indicates how many pixels in a column of the image from the sensor" group.long 0x48++0x07 line.long 0x00 "CSI1_CSICR18,CSI Control Register 18" bitfld.long 0x00 31. " CSI_ENABLE ,CSI global enable signal" "Disabled,Enabled" bitfld.long 0x00 18.--19. " MASK_OPTION ,Methods of masking the CSI input" "1st frame,CSI_ENABLE = 1,2nd frame,Data comes" bitfld.long 0x00 16.--17. " CSI_LCDIF_BUFFER_LINES ,Number of lines are used in handshake mode with LCDIF" "4,8,16,16" textline " " bitfld.long 0x00 12.--15. " AHB_HPROT ,Hprot value in AHB bus protocol" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. " RGB888A_FORMAT_SEL ,Output is 32-bit format" "8h0_data[23:0],data[23:0]_8h0" bitfld.long 0x00 9. " BASEADDR_CHANGE_ERROR_IE ,Base address change error interrupt enable signal" "0,1" textline " " bitfld.long 0x00 8. " LAST_DMA_REQ_SEL ,Choosing the last DMA request condition" "FIFO_full_level,Hburst_length" bitfld.long 0x00 7. " DMA_FIELD1_DONE_IE ,Field 1 done interrupt enable(in interlace mode)" "Disabled,Enabled" bitfld.long 0x00 6. " FIELD0_DONE_IE ,Field 0 means interrupt enabled (interlace)" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " BASEADDR_SWITCH_SEL ,CSI 2 base addresses switching method" "Vsync,First data" bitfld.long 0x00 4. " BASEADDR_SWITCH_EN ,Switching the base address according to BASEADDR_SWITCH_SEL or atomically by DMA completed" "Atomically,BASEADDR_SWITCH_SEL" bitfld.long 0x00 3. " PARALLEL24_EN ,Parallel input rgb888/yuv444 24bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DEINTERLACE_EN ,Output method When input is TVDECODER or standard CCIR656 video" "Deinterlace disabled,Deinterlace enabled" bitfld.long 0x00 1. " TVDECODER_IN_EN ,Input source" "Other,TV decoder" bitfld.long 0x00 0. " NTSC_EN ,Selection of NTSC/PAL mode (when input is TVDECODER or standard CCIR656)" "PAL,NTSC" line.long 0x04 "CSI1_CSICR19,CSI Control Register 19" hexmask.long.byte 0x04 0.--7. 1. " ,Highest FIFO level achieved by CSI FIFO timely" width 0x0b endif tree.end tree "CSI2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0221C000 width 24. if (((per.l(ad:0x0221C000))&0x500)==0x000) group.long 0x00++0x03 line.long 0x00 "CSI2_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO Clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO Clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated Clock Mode Enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x0221C000))&0x500)==0x100) group.long 0x00++0x03 line.long 0x00 "CSI2_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated Clock Mode Enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x0221C000))&0x500)==0x400) group.long 0x00++0x03 line.long 0x00 "CSI2_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO Clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO Clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" else group.long 0x00++0x03 line.long 0x00 "CSI2_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" endif group.long 0x04++0x07 line.long 0x00 "CSI2_CSICR2,CSI Control Register 2" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE_RFF ,Burst Type of DMA Transfer from RxFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 28.--29. " DMA_BURST_TYPE_SFF ,Burst Type of DMA Transfer from STATFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 26. " DRM ,Controls size of statistics grid" "8x6,8x12" bitfld.long 0x00 24.--25. " AFS ,Selects which green pixels are used for auto-focus" "Consecutive,Every third,Every four,Every four" textline " " bitfld.long 0x00 23. " SCE ,Enables or disables the skip count feature" "Disabled,Enabled" bitfld.long 0x00 19.--20. " BTS ,Controls the Bayer pattern starting point" "GR,RG,BG,GB" bitfld.long 0x00 16.--18. " LVRM ,Selects the grid size used for live view resolution" "512x384,448x336,384x288,384x256,320x240,288x216,400x300," textline " " hexmask.long.byte 0x00 8.--15. 1. " VSC ,Number of rows to skip" hexmask.long.byte 0x00 0.--7. 1. " HSC ,Number of pixels to skip" line.long 0x04 "CSI2_CSICR3,CSI Control Register 3" hexmask.long.word 0x04 16.--31. 1. " FRMCNT ,16-bit Frame Counter" bitfld.long 0x04 15. " FRMCNT_RST ,Frame Count Reset" "Not reset,Reset" bitfld.long 0x04 14. " DMA_REFLASH_RFF ,This bit reflash the embedded DMA controller for RxFIFO" "Not reflashing,Reflashed" bitfld.long 0x04 13. " DMA_REFLASH_SFF ,This bit reflash the embedded DMA controller for STATFIFO" "Not reflashing,Reflashed" textline " " bitfld.long 0x04 12. " DMA_REQ_EN_RFF ,DMA Request Enable for RxFIFO" "Disabled,Enabled" bitfld.long 0x04 11. " DMA_REQ_EN_SFF ,DMA Request Enable for STATFIFO" "Disabled,Enabled" bitfld.long 0x04 8.--10. " STATFF_LEVEL ,Number of data words in STATFIFO which generates an interrupt" "4,8,12,16,24,32,48,64" bitfld.long 0x04 7. " HRESP_ERR_EN ,Hresponse error interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 4.--6. " RxFF_LEVEL ,Number of data words after a RxFIFO full interrupt is generated" "4,8,16,24,32,48,64,96" bitfld.long 0x04 3. " TWO_8BIT_SENSOR ,Two 8-bit Sensor Mode" "Only one,Two 8-bit" bitfld.long 0x04 2. " ZERO_PACK_EN ,Dummy Zero Packing Enable" "Disabled,Enabled" bitfld.long 0x04 1. " ECC_INT_EN ,Error Detection Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ECC_AUTO_EN ,Automatic Error Correction Enable" "Disabled,Enabled" hgroup.long 0x0C++0x03 hide.long 0x00 "CSI2_CSISTATFIFO,CSI Statistic FIFO Register" in hgroup.long 0x10++0x03 hide.long 0x04 "CSI2_CSIRFIFO,CSI RX FIFO Register" in group.long 0x14++0x07 line.long 0x00 "CSI2_CSIRXCNT,CSI RX Count Register" hexmask.long.tbyte 0x00 0.--21. 1. " RXCNT ,22-bit counter for RXFIFO" line.long 0x04 "CSI2_CSISR,CSI Status Register" eventfld.long 0x04 28. " BASEADDR_CHHANGE_ERROR ,Switching occurred before DMA completed" "0,1" eventfld.long 0x04 27. " DMA_FIELD0_DONE ,DMA field 0 is complete" "Not completed,Completed" eventfld.long 0x04 26. " DMA_FIELD1_DONE ,DMA field 1 is complete" "Not completed,Completed" eventfld.long 0x04 25. " SF_OR_INT ,STATFIFO Overrun Interrupt Status" "No overflow,Overflow" textline " " eventfld.long 0x04 24. " RF_OR_INT ,RXFIFO Overrun Interrupt Status" "No overflow,Overflow" eventfld.long 0x04 22. " DMA_TSF_DONE_SFF ,DMA Transfer Done from StatFIFO" "Not completed,Completed" bitfld.long 0x04 21. " STATFF_INT ,STATFIFO Full Interrupt Status" "Not full,Full" eventfld.long 0x04 20. " DMA_TSF_DONE_FB2 ,DMA Transfer Done in Frame Buffer2" "Not completed,Completed" textline " " eventfld.long 0x04 19. " DMA_TSF_DONE_FB1 ,DMA Transfer Done in Frame Buffer1" "Not completed,Completed" bitfld.long 0x04 18. " RXFF_INT ,RXFIFO Full Interrupt Status" "Not full,Full" eventfld.long 0x04 17. " EOF_INT ,End of Frame (EOF) Interrupt Status" "Not detected,Detected" eventfld.long 0x04 16. " SOF_INT ,Start of Frame Interrupt Status" "Not detected,Detected" textline " " bitfld.long 0x04 15. " F2_INT ,CCIR Field 2 Interrupt Status" "Not detected,About to start" bitfld.long 0x04 14. " F1_INT ,CCIR Field 1 Interrupt Status" "Not detected,About to start" eventfld.long 0x04 13. " COF_INT ,Change Of Field Interrupt Status" "Not changed,Change detected" textline " " eventfld.long 0x04 7. " HRESP_ERR_INT ,Hresponse Error Interrupt Status" "No error,Error" eventfld.long 0x04 1. " ECC_INT ,CCIR Error Interrupt" "No error,Error" bitfld.long 0x04 0. " DRDY ,Presence of data that is ready for transfer in the RxFIFO" "Not ready,Ready" group.long 0x20++0x2F line.long 0x00 "CSI2_CSIDMASA_STATFIFO,CSI DMA Start Address Register - for STATFIFO" hexmask.long 0x00 2.--31. 0x4 " DMA_START_ADDR_SFF ,Indicates the start address to write data" line.long 0x04 "CSI2_CSIDMATS_STATFIFO,CSI DMA Transfer Size Register - for STATFIFO" line.long 0x08 "CSI2_CSIDMASA_FB1,CSI DMA Start Address Register - for Frame Buffer1" hexmask.long 0x08 2.--31. 0x4 " DMA_START_ADDR_FB1 ,DMA Start Address in Frame Buffer1" line.long 0x0C "CSI2_CSIDMASA_FB2,CSI DMA Transfer Size Register - for Frame Buffer2" hexmask.long 0x0C 2.--31. 0x4 " DMA_START_ADDR_FB2 ,DMA Start Address in Frame Buffer2" line.long 0x10 "CSI2_CSIFBUF_PARA,CSI Frame Buffer Parameter Register" hexmask.long.word 0x10 0.--15. 1. " FBUF_STRIDE ,Indicates the stride of the frame buffer" line.long 0x14 "CSI2_CSIIMAG_PARA,CSI Image Parameter Register" hexmask.long.word 0x14 16.--31. 1. " IMAGE_WIDTH ,Indicates how many pixels in a line of the image from the sensor" hexmask.long.word 0x14 0.--15. 1. " IMAGE_HEIGHT ,Indicates how many pixels in a column of the image from the sensor" group.long 0x48++0x07 line.long 0x00 "CSI2_CSICR18,CSI Control Register 18" bitfld.long 0x00 31. " CSI_ENABLE ,CSI global enable signal" "Disabled,Enabled" bitfld.long 0x00 18.--19. " MASK_OPTION ,Methods of masking the CSI input" "1st frame,CSI_ENABLE = 1,2nd frame,Data comes" bitfld.long 0x00 16.--17. " CSI_LCDIF_BUFFER_LINES ,Number of lines are used in handshake mode with LCDIF" "4,8,16,16" textline " " bitfld.long 0x00 12.--15. " AHB_HPROT ,Hprot value in AHB bus protocol" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. " RGB888A_FORMAT_SEL ,Output is 32-bit format" "8h0_data[23:0],data[23:0]_8h0" bitfld.long 0x00 9. " BASEADDR_CHANGE_ERROR_IE ,Base address change error interrupt enable signal" "0,1" textline " " bitfld.long 0x00 8. " LAST_DMA_REQ_SEL ,Choosing the last DMA request condition" "FIFO_full_level,Hburst_length" bitfld.long 0x00 7. " DMA_FIELD1_DONE_IE ,Field 1 done interrupt enable(in interlace mode)" "Disabled,Enabled" bitfld.long 0x00 6. " FIELD0_DONE_IE ,Field 0 means interrupt enabled (interlace)" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " BASEADDR_SWITCH_SEL ,CSI 2 base addresses switching method" "Vsync,First data" bitfld.long 0x00 4. " BASEADDR_SWITCH_EN ,Switching the base address according to BASEADDR_SWITCH_SEL or atomically by DMA completed" "Atomically,BASEADDR_SWITCH_SEL" bitfld.long 0x00 3. " PARALLEL24_EN ,Parallel input rgb888/yuv444 24bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DEINTERLACE_EN ,Output method When input is TVDECODER or standard CCIR656 video" "Deinterlace disabled,Deinterlace enabled" bitfld.long 0x00 1. " TVDECODER_IN_EN ,Input source" "Other,TV decoder" bitfld.long 0x00 0. " NTSC_EN ,Selection of NTSC/PAL mode (when input is TVDECODER or standard CCIR656)" "PAL,NTSC" line.long 0x04 "CSI2_CSICR19,CSI Control Register 19" hexmask.long.byte 0x04 0.--7. 1. " ,Highest FIFO level achieved by CSI FIFO timely" width 0x0b else base ad:0x4221C000 width 24. if (((per.l(ad:0x4221C000))&0x500)==0x000) group.long 0x00++0x03 line.long 0x00 "CSI2_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO Clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO Clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated Clock Mode Enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x4221C000))&0x500)==0x100) group.long 0x00++0x03 line.long 0x00 "CSI2_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 4. " GCLK_MODE ,Gated Clock Mode Enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" elif (((per.l(ad:0x4221C000))&0x500)==0x400) group.long 0x00++0x03 line.long 0x00 "CSI2_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO Clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO Clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" else group.long 0x00++0x03 line.long 0x00 "CSI2_CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit Enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC Enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP Interface Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " VIDEO_MODE ,Video Mode Select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change Of Image Field Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RxFIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame Buffer2 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame Buffer1 DMA Transfer Done Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXFF_INTEN ,RxFIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF Interrupt Polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start Of Frame Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSYNC_POL ,HSYNC Polarity Select" "Low,High" textline " " bitfld.long 0x00 10. " CCIR_EN ,CCIR656 Interface Enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO Clear Control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data Packing Direction" "From LSB,From MSB" textline " " textline " " bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert Pixel Clock Input" "Direct,Inverted" textline " " bitfld.long 0x00 1. " REDGE ,Valid Pixel Clock Edge Select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" endif group.long 0x04++0x07 line.long 0x00 "CSI2_CSICR2,CSI Control Register 2" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE_RFF ,Burst Type of DMA Transfer from RxFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 28.--29. " DMA_BURST_TYPE_SFF ,Burst Type of DMA Transfer from STATFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x00 26. " DRM ,Controls size of statistics grid" "8x6,8x12" bitfld.long 0x00 24.--25. " AFS ,Selects which green pixels are used for auto-focus" "Consecutive,Every third,Every four,Every four" textline " " bitfld.long 0x00 23. " SCE ,Enables or disables the skip count feature" "Disabled,Enabled" bitfld.long 0x00 19.--20. " BTS ,Controls the Bayer pattern starting point" "GR,RG,BG,GB" bitfld.long 0x00 16.--18. " LVRM ,Selects the grid size used for live view resolution" "512x384,448x336,384x288,384x256,320x240,288x216,400x300," textline " " hexmask.long.byte 0x00 8.--15. 1. " VSC ,Number of rows to skip" hexmask.long.byte 0x00 0.--7. 1. " HSC ,Number of pixels to skip" line.long 0x04 "CSI2_CSICR3,CSI Control Register 3" hexmask.long.word 0x04 16.--31. 1. " FRMCNT ,16-bit Frame Counter" bitfld.long 0x04 15. " FRMCNT_RST ,Frame Count Reset" "Not reset,Reset" bitfld.long 0x04 14. " DMA_REFLASH_RFF ,This bit reflash the embedded DMA controller for RxFIFO" "Not reflashing,Reflashed" bitfld.long 0x04 13. " DMA_REFLASH_SFF ,This bit reflash the embedded DMA controller for STATFIFO" "Not reflashing,Reflashed" textline " " bitfld.long 0x04 12. " DMA_REQ_EN_RFF ,DMA Request Enable for RxFIFO" "Disabled,Enabled" bitfld.long 0x04 11. " DMA_REQ_EN_SFF ,DMA Request Enable for STATFIFO" "Disabled,Enabled" bitfld.long 0x04 8.--10. " STATFF_LEVEL ,Number of data words in STATFIFO which generates an interrupt" "4,8,12,16,24,32,48,64" bitfld.long 0x04 7. " HRESP_ERR_EN ,Hresponse error interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 4.--6. " RxFF_LEVEL ,Number of data words after a RxFIFO full interrupt is generated" "4,8,16,24,32,48,64,96" bitfld.long 0x04 3. " TWO_8BIT_SENSOR ,Two 8-bit Sensor Mode" "Only one,Two 8-bit" bitfld.long 0x04 2. " ZERO_PACK_EN ,Dummy Zero Packing Enable" "Disabled,Enabled" bitfld.long 0x04 1. " ECC_INT_EN ,Error Detection Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ECC_AUTO_EN ,Automatic Error Correction Enable" "Disabled,Enabled" hgroup.long 0x0C++0x03 hide.long 0x00 "CSI2_CSISTATFIFO,CSI Statistic FIFO Register" in hgroup.long 0x10++0x03 hide.long 0x04 "CSI2_CSIRFIFO,CSI RX FIFO Register" in group.long 0x14++0x07 line.long 0x00 "CSI2_CSIRXCNT,CSI RX Count Register" hexmask.long.tbyte 0x00 0.--21. 1. " RXCNT ,22-bit counter for RXFIFO" line.long 0x04 "CSI2_CSISR,CSI Status Register" eventfld.long 0x04 28. " BASEADDR_CHHANGE_ERROR ,Switching occurred before DMA completed" "0,1" eventfld.long 0x04 27. " DMA_FIELD0_DONE ,DMA field 0 is complete" "Not completed,Completed" eventfld.long 0x04 26. " DMA_FIELD1_DONE ,DMA field 1 is complete" "Not completed,Completed" eventfld.long 0x04 25. " SF_OR_INT ,STATFIFO Overrun Interrupt Status" "No overflow,Overflow" textline " " eventfld.long 0x04 24. " RF_OR_INT ,RXFIFO Overrun Interrupt Status" "No overflow,Overflow" eventfld.long 0x04 22. " DMA_TSF_DONE_SFF ,DMA Transfer Done from StatFIFO" "Not completed,Completed" bitfld.long 0x04 21. " STATFF_INT ,STATFIFO Full Interrupt Status" "Not full,Full" eventfld.long 0x04 20. " DMA_TSF_DONE_FB2 ,DMA Transfer Done in Frame Buffer2" "Not completed,Completed" textline " " eventfld.long 0x04 19. " DMA_TSF_DONE_FB1 ,DMA Transfer Done in Frame Buffer1" "Not completed,Completed" bitfld.long 0x04 18. " RXFF_INT ,RXFIFO Full Interrupt Status" "Not full,Full" eventfld.long 0x04 17. " EOF_INT ,End of Frame (EOF) Interrupt Status" "Not detected,Detected" eventfld.long 0x04 16. " SOF_INT ,Start of Frame Interrupt Status" "Not detected,Detected" textline " " bitfld.long 0x04 15. " F2_INT ,CCIR Field 2 Interrupt Status" "Not detected,About to start" bitfld.long 0x04 14. " F1_INT ,CCIR Field 1 Interrupt Status" "Not detected,About to start" eventfld.long 0x04 13. " COF_INT ,Change Of Field Interrupt Status" "Not changed,Change detected" textline " " eventfld.long 0x04 7. " HRESP_ERR_INT ,Hresponse Error Interrupt Status" "No error,Error" eventfld.long 0x04 1. " ECC_INT ,CCIR Error Interrupt" "No error,Error" bitfld.long 0x04 0. " DRDY ,Presence of data that is ready for transfer in the RxFIFO" "Not ready,Ready" group.long 0x20++0x2F line.long 0x00 "CSI2_CSIDMASA_STATFIFO,CSI DMA Start Address Register - for STATFIFO" hexmask.long 0x00 2.--31. 0x4 " DMA_START_ADDR_SFF ,Indicates the start address to write data" line.long 0x04 "CSI2_CSIDMATS_STATFIFO,CSI DMA Transfer Size Register - for STATFIFO" line.long 0x08 "CSI2_CSIDMASA_FB1,CSI DMA Start Address Register - for Frame Buffer1" hexmask.long 0x08 2.--31. 0x4 " DMA_START_ADDR_FB1 ,DMA Start Address in Frame Buffer1" line.long 0x0C "CSI2_CSIDMASA_FB2,CSI DMA Transfer Size Register - for Frame Buffer2" hexmask.long 0x0C 2.--31. 0x4 " DMA_START_ADDR_FB2 ,DMA Start Address in Frame Buffer2" line.long 0x10 "CSI2_CSIFBUF_PARA,CSI Frame Buffer Parameter Register" hexmask.long.word 0x10 0.--15. 1. " FBUF_STRIDE ,Indicates the stride of the frame buffer" line.long 0x14 "CSI2_CSIIMAG_PARA,CSI Image Parameter Register" hexmask.long.word 0x14 16.--31. 1. " IMAGE_WIDTH ,Indicates how many pixels in a line of the image from the sensor" hexmask.long.word 0x14 0.--15. 1. " IMAGE_HEIGHT ,Indicates how many pixels in a column of the image from the sensor" group.long 0x48++0x07 line.long 0x00 "CSI2_CSICR18,CSI Control Register 18" bitfld.long 0x00 31. " CSI_ENABLE ,CSI global enable signal" "Disabled,Enabled" bitfld.long 0x00 18.--19. " MASK_OPTION ,Methods of masking the CSI input" "1st frame,CSI_ENABLE = 1,2nd frame,Data comes" bitfld.long 0x00 16.--17. " CSI_LCDIF_BUFFER_LINES ,Number of lines are used in handshake mode with LCDIF" "4,8,16,16" textline " " bitfld.long 0x00 12.--15. " AHB_HPROT ,Hprot value in AHB bus protocol" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. " RGB888A_FORMAT_SEL ,Output is 32-bit format" "8h0_data[23:0],data[23:0]_8h0" bitfld.long 0x00 9. " BASEADDR_CHANGE_ERROR_IE ,Base address change error interrupt enable signal" "0,1" textline " " bitfld.long 0x00 8. " LAST_DMA_REQ_SEL ,Choosing the last DMA request condition" "FIFO_full_level,Hburst_length" bitfld.long 0x00 7. " DMA_FIELD1_DONE_IE ,Field 1 done interrupt enable(in interlace mode)" "Disabled,Enabled" bitfld.long 0x00 6. " FIELD0_DONE_IE ,Field 0 means interrupt enabled (interlace)" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " BASEADDR_SWITCH_SEL ,CSI 2 base addresses switching method" "Vsync,First data" bitfld.long 0x00 4. " BASEADDR_SWITCH_EN ,Switching the base address according to BASEADDR_SWITCH_SEL or atomically by DMA completed" "Atomically,BASEADDR_SWITCH_SEL" bitfld.long 0x00 3. " PARALLEL24_EN ,Parallel input rgb888/yuv444 24bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DEINTERLACE_EN ,Output method When input is TVDECODER or standard CCIR656 video" "Deinterlace disabled,Deinterlace enabled" bitfld.long 0x00 1. " TVDECODER_IN_EN ,Input source" "Other,TV decoder" bitfld.long 0x00 0. " NTSC_EN ,Selection of NTSC/PAL mode (when input is TVDECODER or standard CCIR656)" "PAL,NTSC" line.long 0x04 "CSI2_CSICR19,CSI Control Register 19" hexmask.long.byte 0x04 0.--7. 1. " ,Highest FIFO level achieved by CSI FIFO timely" width 0x0b endif tree.end tree.end tree "DCIC (Display Content Integrity Checker)" tree "DCIC1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0220C000 width 8. group.long 0x00++0x0B line.long 0x00 "DCICC,DCIC Control Register" bitfld.long 0x00 7. " CLK_POL ,DISP_CLK signal polarity" "Not inverted,Inverted" bitfld.long 0x00 6. " VSYNC_POL ,VSYNC_IN signal polarity" "Active High,Active Low" bitfld.long 0x00 5. " HSYNC_POL ,HSYNC_IN signal polarity" "Active High,Active Low" bitfld.long 0x00 4. " DE_POL ,DATA_EN_IN signal polarity" "Active High,Active Low" textline " " bitfld.long 0x00 0. " IC_EN ,Integrity Check enable" "Disabled,Enabled" line.long 0x04 "DCICIC,DCIC Interrupt Control Register" bitfld.long 0x04 16. " EXT_SIG_EN ,External controller mismatch indication signal" "Disabled,Enabled" bitfld.long 0x04 3. " FREEZE_MASK ,Disable change of interrupt masks" "No,Yes" bitfld.long 0x04 1. " FI_MASK ,Functional Interrupt mask" "Not masked,Masked" bitfld.long 0x04 0. " EI_MASK ,Error Interrupt mask" "Not masked,Masked" line.long 0x08 "DCICS,DCIC Status Register" eventfld.long 0x08 17. " FI_STAT ,Functional Interrupt status" "No interrupt,Interrupt" rbitfld.long 0x08 16. " EI_STAT ,Error Interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x08 15. " ROI_MATCH_STAT[15] ,Mismatch at ROI 15 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 14. " [14] ,Mismatch at ROI 14 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 13. " [13] ,Mismatch at ROI 13 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 12. " [12] ,Mismatch at ROI 12 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 11. " [11] ,Mismatch at ROI 11 calculated CRC" "Not mismatched,Mismatched" textline " " eventfld.long 0x08 10. " [10] ,Mismatch at ROI 10 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 9. " [9] ,Mismatch at ROI 9 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 8. " [8] ,Mismatch at ROI 8 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 7. " [7] ,Mismatch at ROI 7 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 6. " [6] ,Mismatch at ROI 6 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 5. " [5] ,Mismatch at ROI 5 calculated CRC" "Not mismatched,Mismatched" textline " " eventfld.long 0x08 4. " [4] ,Mismatch at ROI 4 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 3. " [3] ,Mismatch at ROI 3 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 2. " [2] ,Mismatch at ROI 2 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 1. " [1] ,Mismatch at ROI 1 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 0. " [0] ,Mismatch at ROI 0 calculated CRC" "Not mismatched,Mismatched" width 9. group.long 0x10++0x0B "ROI Registers" line.long 0x00 "DCICRC,DCIC ROI Config Register" bitfld.long 0x00 31. " ROI_EN ,ROI tracking enable" "Disabled,Enabled" bitfld.long 0x00 30. " ROI_FREEZE ,ROI freeze enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " START_OFFSET_Y ,Row number of ROIs upper-left corner" hexmask.long.word 0x00 0.--12. 1. " START_OFFSET_X ,Column number of ROIs upper-left corner" line.long 0x04 "DCICRS,DCIC ROI Size Register" hexmask.long.word 0x04 16.--27. 1. " END_OFFSET_Y ,Row number of ROIs lower-right corner" hexmask.long.word 0x04 0.--12. 1. " END_OFFSET_X ,Column number of ROIs lower-right corner" line.long 0x08 "DCICRRS,DCIC ROI Reference Signature Register" rgroup.long 0x1C++0x03 line.long 0x00 "DCICRCS,DCIC ROI Calculated Signature" width 0xb else base ad:0x4220C000 width 8. group.long 0x00++0x0B line.long 0x00 "DCICC,DCIC Control Register" bitfld.long 0x00 7. " CLK_POL ,DISP_CLK signal polarity" "Not inverted,Inverted" bitfld.long 0x00 6. " VSYNC_POL ,VSYNC_IN signal polarity" "Active High,Active Low" bitfld.long 0x00 5. " HSYNC_POL ,HSYNC_IN signal polarity" "Active High,Active Low" bitfld.long 0x00 4. " DE_POL ,DATA_EN_IN signal polarity" "Active High,Active Low" textline " " bitfld.long 0x00 0. " IC_EN ,Integrity Check enable" "Disabled,Enabled" line.long 0x04 "DCICIC,DCIC Interrupt Control Register" bitfld.long 0x04 16. " EXT_SIG_EN ,External controller mismatch indication signal" "Disabled,Enabled" bitfld.long 0x04 3. " FREEZE_MASK ,Disable change of interrupt masks" "No,Yes" bitfld.long 0x04 1. " FI_MASK ,Functional Interrupt mask" "Not masked,Masked" bitfld.long 0x04 0. " EI_MASK ,Error Interrupt mask" "Not masked,Masked" line.long 0x08 "DCICS,DCIC Status Register" eventfld.long 0x08 17. " FI_STAT ,Functional Interrupt status" "No interrupt,Interrupt" rbitfld.long 0x08 16. " EI_STAT ,Error Interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x08 15. " ROI_MATCH_STAT[15] ,Mismatch at ROI 15 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 14. " [14] ,Mismatch at ROI 14 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 13. " [13] ,Mismatch at ROI 13 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 12. " [12] ,Mismatch at ROI 12 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 11. " [11] ,Mismatch at ROI 11 calculated CRC" "Not mismatched,Mismatched" textline " " eventfld.long 0x08 10. " [10] ,Mismatch at ROI 10 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 9. " [9] ,Mismatch at ROI 9 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 8. " [8] ,Mismatch at ROI 8 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 7. " [7] ,Mismatch at ROI 7 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 6. " [6] ,Mismatch at ROI 6 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 5. " [5] ,Mismatch at ROI 5 calculated CRC" "Not mismatched,Mismatched" textline " " eventfld.long 0x08 4. " [4] ,Mismatch at ROI 4 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 3. " [3] ,Mismatch at ROI 3 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 2. " [2] ,Mismatch at ROI 2 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 1. " [1] ,Mismatch at ROI 1 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 0. " [0] ,Mismatch at ROI 0 calculated CRC" "Not mismatched,Mismatched" width 9. group.long 0x10++0x0B "ROI Registers" line.long 0x00 "DCICRC,DCIC ROI Config Register" bitfld.long 0x00 31. " ROI_EN ,ROI tracking enable" "Disabled,Enabled" bitfld.long 0x00 30. " ROI_FREEZE ,ROI freeze enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " START_OFFSET_Y ,Row number of ROIs upper-left corner" hexmask.long.word 0x00 0.--12. 1. " START_OFFSET_X ,Column number of ROIs upper-left corner" line.long 0x04 "DCICRS,DCIC ROI Size Register" hexmask.long.word 0x04 16.--27. 1. " END_OFFSET_Y ,Row number of ROIs lower-right corner" hexmask.long.word 0x04 0.--12. 1. " END_OFFSET_X ,Column number of ROIs lower-right corner" line.long 0x08 "DCICRRS,DCIC ROI Reference Signature Register" rgroup.long 0x1C++0x03 line.long 0x00 "DCICRCS,DCIC ROI Calculated Signature" width 0xb endif tree.end tree "DCIC2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02210000 width 8. group.long 0x00++0x0B line.long 0x00 "DCICC,DCIC Control Register" bitfld.long 0x00 7. " CLK_POL ,DISP_CLK signal polarity" "Not inverted,Inverted" bitfld.long 0x00 6. " VSYNC_POL ,VSYNC_IN signal polarity" "Active High,Active Low" bitfld.long 0x00 5. " HSYNC_POL ,HSYNC_IN signal polarity" "Active High,Active Low" bitfld.long 0x00 4. " DE_POL ,DATA_EN_IN signal polarity" "Active High,Active Low" textline " " bitfld.long 0x00 0. " IC_EN ,Integrity Check enable" "Disabled,Enabled" line.long 0x04 "DCICIC,DCIC Interrupt Control Register" bitfld.long 0x04 16. " EXT_SIG_EN ,External controller mismatch indication signal" "Disabled,Enabled" bitfld.long 0x04 3. " FREEZE_MASK ,Disable change of interrupt masks" "No,Yes" bitfld.long 0x04 1. " FI_MASK ,Functional Interrupt mask" "Not masked,Masked" bitfld.long 0x04 0. " EI_MASK ,Error Interrupt mask" "Not masked,Masked" line.long 0x08 "DCICS,DCIC Status Register" eventfld.long 0x08 17. " FI_STAT ,Functional Interrupt status" "No interrupt,Interrupt" rbitfld.long 0x08 16. " EI_STAT ,Error Interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x08 15. " ROI_MATCH_STAT[15] ,Mismatch at ROI 15 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 14. " [14] ,Mismatch at ROI 14 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 13. " [13] ,Mismatch at ROI 13 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 12. " [12] ,Mismatch at ROI 12 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 11. " [11] ,Mismatch at ROI 11 calculated CRC" "Not mismatched,Mismatched" textline " " eventfld.long 0x08 10. " [10] ,Mismatch at ROI 10 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 9. " [9] ,Mismatch at ROI 9 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 8. " [8] ,Mismatch at ROI 8 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 7. " [7] ,Mismatch at ROI 7 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 6. " [6] ,Mismatch at ROI 6 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 5. " [5] ,Mismatch at ROI 5 calculated CRC" "Not mismatched,Mismatched" textline " " eventfld.long 0x08 4. " [4] ,Mismatch at ROI 4 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 3. " [3] ,Mismatch at ROI 3 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 2. " [2] ,Mismatch at ROI 2 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 1. " [1] ,Mismatch at ROI 1 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 0. " [0] ,Mismatch at ROI 0 calculated CRC" "Not mismatched,Mismatched" width 9. group.long 0x10++0x0B "ROI Registers" line.long 0x00 "DCICRC,DCIC ROI Config Register" bitfld.long 0x00 31. " ROI_EN ,ROI tracking enable" "Disabled,Enabled" bitfld.long 0x00 30. " ROI_FREEZE ,ROI freeze enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " START_OFFSET_Y ,Row number of ROIs upper-left corner" hexmask.long.word 0x00 0.--12. 1. " START_OFFSET_X ,Column number of ROIs upper-left corner" line.long 0x04 "DCICRS,DCIC ROI Size Register" hexmask.long.word 0x04 16.--27. 1. " END_OFFSET_Y ,Row number of ROIs lower-right corner" hexmask.long.word 0x04 0.--12. 1. " END_OFFSET_X ,Column number of ROIs lower-right corner" line.long 0x08 "DCICRRS,DCIC ROI Reference Signature Register" rgroup.long 0x1C++0x03 line.long 0x00 "DCICRCS,DCIC ROI Calculated Signature" width 0xb else base ad:0x42210000 width 8. group.long 0x00++0x0B line.long 0x00 "DCICC,DCIC Control Register" bitfld.long 0x00 7. " CLK_POL ,DISP_CLK signal polarity" "Not inverted,Inverted" bitfld.long 0x00 6. " VSYNC_POL ,VSYNC_IN signal polarity" "Active High,Active Low" bitfld.long 0x00 5. " HSYNC_POL ,HSYNC_IN signal polarity" "Active High,Active Low" bitfld.long 0x00 4. " DE_POL ,DATA_EN_IN signal polarity" "Active High,Active Low" textline " " bitfld.long 0x00 0. " IC_EN ,Integrity Check enable" "Disabled,Enabled" line.long 0x04 "DCICIC,DCIC Interrupt Control Register" bitfld.long 0x04 16. " EXT_SIG_EN ,External controller mismatch indication signal" "Disabled,Enabled" bitfld.long 0x04 3. " FREEZE_MASK ,Disable change of interrupt masks" "No,Yes" bitfld.long 0x04 1. " FI_MASK ,Functional Interrupt mask" "Not masked,Masked" bitfld.long 0x04 0. " EI_MASK ,Error Interrupt mask" "Not masked,Masked" line.long 0x08 "DCICS,DCIC Status Register" eventfld.long 0x08 17. " FI_STAT ,Functional Interrupt status" "No interrupt,Interrupt" rbitfld.long 0x08 16. " EI_STAT ,Error Interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x08 15. " ROI_MATCH_STAT[15] ,Mismatch at ROI 15 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 14. " [14] ,Mismatch at ROI 14 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 13. " [13] ,Mismatch at ROI 13 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 12. " [12] ,Mismatch at ROI 12 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 11. " [11] ,Mismatch at ROI 11 calculated CRC" "Not mismatched,Mismatched" textline " " eventfld.long 0x08 10. " [10] ,Mismatch at ROI 10 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 9. " [9] ,Mismatch at ROI 9 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 8. " [8] ,Mismatch at ROI 8 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 7. " [7] ,Mismatch at ROI 7 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 6. " [6] ,Mismatch at ROI 6 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 5. " [5] ,Mismatch at ROI 5 calculated CRC" "Not mismatched,Mismatched" textline " " eventfld.long 0x08 4. " [4] ,Mismatch at ROI 4 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 3. " [3] ,Mismatch at ROI 3 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 2. " [2] ,Mismatch at ROI 2 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 1. " [1] ,Mismatch at ROI 1 calculated CRC" "Not mismatched,Mismatched" eventfld.long 0x08 0. " [0] ,Mismatch at ROI 0 calculated CRC" "Not mismatched,Mismatched" width 9. group.long 0x10++0x0B "ROI Registers" line.long 0x00 "DCICRC,DCIC ROI Config Register" bitfld.long 0x00 31. " ROI_EN ,ROI tracking enable" "Disabled,Enabled" bitfld.long 0x00 30. " ROI_FREEZE ,ROI freeze enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " START_OFFSET_Y ,Row number of ROIs upper-left corner" hexmask.long.word 0x00 0.--12. 1. " START_OFFSET_X ,Column number of ROIs upper-left corner" line.long 0x04 "DCICRS,DCIC ROI Size Register" hexmask.long.word 0x04 16.--27. 1. " END_OFFSET_Y ,Row number of ROIs lower-right corner" hexmask.long.word 0x04 0.--12. 1. " END_OFFSET_X ,Column number of ROIs lower-right corner" line.long 0x08 "DCICRRS,DCIC ROI Reference Signature Register" rgroup.long 0x1C++0x03 line.long 0x00 "DCICRCS,DCIC ROI Calculated Signature" width 0xb endif tree.end tree.end tree "ECSPI (Enhanced Configurable SPI Registers)" sif (cpu()=="IMX6SOLOX-CA9") tree "ECSPI 1" base ad:0x02008000 width 18. if (((per.l(ad:0x02008008+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI1_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI1_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI1_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI1_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x02008008))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02008008))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI1_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI1_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI1_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI1_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI1_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI1_MSGDATA,Message Data Register" width 0xb tree.end tree "ECSPI 2" base ad:0x0200C000 width 18. if (((per.l(ad:0x0200C008+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI2_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI2_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI2_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI2_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x0200C008))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0200C008))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI2_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI2_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI2_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI2_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI2_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI2_MSGDATA,Message Data Register" width 0xb tree.end tree "ECSPI 3" base ad:0x02010000 width 18. if (((per.l(ad:0x02010008+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI3_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI3_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI3_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI3_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x02010008))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02010008))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI3_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI3_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI3_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI3_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI3_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI3_MSGDATA,Message Data Register" width 0xb tree.end tree "ECSPI 4" base ad:0x02014000 width 18. if (((per.l(ad:0x02014008+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI4_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI4_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI4_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI4_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x02014008))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x02014008))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI4_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI4_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI4_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI4_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI4_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI4_MSGDATA,Message Data Register" width 0xb tree.end tree "ECSPI 5" base ad:0x0228C000 width 18. if (((per.l(ad:0x0228C000+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI5_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI5_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI5_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI5_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x0228C000))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x0228C000))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI5_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI5_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI5_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI5_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI5_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI5_MSGDATA,Message Data Register" width 0xb tree.end else tree "ECSPI 1" base ad:0x42008000 width 18. if (((per.l(ad:0x42008008+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI1_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI1_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI1_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI1_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x42008008))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42008008))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI1_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI1_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI1_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI1_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI1_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI1_MSGDATA,Message Data Register" width 0xb tree.end tree "ECSPI 2" base ad:0x4200C000 width 18. if (((per.l(ad:0x4200C008+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI2_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI2_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI2_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI2_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x4200C008))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4200C008))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI2_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI2_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI2_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI2_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI2_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI2_MSGDATA,Message Data Register" width 0xb tree.end tree "ECSPI 3" base ad:0x42010000 width 18. if (((per.l(ad:0x42010008+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI3_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI3_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI3_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI3_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x42010008))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42010008))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI3_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI3_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI3_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI3_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI3_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI3_MSGDATA,Message Data Register" width 0xb tree.end tree "ECSPI 4" base ad:0x42014000 width 18. if (((per.l(ad:0x42014008+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI4_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI4_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI4_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI4_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x42014008))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x42014008))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI4_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI4_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI4_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI4_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI4_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI4_MSGDATA,Message Data Register" width 0xb tree.end tree "ECSPI 5" base ad:0x4228C000 width 18. if (((per.l(ad:0x4228C000+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI5_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI5_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI5_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI5_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" textline " " bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care,Falling edge,Low level," bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" textline " " bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" textline " " bitfld.long 0x00 3. " SMC ,Start Mode Control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI Block Enable Control" "Disabled,Enabled" textline " " if (((per.b(ad:0x4228C000))&(0xF0))==(0x00)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0x10)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0x20)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0x30)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0x40)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0x50)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0x60)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0x70)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "= BURST_LENGTH+1," bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0x80)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0x90)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0xA0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0xB0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "= BURST_LENGTH+1," bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0xC0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0xD0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "= BURST_LENGTH+1," bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0xE0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "= BURST_LENGTH+1," textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.b(ad:0x4228C000))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI5_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" textline " " bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the Chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the Chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the Chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the Chip Select signal for SPI channel 0" "Low,High" textline " " bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the Chip Select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the Chip Select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the Chip Select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the Chip Select signal for SPI channel 0" "Single burst,Multiple bursts" textline " " bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" textline " " bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif textline "" group.long 0x10++0x13 line.long 0x00 "ECSPI5_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI5_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI5_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer Completed Status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO Full bit" "Not Full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO Data Request" "Not greater,Greater" textline " " rbitfld.long 0x08 3. " RR ,RXFIFO Ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO Data Request" "Not greater,Greater" rbitfld.long 0x08 0. " RDR ,RXFIFO Data Request" "Not greater,Greater" line.long 0x0C "ECSPI5_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 0x01 " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI5_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop Back Control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 0x01 " RXCNT ,RXFIFO Counter" hexmask.long.byte 0x10 0.--6. " TXCNT ,TXFIFO Counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI5_MSGDATA,Message Data Register" width 0xb tree.end endif tree.end tree "EIM (External Interface Module)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021B8000 width 18. tree "Chip Select 0" if ((((per.l(ad:0x021B8000+0x0))&0x70000)>=0x10000)&&(((per.l(ad:0x021B8000+0x0))&0x70000)<=0x30000)) group.long 0x0++0x17 line.long 0x00 "EIM_CS0GCR1,Chip Select 0 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x0++0x17 line.long 0x00 "EIM_CS0GCR1,Chip Select 0 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x0+0x04)++0x13 line.long 0x00 "EIM_CS0GCR2,Chip Select 0 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS0RCR1,Chip Select 0 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS0RCR2,Chip Select 0 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS0WCR1,Chip Select 0 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS0WCR2,Chip Select 0 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 1" if ((((per.l(ad:0x021B8000+0x18))&0x70000)>=0x10000)&&(((per.l(ad:0x021B8000+0x18))&0x70000)<=0x30000)) group.long 0x18++0x17 line.long 0x00 "EIM_CS1GCR1,Chip Select 1 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x18++0x17 line.long 0x00 "EIM_CS1GCR1,Chip Select 1 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x18+0x04)++0x13 line.long 0x00 "EIM_CS1GCR2,Chip Select 1 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS1RCR1,Chip Select 1 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS1RCR2,Chip Select 1 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS1WCR1,Chip Select 1 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS1WCR2,Chip Select 1 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 2" if ((((per.l(ad:0x021B8000+0x30))&0x70000)>=0x10000)&&(((per.l(ad:0x021B8000+0x30))&0x70000)<=0x30000)) group.long 0x30++0x17 line.long 0x00 "EIM_CS2GCR1,Chip Select 2 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x30++0x17 line.long 0x00 "EIM_CS2GCR1,Chip Select 2 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x30+0x04)++0x13 line.long 0x00 "EIM_CS2GCR2,Chip Select 2 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS2RCR1,Chip Select 2 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS2RCR2,Chip Select 2 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS2WCR1,Chip Select 2 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS2WCR2,Chip Select 2 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 3" if ((((per.l(ad:0x021B8000+0x48))&0x70000)>=0x10000)&&(((per.l(ad:0x021B8000+0x48))&0x70000)<=0x30000)) group.long 0x48++0x17 line.long 0x00 "EIM_CS3GCR1,Chip Select 3 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x48++0x17 line.long 0x00 "EIM_CS3GCR1,Chip Select 3 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x48+0x04)++0x13 line.long 0x00 "EIM_CS3GCR2,Chip Select 3 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS3RCR1,Chip Select 3 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS3RCR2,Chip Select 3 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS3WCR1,Chip Select 3 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS3WCR2,Chip Select 3 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 4" if ((((per.l(ad:0x021B8000+0x60))&0x70000)>=0x10000)&&(((per.l(ad:0x021B8000+0x60))&0x70000)<=0x30000)) group.long 0x60++0x17 line.long 0x00 "EIM_CS4GCR1,Chip Select 4 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x60++0x17 line.long 0x00 "EIM_CS4GCR1,Chip Select 4 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x60+0x04)++0x13 line.long 0x00 "EIM_CS4GCR2,Chip Select 4 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS4RCR1,Chip Select 4 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS4RCR2,Chip Select 4 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS4WCR1,Chip Select 4 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS4WCR2,Chip Select 4 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 5" if ((((per.l(ad:0x021B8000+0x78))&0x70000)>=0x10000)&&(((per.l(ad:0x021B8000+0x78))&0x70000)<=0x30000)) group.long 0x78++0x17 line.long 0x00 "EIM_CS5GCR1,Chip Select 5 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x78++0x17 line.long 0x00 "EIM_CS5GCR1,Chip Select 5 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x78+0x04)++0x13 line.long 0x00 "EIM_CS5GCR2,Chip Select 5 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS5RCR1,Chip Select 5 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS5RCR2,Chip Select 5 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS5WCR1,Chip Select 5 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS5WCR2,Chip Select 5 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Other registers" group.long 0x90++0x13 line.long 0x00 "EIM_WCR,EIM Configuration Register" bitfld.long 0x00 11. " FRUN_ACLK_EN ,Free run ACLK enable" "0,1" bitfld.long 0x00 9.--10. " WDOG_LIMIT ,Memory Watch Dog cycle limit" "128,256,512,1024" bitfld.long 0x00 8. " WDOG_EN ,Memory WDog enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " INTPOL ,Interrupt Polarity" "Active low,Active high" bitfld.long 0x00 4. " INTEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " CONT_BCLK_SEL ,Continuous BCLK select" "When necessary,Continuous" textline " " bitfld.long 0x00 1.--2. " GBCD ,General Burst Clock Divisor" "/1,/2,/3,/4" bitfld.long 0x00 0. " BCM ,Burst Clock Mode" "SWR/SRD,ACLK active" line.long 0x04 "EIM_DCR,DLL Control Register" bitfld.long 0x04 28.--31. " DLL_CTRL_REF_UPDATE_INT ,Reference DLL Update Interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23.--27. " DLL_CTRL_SLV_UPDATE_INT ,Slave DLL Update Interval" "256,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x04 16.--22. 1. " DLL_CTRL_REF_INITIAL_VAL ,Initial value of reference chain before DLL enabled" textline " " hexmask.long.byte 0x04 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Initial value of reference chain before DLL enabled" bitfld.long 0x04 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain using SLV_OVERRIDE_VAL" "Disabled,Enabled" bitfld.long 0x04 7. " DLL_CTRL_GATE_UPDATE ,DLL updated" "Disabled,Automatically" textline " " bitfld.long 0x04 4.--6. " DLL_CTRL_SLV_OFFSET ,OFFSET Value" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " DLL_CTRL_SLV_OFFSET_DEC ,OFFSET Value" "REF_SEL+SLV_OFFSET,REF_SEL-SLV_OFFSET" textline " " bitfld.long 0x04 2. " DLL_CTRL_SLV_FORCE_UPD ,Forces the slave delay line to update to the DLL calibrated value immediately" "Not forced,Forced" bitfld.long 0x04 1. " DLL_CTRL_RESET ,DLL Reset Bit" "No reset,Reset" bitfld.long 0x04 0. " DLL_CTRL_ENABLE ,DLL and delay chain" "Bypassed,Enabled" line.long 0x08 "EIM_DSR,DLL Status Register" hexmask.long.byte 0x08 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x08 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" bitfld.long 0x08 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Not locked,Locked" textline " " bitfld.long 0x08 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" line.long 0x0C "EIM_WIAR,EIM IP Access Register" bitfld.long 0x0C 4. " ACLK_EN ,Gating the ACLK for the EIM except from FFs that get ipg_aclk_s" "Disabled,Enabled" bitfld.long 0x0C 3. " ERRST ,Initial ready/busy status for external devices on CS0 immediately after hardware reset" "Disabled,Enabled" bitfld.long 0x0C 2. " INT ,Interrupt assertion by an external device according to RDY_INT signal" "Not occurred,Asserted" textline " " bitfld.long 0x0C 1. " IPS_ACK ,The Master requests to access one of the IPS registers" "Not accessed,Accessed" bitfld.long 0x0C 0. " IPS_REQ ,The Master requests to access one of the IPS registers" "Not requested,Requested" line.long 0x10 "EIM_EAR,Error Address Register" tree.end width 0x0b else base ad:0x421B8000 width 18. tree "Chip Select 0" if ((((per.l(ad:0x421B8000+0x0))&0x70000)>=0x10000)&&(((per.l(ad:0x421B8000+0x0))&0x70000)<=0x30000)) group.long 0x0++0x17 line.long 0x00 "EIM_CS0GCR1,Chip Select 0 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x0++0x17 line.long 0x00 "EIM_CS0GCR1,Chip Select 0 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x0+0x04)++0x13 line.long 0x00 "EIM_CS0GCR2,Chip Select 0 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS0RCR1,Chip Select 0 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS0RCR2,Chip Select 0 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS0WCR1,Chip Select 0 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS0WCR2,Chip Select 0 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 1" if ((((per.l(ad:0x421B8000+0x18))&0x70000)>=0x10000)&&(((per.l(ad:0x421B8000+0x18))&0x70000)<=0x30000)) group.long 0x18++0x17 line.long 0x00 "EIM_CS1GCR1,Chip Select 1 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x18++0x17 line.long 0x00 "EIM_CS1GCR1,Chip Select 1 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x18+0x04)++0x13 line.long 0x00 "EIM_CS1GCR2,Chip Select 1 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS1RCR1,Chip Select 1 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS1RCR2,Chip Select 1 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS1WCR1,Chip Select 1 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS1WCR2,Chip Select 1 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 2" if ((((per.l(ad:0x421B8000+0x30))&0x70000)>=0x10000)&&(((per.l(ad:0x421B8000+0x30))&0x70000)<=0x30000)) group.long 0x30++0x17 line.long 0x00 "EIM_CS2GCR1,Chip Select 2 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x30++0x17 line.long 0x00 "EIM_CS2GCR1,Chip Select 2 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x30+0x04)++0x13 line.long 0x00 "EIM_CS2GCR2,Chip Select 2 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS2RCR1,Chip Select 2 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS2RCR2,Chip Select 2 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS2WCR1,Chip Select 2 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS2WCR2,Chip Select 2 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 3" if ((((per.l(ad:0x421B8000+0x48))&0x70000)>=0x10000)&&(((per.l(ad:0x421B8000+0x48))&0x70000)<=0x30000)) group.long 0x48++0x17 line.long 0x00 "EIM_CS3GCR1,Chip Select 3 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x48++0x17 line.long 0x00 "EIM_CS3GCR1,Chip Select 3 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x48+0x04)++0x13 line.long 0x00 "EIM_CS3GCR2,Chip Select 3 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS3RCR1,Chip Select 3 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS3RCR2,Chip Select 3 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS3WCR1,Chip Select 3 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS3WCR2,Chip Select 3 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 4" if ((((per.l(ad:0x421B8000+0x60))&0x70000)>=0x10000)&&(((per.l(ad:0x421B8000+0x60))&0x70000)<=0x30000)) group.long 0x60++0x17 line.long 0x00 "EIM_CS4GCR1,Chip Select 4 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x60++0x17 line.long 0x00 "EIM_CS4GCR1,Chip Select 4 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x60+0x04)++0x13 line.long 0x00 "EIM_CS4GCR2,Chip Select 4 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS4RCR1,Chip Select 4 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS4RCR2,Chip Select 4 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS4WCR1,Chip Select 4 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS4WCR2,Chip Select 4 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Chip Select 5" if ((((per.l(ad:0x421B8000+0x78))&0x70000)>=0x10000)&&(((per.l(ad:0x421B8000+0x78))&0x70000)<=0x30000)) group.long 0x78++0x17 line.long 0x00 "EIM_CS5GCR1,Chip Select 5 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous" bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous" bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" else group.long 0x78++0x17 line.long 0x00 "EIM_CS5GCR1,Chip Select 5 General Configuration Register 1" bitfld.long 0x00 28.--31. " PSZ ,Memory page size in words" "8,16,32,64,128,256,512,1024,2048,,,,,,," bitfld.long 0x00 27. " WP ,Prevention of write accesses to the address range defined by the corresponding chip select" "Allowed,Not allowed" bitfld.long 0x00 24.--26. " GBC ,Minimum time between end of access to the current chip select and start of access to different chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " AUS ,Unshifted mode for address assertion for the relevant chip select accesses" "Shifted,Unshifted" textline " " bitfld.long 0x00 20.--22. " CSREC ,Minimum pulse width of CS, OE, and WE control signals before executing a new back to back access to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " SP ,Prevention of write accesses to the address range defined by the corresponding chip select when attempted in the User mode" "Allowed,Not allowed" bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",15:0,31:16,31:0,7:0,15:8,23:16,31:24" bitfld.long 0x00 14.--15. " BCS ,EIM clock cycles delay from start of access before the first rising edge of BCLK is generated" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " BCD ,Value used to program the burst clock divisor for BCLK generation" "1,2,3,4" bitfld.long 0x00 11. " WC ,Write access to the memory are always continuous accesses regardless of the BL field value" "According to BL,Continuous" bitfld.long 0x00 8.--10. " BL ,Memory burst length in words" "4,8,16,32,Continuous,,," bitfld.long 0x00 7. " CREP ,Configuration Register Enable Polarity" "Active low,Active high" textline " " bitfld.long 0x00 6. " CRE ,CRE memory pin state while executing a memory register set command to PSRAM external device" "Disabled,Enabled" bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Monitored WAIT,Internally" bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous," bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous," bitfld.long 0x00 0. " CSEN ,Operation of the chip select pin" "Disabled,Enabled" endif group.long (0x78+0x04)++0x13 line.long 0x00 "EIM_CS5GCR2,Chip Select 5 General Configuration Register 2" bitfld.long 0x00 12. " MUX16_BYP_GRANT ,EIM to bypass the grant/ack. arbitration with NFC" "Waits for grant,Ignores the grant" bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low" bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " DAPS ,Starting point of DTACK input signal polling" "3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18" textline " " bitfld.long 0x00 0.--1. " ADH ,Address hold time after ADV negation when in muxd mode" "0 cycle,1 cycle,2 cycle," textline "" line.long 0x04 "EIM_CS5RCR1,Chip Select 5 Read Configuration Register 1" bitfld.long 0x04 24.--29. " RWSC ,Number of wait-states for synchronous or asynchronous read access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 20.--22. " RADVA ,ADV signal for synchronous or asynchronous read modes" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. " RAL ,ADV signal negation time" "Ignored,RADVN" bitfld.long 0x04 16.--18. " RADVN ,When ADV signal to memory is negated during read accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 12.--14. " OEA ,OE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " OEN ,OE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RCSA ,This bit field determines when CS signal is asserted during read cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " RCSN ,This bit field determines when CS signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x08 "EIM_CS5RCR2,Chip Select 5 Read Configuration Register 2" bitfld.long 0x08 15. " APR ,Asynchronous read mode to the external device" "Single word,Page read" bitfld.long 0x08 12.--14. " PAT ,Page Access Time" "2 EIM,3 EIM,4 EIM,5 EIM,6 EIM,7 EIM,8 EIM,9 EIM" bitfld.long 0x08 8.--9. " RL ,Read Latency" "1/1.5,2/2.5,3/3.5,4/4.5" bitfld.long 0x08 4.--6. " RBEA ,This bit field determines when BE signal is asserted during read cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3. " RBE ,Read BE enable" "Disabled,Enabled" bitfld.long 0x08 0.--2. " RBEN ,This bit field determines when BE signal is negated during read cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x0C "EIM_CS5WCR1,Chip Select 5 Write Configuration Register 1" bitfld.long 0x0C 31. " WAL ,Write ADV Low" "No,Yes" bitfld.long 0x0C 30. " WBED ,Write Byte Enable Disable" "No,Yes" textline " " bitfld.long 0x0C 24.--29. " WWSC ,Number of wait-states for synchronous or asynchronous write access to the external device connected to the chip select" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 21.--23. " WADVA ,ADV signal for synchronous or asynchronous write modes" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 18.--20. " WADVN ,When ADV signal to memory is negated during write accesses" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 15.--17. " WBEA ,BE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. " WBEN ,BE Negation" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " WEA ,WE Assertion" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 6.--8. " WEN ,WE Negation" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 3.--5. " WCSA ,This bit field determines when CS signal is asserted during write cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " WCSN ,This bit field determines when CS signal is negated during write cycles in asynchronous single mode only" "0,1,2,3,4,5,6,7" line.long 0x10 "EIM_CS5WCR2,Chip Select 5 Write Configuration Register 2" bitfld.long 0x10 0. " WBCDD ,Write Burst Clock Divisor Decrement" "0,1" tree.end tree "Other registers" group.long 0x90++0x13 line.long 0x00 "EIM_WCR,EIM Configuration Register" bitfld.long 0x00 11. " FRUN_ACLK_EN ,Free run ACLK enable" "0,1" bitfld.long 0x00 9.--10. " WDOG_LIMIT ,Memory Watch Dog cycle limit" "128,256,512,1024" bitfld.long 0x00 8. " WDOG_EN ,Memory WDog enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " INTPOL ,Interrupt Polarity" "Active low,Active high" bitfld.long 0x00 4. " INTEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " CONT_BCLK_SEL ,Continuous BCLK select" "When necessary,Continuous" textline " " bitfld.long 0x00 1.--2. " GBCD ,General Burst Clock Divisor" "/1,/2,/3,/4" bitfld.long 0x00 0. " BCM ,Burst Clock Mode" "SWR/SRD,ACLK active" line.long 0x04 "EIM_DCR,DLL Control Register" bitfld.long 0x04 28.--31. " DLL_CTRL_REF_UPDATE_INT ,Reference DLL Update Interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23.--27. " DLL_CTRL_SLV_UPDATE_INT ,Slave DLL Update Interval" "256,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x04 16.--22. 1. " DLL_CTRL_REF_INITIAL_VAL ,Initial value of reference chain before DLL enabled" textline " " hexmask.long.byte 0x04 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Initial value of reference chain before DLL enabled" bitfld.long 0x04 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain using SLV_OVERRIDE_VAL" "Disabled,Enabled" bitfld.long 0x04 7. " DLL_CTRL_GATE_UPDATE ,DLL updated" "Disabled,Automatically" textline " " bitfld.long 0x04 4.--6. " DLL_CTRL_SLV_OFFSET ,OFFSET Value" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " DLL_CTRL_SLV_OFFSET_DEC ,OFFSET Value" "REF_SEL+SLV_OFFSET,REF_SEL-SLV_OFFSET" textline " " bitfld.long 0x04 2. " DLL_CTRL_SLV_FORCE_UPD ,Forces the slave delay line to update to the DLL calibrated value immediately" "Not forced,Forced" bitfld.long 0x04 1. " DLL_CTRL_RESET ,DLL Reset Bit" "No reset,Reset" bitfld.long 0x04 0. " DLL_CTRL_ENABLE ,DLL and delay chain" "Bypassed,Enabled" line.long 0x08 "EIM_DSR,DLL Status Register" hexmask.long.byte 0x08 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x08 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" bitfld.long 0x08 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Not locked,Locked" textline " " bitfld.long 0x08 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" line.long 0x0C "EIM_WIAR,EIM IP Access Register" bitfld.long 0x0C 4. " ACLK_EN ,Gating the ACLK for the EIM except from FFs that get ipg_aclk_s" "Disabled,Enabled" bitfld.long 0x0C 3. " ERRST ,Initial ready/busy status for external devices on CS0 immediately after hardware reset" "Disabled,Enabled" bitfld.long 0x0C 2. " INT ,Interrupt assertion by an external device according to RDY_INT signal" "Not occurred,Asserted" textline " " bitfld.long 0x0C 1. " IPS_ACK ,The Master requests to access one of the IPS registers" "Not accessed,Accessed" bitfld.long 0x0C 0. " IPS_REQ ,The Master requests to access one of the IPS registers" "Not requested,Requested" line.long 0x10 "EIM_EAR,Error Address Register" tree.end width 0x0b endif tree.end tree "ENET (10/100/1000-Mbps Ethernet MAC)" tree "ENET1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02188000 width 25. group.long 0x4++0x07 line.long 0x00 "ENET1_EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling Receive Error" "Not occurred,Occurred" eventfld.long 0x00 29. " BABT ,Babbling Transmit Error" "Not occurred,Occurred" eventfld.long 0x00 28. " GRA ,Graceful Stop Complete" "No interrupt,Interrupt" eventfld.long 0x00 27. " TXF ,Transmit Frame Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 26. " TXB ,Transmit Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive Frame Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " RXB ,Receive Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " EBERR ,Ethernet Bus Error" "Not occurred,Occurred" eventfld.long 0x00 21. " LC ,Late Collision" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision Retry Limit" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "Not occurred,Occurred" textline " " eventfld.long 0x00 18. " PLR ,Payload receive error" "Not occurred,Occurred" eventfld.long 0x00 17. " WAKEUP ,Node wake-up request indication" "Not detected,Detected" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Unavailable,Available" eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer" "No interrupt,Interrupt" textline " " eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" textline " " eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt - class 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt - class 1" "No interrupt,Interrupt" line.long 0x04 "ENET1_EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,BABR interrupt mask" "Masked,Not masked" bitfld.long 0x04 29. " BABT ,BABT interrupt mask" "Masked,Not masked" bitfld.long 0x04 28. " GRA ,GRA interrupt mask" "Masked,Not masked" bitfld.long 0x04 27. " TXF ,TXF interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 26. " TXB ,TXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 25. " RXF ,RXF interrupt mask" "Masked,Not masked" bitfld.long 0x04 24. " RXB ,RXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 23. " MII ,MII interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 22. " EBERR ,EBERR interrupt mask" "Masked,Not masked" bitfld.long 0x04 21. " LC ,LC interrupt mask" "Masked,Not masked" bitfld.long 0x04 20. " RL ,RL interrupt mask" "Masked,Not masked" bitfld.long 0x04 19. " UN ,UN interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 18. " PLR ,PLR interrupt mask" "Masked,Not masked" bitfld.long 0x04 17. " WAKEUP ,WAKEUP interrupt mask" "Masked,Not masked" bitfld.long 0x04 16. " TS_AVAIL ,TS_AVAIL interrupt mask" "Masked,Not masked" bitfld.long 0x04 15. " TS_TIMER ,TS_TIMER interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 14. " RXFLUSH_2 ,RX DMA Ring 2 flush indication" "Masked,Not masked" bitfld.long 0x04 13. " RXFLUSH_1 ,RX DMA Ring 2 flush indication" "Masked,Not masked" bitfld.long 0x04 12. " RXFLUSH_0 ,RX DMA Ring 2 flush indication" "Masked,Not masked" textline " " bitfld.long 0x04 7. " TXF2 ,Transmit frame interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 6. " TXB2 ,Transmit buffer interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 5. " RXF2 ,Receive frame interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 4. " RXB2 ,Receive buffer interrupt - class 2" "Masked,Not masked" textline " " bitfld.long 0x04 3. " TXF1 ,Transmit frame interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 2. " TXB1 ,Transmit buffer interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 1. " RXF1 ,Receive frame interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 0. " RXB1 ,Receive buffer interrupt - class 1" "Masked,Not masked" group.long 0x10++0x07 line.long 0x00 "ENET1_RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "ENET1_TDAR,Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" textline "" if (((per.l(ad:0x02188000+0x24))&0x200)==0x200) group.long 0x24++0x03 line.long 0x00 "ENET1_ECR,Ethernet Control Register" bitfld.long 0x00 11. " SVLANDBL ,S-VLAN double tag" "Disabled,Enabled" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "First,Second" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Not swapped,Swapped" textline " " bitfld.long 0x00 6. " DBGEN ,Debug enable" "Continues operation,Freeze mode" bitfld.long 0x00 5. " SPEED ,Selects between 10/100 and 1000 Mbps modes of operation" "10/100,1000" bitfld.long 0x00 4. " EN1588 ,Enables enhanced functionality of the MAC" "Legacy FEC buffer,Frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Normal operating,Sleep" textline " " bitfld.long 0x00 2. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "No effect,Reset" else group.long 0x24++0x03 line.long 0x00 "ENET1_ECR,Ethernet Control Register" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "First,Second" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Not swapped,Swapped" textline " " bitfld.long 0x00 6. " DBGEN ,Debug enable" "Continues operation,Freeze mode" bitfld.long 0x00 5. " SPEED ,Selects between 10/100 and 1000 Mbps modes of operation" "10/100,1000" bitfld.long 0x00 4. " EN1588 ,Enables enhanced functionality of the MAC" "Legacy FEC buffer,Frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Normal operating,Sleep" textline " " bitfld.long 0x00 2. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "No effect,Reset" endif group.long 0x40++0x07 line.long 0x00 "ENET1_MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "0,1,2,3" bitfld.long 0x00 28.--29. " OP ,Determines the frame operation [Clause 45/Clause 22]" "Write/-,Write,Read,Read/-" bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--17. " TA ,Turn around" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "ENET1_MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,Controls the frequency of the MII management interface clock" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x03 line.long 0x00 "ENET1_MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB idle" "No,Yes" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Clear" group.long 0x84++0x03 line.long 0x00 "ENET1_RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Payload length check disable" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CRCFWD ,Terminate/forward received CRC" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,Enables 10-Mbps mode of the RMII or RGMII" "100 Mbps,10 Mbps" textline " " bitfld.long 0x00 8. " RMII_MODE ,RMII mode enable" "MII mode,RMII operation" bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Non-RGMII,RGMII" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII or RMII mode" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "ENET1_TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Controlled,No CRC" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not modified,Overwritten" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,,,,,,," rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Received" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted" bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "No effect,Stopped" textline "" group.long 0xE4++0x23 line.long 0x00 "ENET1_PALR,Physical Address Lower Register" line.long 0x04 "ENET1_PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 1. " PADDR2 ,Pause address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "ENET1_OPD,Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" line.long 0x0C "ENET1_TXIC0,Transmit Interrupt Coalescing Register" bitfld.long 0x0C 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x0C 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x0C 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x0C 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x10 "ENET1_TXIC1,Transmit Interrupt Coalescing Register" bitfld.long 0x10 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x10 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x10 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x10 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x14 "ENET1_TXIC2,Transmit Interrupt Coalescing Register" bitfld.long 0x14 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x14 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x14 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x14 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x18 "ENET1_RXIC0,Receive Interrupt Coalescing Register" bitfld.long 0x18 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x18 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x18 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x18 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x1C "ENET1_RXIC1,Receive Interrupt Coalescing Register" bitfld.long 0x1C 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x1C 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x1C 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x1C 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x20 "ENET1_RXIC2,Receive Interrupt Coalescing Register" bitfld.long 0x20 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x20 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x20 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x20 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x118++0x0F line.long 0x00 "ENET1_IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "ENET1_IALR,Descriptor Individual Lower Address Register" line.long 0x08 "ENET1_GAUR,Descriptor Group Upper Address Register" line.long 0x0C "ENET1_GALR,Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "ENET1_TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Indicates the number of bytes written to the transmit FIFO" "64,64,128,192,256,320,384,448,512,576,640,704,768,832,896,960,1024,1088,1152,1216,1280,1344,1408,1472,1536,1600,1664,1728,1792,1856,1920,1984,2048,2112,2176,2240,2304,2368,2432,2496,2560,2624,2688,2752,2816,2880,2944,3008,3072,3136,3200,3264,3328,3392,3456,3520,3584,3648,3712,3776,3840,3904,3968,4032" group.long 0x160++0x17 line.long 0x00 "ENET1_RDSR1,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "ENET1_TDSR1,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "ENET1_MRBR1,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" line.long 0x0C "ENET1_RDSR2,Receive Descriptor Ring Start Register" hexmask.long 0x0C 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x10 "ENET1_TDSR2,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x10 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x14 "ENET1_MRBR2,Maximum Receive Buffer Size Register" hexmask.long.byte 0x14 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x180++0x0B line.long 0x00 "ENET1_RDSR,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "ENET1_TDSR,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "ENET1_MRBR,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "ENET1_RSFL,Receive FIFO Section Full Threshold" hexmask.long.word 0x00 0.--9. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "ENET1_RSEM,Receive FIFO Section Empty Threshold" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX Status FIFO Section Empty Threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--9. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "ENET1_RAEM,Receive FIFO Almost Empty Threshold" hexmask.long.word 0x08 0.--9. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "ENET1_RAFL,Receive FIFO Almost Full Threshold" hexmask.long.word 0x0C 0.--9. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "ENET1_TSEM,Transmit FIFO Section Empty Threshold" hexmask.long.word 0x10 0.--9. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "ENET1_TAEM,Transmit FIFO Almost Empty Threshold" hexmask.long.word 0x14 0.--9. 1. " TX_ALMOST_EMPTY ,Value of transmit FIFO almost empty threshold" line.long 0x18 "ENET1_TAFL,Transmit FIFO Almost Full Threshold" hexmask.long.word 0x18 0.--9. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "ENET1_TIPG,Transmit Inter-Packet Gap" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "ENET1_FTRL,Frame Truncation Length" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" textline "" group.long 0x1C0++0x0F line.long 0x00 "ENET1_TACC,Transmit Accelerator Function Configuration" bitfld.long 0x00 4. " PROCHK ,Enables insertion of protocol checksum" "Disabled,Enabled" bitfld.long 0x00 3. " IPCHK ,Enables insertion of IP header checksum" "Disabled,Enabled" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16" "Disabled,Enabled" line.long 0x04 "ENET1_RACC,Receive Accelerator Function Configuration" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" bitfld.long 0x04 1. " IPDIS ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PADREM ,Enable padding removal for short IP frames" "Disabled,Enabled" line.long 0x08 "ENET1_RCMR1,Receive Classification Match Register for Class 1" bitfld.long 0x08 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x08 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" line.long 0x0C "ENET1_RCMR2,Receive Classification Match Register for Class 2" bitfld.long 0x0C 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x0C 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1D8++0x1B line.long 0x00 "ENET1_DMA1CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Consideration of 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations" "Considered,Omitted" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,16-bit value to define the per class idle slope setting used by the credit based shaper defining allocated bandwidth for the class" line.long 0x04 "ENET1_DMA2CFG,DMA Class Based Configuration" bitfld.long 0x04 17. " CALC_NOIPG ,Consideration of 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations" "Considered,Omitted" bitfld.long 0x04 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " IDLE_SLOPE ,16-bit value to define the per class idle slope setting used by the credit based shaper defining allocated bandwidth for the class" line.long 0x08 "ENET1_RDAR1,Receive Descriptor Active Register - Ring 1" bitfld.long 0x08 24. " RDAR ,Receive Descriptor Active" "Inactive,Active" line.long 0x0C "ENET1_TDAR1,Transmit Descriptor Active Register - Ring 1" bitfld.long 0x0C 24. " TDAR ,Transmit Descriptor Active" "Inactive,Active" line.long 0x10 "ENET1_RDAR2,Receive Descriptor Active Register - Ring 2" bitfld.long 0x10 24. " RDAR ,Receive Descriptor Active" "Inactive,Active" line.long 0x14 "ENET1_TDAR2,Transmit Descriptor Active Register - Ring 2" bitfld.long 0x14 24. " TDAR ,Transmit Descriptor Active" "Inactive,Active" line.long 0x18 "ENET1_QOS,QOS Scheme" bitfld.long 0x18 5. " RX_FLUSH2 ,RX Flush Ring 2" "Disabled,Enabled" bitfld.long 0x18 4. " RX_FLUSH1 ,RX Flush Ring 1" "Disabled,Enabled" bitfld.long 0x18 3. " RX_FLUSH0 ,RX Flush Ring 0" "Disabled,Enabled" bitfld.long 0x18 0.--2. " TX_SCHEME ,Configuration information for DMA to select transmitter queue selection/arbitration scheme" "Credit-based,Round-robin,..." textline "" rgroup.long 0x0204++0x43 line.long 0x00 "ENET1_RMON_T_PACKETS,Tx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Packet count" line.long 0x04 "ENET1_RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "ENET1_RMON_T_MC_PKT,Tx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "ENET1_RMON_T_CRC_ALIGN,Tx Packets with CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with CRC/Align Error" line.long 0x10 "ENET1_RMON_T_UNDERSIZE,Tx Packets Less Than Bytes and Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Number of transmit packets less than 64 bytes with good CRC" line.long 0x14 "ENET1_RMON_T_OVERSIZE,Tx Packets GT MAX_FL bytes and Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes with good CRC" line.long 0x18 "ENET1_RMON_T_FRAG,Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Number of packets less than 64 bytes with bad CRC" line.long 0x1C "ENET1_RMON_T_JAB,Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes and bad CRC" line.long 0x20 "ENET1_RMON_T_COL,Tx Collision Count Statistic Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Number of transmit collisions" line.long 0x24 "ENET1_RMON_T_P64,Tx 64-Byte Packets Statistic Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Number of 64-byte transmit packets" line.long 0x28 "ENET1_RMON_T_P65TO127,Tx 65- to 127-byte Packets Statistic Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Number of 65- to 127-byte transmit packets" line.long 0x2C "ENET1_RMON_T_P128TO255,Tx 128- to 255-byte Packets Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Number of 128- to 255-byte transmit packets" line.long 0x30 "ENET1_RMON_T_P256TO511,Tx 256- to 511-byte Packets Statistic Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Number of 256- to 511-byte transmit packets" line.long 0x34 "ENET1_RMON_T_P512TO1023,Tx 512- to 1023-byte Packets Statistic Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Number of 512- to 1023-byte transmit packets" line.long 0x38 "ENET1_RMON_T_P1024TO2047,Tx 1024- to 2047-byte Packets Statistic Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Number of 1024- to 2047-byte transmit packets" line.long 0x3C "ENET1_RMON_T_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than 2048 bytes" line.long 0x40 "ENET1_RMON_T_OCTETS,Tx Octets Statistic Register" rgroup.long 0x24C++0x2B line.long 0x00 "ENET1_IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of frames transmitted OK" line.long 0x04 "ENET1_IEEE_T_1COL,Frames Transmitted with Single Collision Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of frames transmitted with one collision" line.long 0x08 "ENET1_IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of frames transmitted with multiple collisions" line.long 0x0C "ENET1_IEEE_T_DEF,Frames Transmitted after Deferral Delay Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of frames transmitted with deferral delay" line.long 0x10 "ENET1_IEEE_T_LCOL,Frames Transmitted with Late Collision Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of frames transmitted with late collision" line.long 0x14 "ENET1_IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of frames transmitted with excessive collisions" line.long 0x18 "ENET1_IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of frames transmitted with transmit FIFO underrun" line.long 0x1C "ENET1_IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of frames transmitted with carrier sense error" line.long 0x20 "ENET1_IEEE_T_SQE,Frames transmitted with SQE error" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Number of frames transmitted with SQE error" line.long 0x24 "ENET1_IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of flow-control pause frames transmitted" line.long 0x28 "ENET1_IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted w/o Error Statistic Register" rgroup.long 0x284++0x1F line.long 0x00 "ENET1_RMON_R_PACKETS,Rx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of packets received" line.long 0x04 "ENET1_RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of receive broadcast packets" line.long 0x08 "ENET1_RMON_R_MC_PKT,Rx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of receive multicast packets" line.long 0x0C "ENET1_RMON_R_CRC_ALIGN,Rx Packets with CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of receive packets with CRC or align error" line.long 0x10 "ENET1_RMON_R_UNDERSIZE,Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and good CRC" line.long 0x14 "ENET1_RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL and Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and good CRC" line.long 0x18 "ENET1_RMON_R_FRAG,Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and bad CRC" line.long 0x1C "ENET1_RMON_R_JAB,Rx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and bad CRC" rgroup.long 0x2A8++0x3B line.long 0x00 "ENET1_RMON_R_P64,Rx 64-Byte Packets Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of 64-byte receive packets" line.long 0x04 "ENET1_RMON_R_P65TO127,Rx 65- to 127-Byte Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of 65- to 127-byte recieve packets" line.long 0x08 "ENET1_RMON_R_P128TO255,Rx 128- to 255-Byte Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of 128- to 255-byte recieve packets" line.long 0x0C "ENET1_RMON_R_P256TO511,Rx 256- to 511-Byte Packets Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of 256- to 511-byte recieve packets" line.long 0x10 "ENET1_RMON_R_P512TO1023,Rx 512- to 1023-Byte Packets Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of 512- to 1023-byte recieve packets" line.long 0x14 "ENET1_RMON_R_P1024TO2047,Rx 1024- to 2047-Byte Packets Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of 1024- to 2047-byte recieve packets" line.long 0x18 "ENET1_RMON_R_P_GTE2048,Tx 1024- to 2047-byte Packets Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of greater-than-2048-byte recieve packets" line.long 0x1C "ENET1_RMON_R_OCTETS,Rx Octets Statistic Register" line.long 0x20 "ENET1_IEEE_R_DROP,Frames not Counted Correctly Statistic Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "ENET1_IEEE_R_FRAME_OK,Frames Received OK Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of frames received OK" line.long 0x28 "ENET1_IEEE_R_CRC,Frames Received with CRC Error Statistic Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Number of frames received with CRC error" line.long 0x2C "ENET1_IEEE_R_ALIGN,Frames Received with Alignment Error Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Number of frames received with alignment error" line.long 0x30 "ENET1_IEEE_R_MACERR,FIFO Overflow Count Statistic Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Receive FIFO overflow count" line.long 0x34 "ENET1_IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Number of flow-control pause frames received" line.long 0x38 "ENET1_IEEE_R_OCTETS_OK,Octet Count for Frames Received without Error Statistic" group.long 0x400++0x03 line.long 0x00 "ENET1_ATCR,Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "No effect,Captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No effect,Reset" bitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "Disabled,Enabled" bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" group.long 0x404++0x13 line.long 0x00 "ENET1_ATVR,Timer Value Register" line.long 0x04 "ENET1_ATOFF,Timer Offset Register" line.long 0x08 "ENET1_ATPER,Timer Period Register" line.long 0x0C "ENET1_ATCOR,Timer Correction Register" hexmask.long 0x0C 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x10 "ENET1_ATINC,Time-Stamping Clock Period Register" hexmask.long.byte 0x10 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x10 0.--6. 1. " INC ,Clock period of the timestamping clock in nanoseconds" rgroup.long 0x418++0x03 line.long 0x00 "ENET1_ATSTMP,Timestamp of Last Transmitted Frame" group.long 0x604++0x03 line.long 0x00 "ENET1_TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of Timer Flag for channel 3" "Clear,Set" eventfld.long 0x00 2. " TF2 ,Copy of Timer Flag for channel 2" "Clear,Set" eventfld.long 0x00 1. " TF1 ,Copy of Timer Flag for channel 1" "Clear,Set" eventfld.long 0x00 0. " TF0 ,Copy of Timer Flag for channel 0" "Clear,Set" group.long 0x608++0x07 line.long 0x00 "ENET1_TCSR0,Timer Control Status Register 0" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR0,Timer Compare Capture Register 0" group.long 0x610++0x07 line.long 0x00 "ENET1_TCSR1,Timer Control Status Register 1" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR1,Timer Compare Capture Register 1" group.long 0x618++0x07 line.long 0x00 "ENET1_TCSR2,Timer Control Status Register 2" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR2,Timer Compare Capture Register 2" group.long 0x620++0x07 line.long 0x00 "ENET1_TCSR3,Timer Control Status Register 3" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR3,Timer Compare Capture Register 3" width 0xB else base ad:0x42188000 width 25. group.long 0x4++0x07 line.long 0x00 "ENET1_EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling Receive Error" "Not occurred,Occurred" eventfld.long 0x00 29. " BABT ,Babbling Transmit Error" "Not occurred,Occurred" eventfld.long 0x00 28. " GRA ,Graceful Stop Complete" "No interrupt,Interrupt" eventfld.long 0x00 27. " TXF ,Transmit Frame Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 26. " TXB ,Transmit Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive Frame Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " RXB ,Receive Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " EBERR ,Ethernet Bus Error" "Not occurred,Occurred" eventfld.long 0x00 21. " LC ,Late Collision" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision Retry Limit" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "Not occurred,Occurred" textline " " eventfld.long 0x00 18. " PLR ,Payload receive error" "Not occurred,Occurred" eventfld.long 0x00 17. " WAKEUP ,Node wake-up request indication" "Not detected,Detected" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Unavailable,Available" eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer" "No interrupt,Interrupt" textline " " eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" textline " " eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt - class 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt - class 1" "No interrupt,Interrupt" line.long 0x04 "ENET1_EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,BABR interrupt mask" "Masked,Not masked" bitfld.long 0x04 29. " BABT ,BABT interrupt mask" "Masked,Not masked" bitfld.long 0x04 28. " GRA ,GRA interrupt mask" "Masked,Not masked" bitfld.long 0x04 27. " TXF ,TXF interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 26. " TXB ,TXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 25. " RXF ,RXF interrupt mask" "Masked,Not masked" bitfld.long 0x04 24. " RXB ,RXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 23. " MII ,MII interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 22. " EBERR ,EBERR interrupt mask" "Masked,Not masked" bitfld.long 0x04 21. " LC ,LC interrupt mask" "Masked,Not masked" bitfld.long 0x04 20. " RL ,RL interrupt mask" "Masked,Not masked" bitfld.long 0x04 19. " UN ,UN interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 18. " PLR ,PLR interrupt mask" "Masked,Not masked" bitfld.long 0x04 17. " WAKEUP ,WAKEUP interrupt mask" "Masked,Not masked" bitfld.long 0x04 16. " TS_AVAIL ,TS_AVAIL interrupt mask" "Masked,Not masked" bitfld.long 0x04 15. " TS_TIMER ,TS_TIMER interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 14. " RXFLUSH_2 ,RX DMA Ring 2 flush indication" "Masked,Not masked" bitfld.long 0x04 13. " RXFLUSH_1 ,RX DMA Ring 2 flush indication" "Masked,Not masked" bitfld.long 0x04 12. " RXFLUSH_0 ,RX DMA Ring 2 flush indication" "Masked,Not masked" textline " " bitfld.long 0x04 7. " TXF2 ,Transmit frame interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 6. " TXB2 ,Transmit buffer interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 5. " RXF2 ,Receive frame interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 4. " RXB2 ,Receive buffer interrupt - class 2" "Masked,Not masked" textline " " bitfld.long 0x04 3. " TXF1 ,Transmit frame interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 2. " TXB1 ,Transmit buffer interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 1. " RXF1 ,Receive frame interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 0. " RXB1 ,Receive buffer interrupt - class 1" "Masked,Not masked" group.long 0x10++0x07 line.long 0x00 "ENET1_RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "ENET1_TDAR,Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" textline "" if (((per.l(ad:0x42188000+0x24))&0x200)==0x200) group.long 0x24++0x03 line.long 0x00 "ENET1_ECR,Ethernet Control Register" bitfld.long 0x00 11. " SVLANDBL ,S-VLAN double tag" "Disabled,Enabled" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "First,Second" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Not swapped,Swapped" textline " " bitfld.long 0x00 6. " DBGEN ,Debug enable" "Continues operation,Freeze mode" bitfld.long 0x00 5. " SPEED ,Selects between 10/100 and 1000 Mbps modes of operation" "10/100,1000" bitfld.long 0x00 4. " EN1588 ,Enables enhanced functionality of the MAC" "Legacy FEC buffer,Frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Normal operating,Sleep" textline " " bitfld.long 0x00 2. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "No effect,Reset" else group.long 0x24++0x03 line.long 0x00 "ENET1_ECR,Ethernet Control Register" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "First,Second" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Not swapped,Swapped" textline " " bitfld.long 0x00 6. " DBGEN ,Debug enable" "Continues operation,Freeze mode" bitfld.long 0x00 5. " SPEED ,Selects between 10/100 and 1000 Mbps modes of operation" "10/100,1000" bitfld.long 0x00 4. " EN1588 ,Enables enhanced functionality of the MAC" "Legacy FEC buffer,Frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Normal operating,Sleep" textline " " bitfld.long 0x00 2. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "No effect,Reset" endif group.long 0x40++0x07 line.long 0x00 "ENET1_MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "0,1,2,3" bitfld.long 0x00 28.--29. " OP ,Determines the frame operation [Clause 45/Clause 22]" "Write/-,Write,Read,Read/-" bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--17. " TA ,Turn around" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "ENET1_MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,Controls the frequency of the MII management interface clock" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x03 line.long 0x00 "ENET1_MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB idle" "No,Yes" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Clear" group.long 0x84++0x03 line.long 0x00 "ENET1_RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Payload length check disable" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CRCFWD ,Terminate/forward received CRC" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,Enables 10-Mbps mode of the RMII or RGMII" "100 Mbps,10 Mbps" textline " " bitfld.long 0x00 8. " RMII_MODE ,RMII mode enable" "MII mode,RMII operation" bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Non-RGMII,RGMII" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII or RMII mode" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "ENET1_TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Controlled,No CRC" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not modified,Overwritten" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,,,,,,," rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Received" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted" bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "No effect,Stopped" textline "" group.long 0xE4++0x23 line.long 0x00 "ENET1_PALR,Physical Address Lower Register" line.long 0x04 "ENET1_PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 1. " PADDR2 ,Pause address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "ENET1_OPD,Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" line.long 0x0C "ENET1_TXIC0,Transmit Interrupt Coalescing Register" bitfld.long 0x0C 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x0C 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x0C 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x0C 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x10 "ENET1_TXIC1,Transmit Interrupt Coalescing Register" bitfld.long 0x10 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x10 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x10 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x10 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x14 "ENET1_TXIC2,Transmit Interrupt Coalescing Register" bitfld.long 0x14 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x14 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x14 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x14 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x18 "ENET1_RXIC0,Receive Interrupt Coalescing Register" bitfld.long 0x18 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x18 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x18 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x18 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x1C "ENET1_RXIC1,Receive Interrupt Coalescing Register" bitfld.long 0x1C 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x1C 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x1C 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x1C 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x20 "ENET1_RXIC2,Receive Interrupt Coalescing Register" bitfld.long 0x20 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x20 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x20 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x20 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x118++0x0F line.long 0x00 "ENET1_IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "ENET1_IALR,Descriptor Individual Lower Address Register" line.long 0x08 "ENET1_GAUR,Descriptor Group Upper Address Register" line.long 0x0C "ENET1_GALR,Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "ENET1_TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Indicates the number of bytes written to the transmit FIFO" "64,64,128,192,256,320,384,448,512,576,640,704,768,832,896,960,1024,1088,1152,1216,1280,1344,1408,1472,1536,1600,1664,1728,1792,1856,1920,1984,2048,2112,2176,2240,2304,2368,2432,2496,2560,2624,2688,2752,2816,2880,2944,3008,3072,3136,3200,3264,3328,3392,3456,3520,3584,3648,3712,3776,3840,3904,3968,4032" group.long 0x160++0x17 line.long 0x00 "ENET1_RDSR1,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "ENET1_TDSR1,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "ENET1_MRBR1,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" line.long 0x0C "ENET1_RDSR2,Receive Descriptor Ring Start Register" hexmask.long 0x0C 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x10 "ENET1_TDSR2,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x10 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x14 "ENET1_MRBR2,Maximum Receive Buffer Size Register" hexmask.long.byte 0x14 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x180++0x0B line.long 0x00 "ENET1_RDSR,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "ENET1_TDSR,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "ENET1_MRBR,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "ENET1_RSFL,Receive FIFO Section Full Threshold" hexmask.long.word 0x00 0.--9. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "ENET1_RSEM,Receive FIFO Section Empty Threshold" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX Status FIFO Section Empty Threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--9. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "ENET1_RAEM,Receive FIFO Almost Empty Threshold" hexmask.long.word 0x08 0.--9. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "ENET1_RAFL,Receive FIFO Almost Full Threshold" hexmask.long.word 0x0C 0.--9. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "ENET1_TSEM,Transmit FIFO Section Empty Threshold" hexmask.long.word 0x10 0.--9. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "ENET1_TAEM,Transmit FIFO Almost Empty Threshold" hexmask.long.word 0x14 0.--9. 1. " TX_ALMOST_EMPTY ,Value of transmit FIFO almost empty threshold" line.long 0x18 "ENET1_TAFL,Transmit FIFO Almost Full Threshold" hexmask.long.word 0x18 0.--9. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "ENET1_TIPG,Transmit Inter-Packet Gap" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "ENET1_FTRL,Frame Truncation Length" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" textline "" group.long 0x1C0++0x0F line.long 0x00 "ENET1_TACC,Transmit Accelerator Function Configuration" bitfld.long 0x00 4. " PROCHK ,Enables insertion of protocol checksum" "Disabled,Enabled" bitfld.long 0x00 3. " IPCHK ,Enables insertion of IP header checksum" "Disabled,Enabled" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16" "Disabled,Enabled" line.long 0x04 "ENET1_RACC,Receive Accelerator Function Configuration" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" bitfld.long 0x04 1. " IPDIS ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PADREM ,Enable padding removal for short IP frames" "Disabled,Enabled" line.long 0x08 "ENET1_RCMR1,Receive Classification Match Register for Class 1" bitfld.long 0x08 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x08 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" line.long 0x0C "ENET1_RCMR2,Receive Classification Match Register for Class 2" bitfld.long 0x0C 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x0C 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1D8++0x1B line.long 0x00 "ENET1_DMA1CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Consideration of 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations" "Considered,Omitted" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,16-bit value to define the per class idle slope setting used by the credit based shaper defining allocated bandwidth for the class" line.long 0x04 "ENET1_DMA2CFG,DMA Class Based Configuration" bitfld.long 0x04 17. " CALC_NOIPG ,Consideration of 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations" "Considered,Omitted" bitfld.long 0x04 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " IDLE_SLOPE ,16-bit value to define the per class idle slope setting used by the credit based shaper defining allocated bandwidth for the class" line.long 0x08 "ENET1_RDAR1,Receive Descriptor Active Register - Ring 1" bitfld.long 0x08 24. " RDAR ,Receive Descriptor Active" "Inactive,Active" line.long 0x0C "ENET1_TDAR1,Transmit Descriptor Active Register - Ring 1" bitfld.long 0x0C 24. " TDAR ,Transmit Descriptor Active" "Inactive,Active" line.long 0x10 "ENET1_RDAR2,Receive Descriptor Active Register - Ring 2" bitfld.long 0x10 24. " RDAR ,Receive Descriptor Active" "Inactive,Active" line.long 0x14 "ENET1_TDAR2,Transmit Descriptor Active Register - Ring 2" bitfld.long 0x14 24. " TDAR ,Transmit Descriptor Active" "Inactive,Active" line.long 0x18 "ENET1_QOS,QOS Scheme" bitfld.long 0x18 5. " RX_FLUSH2 ,RX Flush Ring 2" "Disabled,Enabled" bitfld.long 0x18 4. " RX_FLUSH1 ,RX Flush Ring 1" "Disabled,Enabled" bitfld.long 0x18 3. " RX_FLUSH0 ,RX Flush Ring 0" "Disabled,Enabled" bitfld.long 0x18 0.--2. " TX_SCHEME ,Configuration information for DMA to select transmitter queue selection/arbitration scheme" "Credit-based,Round-robin,..." textline "" rgroup.long 0x0204++0x43 line.long 0x00 "ENET1_RMON_T_PACKETS,Tx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Packet count" line.long 0x04 "ENET1_RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "ENET1_RMON_T_MC_PKT,Tx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "ENET1_RMON_T_CRC_ALIGN,Tx Packets with CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with CRC/Align Error" line.long 0x10 "ENET1_RMON_T_UNDERSIZE,Tx Packets Less Than Bytes and Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Number of transmit packets less than 64 bytes with good CRC" line.long 0x14 "ENET1_RMON_T_OVERSIZE,Tx Packets GT MAX_FL bytes and Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes with good CRC" line.long 0x18 "ENET1_RMON_T_FRAG,Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Number of packets less than 64 bytes with bad CRC" line.long 0x1C "ENET1_RMON_T_JAB,Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes and bad CRC" line.long 0x20 "ENET1_RMON_T_COL,Tx Collision Count Statistic Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Number of transmit collisions" line.long 0x24 "ENET1_RMON_T_P64,Tx 64-Byte Packets Statistic Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Number of 64-byte transmit packets" line.long 0x28 "ENET1_RMON_T_P65TO127,Tx 65- to 127-byte Packets Statistic Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Number of 65- to 127-byte transmit packets" line.long 0x2C "ENET1_RMON_T_P128TO255,Tx 128- to 255-byte Packets Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Number of 128- to 255-byte transmit packets" line.long 0x30 "ENET1_RMON_T_P256TO511,Tx 256- to 511-byte Packets Statistic Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Number of 256- to 511-byte transmit packets" line.long 0x34 "ENET1_RMON_T_P512TO1023,Tx 512- to 1023-byte Packets Statistic Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Number of 512- to 1023-byte transmit packets" line.long 0x38 "ENET1_RMON_T_P1024TO2047,Tx 1024- to 2047-byte Packets Statistic Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Number of 1024- to 2047-byte transmit packets" line.long 0x3C "ENET1_RMON_T_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than 2048 bytes" line.long 0x40 "ENET1_RMON_T_OCTETS,Tx Octets Statistic Register" rgroup.long 0x24C++0x2B line.long 0x00 "ENET1_IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of frames transmitted OK" line.long 0x04 "ENET1_IEEE_T_1COL,Frames Transmitted with Single Collision Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of frames transmitted with one collision" line.long 0x08 "ENET1_IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of frames transmitted with multiple collisions" line.long 0x0C "ENET1_IEEE_T_DEF,Frames Transmitted after Deferral Delay Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of frames transmitted with deferral delay" line.long 0x10 "ENET1_IEEE_T_LCOL,Frames Transmitted with Late Collision Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of frames transmitted with late collision" line.long 0x14 "ENET1_IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of frames transmitted with excessive collisions" line.long 0x18 "ENET1_IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of frames transmitted with transmit FIFO underrun" line.long 0x1C "ENET1_IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of frames transmitted with carrier sense error" line.long 0x20 "ENET1_IEEE_T_SQE,Frames transmitted with SQE error" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Number of frames transmitted with SQE error" line.long 0x24 "ENET1_IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of flow-control pause frames transmitted" line.long 0x28 "ENET1_IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted w/o Error Statistic Register" rgroup.long 0x284++0x1F line.long 0x00 "ENET1_RMON_R_PACKETS,Rx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of packets received" line.long 0x04 "ENET1_RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of receive broadcast packets" line.long 0x08 "ENET1_RMON_R_MC_PKT,Rx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of receive multicast packets" line.long 0x0C "ENET1_RMON_R_CRC_ALIGN,Rx Packets with CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of receive packets with CRC or align error" line.long 0x10 "ENET1_RMON_R_UNDERSIZE,Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and good CRC" line.long 0x14 "ENET1_RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL and Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and good CRC" line.long 0x18 "ENET1_RMON_R_FRAG,Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and bad CRC" line.long 0x1C "ENET1_RMON_R_JAB,Rx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and bad CRC" rgroup.long 0x2A8++0x3B line.long 0x00 "ENET1_RMON_R_P64,Rx 64-Byte Packets Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of 64-byte receive packets" line.long 0x04 "ENET1_RMON_R_P65TO127,Rx 65- to 127-Byte Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of 65- to 127-byte recieve packets" line.long 0x08 "ENET1_RMON_R_P128TO255,Rx 128- to 255-Byte Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of 128- to 255-byte recieve packets" line.long 0x0C "ENET1_RMON_R_P256TO511,Rx 256- to 511-Byte Packets Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of 256- to 511-byte recieve packets" line.long 0x10 "ENET1_RMON_R_P512TO1023,Rx 512- to 1023-Byte Packets Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of 512- to 1023-byte recieve packets" line.long 0x14 "ENET1_RMON_R_P1024TO2047,Rx 1024- to 2047-Byte Packets Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of 1024- to 2047-byte recieve packets" line.long 0x18 "ENET1_RMON_R_P_GTE2048,Tx 1024- to 2047-byte Packets Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of greater-than-2048-byte recieve packets" line.long 0x1C "ENET1_RMON_R_OCTETS,Rx Octets Statistic Register" line.long 0x20 "ENET1_IEEE_R_DROP,Frames not Counted Correctly Statistic Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "ENET1_IEEE_R_FRAME_OK,Frames Received OK Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of frames received OK" line.long 0x28 "ENET1_IEEE_R_CRC,Frames Received with CRC Error Statistic Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Number of frames received with CRC error" line.long 0x2C "ENET1_IEEE_R_ALIGN,Frames Received with Alignment Error Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Number of frames received with alignment error" line.long 0x30 "ENET1_IEEE_R_MACERR,FIFO Overflow Count Statistic Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Receive FIFO overflow count" line.long 0x34 "ENET1_IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Number of flow-control pause frames received" line.long 0x38 "ENET1_IEEE_R_OCTETS_OK,Octet Count for Frames Received without Error Statistic" group.long 0x400++0x03 line.long 0x00 "ENET1_ATCR,Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "No effect,Captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No effect,Reset" bitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "Disabled,Enabled" bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" group.long 0x404++0x13 line.long 0x00 "ENET1_ATVR,Timer Value Register" line.long 0x04 "ENET1_ATOFF,Timer Offset Register" line.long 0x08 "ENET1_ATPER,Timer Period Register" line.long 0x0C "ENET1_ATCOR,Timer Correction Register" hexmask.long 0x0C 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x10 "ENET1_ATINC,Time-Stamping Clock Period Register" hexmask.long.byte 0x10 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x10 0.--6. 1. " INC ,Clock period of the timestamping clock in nanoseconds" rgroup.long 0x418++0x03 line.long 0x00 "ENET1_ATSTMP,Timestamp of Last Transmitted Frame" group.long 0x604++0x03 line.long 0x00 "ENET1_TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of Timer Flag for channel 3" "Clear,Set" eventfld.long 0x00 2. " TF2 ,Copy of Timer Flag for channel 2" "Clear,Set" eventfld.long 0x00 1. " TF1 ,Copy of Timer Flag for channel 1" "Clear,Set" eventfld.long 0x00 0. " TF0 ,Copy of Timer Flag for channel 0" "Clear,Set" group.long 0x608++0x07 line.long 0x00 "ENET1_TCSR0,Timer Control Status Register 0" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR0,Timer Compare Capture Register 0" group.long 0x610++0x07 line.long 0x00 "ENET1_TCSR1,Timer Control Status Register 1" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR1,Timer Compare Capture Register 1" group.long 0x618++0x07 line.long 0x00 "ENET1_TCSR2,Timer Control Status Register 2" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR2,Timer Compare Capture Register 2" group.long 0x620++0x07 line.long 0x00 "ENET1_TCSR3,Timer Control Status Register 3" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR3,Timer Compare Capture Register 3" width 0xB endif tree.end tree "ENET2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021B4000 width 25. group.long 0x4++0x07 line.long 0x00 "ENET2_EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling Receive Error" "Not occurred,Occurred" eventfld.long 0x00 29. " BABT ,Babbling Transmit Error" "Not occurred,Occurred" eventfld.long 0x00 28. " GRA ,Graceful Stop Complete" "No interrupt,Interrupt" eventfld.long 0x00 27. " TXF ,Transmit Frame Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 26. " TXB ,Transmit Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive Frame Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " RXB ,Receive Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " EBERR ,Ethernet Bus Error" "Not occurred,Occurred" eventfld.long 0x00 21. " LC ,Late Collision" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision Retry Limit" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "Not occurred,Occurred" textline " " eventfld.long 0x00 18. " PLR ,Payload receive error" "Not occurred,Occurred" eventfld.long 0x00 17. " WAKEUP ,Node wake-up request indication" "Not detected,Detected" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Unavailable,Available" eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer" "No interrupt,Interrupt" textline " " eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" textline " " eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt - class 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt - class 1" "No interrupt,Interrupt" line.long 0x04 "ENET2_EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,BABR interrupt mask" "Masked,Not masked" bitfld.long 0x04 29. " BABT ,BABT interrupt mask" "Masked,Not masked" bitfld.long 0x04 28. " GRA ,GRA interrupt mask" "Masked,Not masked" bitfld.long 0x04 27. " TXF ,TXF interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 26. " TXB ,TXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 25. " RXF ,RXF interrupt mask" "Masked,Not masked" bitfld.long 0x04 24. " RXB ,RXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 23. " MII ,MII interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 22. " EBERR ,EBERR interrupt mask" "Masked,Not masked" bitfld.long 0x04 21. " LC ,LC interrupt mask" "Masked,Not masked" bitfld.long 0x04 20. " RL ,RL interrupt mask" "Masked,Not masked" bitfld.long 0x04 19. " UN ,UN interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 18. " PLR ,PLR interrupt mask" "Masked,Not masked" bitfld.long 0x04 17. " WAKEUP ,WAKEUP interrupt mask" "Masked,Not masked" bitfld.long 0x04 16. " TS_AVAIL ,TS_AVAIL interrupt mask" "Masked,Not masked" bitfld.long 0x04 15. " TS_TIMER ,TS_TIMER interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 14. " RXFLUSH_2 ,RX DMA Ring 2 flush indication" "Masked,Not masked" bitfld.long 0x04 13. " RXFLUSH_1 ,RX DMA Ring 2 flush indication" "Masked,Not masked" bitfld.long 0x04 12. " RXFLUSH_0 ,RX DMA Ring 2 flush indication" "Masked,Not masked" textline " " bitfld.long 0x04 7. " TXF2 ,Transmit frame interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 6. " TXB2 ,Transmit buffer interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 5. " RXF2 ,Receive frame interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 4. " RXB2 ,Receive buffer interrupt - class 2" "Masked,Not masked" textline " " bitfld.long 0x04 3. " TXF1 ,Transmit frame interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 2. " TXB1 ,Transmit buffer interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 1. " RXF1 ,Receive frame interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 0. " RXB1 ,Receive buffer interrupt - class 1" "Masked,Not masked" group.long 0x10++0x07 line.long 0x00 "ENET2_RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "ENET2_TDAR,Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" textline "" if (((per.l(ad:0x021B4000+0x24))&0x200)==0x200) group.long 0x24++0x03 line.long 0x00 "ENET2_ECR,Ethernet Control Register" bitfld.long 0x00 11. " SVLANDBL ,S-VLAN double tag" "Disabled,Enabled" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "First,Second" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Not swapped,Swapped" textline " " bitfld.long 0x00 6. " DBGEN ,Debug enable" "Continues operation,Freeze mode" bitfld.long 0x00 5. " SPEED ,Selects between 10/100 and 1000 Mbps modes of operation" "10/100,1000" bitfld.long 0x00 4. " EN1588 ,Enables enhanced functionality of the MAC" "Legacy FEC buffer,Frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Normal operating,Sleep" textline " " bitfld.long 0x00 2. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "No effect,Reset" else group.long 0x24++0x03 line.long 0x00 "ENET2_ECR,Ethernet Control Register" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "First,Second" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Not swapped,Swapped" textline " " bitfld.long 0x00 6. " DBGEN ,Debug enable" "Continues operation,Freeze mode" bitfld.long 0x00 5. " SPEED ,Selects between 10/100 and 1000 Mbps modes of operation" "10/100,1000" bitfld.long 0x00 4. " EN1588 ,Enables enhanced functionality of the MAC" "Legacy FEC buffer,Frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Normal operating,Sleep" textline " " bitfld.long 0x00 2. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "No effect,Reset" endif group.long 0x40++0x07 line.long 0x00 "ENET2_MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "0,1,2,3" bitfld.long 0x00 28.--29. " OP ,Determines the frame operation [Clause 45/Clause 22]" "Write/-,Write,Read,Read/-" bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--17. " TA ,Turn around" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "ENET2_MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,Controls the frequency of the MII management interface clock" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x03 line.long 0x00 "ENET2_MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB idle" "No,Yes" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Clear" group.long 0x84++0x03 line.long 0x00 "ENET2_RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Payload length check disable" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CRCFWD ,Terminate/forward received CRC" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,Enables 10-Mbps mode of the RMII or RGMII" "100 Mbps,10 Mbps" textline " " bitfld.long 0x00 8. " RMII_MODE ,RMII mode enable" "MII mode,RMII operation" bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Non-RGMII,RGMII" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII or RMII mode" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "ENET2_TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Controlled,No CRC" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not modified,Overwritten" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,,,,,,," rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Received" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted" bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "No effect,Stopped" textline "" group.long 0xE4++0x23 line.long 0x00 "ENET2_PALR,Physical Address Lower Register" line.long 0x04 "ENET2_PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 1. " PADDR2 ,Pause address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "ENET2_OPD,Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" line.long 0x0C "ENET2_TXIC0,Transmit Interrupt Coalescing Register" bitfld.long 0x0C 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x0C 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x0C 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x0C 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x10 "ENET2_TXIC1,Transmit Interrupt Coalescing Register" bitfld.long 0x10 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x10 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x10 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x10 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x14 "ENET2_TXIC2,Transmit Interrupt Coalescing Register" bitfld.long 0x14 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x14 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x14 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x14 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x18 "ENET2_RXIC0,Receive Interrupt Coalescing Register" bitfld.long 0x18 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x18 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x18 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x18 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x1C "ENET2_RXIC1,Receive Interrupt Coalescing Register" bitfld.long 0x1C 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x1C 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x1C 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x1C 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x20 "ENET2_RXIC2,Receive Interrupt Coalescing Register" bitfld.long 0x20 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x20 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x20 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x20 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x118++0x0F line.long 0x00 "ENET2_IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "ENET2_IALR,Descriptor Individual Lower Address Register" line.long 0x08 "ENET2_GAUR,Descriptor Group Upper Address Register" line.long 0x0C "ENET2_GALR,Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "ENET2_TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Indicates the number of bytes written to the transmit FIFO" "64,64,128,192,256,320,384,448,512,576,640,704,768,832,896,960,1024,1088,1152,1216,1280,1344,1408,1472,1536,1600,1664,1728,1792,1856,1920,1984,2048,2112,2176,2240,2304,2368,2432,2496,2560,2624,2688,2752,2816,2880,2944,3008,3072,3136,3200,3264,3328,3392,3456,3520,3584,3648,3712,3776,3840,3904,3968,4032" group.long 0x160++0x17 line.long 0x00 "ENET2_RDSR1,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "ENET2_TDSR1,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "ENET2_MRBR1,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" line.long 0x0C "ENET2_RDSR2,Receive Descriptor Ring Start Register" hexmask.long 0x0C 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x10 "ENET2_TDSR2,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x10 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x14 "ENET2_MRBR2,Maximum Receive Buffer Size Register" hexmask.long.byte 0x14 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x180++0x0B line.long 0x00 "ENET2_RDSR,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "ENET2_TDSR,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "ENET2_MRBR,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "ENET2_RSFL,Receive FIFO Section Full Threshold" hexmask.long.word 0x00 0.--9. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "ENET2_RSEM,Receive FIFO Section Empty Threshold" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX Status FIFO Section Empty Threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--9. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "ENET2_RAEM,Receive FIFO Almost Empty Threshold" hexmask.long.word 0x08 0.--9. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "ENET2_RAFL,Receive FIFO Almost Full Threshold" hexmask.long.word 0x0C 0.--9. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "ENET2_TSEM,Transmit FIFO Section Empty Threshold" hexmask.long.word 0x10 0.--9. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "ENET2_TAEM,Transmit FIFO Almost Empty Threshold" hexmask.long.word 0x14 0.--9. 1. " TX_ALMOST_EMPTY ,Value of transmit FIFO almost empty threshold" line.long 0x18 "ENET2_TAFL,Transmit FIFO Almost Full Threshold" hexmask.long.word 0x18 0.--9. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "ENET2_TIPG,Transmit Inter-Packet Gap" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "ENET2_FTRL,Frame Truncation Length" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" textline "" group.long 0x1C0++0x0F line.long 0x00 "ENET2_TACC,Transmit Accelerator Function Configuration" bitfld.long 0x00 4. " PROCHK ,Enables insertion of protocol checksum" "Disabled,Enabled" bitfld.long 0x00 3. " IPCHK ,Enables insertion of IP header checksum" "Disabled,Enabled" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16" "Disabled,Enabled" line.long 0x04 "ENET2_RACC,Receive Accelerator Function Configuration" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" bitfld.long 0x04 1. " IPDIS ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PADREM ,Enable padding removal for short IP frames" "Disabled,Enabled" line.long 0x08 "ENET2_RCMR1,Receive Classification Match Register for Class 1" bitfld.long 0x08 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x08 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" line.long 0x0C "ENET2_RCMR2,Receive Classification Match Register for Class 2" bitfld.long 0x0C 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x0C 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1D8++0x1B line.long 0x00 "ENET2_DMA1CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Consideration of 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations" "Considered,Omitted" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,16-bit value to define the per class idle slope setting used by the credit based shaper defining allocated bandwidth for the class" line.long 0x04 "ENET2_DMA2CFG,DMA Class Based Configuration" bitfld.long 0x04 17. " CALC_NOIPG ,Consideration of 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations" "Considered,Omitted" bitfld.long 0x04 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " IDLE_SLOPE ,16-bit value to define the per class idle slope setting used by the credit based shaper defining allocated bandwidth for the class" line.long 0x08 "ENET2_RDAR1,Receive Descriptor Active Register - Ring 1" bitfld.long 0x08 24. " RDAR ,Receive Descriptor Active" "Inactive,Active" line.long 0x0C "ENET2_TDAR1,Transmit Descriptor Active Register - Ring 1" bitfld.long 0x0C 24. " TDAR ,Transmit Descriptor Active" "Inactive,Active" line.long 0x10 "ENET2_RDAR2,Receive Descriptor Active Register - Ring 2" bitfld.long 0x10 24. " RDAR ,Receive Descriptor Active" "Inactive,Active" line.long 0x14 "ENET2_TDAR2,Transmit Descriptor Active Register - Ring 2" bitfld.long 0x14 24. " TDAR ,Transmit Descriptor Active" "Inactive,Active" line.long 0x18 "ENET2_QOS,QOS Scheme" bitfld.long 0x18 5. " RX_FLUSH2 ,RX Flush Ring 2" "Disabled,Enabled" bitfld.long 0x18 4. " RX_FLUSH1 ,RX Flush Ring 1" "Disabled,Enabled" bitfld.long 0x18 3. " RX_FLUSH0 ,RX Flush Ring 0" "Disabled,Enabled" bitfld.long 0x18 0.--2. " TX_SCHEME ,Configuration information for DMA to select transmitter queue selection/arbitration scheme" "Credit-based,Round-robin,..." textline "" rgroup.long 0x0204++0x43 line.long 0x00 "ENET2_RMON_T_PACKETS,Tx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Packet count" line.long 0x04 "ENET2_RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "ENET2_RMON_T_MC_PKT,Tx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "ENET2_RMON_T_CRC_ALIGN,Tx Packets with CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with CRC/Align Error" line.long 0x10 "ENET2_RMON_T_UNDERSIZE,Tx Packets Less Than Bytes and Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Number of transmit packets less than 64 bytes with good CRC" line.long 0x14 "ENET2_RMON_T_OVERSIZE,Tx Packets GT MAX_FL bytes and Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes with good CRC" line.long 0x18 "ENET2_RMON_T_FRAG,Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Number of packets less than 64 bytes with bad CRC" line.long 0x1C "ENET2_RMON_T_JAB,Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes and bad CRC" line.long 0x20 "ENET2_RMON_T_COL,Tx Collision Count Statistic Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Number of transmit collisions" line.long 0x24 "ENET2_RMON_T_P64,Tx 64-Byte Packets Statistic Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Number of 64-byte transmit packets" line.long 0x28 "ENET2_RMON_T_P65TO127,Tx 65- to 127-byte Packets Statistic Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Number of 65- to 127-byte transmit packets" line.long 0x2C "ENET2_RMON_T_P128TO255,Tx 128- to 255-byte Packets Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Number of 128- to 255-byte transmit packets" line.long 0x30 "ENET2_RMON_T_P256TO511,Tx 256- to 511-byte Packets Statistic Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Number of 256- to 511-byte transmit packets" line.long 0x34 "ENET2_RMON_T_P512TO1023,Tx 512- to 1023-byte Packets Statistic Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Number of 512- to 1023-byte transmit packets" line.long 0x38 "ENET2_RMON_T_P1024TO2047,Tx 1024- to 2047-byte Packets Statistic Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Number of 1024- to 2047-byte transmit packets" line.long 0x3C "ENET2_RMON_T_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than 2048 bytes" line.long 0x40 "ENET2_RMON_T_OCTETS,Tx Octets Statistic Register" rgroup.long 0x24C++0x2B line.long 0x00 "ENET2_IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of frames transmitted OK" line.long 0x04 "ENET2_IEEE_T_1COL,Frames Transmitted with Single Collision Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of frames transmitted with one collision" line.long 0x08 "ENET2_IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of frames transmitted with multiple collisions" line.long 0x0C "ENET2_IEEE_T_DEF,Frames Transmitted after Deferral Delay Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of frames transmitted with deferral delay" line.long 0x10 "ENET2_IEEE_T_LCOL,Frames Transmitted with Late Collision Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of frames transmitted with late collision" line.long 0x14 "ENET2_IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of frames transmitted with excessive collisions" line.long 0x18 "ENET2_IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of frames transmitted with transmit FIFO underrun" line.long 0x1C "ENET2_IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of frames transmitted with carrier sense error" line.long 0x20 "ENET2_IEEE_T_SQE,Frames transmitted with SQE error" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Number of frames transmitted with SQE error" line.long 0x24 "ENET2_IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of flow-control pause frames transmitted" line.long 0x28 "ENET2_IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted w/o Error Statistic Register" rgroup.long 0x284++0x1F line.long 0x00 "ENET2_RMON_R_PACKETS,Rx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of packets received" line.long 0x04 "ENET2_RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of receive broadcast packets" line.long 0x08 "ENET2_RMON_R_MC_PKT,Rx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of receive multicast packets" line.long 0x0C "ENET2_RMON_R_CRC_ALIGN,Rx Packets with CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of receive packets with CRC or align error" line.long 0x10 "ENET2_RMON_R_UNDERSIZE,Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and good CRC" line.long 0x14 "ENET2_RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL and Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and good CRC" line.long 0x18 "ENET2_RMON_R_FRAG,Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and bad CRC" line.long 0x1C "ENET2_RMON_R_JAB,Rx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and bad CRC" rgroup.long 0x2A8++0x3B line.long 0x00 "ENET2_RMON_R_P64,Rx 64-Byte Packets Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of 64-byte receive packets" line.long 0x04 "ENET2_RMON_R_P65TO127,Rx 65- to 127-Byte Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of 65- to 127-byte recieve packets" line.long 0x08 "ENET2_RMON_R_P128TO255,Rx 128- to 255-Byte Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of 128- to 255-byte recieve packets" line.long 0x0C "ENET2_RMON_R_P256TO511,Rx 256- to 511-Byte Packets Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of 256- to 511-byte recieve packets" line.long 0x10 "ENET2_RMON_R_P512TO1023,Rx 512- to 1023-Byte Packets Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of 512- to 1023-byte recieve packets" line.long 0x14 "ENET2_RMON_R_P1024TO2047,Rx 1024- to 2047-Byte Packets Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of 1024- to 2047-byte recieve packets" line.long 0x18 "ENET2_RMON_R_P_GTE2048,Tx 1024- to 2047-byte Packets Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of greater-than-2048-byte recieve packets" line.long 0x1C "ENET2_RMON_R_OCTETS,Rx Octets Statistic Register" line.long 0x20 "ENET2_IEEE_R_DROP,Frames not Counted Correctly Statistic Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "ENET2_IEEE_R_FRAME_OK,Frames Received OK Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of frames received OK" line.long 0x28 "ENET2_IEEE_R_CRC,Frames Received with CRC Error Statistic Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Number of frames received with CRC error" line.long 0x2C "ENET2_IEEE_R_ALIGN,Frames Received with Alignment Error Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Number of frames received with alignment error" line.long 0x30 "ENET2_IEEE_R_MACERR,FIFO Overflow Count Statistic Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Receive FIFO overflow count" line.long 0x34 "ENET2_IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Number of flow-control pause frames received" line.long 0x38 "ENET2_IEEE_R_OCTETS_OK,Octet Count for Frames Received without Error Statistic" group.long 0x400++0x03 line.long 0x00 "ENET2_ATCR,Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "No effect,Captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No effect,Reset" bitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "Disabled,Enabled" bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" group.long 0x404++0x13 line.long 0x00 "ENET2_ATVR,Timer Value Register" line.long 0x04 "ENET2_ATOFF,Timer Offset Register" line.long 0x08 "ENET2_ATPER,Timer Period Register" line.long 0x0C "ENET2_ATCOR,Timer Correction Register" hexmask.long 0x0C 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x10 "ENET2_ATINC,Time-Stamping Clock Period Register" hexmask.long.byte 0x10 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x10 0.--6. 1. " INC ,Clock period of the timestamping clock in nanoseconds" rgroup.long 0x418++0x03 line.long 0x00 "ENET2_ATSTMP,Timestamp of Last Transmitted Frame" group.long 0x604++0x03 line.long 0x00 "ENET2_TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of Timer Flag for channel 3" "Clear,Set" eventfld.long 0x00 2. " TF2 ,Copy of Timer Flag for channel 2" "Clear,Set" eventfld.long 0x00 1. " TF1 ,Copy of Timer Flag for channel 1" "Clear,Set" eventfld.long 0x00 0. " TF0 ,Copy of Timer Flag for channel 0" "Clear,Set" group.long 0x608++0x07 line.long 0x00 "ENET2_TCSR0,Timer Control Status Register 0" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR0,Timer Compare Capture Register 0" group.long 0x610++0x07 line.long 0x00 "ENET2_TCSR1,Timer Control Status Register 1" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR1,Timer Compare Capture Register 1" group.long 0x618++0x07 line.long 0x00 "ENET2_TCSR2,Timer Control Status Register 2" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR2,Timer Compare Capture Register 2" group.long 0x620++0x07 line.long 0x00 "ENET2_TCSR3,Timer Control Status Register 3" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR3,Timer Compare Capture Register 3" width 0xB else base ad:0x421B4000 width 25. group.long 0x4++0x07 line.long 0x00 "ENET2_EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling Receive Error" "Not occurred,Occurred" eventfld.long 0x00 29. " BABT ,Babbling Transmit Error" "Not occurred,Occurred" eventfld.long 0x00 28. " GRA ,Graceful Stop Complete" "No interrupt,Interrupt" eventfld.long 0x00 27. " TXF ,Transmit Frame Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 26. " TXB ,Transmit Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive Frame Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " RXB ,Receive Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " EBERR ,Ethernet Bus Error" "Not occurred,Occurred" eventfld.long 0x00 21. " LC ,Late Collision" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision Retry Limit" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "Not occurred,Occurred" textline " " eventfld.long 0x00 18. " PLR ,Payload receive error" "Not occurred,Occurred" eventfld.long 0x00 17. " WAKEUP ,Node wake-up request indication" "Not detected,Detected" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Unavailable,Available" eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer" "No interrupt,Interrupt" textline " " eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" textline " " eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt - class 2" "No interrupt,Interrupt" eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt - class 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt - class 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt - class 1" "No interrupt,Interrupt" line.long 0x04 "ENET2_EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,BABR interrupt mask" "Masked,Not masked" bitfld.long 0x04 29. " BABT ,BABT interrupt mask" "Masked,Not masked" bitfld.long 0x04 28. " GRA ,GRA interrupt mask" "Masked,Not masked" bitfld.long 0x04 27. " TXF ,TXF interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 26. " TXB ,TXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 25. " RXF ,RXF interrupt mask" "Masked,Not masked" bitfld.long 0x04 24. " RXB ,RXB interrupt mask" "Masked,Not masked" bitfld.long 0x04 23. " MII ,MII interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 22. " EBERR ,EBERR interrupt mask" "Masked,Not masked" bitfld.long 0x04 21. " LC ,LC interrupt mask" "Masked,Not masked" bitfld.long 0x04 20. " RL ,RL interrupt mask" "Masked,Not masked" bitfld.long 0x04 19. " UN ,UN interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 18. " PLR ,PLR interrupt mask" "Masked,Not masked" bitfld.long 0x04 17. " WAKEUP ,WAKEUP interrupt mask" "Masked,Not masked" bitfld.long 0x04 16. " TS_AVAIL ,TS_AVAIL interrupt mask" "Masked,Not masked" bitfld.long 0x04 15. " TS_TIMER ,TS_TIMER interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x04 14. " RXFLUSH_2 ,RX DMA Ring 2 flush indication" "Masked,Not masked" bitfld.long 0x04 13. " RXFLUSH_1 ,RX DMA Ring 2 flush indication" "Masked,Not masked" bitfld.long 0x04 12. " RXFLUSH_0 ,RX DMA Ring 2 flush indication" "Masked,Not masked" textline " " bitfld.long 0x04 7. " TXF2 ,Transmit frame interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 6. " TXB2 ,Transmit buffer interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 5. " RXF2 ,Receive frame interrupt - class 2" "Masked,Not masked" bitfld.long 0x04 4. " RXB2 ,Receive buffer interrupt - class 2" "Masked,Not masked" textline " " bitfld.long 0x04 3. " TXF1 ,Transmit frame interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 2. " TXB1 ,Transmit buffer interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 1. " RXF1 ,Receive frame interrupt - class 1" "Masked,Not masked" bitfld.long 0x04 0. " RXB1 ,Receive buffer interrupt - class 1" "Masked,Not masked" group.long 0x10++0x07 line.long 0x00 "ENET2_RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "ENET2_TDAR,Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" textline "" if (((per.l(ad:0x421B4000+0x24))&0x200)==0x200) group.long 0x24++0x03 line.long 0x00 "ENET2_ECR,Ethernet Control Register" bitfld.long 0x00 11. " SVLANDBL ,S-VLAN double tag" "Disabled,Enabled" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "First,Second" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Not swapped,Swapped" textline " " bitfld.long 0x00 6. " DBGEN ,Debug enable" "Continues operation,Freeze mode" bitfld.long 0x00 5. " SPEED ,Selects between 10/100 and 1000 Mbps modes of operation" "10/100,1000" bitfld.long 0x00 4. " EN1588 ,Enables enhanced functionality of the MAC" "Legacy FEC buffer,Frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Normal operating,Sleep" textline " " bitfld.long 0x00 2. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "No effect,Reset" else group.long 0x24++0x03 line.long 0x00 "ENET2_ECR,Ethernet Control Register" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "First,Second" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Not swapped,Swapped" textline " " bitfld.long 0x00 6. " DBGEN ,Debug enable" "Continues operation,Freeze mode" bitfld.long 0x00 5. " SPEED ,Selects between 10/100 and 1000 Mbps modes of operation" "10/100,1000" bitfld.long 0x00 4. " EN1588 ,Enables enhanced functionality of the MAC" "Legacy FEC buffer,Frame time-stamping" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Normal operating,Sleep" textline " " bitfld.long 0x00 2. " MAGICEN ,Enables/disables magic packet detection" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "No effect,Reset" endif group.long 0x40++0x07 line.long 0x00 "ENET2_MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "0,1,2,3" bitfld.long 0x00 28.--29. " OP ,Determines the frame operation [Clause 45/Clause 22]" "Write/-,Write,Read,Read/-" bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--17. " TA ,Turn around" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "ENET2_MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,Controls the frequency of the MII management interface clock" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x03 line.long 0x00 "ENET2_MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB idle" "No,Yes" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Clear" group.long 0x84++0x03 line.long 0x00 "ENET2_RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Payload length check disable" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CRCFWD ,Terminate/forward received CRC" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,Enables 10-Mbps mode of the RMII or RGMII" "100 Mbps,10 Mbps" textline " " bitfld.long 0x00 8. " RMII_MODE ,RMII mode enable" "MII mode,RMII operation" bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Non-RGMII,RGMII" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII or RMII mode" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "ENET2_TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Controlled,No CRC" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not modified,Overwritten" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,,,,,,," rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Received" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted" bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "No effect,Stopped" textline "" group.long 0xE4++0x23 line.long 0x00 "ENET2_PALR,Physical Address Lower Register" line.long 0x04 "ENET2_PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 1. " PADDR2 ,Pause address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "ENET2_OPD,Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" line.long 0x0C "ENET2_TXIC0,Transmit Interrupt Coalescing Register" bitfld.long 0x0C 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x0C 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x0C 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x0C 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x10 "ENET2_TXIC1,Transmit Interrupt Coalescing Register" bitfld.long 0x10 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x10 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x10 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x10 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x14 "ENET2_TXIC2,Transmit Interrupt Coalescing Register" bitfld.long 0x14 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x14 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x14 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x14 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x18 "ENET2_RXIC0,Receive Interrupt Coalescing Register" bitfld.long 0x18 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x18 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x18 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x18 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x1C "ENET2_RXIC1,Receive Interrupt Coalescing Register" bitfld.long 0x1C 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x1C 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x1C 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x1C 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" line.long 0x20 "ENET2_RXIC2,Receive Interrupt Coalescing Register" bitfld.long 0x20 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x20 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX,ENET system" hexmask.long.byte 0x20 20.--27. 0x10 " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x20 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x118++0x0F line.long 0x00 "ENET2_IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "ENET2_IALR,Descriptor Individual Lower Address Register" line.long 0x08 "ENET2_GAUR,Descriptor Group Upper Address Register" line.long 0x0C "ENET2_GALR,Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "ENET2_TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Indicates the number of bytes written to the transmit FIFO" "64,64,128,192,256,320,384,448,512,576,640,704,768,832,896,960,1024,1088,1152,1216,1280,1344,1408,1472,1536,1600,1664,1728,1792,1856,1920,1984,2048,2112,2176,2240,2304,2368,2432,2496,2560,2624,2688,2752,2816,2880,2944,3008,3072,3136,3200,3264,3328,3392,3456,3520,3584,3648,3712,3776,3840,3904,3968,4032" group.long 0x160++0x17 line.long 0x00 "ENET2_RDSR1,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "ENET2_TDSR1,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "ENET2_MRBR1,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" line.long 0x0C "ENET2_RDSR2,Receive Descriptor Ring Start Register" hexmask.long 0x0C 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x10 "ENET2_TDSR2,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x10 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x14 "ENET2_MRBR2,Maximum Receive Buffer Size Register" hexmask.long.byte 0x14 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x180++0x0B line.long 0x00 "ENET2_RDSR,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x8 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "ENET2_TDSR,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x8 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "ENET2_MRBR,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "ENET2_RSFL,Receive FIFO Section Full Threshold" hexmask.long.word 0x00 0.--9. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "ENET2_RSEM,Receive FIFO Section Empty Threshold" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX Status FIFO Section Empty Threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--9. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "ENET2_RAEM,Receive FIFO Almost Empty Threshold" hexmask.long.word 0x08 0.--9. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "ENET2_RAFL,Receive FIFO Almost Full Threshold" hexmask.long.word 0x0C 0.--9. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "ENET2_TSEM,Transmit FIFO Section Empty Threshold" hexmask.long.word 0x10 0.--9. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "ENET2_TAEM,Transmit FIFO Almost Empty Threshold" hexmask.long.word 0x14 0.--9. 1. " TX_ALMOST_EMPTY ,Value of transmit FIFO almost empty threshold" line.long 0x18 "ENET2_TAFL,Transmit FIFO Almost Full Threshold" hexmask.long.word 0x18 0.--9. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "ENET2_TIPG,Transmit Inter-Packet Gap" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "ENET2_FTRL,Frame Truncation Length" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" textline "" group.long 0x1C0++0x0F line.long 0x00 "ENET2_TACC,Transmit Accelerator Function Configuration" bitfld.long 0x00 4. " PROCHK ,Enables insertion of protocol checksum" "Disabled,Enabled" bitfld.long 0x00 3. " IPCHK ,Enables insertion of IP header checksum" "Disabled,Enabled" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16" "Disabled,Enabled" line.long 0x04 "ENET2_RACC,Receive Accelerator Function Configuration" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" bitfld.long 0x04 1. " IPDIS ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PADREM ,Enable padding removal for short IP frames" "Disabled,Enabled" line.long 0x08 "ENET2_RCMR1,Receive Classification Match Register for Class 1" bitfld.long 0x08 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x08 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" line.long 0x0C "ENET2_RCMR2,Receive Classification Match Register for Class 2" bitfld.long 0x0C 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x0C 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1D8++0x1B line.long 0x00 "ENET2_DMA1CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Consideration of 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations" "Considered,Omitted" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,16-bit value to define the per class idle slope setting used by the credit based shaper defining allocated bandwidth for the class" line.long 0x04 "ENET2_DMA2CFG,DMA Class Based Configuration" bitfld.long 0x04 17. " CALC_NOIPG ,Consideration of 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations" "Considered,Omitted" bitfld.long 0x04 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " IDLE_SLOPE ,16-bit value to define the per class idle slope setting used by the credit based shaper defining allocated bandwidth for the class" line.long 0x08 "ENET2_RDAR1,Receive Descriptor Active Register - Ring 1" bitfld.long 0x08 24. " RDAR ,Receive Descriptor Active" "Inactive,Active" line.long 0x0C "ENET2_TDAR1,Transmit Descriptor Active Register - Ring 1" bitfld.long 0x0C 24. " TDAR ,Transmit Descriptor Active" "Inactive,Active" line.long 0x10 "ENET2_RDAR2,Receive Descriptor Active Register - Ring 2" bitfld.long 0x10 24. " RDAR ,Receive Descriptor Active" "Inactive,Active" line.long 0x14 "ENET2_TDAR2,Transmit Descriptor Active Register - Ring 2" bitfld.long 0x14 24. " TDAR ,Transmit Descriptor Active" "Inactive,Active" line.long 0x18 "ENET2_QOS,QOS Scheme" bitfld.long 0x18 5. " RX_FLUSH2 ,RX Flush Ring 2" "Disabled,Enabled" bitfld.long 0x18 4. " RX_FLUSH1 ,RX Flush Ring 1" "Disabled,Enabled" bitfld.long 0x18 3. " RX_FLUSH0 ,RX Flush Ring 0" "Disabled,Enabled" bitfld.long 0x18 0.--2. " TX_SCHEME ,Configuration information for DMA to select transmitter queue selection/arbitration scheme" "Credit-based,Round-robin,..." textline "" rgroup.long 0x0204++0x43 line.long 0x00 "ENET2_RMON_T_PACKETS,Tx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Packet count" line.long 0x04 "ENET2_RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "ENET2_RMON_T_MC_PKT,Tx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "ENET2_RMON_T_CRC_ALIGN,Tx Packets with CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with CRC/Align Error" line.long 0x10 "ENET2_RMON_T_UNDERSIZE,Tx Packets Less Than Bytes and Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Number of transmit packets less than 64 bytes with good CRC" line.long 0x14 "ENET2_RMON_T_OVERSIZE,Tx Packets GT MAX_FL bytes and Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes with good CRC" line.long 0x18 "ENET2_RMON_T_FRAG,Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Number of packets less than 64 bytes with bad CRC" line.long 0x1C "ENET2_RMON_T_JAB,Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes and bad CRC" line.long 0x20 "ENET2_RMON_T_COL,Tx Collision Count Statistic Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Number of transmit collisions" line.long 0x24 "ENET2_RMON_T_P64,Tx 64-Byte Packets Statistic Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Number of 64-byte transmit packets" line.long 0x28 "ENET2_RMON_T_P65TO127,Tx 65- to 127-byte Packets Statistic Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Number of 65- to 127-byte transmit packets" line.long 0x2C "ENET2_RMON_T_P128TO255,Tx 128- to 255-byte Packets Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Number of 128- to 255-byte transmit packets" line.long 0x30 "ENET2_RMON_T_P256TO511,Tx 256- to 511-byte Packets Statistic Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Number of 256- to 511-byte transmit packets" line.long 0x34 "ENET2_RMON_T_P512TO1023,Tx 512- to 1023-byte Packets Statistic Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Number of 512- to 1023-byte transmit packets" line.long 0x38 "ENET2_RMON_T_P1024TO2047,Tx 1024- to 2047-byte Packets Statistic Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Number of 1024- to 2047-byte transmit packets" line.long 0x3C "ENET2_RMON_T_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than 2048 bytes" line.long 0x40 "ENET2_RMON_T_OCTETS,Tx Octets Statistic Register" rgroup.long 0x24C++0x2B line.long 0x00 "ENET2_IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of frames transmitted OK" line.long 0x04 "ENET2_IEEE_T_1COL,Frames Transmitted with Single Collision Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of frames transmitted with one collision" line.long 0x08 "ENET2_IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of frames transmitted with multiple collisions" line.long 0x0C "ENET2_IEEE_T_DEF,Frames Transmitted after Deferral Delay Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of frames transmitted with deferral delay" line.long 0x10 "ENET2_IEEE_T_LCOL,Frames Transmitted with Late Collision Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of frames transmitted with late collision" line.long 0x14 "ENET2_IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of frames transmitted with excessive collisions" line.long 0x18 "ENET2_IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of frames transmitted with transmit FIFO underrun" line.long 0x1C "ENET2_IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of frames transmitted with carrier sense error" line.long 0x20 "ENET2_IEEE_T_SQE,Frames transmitted with SQE error" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Number of frames transmitted with SQE error" line.long 0x24 "ENET2_IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of flow-control pause frames transmitted" line.long 0x28 "ENET2_IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted w/o Error Statistic Register" rgroup.long 0x284++0x1F line.long 0x00 "ENET2_RMON_R_PACKETS,Rx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of packets received" line.long 0x04 "ENET2_RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of receive broadcast packets" line.long 0x08 "ENET2_RMON_R_MC_PKT,Rx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of receive multicast packets" line.long 0x0C "ENET2_RMON_R_CRC_ALIGN,Rx Packets with CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of receive packets with CRC or align error" line.long 0x10 "ENET2_RMON_R_UNDERSIZE,Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and good CRC" line.long 0x14 "ENET2_RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL and Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and good CRC" line.long 0x18 "ENET2_RMON_R_FRAG,Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and bad CRC" line.long 0x1C "ENET2_RMON_R_JAB,Rx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and bad CRC" rgroup.long 0x2A8++0x3B line.long 0x00 "ENET2_RMON_R_P64,Rx 64-Byte Packets Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of 64-byte receive packets" line.long 0x04 "ENET2_RMON_R_P65TO127,Rx 65- to 127-Byte Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of 65- to 127-byte recieve packets" line.long 0x08 "ENET2_RMON_R_P128TO255,Rx 128- to 255-Byte Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of 128- to 255-byte recieve packets" line.long 0x0C "ENET2_RMON_R_P256TO511,Rx 256- to 511-Byte Packets Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of 256- to 511-byte recieve packets" line.long 0x10 "ENET2_RMON_R_P512TO1023,Rx 512- to 1023-Byte Packets Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of 512- to 1023-byte recieve packets" line.long 0x14 "ENET2_RMON_R_P1024TO2047,Rx 1024- to 2047-Byte Packets Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of 1024- to 2047-byte recieve packets" line.long 0x18 "ENET2_RMON_R_P_GTE2048,Tx 1024- to 2047-byte Packets Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of greater-than-2048-byte recieve packets" line.long 0x1C "ENET2_RMON_R_OCTETS,Rx Octets Statistic Register" line.long 0x20 "ENET2_IEEE_R_DROP,Frames not Counted Correctly Statistic Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "ENET2_IEEE_R_FRAME_OK,Frames Received OK Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of frames received OK" line.long 0x28 "ENET2_IEEE_R_CRC,Frames Received with CRC Error Statistic Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Number of frames received with CRC error" line.long 0x2C "ENET2_IEEE_R_ALIGN,Frames Received with Alignment Error Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Number of frames received with alignment error" line.long 0x30 "ENET2_IEEE_R_MACERR,FIFO Overflow Count Statistic Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Receive FIFO overflow count" line.long 0x34 "ENET2_IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Number of flow-control pause frames received" line.long 0x38 "ENET2_IEEE_R_OCTETS_OK,Octet Count for Frames Received without Error Statistic" group.long 0x400++0x03 line.long 0x00 "ENET2_ATCR,Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "No effect,Captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No effect,Reset" bitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "Disabled,Enabled" bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" group.long 0x404++0x13 line.long 0x00 "ENET2_ATVR,Timer Value Register" line.long 0x04 "ENET2_ATOFF,Timer Offset Register" line.long 0x08 "ENET2_ATPER,Timer Period Register" line.long 0x0C "ENET2_ATCOR,Timer Correction Register" hexmask.long 0x0C 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x10 "ENET2_ATINC,Time-Stamping Clock Period Register" hexmask.long.byte 0x10 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x10 0.--6. 1. " INC ,Clock period of the timestamping clock in nanoseconds" rgroup.long 0x418++0x03 line.long 0x00 "ENET2_ATSTMP,Timestamp of Last Transmitted Frame" group.long 0x604++0x03 line.long 0x00 "ENET2_TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of Timer Flag for channel 3" "Clear,Set" eventfld.long 0x00 2. " TF2 ,Copy of Timer Flag for channel 2" "Clear,Set" eventfld.long 0x00 1. " TF1 ,Copy of Timer Flag for channel 1" "Clear,Set" eventfld.long 0x00 0. " TF0 ,Copy of Timer Flag for channel 0" "Clear,Set" group.long 0x608++0x07 line.long 0x00 "ENET2_TCSR0,Timer Control Status Register 0" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR0,Timer Compare Capture Register 0" group.long 0x610++0x07 line.long 0x00 "ENET2_TCSR1,Timer Control Status Register 1" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR1,Timer Compare Capture Register 1" group.long 0x618++0x07 line.long 0x00 "ENET2_TCSR2,Timer Control Status Register 2" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR2,Timer Compare Capture Register 2" group.long 0x620++0x07 line.long 0x00 "ENET2_TCSR3,Timer Control Status Register 3" eventfld.long 0x00 7. " TF ,Timer Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer Mode" "Disabled,Input/Rising edge,Input/Falling edge,Input/Both,Output/Software only,Output/Toggle,Output/Clear,Output/Set,,Output/Set/Clear,Output/Clear/Set,Output/Set/Clear,,,Output/Low pulse,Output/High pulse" bitfld.long 0x00 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long 0x04 "ENET_TCCR3,Timer Compare Capture Register 3" width 0xB endif tree.end tree.end tree "EPIT (Enhanced Periodic Interrupt Timer)" tree "EPIT1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020D0000 else base ad:0x420D0000 endif width 12. group.long 0x00++0x0F line.long 0x00 "EPIT1_CR,Control register" bitfld.long 0x00 24.--25. " CLKSRC ,Select clock source" "Off,Peripheral,High-freq,Low-freq" bitfld.long 0x00 22.--23. " OM ,EPIT output mode" "EPIT,Toggle,Clear,Set" bitfld.long 0x00 21. " STOPEN ,Operation of the EPIT during stop mode" "Disabled,Enabled" bitfld.long 0x00 19. " WAITEN ,Operation of the EPIT during wait mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " DBGEN ,Operation of the EPIT during debug mode" "Inactive,Active" bitfld.long 0x00 17. " IOVW ,Counter data when the modulus register is written" "Not overwritten,Overwritten" eventfld.long 0x00 16. " SWR ,Software reset" "Out of,Undergoing" hexmask.long.word 0x00 4.--15. 1. " PRESCALAR ,Prescaler value by which the clock is divided before it goes to the counter" textline " " bitfld.long 0x00 3. " RLD ,Counter reload control" "Free-running,Set-and-forget" bitfld.long 0x00 2. " OCIEN ,Output compare interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENMOD ,EPIT enable mode" "Previous value,Loaded value" bitfld.long 0x00 0. " EN ,EPIT counter" "Disabled,Enabled" line.long 0x04 "EPIT1_SR,Status register" eventfld.long 0x04 0. " OCIF ,Output compare interrupt flag" "Not occurred,Occurred" line.long 0x08 "EPIT1_LR,Load register" line.long 0x0C "EPIT1_CMPR,Compare register" rgroup.long 0x10++0x03 line.long 0x00 "EPIT1_CNR,Counter register" width 0xB tree.end tree "EPIT2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020D4000 else base ad:0x420D4000 endif width 12. group.long 0x00++0x0F line.long 0x00 "EPIT2_CR,Control register" bitfld.long 0x00 24.--25. " CLKSRC ,Select clock source" "Off,Peripheral,High-freq,Low-freq" bitfld.long 0x00 22.--23. " OM ,EPIT output mode" "EPIT,Toggle,Clear,Set" bitfld.long 0x00 21. " STOPEN ,Operation of the EPIT during stop mode" "Disabled,Enabled" bitfld.long 0x00 19. " WAITEN ,Operation of the EPIT during wait mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " DBGEN ,Operation of the EPIT during debug mode" "Inactive,Active" bitfld.long 0x00 17. " IOVW ,Counter data when the modulus register is written" "Not overwritten,Overwritten" eventfld.long 0x00 16. " SWR ,Software reset" "Out of,Undergoing" hexmask.long.word 0x00 4.--15. 1. " PRESCALAR ,Prescaler value by which the clock is divided before it goes to the counter" textline " " bitfld.long 0x00 3. " RLD ,Counter reload control" "Free-running,Set-and-forget" bitfld.long 0x00 2. " OCIEN ,Output compare interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENMOD ,EPIT enable mode" "Previous value,Loaded value" bitfld.long 0x00 0. " EN ,EPIT counter" "Disabled,Enabled" line.long 0x04 "EPIT2_SR,Status register" eventfld.long 0x04 0. " OCIF ,Output compare interrupt flag" "Not occurred,Occurred" line.long 0x08 "EPIT2_LR,Load register" line.long 0x0C "EPIT2_CMPR,Compare register" rgroup.long 0x10++0x03 line.long 0x00 "EPIT2_CNR,Counter register" width 0xB tree.end tree.end tree "ESAI (Enhanced Serial Audio Interface)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02024000 width 7. wgroup.long 0x00++0x03 line.long 0x00 "ETDR,ESAI Transmit Data Register" hgroup.long 0x04++0x03 hide.long 0x00 "ERDR,ESAI Receive Data Register" in group.long 0x08++0x03 line.long 0x00 "ECR,ESAI Control Register" bitfld.long 0x00 19. " ETI ,EXTAL transmitter in" "HCKT normal,EXTAL muxed into HCKT" bitfld.long 0x00 18. " ETO ,EXTAL transmitter out" "HCKT normal,EXTAL driven onto HCKT" bitfld.long 0x00 17. " ERI ,EXTAL receiver in" "HCKR normal,EXTAL muxed into HCKR" bitfld.long 0x00 16. " ERO ,EXTAL receiver out" "HCKR normal,EXTAL driven onto HCKR" newline bitfld.long 0x00 1. " ERST ,ESAI reset" "No reset,Reset" bitfld.long 0x00 0. " ESAIEN ,ESAI enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "ESR,ESAI Status Register" bitfld.long 0x00 10. " TINIT ,Transmit initialization" "Finished,Not finished" newline bitfld.long 0x00 9. " RFF ,Receive FIFO full" "< Rx FIFO watermark,>= Rx FIFO watermark" bitfld.long 0x00 8. " TFE ,Transmit FIFO empty" "< Tx FIFO watermark,>= Tx FIFO watermark" newline bitfld.long 0x00 7. " TLS ,Transmit last slot" "Not highest priority,Highest priority" bitfld.long 0x00 6. " TDE ,Transmit data exception" "Not highest priority,Highest priority" newline bitfld.long 0x00 5. " TED ,Transmit even data" "Not highest priority,Highest priority" bitfld.long 0x00 4. " TD ,Transmit data" "Not highest priority,Highest priority" newline bitfld.long 0x00 3. " RLS ,Receive last slot" "Not highest priority,Highest priority" bitfld.long 0x00 2. " RDE ,Receive data exception" "Not highest priority,Highest priority" newline bitfld.long 0x00 1. " RED ,Receive even data" "Not highest priority,Highest priority" bitfld.long 0x00 0. " RD ,Receive data" "Not highest priority,Highest priority" sif !cpuis("IMX8DX*")&&!cpuis("IMX8QXP*") group.long 0x10++0x03 line.long 0x00 "TFCR,Transmit FIFO Configuration Register" sif (cpu()=="IMX6ULL") bitfld.long 0x00 21. " TFIN ,Tx FIFO interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TAENB ,Tx FIFO align enable" "Disabled,Enabled" newline endif bitfld.long 0x00 19. " TIEN ,Transmitter initialization enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " TWA ,Transmit word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " TFWM ,Transmit FIFO watermark" bitfld.long 0x00 7. " TE5 ,Transmitter #5 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 6. " TE4 ,Transmitter #4 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 5. " TE3 ,Transmitter #3 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " TE2 ,Transmitter #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE1 ,Transmitter #1 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE0 ,Transmitter #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFR ,Transmit FIFO reset" "No reset,Reset" newline bitfld.long 0x00 0. " TFE ,Transmit FIFO enable" "Disabled,Enabled" else if (((per.l(ad:0x02024000+0x10))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "TFCR,Transmit FIFO Configuration Register" bitfld.long 0x00 19. " TIEN ,Transmitter initialization enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " TWA ,Transmit word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " TFWM ,Transmit FIFO watermark" rbitfld.long 0x00 7. " TE5 ,Transmitter #5 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 6. " TE4 ,Transmitter #4 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 5. " TE3 ,Transmitter #3 FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " TE2 ,Transmitter #2 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 3. " TE1 ,Transmitter #1 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TE0 ,Transmitter #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFR ,Transmit FIFO reset" "No reset,Reset" newline bitfld.long 0x00 0. " TFE ,Transmit FIFO enable" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "TFCR,Transmit FIFO Configuration Register" bitfld.long 0x00 19. " TIEN ,Transmitter initialization enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " TWA ,Transmit word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " TFWM ,Transmit FIFO watermark" bitfld.long 0x00 7. " TE5 ,Transmitter #5 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 6. " TE4 ,Transmitter #4 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 5. " TE3 ,Transmitter #3 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " TE2 ,Transmitter #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE1 ,Transmitter #1 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE0 ,Transmitter #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFR ,Transmit FIFO reset" "No reset,Reset" newline bitfld.long 0x00 0. " TFE ,Transmit FIFO enable" "Disabled,Enabled" endif endif rgroup.long 0x14++0x03 line.long 0x00 "TFSR,Transmit FIFO Status Register" bitfld.long 0x00 12.--14. " NTFO ,Next transmitter FIFO out" "#0,#1,#2,#3,#4,#5,,?..." bitfld.long 0x00 8.--10. " NTFI ,Next transmitter FIFO in" "#0,#1,#2,#3,#4,#5,,?..." hexmask.long.byte 0x00 0.--7. 1. " TFCNT ,Transmit FIFO counter" sif !cpuis("IMX8DX*")&&!cpuis("IMX8QXP*") group.long 0x18++0x03 line.long 0x00 "RFCR,Receive FIFO Configuration Register" sif (cpu()=="IMX6ULL") bitfld.long 0x00 21. " RFIN ,Rx FIFO interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " RAENB ,Rx FIFO align enable" "Disabled,Enabled" newline endif bitfld.long 0x00 19. " REXT ,Receive extension" "Zero,Sign" newline bitfld.long 0x00 16.--18. " RWA ,Receive word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " RFWM ,Receive FIFO watermark" bitfld.long 0x00 5. " RE3 ,Receiver #3 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4. " RE2 ,Receiver #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " RE1 ,Receiver #1 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE0 ,Receiver #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " RFR ,Receive FIFO reset" "No reset,Reset" bitfld.long 0x00 0. " RFE ,Receive FIFO enable" "Disabled,Enabled" else if (((per.l(ad:0x02024000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "RFCR,Receive FIFO Configuration Register" bitfld.long 0x00 19. " REXT ,Receive extension" "Zero,Sign" newline bitfld.long 0x00 16.--18. " RWA ,Receive word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " RFWM ,Receive FIFO watermark" rbitfld.long 0x00 5. " RE3 ,Receiver #3 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4. " RE2 ,Receiver #2 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 3. " RE1 ,Receiver #1 FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " RE0 ,Receiver #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " RFR ,Receive FIFO reset" "No reset,Reset" bitfld.long 0x00 0. " RFE ,Receive FIFO enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "RFCR,Receive FIFO Configuration Register" bitfld.long 0x00 19. " REXT ,Receive extension" "Zero,Sign" newline bitfld.long 0x00 16.--18. " RWA ,Receive word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " RFWM ,Receive FIFO watermark" bitfld.long 0x00 5. " RE3 ,Receiver #3 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4. " RE2 ,Receiver #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " RE1 ,Receiver #1 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE0 ,Receiver #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " RFR ,Receive FIFO reset" "No reset,Reset" bitfld.long 0x00 0. " RFE ,Receive FIFO enable" "Disabled,Enabled" endif endif rgroup.long 0x1C++0x03 line.long 0x00 "RFSR,Receive FIFO Status Register" bitfld.long 0x00 12.--13. " NRFI ,Next receiver FIFO in" "#0,#1,#2,#3" bitfld.long 0x00 8.--9. " NRFO ,Next receiver FIFO out" "#0,#1,#2,#3" hexmask.long.byte 0x00 0.--7. 1. " RFCNT ,Receive FIFO counter" newline wgroup.long 0x80++0x03 line.long 0x00 "TX0,ESAI Transmit Data Register 0" hexmask.long.tbyte 0x00 0.--23. 1. " TX0 ,Stores the data to be transmitted" wgroup.long 0x84++0x03 line.long 0x00 "TX1,ESAI Transmit Data Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " TX1 ,Stores the data to be transmitted" wgroup.long 0x88++0x03 line.long 0x00 "TX2,ESAI Transmit Data Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " TX2 ,Stores the data to be transmitted" wgroup.long 0x8C++0x03 line.long 0x00 "TX3,ESAI Transmit Data Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " TX3 ,Stores the data to be transmitted" wgroup.long 0x90++0x03 line.long 0x00 "TX4,ESAI Transmit Data Register 4" hexmask.long.tbyte 0x00 0.--23. 1. " TX4 ,Stores the data to be transmitted" wgroup.long 0x94++0x03 line.long 0x00 "TX5,ESAI Transmit Data Register 5" hexmask.long.tbyte 0x00 0.--23. 1. " TX5 ,Stores the data to be transmitted" wgroup.long 0x98++0x03 line.long 0x00 "TSR,ESAI Transmit Slot Register" hexmask.long.tbyte 0x00 0.--23. 1. " TSR ,Transmit slot register" rgroup.long 0xA0++0x03 line.long 0x00 "RX0,ESAI Receive Data Registers 0" hexmask.long.tbyte 0x00 0.--23. 1. " RX0 ,Data from the receive shift register" rgroup.long 0xA0++0x03 line.long 0x00 "RX1,ESAI Receive Data Registers 1" hexmask.long.tbyte 0x00 0.--23. 1. " RX1 ,Data from the receive shift register" rgroup.long 0xA0++0x03 line.long 0x00 "RX2,ESAI Receive Data Registers 2" hexmask.long.tbyte 0x00 0.--23. 1. " RX2 ,Data from the receive shift register" rgroup.long 0xA0++0x03 line.long 0x00 "RX3,ESAI Receive Data Registers 3" hexmask.long.tbyte 0x00 0.--23. 1. " RX3 ,Data from the receive shift register" newline rgroup.long 0xCC++0x03 line.long 0x00 "SAISR,ESAI Status Register" bitfld.long 0x00 17. " TODFE ,SAISR transmit odd-data register empty" "Not empty,Empty" bitfld.long 0x00 16. " TEDE ,SAISR transmit even-data register empty" "Not empty,Empty" bitfld.long 0x00 15. " TDE ,SAISR transmit data register empty" "Not empty,Empty" newline bitfld.long 0x00 14. " TUE ,SAISR transmit underrun error flag" "No error,Error" bitfld.long 0x00 13. " TFS ,SAISR transmit frame sync flag" "Not occurred,Occurred" bitfld.long 0x00 10. " RODF ,SAISR receive odd-data register full" "Not full,Full" newline bitfld.long 0x00 9. " REDF ,SAISR receive even-data register full" "Not full,Full" bitfld.long 0x00 8. " RDF ,SAISR receive data register full" "Not full,Full" bitfld.long 0x00 7. " ROE ,SAISR receive overrun error flag" "No error,Error" newline bitfld.long 0x00 6. " RFS ,SAISR receive frame sync flag" "Not occurred,Occurred" bitfld.long 0x00 2. " IF2 ,SAISR serial input flag 2" "Not occurred,Occurred" newline bitfld.long 0x00 1. " IF1 ,SAISR serial input flag 1" "Not occurred,Occurred" bitfld.long 0x00 0. " IF0 ,SAISR serial input flag 0" "Not occurred,Occurred" group.long 0xD0++0x03 line.long 0x00 "SAICR,ESAI Common Control Register" bitfld.long 0x00 8. " ALC ,SAICR alignment control" "23 bit,15 bit" bitfld.long 0x00 7. " TEBE ,SAICR transmit external buffer enable" "Disabled,Enabled" bitfld.long 0x00 6. " SYN ,SAICR synchronous mode selection" "Asynchronous,Synchronous" newline bitfld.long 0x00 2. " OF2 ,SAICR serial output flag 2" "Not occurred,Occurred" bitfld.long 0x00 1. " OF1 ,SAICR serial output flag 1" "Not occurred,Occurred" bitfld.long 0x00 0. " OF0 ,SAICR serial output flag 0" "Not occurred,Occurred" newline if ((per.l(ad:0x02024000+0xD8)&0x3E00)==0x00) group.long 0xD4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 23. " TLIE ,Transmit last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " TEDIE ,Transmit even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TEIE ,Transmit exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TPR ,Transmit section personal reset" "No effect,Reset" bitfld.long 0x00 17. " PADC ,Transmit zero padding control" "Disabled,Enabled" newline bitfld.long 0x00 16. " TFSR ,Transmit frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " TFSL ,Transmit frame sync length" "Word-length,1-bit clock period" newline bitfld.long 0x00 10.--14. " TSWS ,Transmit slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" bitfld.long 0x00 8.--9. " TMOD ,Transmit network mode control" "Normal,On-demand,?..." newline bitfld.long 0x00 7. " TWA ,Transmit word alignment control" "Left,Right" bitfld.long 0x00 6. " TSHFD ,Transmit shift direction" "MSB first,LSB first" newline bitfld.long 0x00 5. " TE5 ,ESAI transmit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " TE4 ,ESAI transmit 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " TE3 ,ESAI transmit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE2 ,ESAI transmit 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TE1 ,ESAI transmit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " TE0 ,ESAI transmit 0 enable" "Disabled,Enabled" elif ((per.l(ad:0x02024000+0xD8)&0x3e00)==0x1800) group.long 0xD4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 23. " TLIE ,Transmit last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " TEDIE ,Transmit even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TEIE ,Transmit exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TPR ,Transmit section personal reset" "No effect,Reset" bitfld.long 0x00 17. " PADC ,Transmit zero padding control" "Disabled,Enabled" newline bitfld.long 0x00 16. " TFSR ,Transmit frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " TFSL ,Transmit frame sync length" "Word-length,1-bit clock period" newline bitfld.long 0x00 10.--14. " TSWS ,Transmit slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" bitfld.long 0x00 8.--9. " TMOD ,Transmit network mode control" "Normal,Network,,AC97" newline bitfld.long 0x00 7. " TWA ,Transmit word alignment control" "Left,Right" bitfld.long 0x00 6. " TSHFD ,Transmit shift direction" "MSB first,LSB first" newline bitfld.long 0x00 5. " TE5 ,ESAI transmit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " TE4 ,ESAI transmit 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " TE3 ,ESAI transmit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE2 ,ESAI transmit 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TE1 ,ESAI transmit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " TE0 ,ESAI transmit 0 enable" "Disabled,Enabled" else group.long 0xD4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 23. " TLIE ,Transmit last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " TEDIE ,Transmit even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TEIE ,Transmit exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TPR ,Transmit section personal reset" "No effect,Reset" bitfld.long 0x00 17. " PADC ,Transmit zero padding control" "Disabled,Enabled" newline bitfld.long 0x00 16. " TFSR ,Transmit frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " TFSL ,Transmit frame sync length" "Word-length,1-bit clock period" newline bitfld.long 0x00 10.--14. " TSWS ,Transmit slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" bitfld.long 0x00 8.--9. " TMOD ,Transmit network mode control" "Normal,Network,?..." newline bitfld.long 0x00 7. " TWA ,Transmit word alignment control" "Left,Right" bitfld.long 0x00 6. " TSHFD ,Transmit shift direction" "MSB first,LSB first" newline bitfld.long 0x00 5. " TE5 ,ESAI transmit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " TE4 ,ESAI transmit 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " TE3 ,ESAI transmit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE2 ,ESAI transmit 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TE1 ,ESAI transmit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " TE0 ,ESAI transmit 0 enable" "Disabled,Enabled" endif group.long 0xD8++0x03 line.long 0x00 "TCCR,Transmit Clock Control Register" bitfld.long 0x00 23. " THCKD ,High frequency clock direction (HCKR pin) (HCKT pin)" "Input,Output" bitfld.long 0x00 22. " TFSD ,Frame sync signal direction (FST pin)" "Input,Output" newline bitfld.long 0x00 21. " TCKD ,Transmitter Clock source direction (SCKT pin)" "External,Internal" bitfld.long 0x00 20. " THCKP ,Transmitter high frequency clock polarity" "Normal,Inverted" newline bitfld.long 0x00 19. " TFSP ,Transmitter frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " TCKP ,Transmitter clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " TFP ,Tx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " TDC ,Frame rate divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " TPSR ,Transmit prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " TPM ,Transmit prescale modulus select" if ((per.l(ad:0x02024000+0xE0)&0x3E00)==0x00) group.long 0xDC++0x03 line.long 0x00 "RCR,Receive Control Register" bitfld.long 0x00 23. " RLIE ,Receive last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " RIE ,Receive interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " REDIE ,Receive even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " REIE ,Receive exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RPR ,Receiver section personal reset" "No effect,Reset" bitfld.long 0x00 16. " RFSR ,Receiver frame sync relative timing" "First bit of data,Last bit of prev data" newline bitfld.long 0x00 15. " RFSL ,Receiver frame sync length" "Word-length,1-bit clock period" bitfld.long 0x00 10.--14. " RSWS ,Receiver slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" newline bitfld.long 0x00 8.--9. " RMOD ,Receiver network mode control" "Normal,On-demand,?..." bitfld.long 0x00 7. " RWA ,Receiver word alignment control" "Left,Right" newline bitfld.long 0x00 6. " RSHFD ,Receiver shift direction" "MSB first,LSB first" bitfld.long 0x00 3. " RE3 ,ESAI receiver 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE2 ,ESAI receiver 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " RE1 ,ESAI receiver 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RE0 ,ESAI receiver 0 enable" "Disabled,Enabled" elif ((per.l(ad:0x02024000+0xE0)&0x3E00)==0x1800) group.long 0xDC++0x03 line.long 0x00 "RCR,Receive Control Register" bitfld.long 0x00 23. " RLIE ,Receive last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " RIE ,Receive interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " REDIE ,Receive even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " REIE ,Receive exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RPR ,Receiver section personal reset" "No effect,Reset" bitfld.long 0x00 16. " RFSR ,Receiver frame sync relative timing" "First bit of data,Last bit of prev data" newline bitfld.long 0x00 15. " RFSL ,Receiver frame sync length" "Word-length,1-bit clock period" bitfld.long 0x00 10.--14. " RSWS ,Receiver slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" newline bitfld.long 0x00 8.--9. " RMOD ,Receiver network mode control" "Normal,Network,,AC97" bitfld.long 0x00 7. " RWA ,Receiver word alignment control" "Left,Right" newline bitfld.long 0x00 6. " RSHFD ,Receiver shift direction" "MSB first,LSB first" bitfld.long 0x00 3. " RE3 ,ESAI receiver 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE2 ,ESAI receiver 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " RE1 ,ESAI receiver 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RE0 ,ESAI receiver 0 enable" "Disabled,Enabled" else group.long 0xDC++0x03 line.long 0x00 "RCR,Receive Control Register" bitfld.long 0x00 23. " RLIE ,Receive last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " RIE ,Receive interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " REDIE ,Receive even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " REIE ,Receive exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RPR ,Receiver section personal reset" "No effect,Reset" bitfld.long 0x00 16. " RFSR ,Receiver frame sync relative timing" "First bit of data,Last bit of prev data" newline bitfld.long 0x00 15. " RFSL ,Receiver frame sync length" "Word-length,1-bit clock period" bitfld.long 0x00 10.--14. " RSWS ,Receiver slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" newline bitfld.long 0x00 8.--9. " RMOD ,Receiver network mode control" "Normal,Network,?..." bitfld.long 0x00 7. " RWA ,Receiver word alignment control" "Left,Right" newline bitfld.long 0x00 6. " RSHFD ,Receiver shift direction" "MSB first,LSB first" bitfld.long 0x00 3. " RE3 ,ESAI receiver 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE2 ,ESAI receiver 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " RE1 ,ESAI receiver 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RE0 ,ESAI receiver 0 enable" "Disabled,Enabled" endif if ((per.l(ad:0x02024000+0xDC)&0x300)==0x100)&&((per.l(ad:0x02024000+0xD0)&0x40)==0x00) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "HCKR input,HCKR output" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "FSR input,FSR output" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "SCKR input,SCKR output" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "On-demand,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif ((per.l(ad:0x02024000+0xDC)&0x300)==0x100)&&((per.l(ad:0x02024000+0xD0)&0x40)==0x40)&&((per.l(ad:0x02024000+0xD0)&0x80)==0x0) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "IF1,OF1" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "On-demand,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif ((per.l(ad:0x02024000+0xDC)&0x300)==0x100)&&((per.l(ad:0x02024000+0xD0)&0x40)==0x40)&&((per.l(ad:0x02024000+0xD0)&0x80)==0x80) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" ",TxBufferEnable" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "On-demand,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif ((per.l(ad:0x02024000+0xD0)&0x40)==0x00) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "HCKR input,HCKR output" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "FSR input,FSR output" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "SCKR input,SCKR output" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif (((per.l(ad:0x02024000+0xD0)&0x40)==0x40)&&((per.l(ad:0x02024000+0xD0)&0x80)==0x00)) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "IF1,OF1" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif (((per.l(ad:0x02024000+0xD0)&0x40)==0x40)&&((per.l(ad:0x02024000+0xD0)&0x80)==0x80)) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" ",TxBufferEnable" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" endif newline group.long 0xE4++0x0F line.long 0x00 "TSMA,Transmit Slot Mask Register A" bitfld.long 0x00 15. " TS[15] ,Transmit slot 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Transmit slot 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Transmit slot 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Transmit slot 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Transmit slot 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Transmit slot 10" "Disabled,Enabled" bitfld.long 0x00 9. " [09] ,Transmit slot 9" "Disabled,Enabled" bitfld.long 0x00 8. " [08] ,Transmit slot 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [07] ,Transmit slot 7" "Disabled,Enabled" bitfld.long 0x00 6. " [06] ,Transmit slot 6" "Disabled,Enabled" bitfld.long 0x00 5. " [05] ,Transmit slot 5" "Disabled,Enabled" bitfld.long 0x00 4. " [04] ,Transmit slot 4" "Disabled,Enabled" bitfld.long 0x00 3. " [03] ,Transmit slot 3" "Disabled,Enabled" bitfld.long 0x00 2. " [02] ,Transmit slot 2" "Disabled,Enabled" bitfld.long 0x00 1. " [01] ,Transmit slot 1" "Disabled,Enabled" bitfld.long 0x00 0. " [00] ,Transmit slot 0" "Disabled,Enabled" line.long 0x04 "TSMB,Transmit Slot Mask Register B" bitfld.long 0x04 15. " TS[31] ,Transmit slot 31" "Disabled,Enabled" bitfld.long 0x04 14. " [30] ,Transmit slot 30" "Disabled,Enabled" bitfld.long 0x04 13. " [29] ,Transmit slot 29" "Disabled,Enabled" bitfld.long 0x04 12. " [28] ,Transmit slot 28" "Disabled,Enabled" bitfld.long 0x04 11. " [27] ,Transmit slot 27" "Disabled,Enabled" bitfld.long 0x04 10. " [26] ,Transmit slot 26" "Disabled,Enabled" bitfld.long 0x04 9. " [25] ,Transmit slot 25" "Disabled,Enabled" bitfld.long 0x04 8. " [24] ,Transmit slot 24" "Disabled,Enabled" newline bitfld.long 0x04 7. " [23] ,Transmit slot 23" "Disabled,Enabled" bitfld.long 0x04 6. " [22] ,Transmit slot 22" "Disabled,Enabled" bitfld.long 0x04 5. " [21] ,Transmit slot 21" "Disabled,Enabled" bitfld.long 0x04 4. " [20] ,Transmit slot 20" "Disabled,Enabled" bitfld.long 0x04 3. " [19] ,Transmit slot 19" "Disabled,Enabled" bitfld.long 0x04 2. " [18] ,Transmit slot 18" "Disabled,Enabled" bitfld.long 0x04 1. " [17] ,Transmit slot 17" "Disabled,Enabled" bitfld.long 0x04 0. " [16] ,Transmit slot 16" "Disabled,Enabled" line.long 0x08 "RSMA,Receive Slot Mask Register A" bitfld.long 0x08 15. " RS[15] ,Receive slot 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Receive slot 14" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Receive slot 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Receive slot 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Receive slot 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Receive slot 10" "Disabled,Enabled" bitfld.long 0x08 9. " [09] ,Receive slot 9" "Disabled,Enabled" bitfld.long 0x08 8. " [08] ,Receive slot 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [07] ,Receive slot 7" "Disabled,Enabled" bitfld.long 0x08 6. " [06] ,Receive slot 6" "Disabled,Enabled" bitfld.long 0x08 5. " [05] ,Receive slot 5" "Disabled,Enabled" bitfld.long 0x08 4. " [04] ,Receive slot 4" "Disabled,Enabled" bitfld.long 0x08 3. " [03] ,Receive slot 3" "Disabled,Enabled" bitfld.long 0x08 2. " [02] ,Receive slot 2" "Disabled,Enabled" bitfld.long 0x08 1. " [01] ,Receive slot 1" "Disabled,Enabled" bitfld.long 0x08 0. " [00] ,Receive slot 0" "Disabled,Enabled" line.long 0x0C "RSMB,Receive Slot Mask Register B" bitfld.long 0x0C 15. " RS[31] ,Receive slot 31" "Disabled,Enabled" bitfld.long 0x0C 14. " [30] ,Receive slot 30" "Disabled,Enabled" bitfld.long 0x0C 13. " [29] ,Receive slot 29" "Disabled,Enabled" bitfld.long 0x0C 12. " [28] ,Receive slot 28" "Disabled,Enabled" bitfld.long 0x0C 11. " [27] ,Receive slot 27" "Disabled,Enabled" bitfld.long 0x0C 10. " [26] ,Receive slot 26" "Disabled,Enabled" bitfld.long 0x0C 9. " [25] ,Receive slot 25" "Disabled,Enabled" bitfld.long 0x0C 8. " [24] ,Receive slot 24" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [23] ,Receive slot 23" "Disabled,Enabled" bitfld.long 0x0C 6. " [22] ,Receive slot 22" "Disabled,Enabled" bitfld.long 0x0C 5. " [21] ,Receive slot 21" "Disabled,Enabled" bitfld.long 0x0C 4. " [20] ,Receive slot 20" "Disabled,Enabled" bitfld.long 0x0C 3. " [19] ,Receive slot 19" "Disabled,Enabled" bitfld.long 0x0C 2. " [18] ,Receive slot 18" "Disabled,Enabled" bitfld.long 0x0C 1. " [17] ,Receive slot 17" "Disabled,Enabled" bitfld.long 0x0C 0. " [16] ,Receive slot 16" "Disabled,Enabled" newline sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") group.long 0xF4++0x03 line.long 0x00 "PDRC,Port C Data Register" bitfld.long 0x00 11. " PD[11] ,GPIO input/output reflection bit 11" "0,1" bitfld.long 0x00 10. " [10] ,GPIO input/output reflection bit 10" "0,1" bitfld.long 0x00 9. " [9] ,GPIO input/output reflection bit 9" "0,1" bitfld.long 0x00 8. " [8] ,GPIO input/output reflection bit 8" "0,1" bitfld.long 0x00 7. " [7] ,GPIO input/output reflection bit 7" "0,1" bitfld.long 0x00 6. " [6] ,GPIO input/output reflection bit 6" "0,1" bitfld.long 0x00 5. " [5] ,GPIO input/output reflection bit 5" "0,1" bitfld.long 0x00 4. " [4] ,GPIO input/output reflection bit 4" "0,1" bitfld.long 0x00 3. " [3] ,GPIO input/output reflection bit 3" "0,1" bitfld.long 0x00 2. " [2] ,GPIO input/output reflection bit 2" "0,1" bitfld.long 0x00 1. " [1] ,GPIO input/output reflection bit 1" "0,1" bitfld.long 0x00 0. " [0] ,GPIO input/output reflection bit 0" "0,1" endif group.long 0xF8++0x07 line.long 0x00 "PRRC,Port C Direction Register" bitfld.long 0x00 11. " PDC[11] ,Port C direction pin 11" "0,1" bitfld.long 0x00 10. " [10] ,Port C direction pin 10" "0,1" bitfld.long 0x00 9. " [9] ,Port C direction pin 9" "0,1" bitfld.long 0x00 8. " [8] ,Port C direction pin 8" "0,1" bitfld.long 0x00 7. " [7] ,Port C direction pin 7" "0,1" bitfld.long 0x00 6. " [6] ,Port C direction pin 6" "0,1" bitfld.long 0x00 5. " [5] ,Port C direction pin 5" "0,1" bitfld.long 0x00 4. " [4] ,Port C direction pin 4" "0,1" bitfld.long 0x00 3. " [3] ,Port C direction pin 3" "0,1" bitfld.long 0x00 2. " [2] ,Port C direction pin 2" "0,1" bitfld.long 0x00 1. " [1] ,Port C direction pin 1" "0,1" bitfld.long 0x00 0. " [0] ,Port C direction pin 0" "0,1" line.long 0x04 "PCRC,Port C Control Register" bitfld.long 0x04 11. " PC[11] ,Port C control pin 11" "0,1" bitfld.long 0x04 10. " [10] ,Port C control pin 10" "0,1" bitfld.long 0x04 9. " [9] ,Port C control pin 9" "0,1" bitfld.long 0x04 8. " [8] ,Port C control pin 8" "0,1" bitfld.long 0x04 7. " [7] ,Port C control pin 7" "0,1" bitfld.long 0x04 6. " [6] ,Port C control pin 6" "0,1" bitfld.long 0x04 5. " [5] ,Port C control pin 5" "0,1" bitfld.long 0x04 4. " [4] ,Port C control pin 4" "0,1" bitfld.long 0x04 3. " [3] ,Port C control pin 3" "0,1" bitfld.long 0x04 2. " [2] ,Port C control pin 2" "0,1" bitfld.long 0x04 1. " [1] ,Port C control pin 1" "0,1" bitfld.long 0x04 0. " [0] ,Port C control pin 0" "0,1" width 0x0B else base ad:0x42024000 width 7. wgroup.long 0x00++0x03 line.long 0x00 "ETDR,ESAI Transmit Data Register" hgroup.long 0x04++0x03 hide.long 0x00 "ERDR,ESAI Receive Data Register" in group.long 0x08++0x03 line.long 0x00 "ECR,ESAI Control Register" bitfld.long 0x00 19. " ETI ,EXTAL transmitter in" "HCKT normal,EXTAL muxed into HCKT" bitfld.long 0x00 18. " ETO ,EXTAL transmitter out" "HCKT normal,EXTAL driven onto HCKT" bitfld.long 0x00 17. " ERI ,EXTAL receiver in" "HCKR normal,EXTAL muxed into HCKR" bitfld.long 0x00 16. " ERO ,EXTAL receiver out" "HCKR normal,EXTAL driven onto HCKR" newline bitfld.long 0x00 1. " ERST ,ESAI reset" "No reset,Reset" bitfld.long 0x00 0. " ESAIEN ,ESAI enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "ESR,ESAI Status Register" bitfld.long 0x00 10. " TINIT ,Transmit initialization" "Finished,Not finished" newline bitfld.long 0x00 9. " RFF ,Receive FIFO full" "< Rx FIFO watermark,>= Rx FIFO watermark" bitfld.long 0x00 8. " TFE ,Transmit FIFO empty" "< Tx FIFO watermark,>= Tx FIFO watermark" newline bitfld.long 0x00 7. " TLS ,Transmit last slot" "Not highest priority,Highest priority" bitfld.long 0x00 6. " TDE ,Transmit data exception" "Not highest priority,Highest priority" newline bitfld.long 0x00 5. " TED ,Transmit even data" "Not highest priority,Highest priority" bitfld.long 0x00 4. " TD ,Transmit data" "Not highest priority,Highest priority" newline bitfld.long 0x00 3. " RLS ,Receive last slot" "Not highest priority,Highest priority" bitfld.long 0x00 2. " RDE ,Receive data exception" "Not highest priority,Highest priority" newline bitfld.long 0x00 1. " RED ,Receive even data" "Not highest priority,Highest priority" bitfld.long 0x00 0. " RD ,Receive data" "Not highest priority,Highest priority" sif !cpuis("IMX8DX*")&&!cpuis("IMX8QXP*") group.long 0x10++0x03 line.long 0x00 "TFCR,Transmit FIFO Configuration Register" sif (cpu()=="IMX6ULL") bitfld.long 0x00 21. " TFIN ,Tx FIFO interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TAENB ,Tx FIFO align enable" "Disabled,Enabled" newline endif bitfld.long 0x00 19. " TIEN ,Transmitter initialization enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " TWA ,Transmit word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " TFWM ,Transmit FIFO watermark" bitfld.long 0x00 7. " TE5 ,Transmitter #5 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 6. " TE4 ,Transmitter #4 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 5. " TE3 ,Transmitter #3 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " TE2 ,Transmitter #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE1 ,Transmitter #1 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE0 ,Transmitter #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFR ,Transmit FIFO reset" "No reset,Reset" newline bitfld.long 0x00 0. " TFE ,Transmit FIFO enable" "Disabled,Enabled" else if (((per.l(ad:0x42024000+0x10))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "TFCR,Transmit FIFO Configuration Register" bitfld.long 0x00 19. " TIEN ,Transmitter initialization enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " TWA ,Transmit word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " TFWM ,Transmit FIFO watermark" rbitfld.long 0x00 7. " TE5 ,Transmitter #5 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 6. " TE4 ,Transmitter #4 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 5. " TE3 ,Transmitter #3 FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " TE2 ,Transmitter #2 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 3. " TE1 ,Transmitter #1 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TE0 ,Transmitter #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFR ,Transmit FIFO reset" "No reset,Reset" newline bitfld.long 0x00 0. " TFE ,Transmit FIFO enable" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "TFCR,Transmit FIFO Configuration Register" bitfld.long 0x00 19. " TIEN ,Transmitter initialization enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " TWA ,Transmit word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " TFWM ,Transmit FIFO watermark" bitfld.long 0x00 7. " TE5 ,Transmitter #5 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 6. " TE4 ,Transmitter #4 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 5. " TE3 ,Transmitter #3 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " TE2 ,Transmitter #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE1 ,Transmitter #1 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE0 ,Transmitter #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFR ,Transmit FIFO reset" "No reset,Reset" newline bitfld.long 0x00 0. " TFE ,Transmit FIFO enable" "Disabled,Enabled" endif endif rgroup.long 0x14++0x03 line.long 0x00 "TFSR,Transmit FIFO Status Register" bitfld.long 0x00 12.--14. " NTFO ,Next transmitter FIFO out" "#0,#1,#2,#3,#4,#5,,?..." bitfld.long 0x00 8.--10. " NTFI ,Next transmitter FIFO in" "#0,#1,#2,#3,#4,#5,,?..." hexmask.long.byte 0x00 0.--7. 1. " TFCNT ,Transmit FIFO counter" sif !cpuis("IMX8DX*")&&!cpuis("IMX8QXP*") group.long 0x18++0x03 line.long 0x00 "RFCR,Receive FIFO Configuration Register" sif (cpu()=="IMX6ULL") bitfld.long 0x00 21. " RFIN ,Rx FIFO interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " RAENB ,Rx FIFO align enable" "Disabled,Enabled" newline endif bitfld.long 0x00 19. " REXT ,Receive extension" "Zero,Sign" newline bitfld.long 0x00 16.--18. " RWA ,Receive word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " RFWM ,Receive FIFO watermark" bitfld.long 0x00 5. " RE3 ,Receiver #3 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4. " RE2 ,Receiver #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " RE1 ,Receiver #1 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE0 ,Receiver #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " RFR ,Receive FIFO reset" "No reset,Reset" bitfld.long 0x00 0. " RFE ,Receive FIFO enable" "Disabled,Enabled" else if (((per.l(ad:0x42024000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "RFCR,Receive FIFO Configuration Register" bitfld.long 0x00 19. " REXT ,Receive extension" "Zero,Sign" newline bitfld.long 0x00 16.--18. " RWA ,Receive word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " RFWM ,Receive FIFO watermark" rbitfld.long 0x00 5. " RE3 ,Receiver #3 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4. " RE2 ,Receiver #2 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 3. " RE1 ,Receiver #1 FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " RE0 ,Receiver #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " RFR ,Receive FIFO reset" "No reset,Reset" bitfld.long 0x00 0. " RFE ,Receive FIFO enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "RFCR,Receive FIFO Configuration Register" bitfld.long 0x00 19. " REXT ,Receive extension" "Zero,Sign" newline bitfld.long 0x00 16.--18. " RWA ,Receive word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" newline hexmask.long.byte 0x00 8.--15. 1. " RFWM ,Receive FIFO watermark" bitfld.long 0x00 5. " RE3 ,Receiver #3 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4. " RE2 ,Receiver #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " RE1 ,Receiver #1 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE0 ,Receiver #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " RFR ,Receive FIFO reset" "No reset,Reset" bitfld.long 0x00 0. " RFE ,Receive FIFO enable" "Disabled,Enabled" endif endif rgroup.long 0x1C++0x03 line.long 0x00 "RFSR,Receive FIFO Status Register" bitfld.long 0x00 12.--13. " NRFI ,Next receiver FIFO in" "#0,#1,#2,#3" bitfld.long 0x00 8.--9. " NRFO ,Next receiver FIFO out" "#0,#1,#2,#3" hexmask.long.byte 0x00 0.--7. 1. " RFCNT ,Receive FIFO counter" newline wgroup.long 0x80++0x03 line.long 0x00 "TX0,ESAI Transmit Data Register 0" hexmask.long.tbyte 0x00 0.--23. 1. " TX0 ,Stores the data to be transmitted" wgroup.long 0x84++0x03 line.long 0x00 "TX1,ESAI Transmit Data Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " TX1 ,Stores the data to be transmitted" wgroup.long 0x88++0x03 line.long 0x00 "TX2,ESAI Transmit Data Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " TX2 ,Stores the data to be transmitted" wgroup.long 0x8C++0x03 line.long 0x00 "TX3,ESAI Transmit Data Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " TX3 ,Stores the data to be transmitted" wgroup.long 0x90++0x03 line.long 0x00 "TX4,ESAI Transmit Data Register 4" hexmask.long.tbyte 0x00 0.--23. 1. " TX4 ,Stores the data to be transmitted" wgroup.long 0x94++0x03 line.long 0x00 "TX5,ESAI Transmit Data Register 5" hexmask.long.tbyte 0x00 0.--23. 1. " TX5 ,Stores the data to be transmitted" wgroup.long 0x98++0x03 line.long 0x00 "TSR,ESAI Transmit Slot Register" hexmask.long.tbyte 0x00 0.--23. 1. " TSR ,Transmit slot register" rgroup.long 0xA0++0x03 line.long 0x00 "RX0,ESAI Receive Data Registers 0" hexmask.long.tbyte 0x00 0.--23. 1. " RX0 ,Data from the receive shift register" rgroup.long 0xA0++0x03 line.long 0x00 "RX1,ESAI Receive Data Registers 1" hexmask.long.tbyte 0x00 0.--23. 1. " RX1 ,Data from the receive shift register" rgroup.long 0xA0++0x03 line.long 0x00 "RX2,ESAI Receive Data Registers 2" hexmask.long.tbyte 0x00 0.--23. 1. " RX2 ,Data from the receive shift register" rgroup.long 0xA0++0x03 line.long 0x00 "RX3,ESAI Receive Data Registers 3" hexmask.long.tbyte 0x00 0.--23. 1. " RX3 ,Data from the receive shift register" newline rgroup.long 0xCC++0x03 line.long 0x00 "SAISR,ESAI Status Register" bitfld.long 0x00 17. " TODFE ,SAISR transmit odd-data register empty" "Not empty,Empty" bitfld.long 0x00 16. " TEDE ,SAISR transmit even-data register empty" "Not empty,Empty" bitfld.long 0x00 15. " TDE ,SAISR transmit data register empty" "Not empty,Empty" newline bitfld.long 0x00 14. " TUE ,SAISR transmit underrun error flag" "No error,Error" bitfld.long 0x00 13. " TFS ,SAISR transmit frame sync flag" "Not occurred,Occurred" bitfld.long 0x00 10. " RODF ,SAISR receive odd-data register full" "Not full,Full" newline bitfld.long 0x00 9. " REDF ,SAISR receive even-data register full" "Not full,Full" bitfld.long 0x00 8. " RDF ,SAISR receive data register full" "Not full,Full" bitfld.long 0x00 7. " ROE ,SAISR receive overrun error flag" "No error,Error" newline bitfld.long 0x00 6. " RFS ,SAISR receive frame sync flag" "Not occurred,Occurred" bitfld.long 0x00 2. " IF2 ,SAISR serial input flag 2" "Not occurred,Occurred" newline bitfld.long 0x00 1. " IF1 ,SAISR serial input flag 1" "Not occurred,Occurred" bitfld.long 0x00 0. " IF0 ,SAISR serial input flag 0" "Not occurred,Occurred" group.long 0xD0++0x03 line.long 0x00 "SAICR,ESAI Common Control Register" bitfld.long 0x00 8. " ALC ,SAICR alignment control" "23 bit,15 bit" bitfld.long 0x00 7. " TEBE ,SAICR transmit external buffer enable" "Disabled,Enabled" bitfld.long 0x00 6. " SYN ,SAICR synchronous mode selection" "Asynchronous,Synchronous" newline bitfld.long 0x00 2. " OF2 ,SAICR serial output flag 2" "Not occurred,Occurred" bitfld.long 0x00 1. " OF1 ,SAICR serial output flag 1" "Not occurred,Occurred" bitfld.long 0x00 0. " OF0 ,SAICR serial output flag 0" "Not occurred,Occurred" newline if ((per.l(ad:0x42024000+0xD8)&0x3E00)==0x00) group.long 0xD4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 23. " TLIE ,Transmit last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " TEDIE ,Transmit even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TEIE ,Transmit exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TPR ,Transmit section personal reset" "No effect,Reset" bitfld.long 0x00 17. " PADC ,Transmit zero padding control" "Disabled,Enabled" newline bitfld.long 0x00 16. " TFSR ,Transmit frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " TFSL ,Transmit frame sync length" "Word-length,1-bit clock period" newline bitfld.long 0x00 10.--14. " TSWS ,Transmit slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" bitfld.long 0x00 8.--9. " TMOD ,Transmit network mode control" "Normal,On-demand,?..." newline bitfld.long 0x00 7. " TWA ,Transmit word alignment control" "Left,Right" bitfld.long 0x00 6. " TSHFD ,Transmit shift direction" "MSB first,LSB first" newline bitfld.long 0x00 5. " TE5 ,ESAI transmit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " TE4 ,ESAI transmit 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " TE3 ,ESAI transmit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE2 ,ESAI transmit 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TE1 ,ESAI transmit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " TE0 ,ESAI transmit 0 enable" "Disabled,Enabled" elif ((per.l(ad:0x42024000+0xD8)&0x3e00)==0x1800) group.long 0xD4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 23. " TLIE ,Transmit last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " TEDIE ,Transmit even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TEIE ,Transmit exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TPR ,Transmit section personal reset" "No effect,Reset" bitfld.long 0x00 17. " PADC ,Transmit zero padding control" "Disabled,Enabled" newline bitfld.long 0x00 16. " TFSR ,Transmit frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " TFSL ,Transmit frame sync length" "Word-length,1-bit clock period" newline bitfld.long 0x00 10.--14. " TSWS ,Transmit slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" bitfld.long 0x00 8.--9. " TMOD ,Transmit network mode control" "Normal,Network,,AC97" newline bitfld.long 0x00 7. " TWA ,Transmit word alignment control" "Left,Right" bitfld.long 0x00 6. " TSHFD ,Transmit shift direction" "MSB first,LSB first" newline bitfld.long 0x00 5. " TE5 ,ESAI transmit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " TE4 ,ESAI transmit 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " TE3 ,ESAI transmit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE2 ,ESAI transmit 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TE1 ,ESAI transmit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " TE0 ,ESAI transmit 0 enable" "Disabled,Enabled" else group.long 0xD4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 23. " TLIE ,Transmit last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " TEDIE ,Transmit even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TEIE ,Transmit exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TPR ,Transmit section personal reset" "No effect,Reset" bitfld.long 0x00 17. " PADC ,Transmit zero padding control" "Disabled,Enabled" newline bitfld.long 0x00 16. " TFSR ,Transmit frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " TFSL ,Transmit frame sync length" "Word-length,1-bit clock period" newline bitfld.long 0x00 10.--14. " TSWS ,Transmit slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" bitfld.long 0x00 8.--9. " TMOD ,Transmit network mode control" "Normal,Network,?..." newline bitfld.long 0x00 7. " TWA ,Transmit word alignment control" "Left,Right" bitfld.long 0x00 6. " TSHFD ,Transmit shift direction" "MSB first,LSB first" newline bitfld.long 0x00 5. " TE5 ,ESAI transmit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " TE4 ,ESAI transmit 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " TE3 ,ESAI transmit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " TE2 ,ESAI transmit 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TE1 ,ESAI transmit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " TE0 ,ESAI transmit 0 enable" "Disabled,Enabled" endif group.long 0xD8++0x03 line.long 0x00 "TCCR,Transmit Clock Control Register" bitfld.long 0x00 23. " THCKD ,High frequency clock direction (HCKR pin) (HCKT pin)" "Input,Output" bitfld.long 0x00 22. " TFSD ,Frame sync signal direction (FST pin)" "Input,Output" newline bitfld.long 0x00 21. " TCKD ,Transmitter Clock source direction (SCKT pin)" "External,Internal" bitfld.long 0x00 20. " THCKP ,Transmitter high frequency clock polarity" "Normal,Inverted" newline bitfld.long 0x00 19. " TFSP ,Transmitter frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " TCKP ,Transmitter clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " TFP ,Tx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " TDC ,Frame rate divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " TPSR ,Transmit prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " TPM ,Transmit prescale modulus select" if ((per.l(ad:0x42024000+0xE0)&0x3E00)==0x00) group.long 0xDC++0x03 line.long 0x00 "RCR,Receive Control Register" bitfld.long 0x00 23. " RLIE ,Receive last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " RIE ,Receive interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " REDIE ,Receive even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " REIE ,Receive exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RPR ,Receiver section personal reset" "No effect,Reset" bitfld.long 0x00 16. " RFSR ,Receiver frame sync relative timing" "First bit of data,Last bit of prev data" newline bitfld.long 0x00 15. " RFSL ,Receiver frame sync length" "Word-length,1-bit clock period" bitfld.long 0x00 10.--14. " RSWS ,Receiver slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" newline bitfld.long 0x00 8.--9. " RMOD ,Receiver network mode control" "Normal,On-demand,?..." bitfld.long 0x00 7. " RWA ,Receiver word alignment control" "Left,Right" newline bitfld.long 0x00 6. " RSHFD ,Receiver shift direction" "MSB first,LSB first" bitfld.long 0x00 3. " RE3 ,ESAI receiver 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE2 ,ESAI receiver 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " RE1 ,ESAI receiver 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RE0 ,ESAI receiver 0 enable" "Disabled,Enabled" elif ((per.l(ad:0x42024000+0xE0)&0x3E00)==0x1800) group.long 0xDC++0x03 line.long 0x00 "RCR,Receive Control Register" bitfld.long 0x00 23. " RLIE ,Receive last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " RIE ,Receive interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " REDIE ,Receive even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " REIE ,Receive exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RPR ,Receiver section personal reset" "No effect,Reset" bitfld.long 0x00 16. " RFSR ,Receiver frame sync relative timing" "First bit of data,Last bit of prev data" newline bitfld.long 0x00 15. " RFSL ,Receiver frame sync length" "Word-length,1-bit clock period" bitfld.long 0x00 10.--14. " RSWS ,Receiver slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" newline bitfld.long 0x00 8.--9. " RMOD ,Receiver network mode control" "Normal,Network,,AC97" bitfld.long 0x00 7. " RWA ,Receiver word alignment control" "Left,Right" newline bitfld.long 0x00 6. " RSHFD ,Receiver shift direction" "MSB first,LSB first" bitfld.long 0x00 3. " RE3 ,ESAI receiver 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE2 ,ESAI receiver 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " RE1 ,ESAI receiver 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RE0 ,ESAI receiver 0 enable" "Disabled,Enabled" else group.long 0xDC++0x03 line.long 0x00 "RCR,Receive Control Register" bitfld.long 0x00 23. " RLIE ,Receive last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " RIE ,Receive interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " REDIE ,Receive even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " REIE ,Receive exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RPR ,Receiver section personal reset" "No effect,Reset" bitfld.long 0x00 16. " RFSR ,Receiver frame sync relative timing" "First bit of data,Last bit of prev data" newline bitfld.long 0x00 15. " RFSL ,Receiver frame sync length" "Word-length,1-bit clock period" bitfld.long 0x00 10.--14. " RSWS ,Receiver slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" newline bitfld.long 0x00 8.--9. " RMOD ,Receiver network mode control" "Normal,Network,?..." bitfld.long 0x00 7. " RWA ,Receiver word alignment control" "Left,Right" newline bitfld.long 0x00 6. " RSHFD ,Receiver shift direction" "MSB first,LSB first" bitfld.long 0x00 3. " RE3 ,ESAI receiver 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RE2 ,ESAI receiver 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " RE1 ,ESAI receiver 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RE0 ,ESAI receiver 0 enable" "Disabled,Enabled" endif if ((per.l(ad:0x42024000+0xDC)&0x300)==0x100)&&((per.l(ad:0x42024000+0xD0)&0x40)==0x00) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "HCKR input,HCKR output" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "FSR input,FSR output" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "SCKR input,SCKR output" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "On-demand,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif ((per.l(ad:0x42024000+0xDC)&0x300)==0x100)&&((per.l(ad:0x42024000+0xD0)&0x40)==0x40)&&((per.l(ad:0x42024000+0xD0)&0x80)==0x0) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "IF1,OF1" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "On-demand,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif ((per.l(ad:0x42024000+0xDC)&0x300)==0x100)&&((per.l(ad:0x42024000+0xD0)&0x40)==0x40)&&((per.l(ad:0x42024000+0xD0)&0x80)==0x80) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" ",TxBufferEnable" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "On-demand,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif ((per.l(ad:0x42024000+0xD0)&0x40)==0x00) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "HCKR input,HCKR output" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "FSR input,FSR output" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "SCKR input,SCKR output" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif (((per.l(ad:0x42024000+0xD0)&0x40)==0x40)&&((per.l(ad:0x42024000+0xD0)&0x80)==0x00)) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "IF1,OF1" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif (((per.l(ad:0x42024000+0xD0)&0x40)==0x40)&&((per.l(ad:0x42024000+0xD0)&0x80)==0x80)) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" ",TxBufferEnable" newline bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" endif newline group.long 0xE4++0x0F line.long 0x00 "TSMA,Transmit Slot Mask Register A" bitfld.long 0x00 15. " TS[15] ,Transmit slot 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Transmit slot 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Transmit slot 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Transmit slot 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Transmit slot 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Transmit slot 10" "Disabled,Enabled" bitfld.long 0x00 9. " [09] ,Transmit slot 9" "Disabled,Enabled" bitfld.long 0x00 8. " [08] ,Transmit slot 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [07] ,Transmit slot 7" "Disabled,Enabled" bitfld.long 0x00 6. " [06] ,Transmit slot 6" "Disabled,Enabled" bitfld.long 0x00 5. " [05] ,Transmit slot 5" "Disabled,Enabled" bitfld.long 0x00 4. " [04] ,Transmit slot 4" "Disabled,Enabled" bitfld.long 0x00 3. " [03] ,Transmit slot 3" "Disabled,Enabled" bitfld.long 0x00 2. " [02] ,Transmit slot 2" "Disabled,Enabled" bitfld.long 0x00 1. " [01] ,Transmit slot 1" "Disabled,Enabled" bitfld.long 0x00 0. " [00] ,Transmit slot 0" "Disabled,Enabled" line.long 0x04 "TSMB,Transmit Slot Mask Register B" bitfld.long 0x04 15. " TS[31] ,Transmit slot 31" "Disabled,Enabled" bitfld.long 0x04 14. " [30] ,Transmit slot 30" "Disabled,Enabled" bitfld.long 0x04 13. " [29] ,Transmit slot 29" "Disabled,Enabled" bitfld.long 0x04 12. " [28] ,Transmit slot 28" "Disabled,Enabled" bitfld.long 0x04 11. " [27] ,Transmit slot 27" "Disabled,Enabled" bitfld.long 0x04 10. " [26] ,Transmit slot 26" "Disabled,Enabled" bitfld.long 0x04 9. " [25] ,Transmit slot 25" "Disabled,Enabled" bitfld.long 0x04 8. " [24] ,Transmit slot 24" "Disabled,Enabled" newline bitfld.long 0x04 7. " [23] ,Transmit slot 23" "Disabled,Enabled" bitfld.long 0x04 6. " [22] ,Transmit slot 22" "Disabled,Enabled" bitfld.long 0x04 5. " [21] ,Transmit slot 21" "Disabled,Enabled" bitfld.long 0x04 4. " [20] ,Transmit slot 20" "Disabled,Enabled" bitfld.long 0x04 3. " [19] ,Transmit slot 19" "Disabled,Enabled" bitfld.long 0x04 2. " [18] ,Transmit slot 18" "Disabled,Enabled" bitfld.long 0x04 1. " [17] ,Transmit slot 17" "Disabled,Enabled" bitfld.long 0x04 0. " [16] ,Transmit slot 16" "Disabled,Enabled" line.long 0x08 "RSMA,Receive Slot Mask Register A" bitfld.long 0x08 15. " RS[15] ,Receive slot 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Receive slot 14" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Receive slot 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Receive slot 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Receive slot 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Receive slot 10" "Disabled,Enabled" bitfld.long 0x08 9. " [09] ,Receive slot 9" "Disabled,Enabled" bitfld.long 0x08 8. " [08] ,Receive slot 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [07] ,Receive slot 7" "Disabled,Enabled" bitfld.long 0x08 6. " [06] ,Receive slot 6" "Disabled,Enabled" bitfld.long 0x08 5. " [05] ,Receive slot 5" "Disabled,Enabled" bitfld.long 0x08 4. " [04] ,Receive slot 4" "Disabled,Enabled" bitfld.long 0x08 3. " [03] ,Receive slot 3" "Disabled,Enabled" bitfld.long 0x08 2. " [02] ,Receive slot 2" "Disabled,Enabled" bitfld.long 0x08 1. " [01] ,Receive slot 1" "Disabled,Enabled" bitfld.long 0x08 0. " [00] ,Receive slot 0" "Disabled,Enabled" line.long 0x0C "RSMB,Receive Slot Mask Register B" bitfld.long 0x0C 15. " RS[31] ,Receive slot 31" "Disabled,Enabled" bitfld.long 0x0C 14. " [30] ,Receive slot 30" "Disabled,Enabled" bitfld.long 0x0C 13. " [29] ,Receive slot 29" "Disabled,Enabled" bitfld.long 0x0C 12. " [28] ,Receive slot 28" "Disabled,Enabled" bitfld.long 0x0C 11. " [27] ,Receive slot 27" "Disabled,Enabled" bitfld.long 0x0C 10. " [26] ,Receive slot 26" "Disabled,Enabled" bitfld.long 0x0C 9. " [25] ,Receive slot 25" "Disabled,Enabled" bitfld.long 0x0C 8. " [24] ,Receive slot 24" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [23] ,Receive slot 23" "Disabled,Enabled" bitfld.long 0x0C 6. " [22] ,Receive slot 22" "Disabled,Enabled" bitfld.long 0x0C 5. " [21] ,Receive slot 21" "Disabled,Enabled" bitfld.long 0x0C 4. " [20] ,Receive slot 20" "Disabled,Enabled" bitfld.long 0x0C 3. " [19] ,Receive slot 19" "Disabled,Enabled" bitfld.long 0x0C 2. " [18] ,Receive slot 18" "Disabled,Enabled" bitfld.long 0x0C 1. " [17] ,Receive slot 17" "Disabled,Enabled" bitfld.long 0x0C 0. " [16] ,Receive slot 16" "Disabled,Enabled" newline sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*") group.long 0xF4++0x03 line.long 0x00 "PDRC,Port C Data Register" bitfld.long 0x00 11. " PD[11] ,GPIO input/output reflection bit 11" "0,1" bitfld.long 0x00 10. " [10] ,GPIO input/output reflection bit 10" "0,1" bitfld.long 0x00 9. " [9] ,GPIO input/output reflection bit 9" "0,1" bitfld.long 0x00 8. " [8] ,GPIO input/output reflection bit 8" "0,1" bitfld.long 0x00 7. " [7] ,GPIO input/output reflection bit 7" "0,1" bitfld.long 0x00 6. " [6] ,GPIO input/output reflection bit 6" "0,1" bitfld.long 0x00 5. " [5] ,GPIO input/output reflection bit 5" "0,1" bitfld.long 0x00 4. " [4] ,GPIO input/output reflection bit 4" "0,1" bitfld.long 0x00 3. " [3] ,GPIO input/output reflection bit 3" "0,1" bitfld.long 0x00 2. " [2] ,GPIO input/output reflection bit 2" "0,1" bitfld.long 0x00 1. " [1] ,GPIO input/output reflection bit 1" "0,1" bitfld.long 0x00 0. " [0] ,GPIO input/output reflection bit 0" "0,1" endif group.long 0xF8++0x07 line.long 0x00 "PRRC,Port C Direction Register" bitfld.long 0x00 11. " PDC[11] ,Port C direction pin 11" "0,1" bitfld.long 0x00 10. " [10] ,Port C direction pin 10" "0,1" bitfld.long 0x00 9. " [9] ,Port C direction pin 9" "0,1" bitfld.long 0x00 8. " [8] ,Port C direction pin 8" "0,1" bitfld.long 0x00 7. " [7] ,Port C direction pin 7" "0,1" bitfld.long 0x00 6. " [6] ,Port C direction pin 6" "0,1" bitfld.long 0x00 5. " [5] ,Port C direction pin 5" "0,1" bitfld.long 0x00 4. " [4] ,Port C direction pin 4" "0,1" bitfld.long 0x00 3. " [3] ,Port C direction pin 3" "0,1" bitfld.long 0x00 2. " [2] ,Port C direction pin 2" "0,1" bitfld.long 0x00 1. " [1] ,Port C direction pin 1" "0,1" bitfld.long 0x00 0. " [0] ,Port C direction pin 0" "0,1" line.long 0x04 "PCRC,Port C Control Register" bitfld.long 0x04 11. " PC[11] ,Port C control pin 11" "0,1" bitfld.long 0x04 10. " [10] ,Port C control pin 10" "0,1" bitfld.long 0x04 9. " [9] ,Port C control pin 9" "0,1" bitfld.long 0x04 8. " [8] ,Port C control pin 8" "0,1" bitfld.long 0x04 7. " [7] ,Port C control pin 7" "0,1" bitfld.long 0x04 6. " [6] ,Port C control pin 6" "0,1" bitfld.long 0x04 5. " [5] ,Port C control pin 5" "0,1" bitfld.long 0x04 4. " [4] ,Port C control pin 4" "0,1" bitfld.long 0x04 3. " [3] ,Port C control pin 3" "0,1" bitfld.long 0x04 2. " [2] ,Port C control pin 2" "0,1" bitfld.long 0x04 1. " [1] ,Port C control pin 1" "0,1" bitfld.long 0x04 0. " [0] ,Port C control pin 0" "0,1" width 0x0B endif tree.end tree "FlexCAN (Flexible Controller Area Network)" tree "FlexCAN 1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02090000 width 16. group.long 0x00++0x0B line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,FLEXCAN disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at ARM level" "Freeze Mode,Not Freeze Mode" bitfld.long 0x00 29. " RFEN ,Rx FIFO feature" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Freeze Mode" "Not requested,Entered" textline " " rbitfld.long 0x00 27. " NOT_RDY ,FLEXCAN current mode" "Disable/Stop/Freeze,Normal/Listen-Only/Loop-Back" bitfld.long 0x00 26. " WAK_MSK ,Wake Up Interrupt generation" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,FLEXCAN registers reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped" "Not in Freeze mode,In Freeze mode" textline " " bitfld.long 0x00 23. " SUPV ,This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode" "User,Supervisor" bitfld.long 0x00 22. " SLF_WAK ,FLEXCAN Self Wake Up feature" "Disabled,Enabled" bitfld.long 0x00 21. " WRN_EN ,TWRN_INT and RWRN_INT flags generation in the Error and Status Register" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,FLEXCAN low power mode" "None,Disable/Stop" textline " " bitfld.long 0x00 19. " WAK_SRC ,Low-pass filter to protect the FLEXCAN_RX input from spurious wake up" "Disabled,Enabled" bitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "Enabled,Disabled" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue feature" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIO_EN ,Local Priority" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,Tx abort feature" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,The format of the elements of the Rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,The number of the last Message Buffers that will take part in the matching and arbitration processes" line.long 0x04 "CTRL1,Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Ratio between the PE clock frequency and the Serial Clock frequency" bitfld.long 0x04 22.--23. " RJW ,Maximum number of time quanta that a bit time can be changed by one resynchronization" "0,1,2,3" bitfld.long 0x04 19.--21. " PSEG1 ,Length of Phase Buffer Segment 1 in the bit time" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PSEG2 ,Length of Phase Buffer Segment 2 in the bit time" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 15. " BOFF_MSK ,Bus Off Interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " ERR_MSK ,Error Interrupt" "Disabled,Enabled" bitfld.long 0x04 12. " LPB ,Loop-Back Mode" "Disabled,Enabled" bitfld.long 0x04 11. " TWRN_MSK ,Tx Warning Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " RWRN_MSK ,Rx Warning Interrupt" "Disabled,Enabled" bitfld.long 0x04 7. " SMP ,Sampling mode of CAN bits at the FLEXCAN_RX" "1 sample/bit,3 samples/bit" bitfld.long 0x04 6. " BOFF_REC ,FLEXCAN automatic recovery from Bus Off state" "Enabled,Disabled" bitfld.long 0x04 5. " TSYN ,Mechanism that resets the free-running timer each time a message is received in Message Buffer 0" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " LBUF ,Ordering mechanism for Message Buffer transmission" "Highest priority,Lowest number" bitfld.long 0x04 3. " LOM ,Listen Only Mode" "Disabled,Enabled" bitfld.long 0x04 0.--2. " PROP_SEG ,Length of the Propagation Segment in the bit time" "0,1,2,3,4,5,6,7" line.long 0x08 "TIMER,Control 1 Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Timer value" textline " " group.long 0x10++0x27 line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG31 ,Mailbox filter 31 mask" "Masked,Not masked" bitfld.long 0x00 30. " MG30 ,Mailbox filter 30 mask" "Masked,Not masked" bitfld.long 0x00 29. " MG29 ,Mailbox filter 29 mask" "Masked,Not masked" bitfld.long 0x00 28. " MG28 ,Mailbox filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MG27 ,Mailbox filter 27 mask" "Masked,Not masked" bitfld.long 0x00 26. " MG26 ,Mailbox filter 26 mask" "Masked,Not masked" bitfld.long 0x00 25. " MG25 ,Mailbox filter 25 mask" "Masked,Not masked" bitfld.long 0x00 24. " MG24 ,Mailbox filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MG23 ,Mailbox filter 23 mask" "Masked,Not masked" bitfld.long 0x00 22. " MG22 ,Mailbox filter 22 mask" "Masked,Not masked" bitfld.long 0x00 21. " MG21 ,Mailbox filter 21 mask" "Masked,Not masked" bitfld.long 0x00 20. " MG20 ,Mailbox filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MG19 ,Mailbox filter 19 mask" "Masked,Not masked" bitfld.long 0x00 18. " MG18 ,Mailbox filter 18 mask" "Masked,Not masked" bitfld.long 0x00 17. " MG17 ,Mailbox filter 17 mask" "Masked,Not masked" bitfld.long 0x00 16. " MG16 ,Mailbox filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MG15 ,Mailbox filter 15 mask" "Masked,Not masked" bitfld.long 0x00 14. " MG14 ,Mailbox filter 14 mask" "Masked,Not masked" bitfld.long 0x00 13. " MG13 ,Mailbox filter 13 mask" "Masked,Not masked" bitfld.long 0x00 12. " MG12 ,Mailbox filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MG11 ,Mailbox filter 11 mask" "Masked,Not masked" bitfld.long 0x00 10. " MG10 ,Mailbox filter 10 mask" "Masked,Not masked" bitfld.long 0x00 9. " MG9 ,Mailbox filter 9 mask" "Masked,Not masked" bitfld.long 0x00 8. " MG8 ,Mailbox filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MG7 ,Mailbox filter 7 mask" "Masked,Not masked" bitfld.long 0x00 6. " MG6 ,Mailbox filter 6 mask" "Masked,Not masked" bitfld.long 0x00 5. " MG5 ,Mailbox filter 5 mask" "Masked,Not masked" bitfld.long 0x00 4. " MG4 ,Mailbox filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MG3 ,Mailbox filter 3 mask" "Masked,Not masked" bitfld.long 0x00 2. " MG2 ,Mailbox filter 2 mask" "Masked,Not masked" bitfld.long 0x00 1. " MG1 ,Mailbox filter 1 mask" "Masked,Not masked" bitfld.long 0x00 0. " MG0 ,Mailbox filter 0 mask" "Masked,Not masked" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Mailbox 14 filter 31 mask" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Mailbox 14 filter 30 mask" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Mailbox 14 filter 29 mask" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Mailbox 14 filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Mailbox 14 filter 27 mask" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Mailbox 14 filter 26 mask" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Mailbox 14 filter 25 mask" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Mailbox 14 filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Mailbox 14 filter 23 mask" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Mailbox 14 filter 22 mask" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Mailbox 14 filter 21 mask" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Mailbox 14 filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Mailbox 14 filter 19 mask" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Mailbox 14 filter 18 mask" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Mailbox 14 filter 17 mask" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Mailbox 14 filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Mailbox 14 filter 15 mask" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Mailbox 14 filter 14 mask" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Mailbox 14 filter 13 mask" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Mailbox 14 filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Mailbox 14 filter 11 mask" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Mailbox 14 filter 10 mask" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Mailbox 14 filter 9 mask" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Mailbox 14 filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Mailbox 14 filter 7 mask" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Mailbox 14 filter 6 mask" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Mailbox 14 filter 5 mask" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Mailbox 14 filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Mailbox 14 filter 3 mask" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Mailbox 14 filter 2 mask" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Mailbox 14 filter 1 mask" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Mailbox 14 filter 0 mask" "Masked,Not masked" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Mailbox 15 filter 31 mask" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Mailbox 15 filter 30 mask" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Mailbox 15 filter 29 mask" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Mailbox 15 filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Mailbox 15 filter 27 mask" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Mailbox 15 filter 26 mask" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Mailbox 15 filter 25 mask" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Mailbox 15 filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Mailbox 15 filter 23 mask" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Mailbox 15 filter 22 mask" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Mailbox 15 filter 21 mask" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Mailbox 15 filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Mailbox 15 filter 19 mask" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Mailbox 15 filter 18 mask" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Mailbox 15 filter 17 mask" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Mailbox 15 filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Mailbox 15 filter 15 mask" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Mailbox 15 filter 14 mask" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Mailbox 15 filter 13 mask" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Mailbox 15 filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Mailbox 15 filter 11 mask" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Mailbox 15 filter 10 mask" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Mailbox 15 filter 9 mask" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Mailbox 15 filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Mailbox 15 filter 7 mask" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Mailbox 15 filter 6 mask" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Mailbox 15 filter 5 mask" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Mailbox 15 filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Mailbox 15 filter 3 mask" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Mailbox 15 filter 2 mask" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Mailbox 15 filter 1 mask" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Mailbox 15 filter 0 mask" "Masked,Not masked" textline "" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " Rx_Err_Counter ,Receiver Error Counter" hexmask.long.byte 0x0C 0.--7. 1. " Tx_Err_Counter ,Transmitter Error Counter" line.long 0x10 "ESR1,Error and Status 1 Register" rbitfld.long 0x10 18. " SYNCH ,Synchronization between FLEXCAN and CAN bus" "Not synchronized,Synchronized" bitfld.long 0x10 17. " TWRN_INT ,Tx error counter transition from < 96 to >= 96" "Not occurred,Occurred" bitfld.long 0x10 16. " RWRN_INT ,Rx error counter transition from < 96 to >= 96" "Not occurred,Occurred" bitfld.long 0x10 15. " BIT1_ERR ,Inconsistency between the transmitted and the received bit in a message" "No error,Error" textline " " bitfld.long 0x10 14. " BIT0_ERR ,Inconsistency between the transmitted and the received bit in a message" "No error,Error" bitfld.long 0x10 13. " ACK_ERR ,Acknowledge Error detection by the transmitter node" "No error,Error" bitfld.long 0x10 12. " CRC_ERR ,CRC Error detection by the receiver node" "No error,Error" bitfld.long 0x10 11. " FRM_ERR ,Form Error detection by the receiver node" "No error,Error" textline " " bitfld.long 0x10 10. " STF_ERR ,Stuffing Error detection" "No error,Error" bitfld.long 0x10 9. " TX_WRN ,Repetitive errors during message transmission >= 96" "Not occurred,Occurred" bitfld.long 0x10 8. " RX_WRN ,Repetitive errors during message reception >= 96" "Not occurred,Occurred" bitfld.long 0x10 7. " IDLE ,IDLE state" "Not IDLE,IDLE" textline " " bitfld.long 0x10 6. " TX ,FLEXCAN message" "Receiving,Transmitting" bitfld.long 0x10 4.--5. " FLT_CONF ,Confinement State of the FLEXCAN module" "Error Active,Error Passive,Bus off,Bus off" bitfld.long 0x10 3. " RX ,FLEXCAN message" "Receiving,Transmitting" bitfld.long 0x10 2. " BOFF_INT ,FLEXCAN enters 'Bus Off' state" "Not occurred,Occurred" textline " " bitfld.long 0x10 1. " ERR_INT ,At least one of the Error Bits is set" "Not occurred,Occurred" bitfld.long 0x10 0. " WAK_INT ,Recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode" "Not occurred,Occurred" textline " " line.long 0x14 "IMASK2,Interrupt Masks 2 Register" bitfld.long 0x14 31. " BUF_M[63] ,FLEXCAN Message Buffer 63 Enable" "Disabled,Enabled" bitfld.long 0x14 30. " [62] ,FLEXCAN Message Buffer 62 Enable" "Disabled,Enabled" bitfld.long 0x14 29. " [61] ,FLEXCAN Message Buffer 61 Enable" "Disabled,Enabled" bitfld.long 0x14 28. " [60] ,FLEXCAN Message Buffer 60 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " [59] ,FLEXCAN Message Buffer 59 Enable" "Disabled,Enabled" bitfld.long 0x14 26. " [58] ,FLEXCAN Message Buffer 58 Enable" "Disabled,Enabled" bitfld.long 0x14 25. " [57] ,FLEXCAN Message Buffer 57 Enable" "Disabled,Enabled" bitfld.long 0x14 24. " [56] ,FLEXCAN Message Buffer 56 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " [55] ,FLEXCAN Message Buffer 55 Enable" "Disabled,Enabled" bitfld.long 0x14 22. " [54] ,FLEXCAN Message Buffer 54 Enable" "Disabled,Enabled" bitfld.long 0x14 21. " [53] ,FLEXCAN Message Buffer 53 Enable" "Disabled,Enabled" bitfld.long 0x14 20. " [52] ,FLEXCAN Message Buffer 52 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " [51] ,FLEXCAN Message Buffer 51 Enable" "Disabled,Enabled" bitfld.long 0x14 18. " [50] ,FLEXCAN Message Buffer 50 Enable" "Disabled,Enabled" bitfld.long 0x14 17. " [49] ,FLEXCAN Message Buffer 49 Enable" "Disabled,Enabled" bitfld.long 0x14 16. " [48] ,FLEXCAN Message Buffer 48 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " [47] ,FLEXCAN Message Buffer 47 Enable" "Disabled,Enabled" bitfld.long 0x14 14. " [46] ,FLEXCAN Message Buffer 46 Enable" "Disabled,Enabled" bitfld.long 0x14 13. " [45] ,FLEXCAN Message Buffer 45 Enable" "Disabled,Enabled" bitfld.long 0x14 12. " [44] ,FLEXCAN Message Buffer 44 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " [43] ,FLEXCAN Message Buffer 43 Enable" "Disabled,Enabled" bitfld.long 0x14 10. " [42] ,FLEXCAN Message Buffer 42 Enable" "Disabled,Enabled" bitfld.long 0x14 9. " [41] ,FLEXCAN Message Buffer 41 Enable" "Disabled,Enabled" bitfld.long 0x14 8. " [40] ,FLEXCAN Message Buffer 40 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " [39] ,FLEXCAN Message Buffer 39 Enable" "Disabled,Enabled" bitfld.long 0x14 6. " [38] ,FLEXCAN Message Buffer 38 Enable" "Disabled,Enabled" bitfld.long 0x14 5. " [37] ,FLEXCAN Message Buffer 37 Enable" "Disabled,Enabled" bitfld.long 0x14 4. " [36] ,FLEXCAN Message Buffer 36 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " [35] ,FLEXCAN Message Buffer 35 Enable" "Disabled,Enabled" bitfld.long 0x14 2. " [34] ,FLEXCAN Message Buffer 34 Enable" "Disabled,Enabled" bitfld.long 0x14 1. " [33] ,FLEXCAN Message Buffer 33 Enable" "Disabled,Enabled" bitfld.long 0x14 0. " [32] ,FLEXCAN Message Buffer 32 Enable" "Disabled,Enabled" line.long 0x18 "IMASK1,Interrupt Masks 1 Register" bitfld.long 0x18 31. " [31] ,FLEXCAN Message Buffer 31 Enable" "Disabled,Enabled" bitfld.long 0x18 30. " [30] ,FLEXCAN Message Buffer 30 Enable" "Disabled,Enabled" bitfld.long 0x18 29. " [29] ,FLEXCAN Message Buffer 29 Enable" "Disabled,Enabled" bitfld.long 0x18 28. " [28] ,FLEXCAN Message Buffer 28 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 27. " [27] ,FLEXCAN Message Buffer 27 Enable" "Disabled,Enabled" bitfld.long 0x18 26. " [26] ,FLEXCAN Message Buffer 26 Enable" "Disabled,Enabled" bitfld.long 0x18 25. " [25] ,FLEXCAN Message Buffer 25 Enable" "Disabled,Enabled" bitfld.long 0x18 24. " [24] ,FLEXCAN Message Buffer 24 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 23. " [23] ,FLEXCAN Message Buffer 23 Enable" "Disabled,Enabled" bitfld.long 0x18 22. " [22] ,FLEXCAN Message Buffer 22 Enable" "Disabled,Enabled" bitfld.long 0x18 21. " [21] ,FLEXCAN Message Buffer 21 Enable" "Disabled,Enabled" bitfld.long 0x18 20. " [20] ,FLEXCAN Message Buffer 20 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 19. " [19] ,FLEXCAN Message Buffer 19 Enable" "Disabled,Enabled" bitfld.long 0x18 18. " [18] ,FLEXCAN Message Buffer 18 Enable" "Disabled,Enabled" bitfld.long 0x18 17. " [17] ,FLEXCAN Message Buffer 17 Enable" "Disabled,Enabled" bitfld.long 0x18 16. " [16] ,FLEXCAN Message Buffer 16 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 15. " [15] ,FLEXCAN Message Buffer 15 Enable" "Disabled,Enabled" bitfld.long 0x18 14. " [14] ,FLEXCAN Message Buffer 14 Enable" "Disabled,Enabled" bitfld.long 0x18 13. " [13] ,FLEXCAN Message Buffer 13 Enable" "Disabled,Enabled" bitfld.long 0x18 12. " [12] ,FLEXCAN Message Buffer 12 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " [11] ,FLEXCAN Message Buffer 11 Enable" "Disabled,Enabled" bitfld.long 0x18 10. " [10] ,FLEXCAN Message Buffer 10 Enable" "Disabled,Enabled" bitfld.long 0x18 9. " [9] ,FLEXCAN Message Buffer 9 Enable" "Disabled,Enabled" bitfld.long 0x18 8. " [8] ,FLEXCAN Message Buffer 8 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 7. " [7] ,FLEXCAN Message Buffer 7 Enable" "Disabled,Enabled" bitfld.long 0x18 6. " [6] ,FLEXCAN Message Buffer 6 Enable" "Disabled,Enabled" bitfld.long 0x18 5. " [5] ,FLEXCAN Message Buffer 5 Enable" "Disabled,Enabled" bitfld.long 0x18 4. " [4] ,FLEXCAN Message Buffer 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " [3] ,FLEXCAN Message Buffer 3 Enable" "Disabled,Enabled" bitfld.long 0x18 2. " [2] ,FLEXCAN Message Buffer 2 Enable" "Disabled,Enabled" bitfld.long 0x18 1. " [1] ,FLEXCAN Message Buffer 1 Enable" "Disabled,Enabled" bitfld.long 0x18 0. " [0] ,FLEXCAN Message Buffer 0 Enable" "Disabled,Enabled" textline " " line.long 0x1C "IFLAG2,Interrupt Flags 2 Register" bitfld.long 0x1C 31. " BUF_I[63] ,FLEXCAN Message Buffer 63 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 30. " [62] ,FLEXCAN Message Buffer 62 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 29. " [61] ,FLEXCAN Message Buffer 61 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 28. " [60] ,FLEXCAN Message Buffer 60 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 27. " [59] ,FLEXCAN Message Buffer 59 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 26. " [58] ,FLEXCAN Message Buffer 58 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 25. " [57] ,FLEXCAN Message Buffer 57 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 24. " [56] ,FLEXCAN Message Buffer 56 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 23. " [55] ,FLEXCAN Message Buffer 55 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 22. " [54] ,FLEXCAN Message Buffer 54 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 21. " [53] ,FLEXCAN Message Buffer 53 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 20. " [52] ,FLEXCAN Message Buffer 52 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 19. " [51] ,FLEXCAN Message Buffer 51 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 18. " [50] ,FLEXCAN Message Buffer 50 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 17. " [49] ,FLEXCAN Message Buffer 49 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 16. " [48] ,FLEXCAN Message Buffer 48 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 15. " [47] ,FLEXCAN Message Buffer 47 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 14. " [46] ,FLEXCAN Message Buffer 46 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 13. " [45] ,FLEXCAN Message Buffer 45 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 12. " [44] ,FLEXCAN Message Buffer 44 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " [43] ,FLEXCAN Message Buffer 43 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 10. " [42] ,FLEXCAN Message Buffer 42 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 9. " [41] ,FLEXCAN Message Buffer 41 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 8. " [40] ,FLEXCAN Message Buffer 40 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 7. " [39] ,FLEXCAN Message Buffer 39 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 6. " [38] ,FLEXCAN Message Buffer 38 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 5. " [37] ,FLEXCAN Message Buffer 37 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 4. " [36] ,FLEXCAN Message Buffer 36 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 3. " [35] ,FLEXCAN Message Buffer 35 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 2. " [34] ,FLEXCAN Message Buffer 34 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 1. " [33] ,FLEXCAN Message Buffer 33 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 0. " [32] ,FLEXCAN Message Buffer 32 Interrupt" "Disabled,Enabled" line.long 0x20 "IFLAG1,Interrupt Flags 1 Register" bitfld.long 0x20 31. " [31] ,FLEXCAN Message Buffer 31 Interrupt" "Disabled,Enabled" bitfld.long 0x20 30. " [30] ,FLEXCAN Message Buffer 30 Interrupt" "Disabled,Enabled" bitfld.long 0x20 29. " [29] ,FLEXCAN Message Buffer 29 Interrupt" "Disabled,Enabled" bitfld.long 0x20 28. " [28] ,FLEXCAN Message Buffer 28 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 27. " [27] ,FLEXCAN Message Buffer 27 Interrupt" "Disabled,Enabled" bitfld.long 0x20 26. " [26] ,FLEXCAN Message Buffer 26 Interrupt" "Disabled,Enabled" bitfld.long 0x20 25. " [25] ,FLEXCAN Message Buffer 25 Interrupt" "Disabled,Enabled" bitfld.long 0x20 24. " [24] ,FLEXCAN Message Buffer 24 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 23. " [23] ,FLEXCAN Message Buffer 23 Interrupt" "Disabled,Enabled" bitfld.long 0x20 22. " [22] ,FLEXCAN Message Buffer 22 Interrupt" "Disabled,Enabled" bitfld.long 0x20 21. " [21] ,FLEXCAN Message Buffer 21 Interrupt" "Disabled,Enabled" bitfld.long 0x20 20. " [20] ,FLEXCAN Message Buffer 20 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " [19] ,FLEXCAN Message Buffer 19 Interrupt" "Disabled,Enabled" bitfld.long 0x20 18. " [18] ,FLEXCAN Message Buffer 18 Interrupt" "Disabled,Enabled" bitfld.long 0x20 17. " [17] ,FLEXCAN Message Buffer 17 Interrupt" "Disabled,Enabled" bitfld.long 0x20 16. " [16] ,FLEXCAN Message Buffer 16 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " [15] ,FLEXCAN Message Buffer 15 Interrupt" "Disabled,Enabled" bitfld.long 0x20 14. " [14] ,FLEXCAN Message Buffer 14 Interrupt" "Disabled,Enabled" bitfld.long 0x20 13. " [13] ,FLEXCAN Message Buffer 13 Interrupt" "Disabled,Enabled" bitfld.long 0x20 12. " [12] ,FLEXCAN Message Buffer 12 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " [11] ,FLEXCAN Message Buffer 11 Interrupt" "Disabled,Enabled" bitfld.long 0x20 10. " [10] ,FLEXCAN Message Buffer 10 Interrupt" "Disabled,Enabled" bitfld.long 0x20 9. " [9] ,FLEXCAN Message Buffer 9 Interrupt" "Disabled,Enabled" bitfld.long 0x20 8. " [8] ,FLEXCAN Message Buffer 8 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " [7] ,FLEXCAN Message Buffer 7 Interrupt" "Disabled,Enabled" bitfld.long 0x20 6. " [6] ,FLEXCAN Message Buffer 6 Interrupt" "Disabled,Enabled" bitfld.long 0x20 5. " [5] ,FLEXCAN Message Buffer 5 Interrupt" "Disabled,Enabled" bitfld.long 0x20 4. " [4] ,FLEXCAN Message Buffer 4 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 3. " [3] ,FLEXCAN Message Buffer 3 Interrupt" "Disabled,Enabled" bitfld.long 0x20 2. " [2] ,FLEXCAN Message Buffer 2 Interrupt" "Disabled,Enabled" bitfld.long 0x20 1. " [1] ,FLEXCAN Message Buffer 1 Interrupt" "Disabled,Enabled" bitfld.long 0x20 0. " [0] ,FLEXCAN Message Buffer 0 Interrupt" "Disabled,Enabled" textline " " textline "" line.long 0x24 "CTRL2,Control 2 Register" bitfld.long 0x24 28. " WRMFRZ ,Unrestricted write access to FlexCAN memory" "Restricted,Unrestricted" bitfld.long 0x24 24.--27. " RFEN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x24 19.--23. " TASD ,Number of CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 18. " MRP ,Set the matching process start" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x24 17. " RRS ,Remote Request Frame" "Generated,Stored" bitfld.long 0x24 16. " EACEN ,Comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process" "Both compared,IDE only" rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest number inactive Mailbox" bitfld.long 0x00 14. " VPS ,This bit indicates whether IMB and LPTM contents are currently valid or not" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Indicates if any Mailbox is inactive" "No,Yes" textline " " rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,Number of the Mailbox corresponding to the value in TXCRC field" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC value of the last message transmitted" textline " " if ((per.l(ad:0x02090000)&0x01000000)==0x01000000) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" else rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" endif rgroup.long 0x4C++0x03 line.long 0x00 "RXFIR,Rx FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ,Identifier Acceptance Filter hit by the received message that is in the output of the Rx FIFO" group.long 0x880++0x03 line.long 0x00 "RXIMR0_RXIMR63,Rx FIFO Information Register" bitfld.long 0x00 31. " MI[31] ,Mailbox filter 31 and Rx FIFO ID Filter 31 maks" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 and Rx FIFO ID Filter 30 maks" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 and Rx FIFO ID Filter 29 maks" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 and Rx FIFO ID Filter 28 maks" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Mailbox filter 27 and Rx FIFO ID Filter 27 maks" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 and Rx FIFO ID Filter 26 maks" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 and Rx FIFO ID Filter 25 maks" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 and Rx FIFO ID Filter 24 maks" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Mailbox filter 23 and Rx FIFO ID Filter 23 maks" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 and Rx FIFO ID Filter 22 maks" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 and Rx FIFO ID Filter 21 maks" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 and Rx FIFO ID Filter 20 maks" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Mailbox filter 19 and Rx FIFO ID Filter 19 maks" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 and Rx FIFO ID Filter 18 maks" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 and Rx FIFO ID Filter 17 maks" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 and Rx FIFO ID Filter 16 maks" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Mailbox filter 15 and Rx FIFO ID Filter 15 maks" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 and Rx FIFO ID Filter 14 maks" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 and Rx FIFO ID Filter 13 maks" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 and Rx FIFO ID Filter 12 maks" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Mailbox filter 11 and Rx FIFO ID Filter 11 maks" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 and Rx FIFO ID Filter 10 maks" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 and Rx FIFO ID Filter 9 maks" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 and Rx FIFO ID Filter 8 maks" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Mailbox filter 7 and Rx FIFO ID Filter 7 maks" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 and Rx FIFO ID Filter 6 maks" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 and Rx FIFO ID Filter 5 maks" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 and Rx FIFO ID Filter 4 maks" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Mailbox filter 3 and Rx FIFO ID Filter 3 maks" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 and Rx FIFO ID Filter 2 maks" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 and Rx FIFO ID Filter 1 maks" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 and Rx FIFO ID Filter 0 maks" "Masked,Not masked" group.long 0x9E0++0x03 line.long 0x00 "GFWR,Glitch Filter Width Registers" hexmask.long.byte 0x00 0.--7. 1. " GFWR ,Determines the Glitch Filter Width" width 0x0b else base ad:0x42090000 width 16. group.long 0x00++0x0B line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,FLEXCAN disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at ARM level" "Freeze Mode,Not Freeze Mode" bitfld.long 0x00 29. " RFEN ,Rx FIFO feature" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Freeze Mode" "Not requested,Entered" textline " " rbitfld.long 0x00 27. " NOT_RDY ,FLEXCAN current mode" "Disable/Stop/Freeze,Normal/Listen-Only/Loop-Back" bitfld.long 0x00 26. " WAK_MSK ,Wake Up Interrupt generation" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,FLEXCAN registers reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped" "Not in Freeze mode,In Freeze mode" textline " " bitfld.long 0x00 23. " SUPV ,This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode" "User,Supervisor" bitfld.long 0x00 22. " SLF_WAK ,FLEXCAN Self Wake Up feature" "Disabled,Enabled" bitfld.long 0x00 21. " WRN_EN ,TWRN_INT and RWRN_INT flags generation in the Error and Status Register" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,FLEXCAN low power mode" "None,Disable/Stop" textline " " bitfld.long 0x00 19. " WAK_SRC ,Low-pass filter to protect the FLEXCAN_RX input from spurious wake up" "Disabled,Enabled" bitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "Enabled,Disabled" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue feature" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIO_EN ,Local Priority" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,Tx abort feature" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,The format of the elements of the Rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,The number of the last Message Buffers that will take part in the matching and arbitration processes" line.long 0x04 "CTRL1,Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Ratio between the PE clock frequency and the Serial Clock frequency" bitfld.long 0x04 22.--23. " RJW ,Maximum number of time quanta that a bit time can be changed by one resynchronization" "0,1,2,3" bitfld.long 0x04 19.--21. " PSEG1 ,Length of Phase Buffer Segment 1 in the bit time" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PSEG2 ,Length of Phase Buffer Segment 2 in the bit time" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 15. " BOFF_MSK ,Bus Off Interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " ERR_MSK ,Error Interrupt" "Disabled,Enabled" bitfld.long 0x04 12. " LPB ,Loop-Back Mode" "Disabled,Enabled" bitfld.long 0x04 11. " TWRN_MSK ,Tx Warning Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " RWRN_MSK ,Rx Warning Interrupt" "Disabled,Enabled" bitfld.long 0x04 7. " SMP ,Sampling mode of CAN bits at the FLEXCAN_RX" "1 sample/bit,3 samples/bit" bitfld.long 0x04 6. " BOFF_REC ,FLEXCAN automatic recovery from Bus Off state" "Enabled,Disabled" bitfld.long 0x04 5. " TSYN ,Mechanism that resets the free-running timer each time a message is received in Message Buffer 0" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " LBUF ,Ordering mechanism for Message Buffer transmission" "Highest priority,Lowest number" bitfld.long 0x04 3. " LOM ,Listen Only Mode" "Disabled,Enabled" bitfld.long 0x04 0.--2. " PROP_SEG ,Length of the Propagation Segment in the bit time" "0,1,2,3,4,5,6,7" line.long 0x08 "TIMER,Control 1 Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Timer value" textline " " group.long 0x10++0x27 line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG31 ,Mailbox filter 31 mask" "Masked,Not masked" bitfld.long 0x00 30. " MG30 ,Mailbox filter 30 mask" "Masked,Not masked" bitfld.long 0x00 29. " MG29 ,Mailbox filter 29 mask" "Masked,Not masked" bitfld.long 0x00 28. " MG28 ,Mailbox filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MG27 ,Mailbox filter 27 mask" "Masked,Not masked" bitfld.long 0x00 26. " MG26 ,Mailbox filter 26 mask" "Masked,Not masked" bitfld.long 0x00 25. " MG25 ,Mailbox filter 25 mask" "Masked,Not masked" bitfld.long 0x00 24. " MG24 ,Mailbox filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MG23 ,Mailbox filter 23 mask" "Masked,Not masked" bitfld.long 0x00 22. " MG22 ,Mailbox filter 22 mask" "Masked,Not masked" bitfld.long 0x00 21. " MG21 ,Mailbox filter 21 mask" "Masked,Not masked" bitfld.long 0x00 20. " MG20 ,Mailbox filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MG19 ,Mailbox filter 19 mask" "Masked,Not masked" bitfld.long 0x00 18. " MG18 ,Mailbox filter 18 mask" "Masked,Not masked" bitfld.long 0x00 17. " MG17 ,Mailbox filter 17 mask" "Masked,Not masked" bitfld.long 0x00 16. " MG16 ,Mailbox filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MG15 ,Mailbox filter 15 mask" "Masked,Not masked" bitfld.long 0x00 14. " MG14 ,Mailbox filter 14 mask" "Masked,Not masked" bitfld.long 0x00 13. " MG13 ,Mailbox filter 13 mask" "Masked,Not masked" bitfld.long 0x00 12. " MG12 ,Mailbox filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MG11 ,Mailbox filter 11 mask" "Masked,Not masked" bitfld.long 0x00 10. " MG10 ,Mailbox filter 10 mask" "Masked,Not masked" bitfld.long 0x00 9. " MG9 ,Mailbox filter 9 mask" "Masked,Not masked" bitfld.long 0x00 8. " MG8 ,Mailbox filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MG7 ,Mailbox filter 7 mask" "Masked,Not masked" bitfld.long 0x00 6. " MG6 ,Mailbox filter 6 mask" "Masked,Not masked" bitfld.long 0x00 5. " MG5 ,Mailbox filter 5 mask" "Masked,Not masked" bitfld.long 0x00 4. " MG4 ,Mailbox filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MG3 ,Mailbox filter 3 mask" "Masked,Not masked" bitfld.long 0x00 2. " MG2 ,Mailbox filter 2 mask" "Masked,Not masked" bitfld.long 0x00 1. " MG1 ,Mailbox filter 1 mask" "Masked,Not masked" bitfld.long 0x00 0. " MG0 ,Mailbox filter 0 mask" "Masked,Not masked" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Mailbox 14 filter 31 mask" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Mailbox 14 filter 30 mask" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Mailbox 14 filter 29 mask" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Mailbox 14 filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Mailbox 14 filter 27 mask" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Mailbox 14 filter 26 mask" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Mailbox 14 filter 25 mask" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Mailbox 14 filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Mailbox 14 filter 23 mask" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Mailbox 14 filter 22 mask" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Mailbox 14 filter 21 mask" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Mailbox 14 filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Mailbox 14 filter 19 mask" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Mailbox 14 filter 18 mask" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Mailbox 14 filter 17 mask" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Mailbox 14 filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Mailbox 14 filter 15 mask" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Mailbox 14 filter 14 mask" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Mailbox 14 filter 13 mask" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Mailbox 14 filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Mailbox 14 filter 11 mask" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Mailbox 14 filter 10 mask" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Mailbox 14 filter 9 mask" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Mailbox 14 filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Mailbox 14 filter 7 mask" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Mailbox 14 filter 6 mask" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Mailbox 14 filter 5 mask" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Mailbox 14 filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Mailbox 14 filter 3 mask" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Mailbox 14 filter 2 mask" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Mailbox 14 filter 1 mask" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Mailbox 14 filter 0 mask" "Masked,Not masked" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Mailbox 15 filter 31 mask" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Mailbox 15 filter 30 mask" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Mailbox 15 filter 29 mask" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Mailbox 15 filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Mailbox 15 filter 27 mask" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Mailbox 15 filter 26 mask" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Mailbox 15 filter 25 mask" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Mailbox 15 filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Mailbox 15 filter 23 mask" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Mailbox 15 filter 22 mask" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Mailbox 15 filter 21 mask" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Mailbox 15 filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Mailbox 15 filter 19 mask" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Mailbox 15 filter 18 mask" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Mailbox 15 filter 17 mask" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Mailbox 15 filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Mailbox 15 filter 15 mask" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Mailbox 15 filter 14 mask" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Mailbox 15 filter 13 mask" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Mailbox 15 filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Mailbox 15 filter 11 mask" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Mailbox 15 filter 10 mask" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Mailbox 15 filter 9 mask" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Mailbox 15 filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Mailbox 15 filter 7 mask" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Mailbox 15 filter 6 mask" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Mailbox 15 filter 5 mask" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Mailbox 15 filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Mailbox 15 filter 3 mask" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Mailbox 15 filter 2 mask" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Mailbox 15 filter 1 mask" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Mailbox 15 filter 0 mask" "Masked,Not masked" textline "" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " Rx_Err_Counter ,Receiver Error Counter" hexmask.long.byte 0x0C 0.--7. 1. " Tx_Err_Counter ,Transmitter Error Counter" line.long 0x10 "ESR1,Error and Status 1 Register" rbitfld.long 0x10 18. " SYNCH ,Synchronization between FLEXCAN and CAN bus" "Not synchronized,Synchronized" bitfld.long 0x10 17. " TWRN_INT ,Tx error counter transition from < 96 to >= 96" "Not occurred,Occurred" bitfld.long 0x10 16. " RWRN_INT ,Rx error counter transition from < 96 to >= 96" "Not occurred,Occurred" bitfld.long 0x10 15. " BIT1_ERR ,Inconsistency between the transmitted and the received bit in a message" "No error,Error" textline " " bitfld.long 0x10 14. " BIT0_ERR ,Inconsistency between the transmitted and the received bit in a message" "No error,Error" bitfld.long 0x10 13. " ACK_ERR ,Acknowledge Error detection by the transmitter node" "No error,Error" bitfld.long 0x10 12. " CRC_ERR ,CRC Error detection by the receiver node" "No error,Error" bitfld.long 0x10 11. " FRM_ERR ,Form Error detection by the receiver node" "No error,Error" textline " " bitfld.long 0x10 10. " STF_ERR ,Stuffing Error detection" "No error,Error" bitfld.long 0x10 9. " TX_WRN ,Repetitive errors during message transmission >= 96" "Not occurred,Occurred" bitfld.long 0x10 8. " RX_WRN ,Repetitive errors during message reception >= 96" "Not occurred,Occurred" bitfld.long 0x10 7. " IDLE ,IDLE state" "Not IDLE,IDLE" textline " " bitfld.long 0x10 6. " TX ,FLEXCAN message" "Receiving,Transmitting" bitfld.long 0x10 4.--5. " FLT_CONF ,Confinement State of the FLEXCAN module" "Error Active,Error Passive,Bus off,Bus off" bitfld.long 0x10 3. " RX ,FLEXCAN message" "Receiving,Transmitting" bitfld.long 0x10 2. " BOFF_INT ,FLEXCAN enters 'Bus Off' state" "Not occurred,Occurred" textline " " bitfld.long 0x10 1. " ERR_INT ,At least one of the Error Bits is set" "Not occurred,Occurred" bitfld.long 0x10 0. " WAK_INT ,Recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode" "Not occurred,Occurred" textline " " line.long 0x14 "IMASK2,Interrupt Masks 2 Register" bitfld.long 0x14 31. " BUF_M[63] ,FLEXCAN Message Buffer 63 Enable" "Disabled,Enabled" bitfld.long 0x14 30. " [62] ,FLEXCAN Message Buffer 62 Enable" "Disabled,Enabled" bitfld.long 0x14 29. " [61] ,FLEXCAN Message Buffer 61 Enable" "Disabled,Enabled" bitfld.long 0x14 28. " [60] ,FLEXCAN Message Buffer 60 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " [59] ,FLEXCAN Message Buffer 59 Enable" "Disabled,Enabled" bitfld.long 0x14 26. " [58] ,FLEXCAN Message Buffer 58 Enable" "Disabled,Enabled" bitfld.long 0x14 25. " [57] ,FLEXCAN Message Buffer 57 Enable" "Disabled,Enabled" bitfld.long 0x14 24. " [56] ,FLEXCAN Message Buffer 56 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " [55] ,FLEXCAN Message Buffer 55 Enable" "Disabled,Enabled" bitfld.long 0x14 22. " [54] ,FLEXCAN Message Buffer 54 Enable" "Disabled,Enabled" bitfld.long 0x14 21. " [53] ,FLEXCAN Message Buffer 53 Enable" "Disabled,Enabled" bitfld.long 0x14 20. " [52] ,FLEXCAN Message Buffer 52 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " [51] ,FLEXCAN Message Buffer 51 Enable" "Disabled,Enabled" bitfld.long 0x14 18. " [50] ,FLEXCAN Message Buffer 50 Enable" "Disabled,Enabled" bitfld.long 0x14 17. " [49] ,FLEXCAN Message Buffer 49 Enable" "Disabled,Enabled" bitfld.long 0x14 16. " [48] ,FLEXCAN Message Buffer 48 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " [47] ,FLEXCAN Message Buffer 47 Enable" "Disabled,Enabled" bitfld.long 0x14 14. " [46] ,FLEXCAN Message Buffer 46 Enable" "Disabled,Enabled" bitfld.long 0x14 13. " [45] ,FLEXCAN Message Buffer 45 Enable" "Disabled,Enabled" bitfld.long 0x14 12. " [44] ,FLEXCAN Message Buffer 44 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " [43] ,FLEXCAN Message Buffer 43 Enable" "Disabled,Enabled" bitfld.long 0x14 10. " [42] ,FLEXCAN Message Buffer 42 Enable" "Disabled,Enabled" bitfld.long 0x14 9. " [41] ,FLEXCAN Message Buffer 41 Enable" "Disabled,Enabled" bitfld.long 0x14 8. " [40] ,FLEXCAN Message Buffer 40 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " [39] ,FLEXCAN Message Buffer 39 Enable" "Disabled,Enabled" bitfld.long 0x14 6. " [38] ,FLEXCAN Message Buffer 38 Enable" "Disabled,Enabled" bitfld.long 0x14 5. " [37] ,FLEXCAN Message Buffer 37 Enable" "Disabled,Enabled" bitfld.long 0x14 4. " [36] ,FLEXCAN Message Buffer 36 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " [35] ,FLEXCAN Message Buffer 35 Enable" "Disabled,Enabled" bitfld.long 0x14 2. " [34] ,FLEXCAN Message Buffer 34 Enable" "Disabled,Enabled" bitfld.long 0x14 1. " [33] ,FLEXCAN Message Buffer 33 Enable" "Disabled,Enabled" bitfld.long 0x14 0. " [32] ,FLEXCAN Message Buffer 32 Enable" "Disabled,Enabled" line.long 0x18 "IMASK1,Interrupt Masks 1 Register" bitfld.long 0x18 31. " [31] ,FLEXCAN Message Buffer 31 Enable" "Disabled,Enabled" bitfld.long 0x18 30. " [30] ,FLEXCAN Message Buffer 30 Enable" "Disabled,Enabled" bitfld.long 0x18 29. " [29] ,FLEXCAN Message Buffer 29 Enable" "Disabled,Enabled" bitfld.long 0x18 28. " [28] ,FLEXCAN Message Buffer 28 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 27. " [27] ,FLEXCAN Message Buffer 27 Enable" "Disabled,Enabled" bitfld.long 0x18 26. " [26] ,FLEXCAN Message Buffer 26 Enable" "Disabled,Enabled" bitfld.long 0x18 25. " [25] ,FLEXCAN Message Buffer 25 Enable" "Disabled,Enabled" bitfld.long 0x18 24. " [24] ,FLEXCAN Message Buffer 24 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 23. " [23] ,FLEXCAN Message Buffer 23 Enable" "Disabled,Enabled" bitfld.long 0x18 22. " [22] ,FLEXCAN Message Buffer 22 Enable" "Disabled,Enabled" bitfld.long 0x18 21. " [21] ,FLEXCAN Message Buffer 21 Enable" "Disabled,Enabled" bitfld.long 0x18 20. " [20] ,FLEXCAN Message Buffer 20 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 19. " [19] ,FLEXCAN Message Buffer 19 Enable" "Disabled,Enabled" bitfld.long 0x18 18. " [18] ,FLEXCAN Message Buffer 18 Enable" "Disabled,Enabled" bitfld.long 0x18 17. " [17] ,FLEXCAN Message Buffer 17 Enable" "Disabled,Enabled" bitfld.long 0x18 16. " [16] ,FLEXCAN Message Buffer 16 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 15. " [15] ,FLEXCAN Message Buffer 15 Enable" "Disabled,Enabled" bitfld.long 0x18 14. " [14] ,FLEXCAN Message Buffer 14 Enable" "Disabled,Enabled" bitfld.long 0x18 13. " [13] ,FLEXCAN Message Buffer 13 Enable" "Disabled,Enabled" bitfld.long 0x18 12. " [12] ,FLEXCAN Message Buffer 12 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " [11] ,FLEXCAN Message Buffer 11 Enable" "Disabled,Enabled" bitfld.long 0x18 10. " [10] ,FLEXCAN Message Buffer 10 Enable" "Disabled,Enabled" bitfld.long 0x18 9. " [9] ,FLEXCAN Message Buffer 9 Enable" "Disabled,Enabled" bitfld.long 0x18 8. " [8] ,FLEXCAN Message Buffer 8 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 7. " [7] ,FLEXCAN Message Buffer 7 Enable" "Disabled,Enabled" bitfld.long 0x18 6. " [6] ,FLEXCAN Message Buffer 6 Enable" "Disabled,Enabled" bitfld.long 0x18 5. " [5] ,FLEXCAN Message Buffer 5 Enable" "Disabled,Enabled" bitfld.long 0x18 4. " [4] ,FLEXCAN Message Buffer 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " [3] ,FLEXCAN Message Buffer 3 Enable" "Disabled,Enabled" bitfld.long 0x18 2. " [2] ,FLEXCAN Message Buffer 2 Enable" "Disabled,Enabled" bitfld.long 0x18 1. " [1] ,FLEXCAN Message Buffer 1 Enable" "Disabled,Enabled" bitfld.long 0x18 0. " [0] ,FLEXCAN Message Buffer 0 Enable" "Disabled,Enabled" textline " " line.long 0x1C "IFLAG2,Interrupt Flags 2 Register" bitfld.long 0x1C 31. " BUF_I[63] ,FLEXCAN Message Buffer 63 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 30. " [62] ,FLEXCAN Message Buffer 62 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 29. " [61] ,FLEXCAN Message Buffer 61 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 28. " [60] ,FLEXCAN Message Buffer 60 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 27. " [59] ,FLEXCAN Message Buffer 59 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 26. " [58] ,FLEXCAN Message Buffer 58 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 25. " [57] ,FLEXCAN Message Buffer 57 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 24. " [56] ,FLEXCAN Message Buffer 56 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 23. " [55] ,FLEXCAN Message Buffer 55 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 22. " [54] ,FLEXCAN Message Buffer 54 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 21. " [53] ,FLEXCAN Message Buffer 53 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 20. " [52] ,FLEXCAN Message Buffer 52 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 19. " [51] ,FLEXCAN Message Buffer 51 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 18. " [50] ,FLEXCAN Message Buffer 50 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 17. " [49] ,FLEXCAN Message Buffer 49 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 16. " [48] ,FLEXCAN Message Buffer 48 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 15. " [47] ,FLEXCAN Message Buffer 47 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 14. " [46] ,FLEXCAN Message Buffer 46 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 13. " [45] ,FLEXCAN Message Buffer 45 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 12. " [44] ,FLEXCAN Message Buffer 44 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " [43] ,FLEXCAN Message Buffer 43 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 10. " [42] ,FLEXCAN Message Buffer 42 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 9. " [41] ,FLEXCAN Message Buffer 41 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 8. " [40] ,FLEXCAN Message Buffer 40 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 7. " [39] ,FLEXCAN Message Buffer 39 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 6. " [38] ,FLEXCAN Message Buffer 38 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 5. " [37] ,FLEXCAN Message Buffer 37 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 4. " [36] ,FLEXCAN Message Buffer 36 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 3. " [35] ,FLEXCAN Message Buffer 35 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 2. " [34] ,FLEXCAN Message Buffer 34 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 1. " [33] ,FLEXCAN Message Buffer 33 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 0. " [32] ,FLEXCAN Message Buffer 32 Interrupt" "Disabled,Enabled" line.long 0x20 "IFLAG1,Interrupt Flags 1 Register" bitfld.long 0x20 31. " [31] ,FLEXCAN Message Buffer 31 Interrupt" "Disabled,Enabled" bitfld.long 0x20 30. " [30] ,FLEXCAN Message Buffer 30 Interrupt" "Disabled,Enabled" bitfld.long 0x20 29. " [29] ,FLEXCAN Message Buffer 29 Interrupt" "Disabled,Enabled" bitfld.long 0x20 28. " [28] ,FLEXCAN Message Buffer 28 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 27. " [27] ,FLEXCAN Message Buffer 27 Interrupt" "Disabled,Enabled" bitfld.long 0x20 26. " [26] ,FLEXCAN Message Buffer 26 Interrupt" "Disabled,Enabled" bitfld.long 0x20 25. " [25] ,FLEXCAN Message Buffer 25 Interrupt" "Disabled,Enabled" bitfld.long 0x20 24. " [24] ,FLEXCAN Message Buffer 24 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 23. " [23] ,FLEXCAN Message Buffer 23 Interrupt" "Disabled,Enabled" bitfld.long 0x20 22. " [22] ,FLEXCAN Message Buffer 22 Interrupt" "Disabled,Enabled" bitfld.long 0x20 21. " [21] ,FLEXCAN Message Buffer 21 Interrupt" "Disabled,Enabled" bitfld.long 0x20 20. " [20] ,FLEXCAN Message Buffer 20 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " [19] ,FLEXCAN Message Buffer 19 Interrupt" "Disabled,Enabled" bitfld.long 0x20 18. " [18] ,FLEXCAN Message Buffer 18 Interrupt" "Disabled,Enabled" bitfld.long 0x20 17. " [17] ,FLEXCAN Message Buffer 17 Interrupt" "Disabled,Enabled" bitfld.long 0x20 16. " [16] ,FLEXCAN Message Buffer 16 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " [15] ,FLEXCAN Message Buffer 15 Interrupt" "Disabled,Enabled" bitfld.long 0x20 14. " [14] ,FLEXCAN Message Buffer 14 Interrupt" "Disabled,Enabled" bitfld.long 0x20 13. " [13] ,FLEXCAN Message Buffer 13 Interrupt" "Disabled,Enabled" bitfld.long 0x20 12. " [12] ,FLEXCAN Message Buffer 12 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " [11] ,FLEXCAN Message Buffer 11 Interrupt" "Disabled,Enabled" bitfld.long 0x20 10. " [10] ,FLEXCAN Message Buffer 10 Interrupt" "Disabled,Enabled" bitfld.long 0x20 9. " [9] ,FLEXCAN Message Buffer 9 Interrupt" "Disabled,Enabled" bitfld.long 0x20 8. " [8] ,FLEXCAN Message Buffer 8 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " [7] ,FLEXCAN Message Buffer 7 Interrupt" "Disabled,Enabled" bitfld.long 0x20 6. " [6] ,FLEXCAN Message Buffer 6 Interrupt" "Disabled,Enabled" bitfld.long 0x20 5. " [5] ,FLEXCAN Message Buffer 5 Interrupt" "Disabled,Enabled" bitfld.long 0x20 4. " [4] ,FLEXCAN Message Buffer 4 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 3. " [3] ,FLEXCAN Message Buffer 3 Interrupt" "Disabled,Enabled" bitfld.long 0x20 2. " [2] ,FLEXCAN Message Buffer 2 Interrupt" "Disabled,Enabled" bitfld.long 0x20 1. " [1] ,FLEXCAN Message Buffer 1 Interrupt" "Disabled,Enabled" bitfld.long 0x20 0. " [0] ,FLEXCAN Message Buffer 0 Interrupt" "Disabled,Enabled" textline " " textline "" line.long 0x24 "CTRL2,Control 2 Register" bitfld.long 0x24 28. " WRMFRZ ,Unrestricted write access to FlexCAN memory" "Restricted,Unrestricted" bitfld.long 0x24 24.--27. " RFEN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x24 19.--23. " TASD ,Number of CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 18. " MRP ,Set the matching process start" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x24 17. " RRS ,Remote Request Frame" "Generated,Stored" bitfld.long 0x24 16. " EACEN ,Comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process" "Both compared,IDE only" rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest number inactive Mailbox" bitfld.long 0x00 14. " VPS ,This bit indicates whether IMB and LPTM contents are currently valid or not" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Indicates if any Mailbox is inactive" "No,Yes" textline " " rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,Number of the Mailbox corresponding to the value in TXCRC field" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC value of the last message transmitted" textline " " if ((per.l(ad:0x42090000)&0x01000000)==0x01000000) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" else rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" endif rgroup.long 0x4C++0x03 line.long 0x00 "RXFIR,Rx FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ,Identifier Acceptance Filter hit by the received message that is in the output of the Rx FIFO" group.long 0x880++0x03 line.long 0x00 "RXIMR0_RXIMR63,Rx FIFO Information Register" bitfld.long 0x00 31. " MI[31] ,Mailbox filter 31 and Rx FIFO ID Filter 31 maks" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 and Rx FIFO ID Filter 30 maks" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 and Rx FIFO ID Filter 29 maks" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 and Rx FIFO ID Filter 28 maks" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Mailbox filter 27 and Rx FIFO ID Filter 27 maks" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 and Rx FIFO ID Filter 26 maks" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 and Rx FIFO ID Filter 25 maks" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 and Rx FIFO ID Filter 24 maks" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Mailbox filter 23 and Rx FIFO ID Filter 23 maks" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 and Rx FIFO ID Filter 22 maks" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 and Rx FIFO ID Filter 21 maks" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 and Rx FIFO ID Filter 20 maks" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Mailbox filter 19 and Rx FIFO ID Filter 19 maks" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 and Rx FIFO ID Filter 18 maks" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 and Rx FIFO ID Filter 17 maks" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 and Rx FIFO ID Filter 16 maks" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Mailbox filter 15 and Rx FIFO ID Filter 15 maks" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 and Rx FIFO ID Filter 14 maks" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 and Rx FIFO ID Filter 13 maks" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 and Rx FIFO ID Filter 12 maks" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Mailbox filter 11 and Rx FIFO ID Filter 11 maks" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 and Rx FIFO ID Filter 10 maks" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 and Rx FIFO ID Filter 9 maks" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 and Rx FIFO ID Filter 8 maks" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Mailbox filter 7 and Rx FIFO ID Filter 7 maks" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 and Rx FIFO ID Filter 6 maks" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 and Rx FIFO ID Filter 5 maks" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 and Rx FIFO ID Filter 4 maks" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Mailbox filter 3 and Rx FIFO ID Filter 3 maks" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 and Rx FIFO ID Filter 2 maks" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 and Rx FIFO ID Filter 1 maks" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 and Rx FIFO ID Filter 0 maks" "Masked,Not masked" group.long 0x9E0++0x03 line.long 0x00 "GFWR,Glitch Filter Width Registers" hexmask.long.byte 0x00 0.--7. 1. " GFWR ,Determines the Glitch Filter Width" width 0x0b endif tree.end tree "FlexCAN 2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02094000 width 16. group.long 0x00++0x0B line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,FLEXCAN disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at ARM level" "Freeze Mode,Not Freeze Mode" bitfld.long 0x00 29. " RFEN ,Rx FIFO feature" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Freeze Mode" "Not requested,Entered" textline " " rbitfld.long 0x00 27. " NOT_RDY ,FLEXCAN current mode" "Disable/Stop/Freeze,Normal/Listen-Only/Loop-Back" bitfld.long 0x00 26. " WAK_MSK ,Wake Up Interrupt generation" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,FLEXCAN registers reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped" "Not in Freeze mode,In Freeze mode" textline " " bitfld.long 0x00 23. " SUPV ,This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode" "User,Supervisor" bitfld.long 0x00 22. " SLF_WAK ,FLEXCAN Self Wake Up feature" "Disabled,Enabled" bitfld.long 0x00 21. " WRN_EN ,TWRN_INT and RWRN_INT flags generation in the Error and Status Register" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,FLEXCAN low power mode" "None,Disable/Stop" textline " " bitfld.long 0x00 19. " WAK_SRC ,Low-pass filter to protect the FLEXCAN_RX input from spurious wake up" "Disabled,Enabled" bitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "Enabled,Disabled" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue feature" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIO_EN ,Local Priority" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,Tx abort feature" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,The format of the elements of the Rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,The number of the last Message Buffers that will take part in the matching and arbitration processes" line.long 0x04 "CTRL1,Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Ratio between the PE clock frequency and the Serial Clock frequency" bitfld.long 0x04 22.--23. " RJW ,Maximum number of time quanta that a bit time can be changed by one resynchronization" "0,1,2,3" bitfld.long 0x04 19.--21. " PSEG1 ,Length of Phase Buffer Segment 1 in the bit time" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PSEG2 ,Length of Phase Buffer Segment 2 in the bit time" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 15. " BOFF_MSK ,Bus Off Interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " ERR_MSK ,Error Interrupt" "Disabled,Enabled" bitfld.long 0x04 12. " LPB ,Loop-Back Mode" "Disabled,Enabled" bitfld.long 0x04 11. " TWRN_MSK ,Tx Warning Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " RWRN_MSK ,Rx Warning Interrupt" "Disabled,Enabled" bitfld.long 0x04 7. " SMP ,Sampling mode of CAN bits at the FLEXCAN_RX" "1 sample/bit,3 samples/bit" bitfld.long 0x04 6. " BOFF_REC ,FLEXCAN automatic recovery from Bus Off state" "Enabled,Disabled" bitfld.long 0x04 5. " TSYN ,Mechanism that resets the free-running timer each time a message is received in Message Buffer 0" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " LBUF ,Ordering mechanism for Message Buffer transmission" "Highest priority,Lowest number" bitfld.long 0x04 3. " LOM ,Listen Only Mode" "Disabled,Enabled" bitfld.long 0x04 0.--2. " PROP_SEG ,Length of the Propagation Segment in the bit time" "0,1,2,3,4,5,6,7" line.long 0x08 "TIMER,Control 1 Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Timer value" textline " " group.long 0x10++0x27 line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG31 ,Mailbox filter 31 mask" "Masked,Not masked" bitfld.long 0x00 30. " MG30 ,Mailbox filter 30 mask" "Masked,Not masked" bitfld.long 0x00 29. " MG29 ,Mailbox filter 29 mask" "Masked,Not masked" bitfld.long 0x00 28. " MG28 ,Mailbox filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MG27 ,Mailbox filter 27 mask" "Masked,Not masked" bitfld.long 0x00 26. " MG26 ,Mailbox filter 26 mask" "Masked,Not masked" bitfld.long 0x00 25. " MG25 ,Mailbox filter 25 mask" "Masked,Not masked" bitfld.long 0x00 24. " MG24 ,Mailbox filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MG23 ,Mailbox filter 23 mask" "Masked,Not masked" bitfld.long 0x00 22. " MG22 ,Mailbox filter 22 mask" "Masked,Not masked" bitfld.long 0x00 21. " MG21 ,Mailbox filter 21 mask" "Masked,Not masked" bitfld.long 0x00 20. " MG20 ,Mailbox filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MG19 ,Mailbox filter 19 mask" "Masked,Not masked" bitfld.long 0x00 18. " MG18 ,Mailbox filter 18 mask" "Masked,Not masked" bitfld.long 0x00 17. " MG17 ,Mailbox filter 17 mask" "Masked,Not masked" bitfld.long 0x00 16. " MG16 ,Mailbox filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MG15 ,Mailbox filter 15 mask" "Masked,Not masked" bitfld.long 0x00 14. " MG14 ,Mailbox filter 14 mask" "Masked,Not masked" bitfld.long 0x00 13. " MG13 ,Mailbox filter 13 mask" "Masked,Not masked" bitfld.long 0x00 12. " MG12 ,Mailbox filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MG11 ,Mailbox filter 11 mask" "Masked,Not masked" bitfld.long 0x00 10. " MG10 ,Mailbox filter 10 mask" "Masked,Not masked" bitfld.long 0x00 9. " MG9 ,Mailbox filter 9 mask" "Masked,Not masked" bitfld.long 0x00 8. " MG8 ,Mailbox filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MG7 ,Mailbox filter 7 mask" "Masked,Not masked" bitfld.long 0x00 6. " MG6 ,Mailbox filter 6 mask" "Masked,Not masked" bitfld.long 0x00 5. " MG5 ,Mailbox filter 5 mask" "Masked,Not masked" bitfld.long 0x00 4. " MG4 ,Mailbox filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MG3 ,Mailbox filter 3 mask" "Masked,Not masked" bitfld.long 0x00 2. " MG2 ,Mailbox filter 2 mask" "Masked,Not masked" bitfld.long 0x00 1. " MG1 ,Mailbox filter 1 mask" "Masked,Not masked" bitfld.long 0x00 0. " MG0 ,Mailbox filter 0 mask" "Masked,Not masked" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Mailbox 14 filter 31 mask" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Mailbox 14 filter 30 mask" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Mailbox 14 filter 29 mask" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Mailbox 14 filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Mailbox 14 filter 27 mask" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Mailbox 14 filter 26 mask" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Mailbox 14 filter 25 mask" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Mailbox 14 filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Mailbox 14 filter 23 mask" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Mailbox 14 filter 22 mask" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Mailbox 14 filter 21 mask" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Mailbox 14 filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Mailbox 14 filter 19 mask" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Mailbox 14 filter 18 mask" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Mailbox 14 filter 17 mask" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Mailbox 14 filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Mailbox 14 filter 15 mask" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Mailbox 14 filter 14 mask" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Mailbox 14 filter 13 mask" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Mailbox 14 filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Mailbox 14 filter 11 mask" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Mailbox 14 filter 10 mask" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Mailbox 14 filter 9 mask" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Mailbox 14 filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Mailbox 14 filter 7 mask" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Mailbox 14 filter 6 mask" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Mailbox 14 filter 5 mask" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Mailbox 14 filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Mailbox 14 filter 3 mask" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Mailbox 14 filter 2 mask" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Mailbox 14 filter 1 mask" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Mailbox 14 filter 0 mask" "Masked,Not masked" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Mailbox 15 filter 31 mask" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Mailbox 15 filter 30 mask" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Mailbox 15 filter 29 mask" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Mailbox 15 filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Mailbox 15 filter 27 mask" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Mailbox 15 filter 26 mask" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Mailbox 15 filter 25 mask" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Mailbox 15 filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Mailbox 15 filter 23 mask" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Mailbox 15 filter 22 mask" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Mailbox 15 filter 21 mask" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Mailbox 15 filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Mailbox 15 filter 19 mask" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Mailbox 15 filter 18 mask" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Mailbox 15 filter 17 mask" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Mailbox 15 filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Mailbox 15 filter 15 mask" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Mailbox 15 filter 14 mask" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Mailbox 15 filter 13 mask" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Mailbox 15 filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Mailbox 15 filter 11 mask" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Mailbox 15 filter 10 mask" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Mailbox 15 filter 9 mask" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Mailbox 15 filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Mailbox 15 filter 7 mask" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Mailbox 15 filter 6 mask" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Mailbox 15 filter 5 mask" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Mailbox 15 filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Mailbox 15 filter 3 mask" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Mailbox 15 filter 2 mask" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Mailbox 15 filter 1 mask" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Mailbox 15 filter 0 mask" "Masked,Not masked" textline "" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " Rx_Err_Counter ,Receiver Error Counter" hexmask.long.byte 0x0C 0.--7. 1. " Tx_Err_Counter ,Transmitter Error Counter" line.long 0x10 "ESR1,Error and Status 1 Register" rbitfld.long 0x10 18. " SYNCH ,Synchronization between FLEXCAN and CAN bus" "Not synchronized,Synchronized" bitfld.long 0x10 17. " TWRN_INT ,Tx error counter transition from < 96 to >= 96" "Not occurred,Occurred" bitfld.long 0x10 16. " RWRN_INT ,Rx error counter transition from < 96 to >= 96" "Not occurred,Occurred" bitfld.long 0x10 15. " BIT1_ERR ,Inconsistency between the transmitted and the received bit in a message" "No error,Error" textline " " bitfld.long 0x10 14. " BIT0_ERR ,Inconsistency between the transmitted and the received bit in a message" "No error,Error" bitfld.long 0x10 13. " ACK_ERR ,Acknowledge Error detection by the transmitter node" "No error,Error" bitfld.long 0x10 12. " CRC_ERR ,CRC Error detection by the receiver node" "No error,Error" bitfld.long 0x10 11. " FRM_ERR ,Form Error detection by the receiver node" "No error,Error" textline " " bitfld.long 0x10 10. " STF_ERR ,Stuffing Error detection" "No error,Error" bitfld.long 0x10 9. " TX_WRN ,Repetitive errors during message transmission >= 96" "Not occurred,Occurred" bitfld.long 0x10 8. " RX_WRN ,Repetitive errors during message reception >= 96" "Not occurred,Occurred" bitfld.long 0x10 7. " IDLE ,IDLE state" "Not IDLE,IDLE" textline " " bitfld.long 0x10 6. " TX ,FLEXCAN message" "Receiving,Transmitting" bitfld.long 0x10 4.--5. " FLT_CONF ,Confinement State of the FLEXCAN module" "Error Active,Error Passive,Bus off,Bus off" bitfld.long 0x10 3. " RX ,FLEXCAN message" "Receiving,Transmitting" bitfld.long 0x10 2. " BOFF_INT ,FLEXCAN enters 'Bus Off' state" "Not occurred,Occurred" textline " " bitfld.long 0x10 1. " ERR_INT ,At least one of the Error Bits is set" "Not occurred,Occurred" bitfld.long 0x10 0. " WAK_INT ,Recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode" "Not occurred,Occurred" textline " " line.long 0x14 "IMASK2,Interrupt Masks 2 Register" bitfld.long 0x14 31. " BUF_M[63] ,FLEXCAN Message Buffer 63 Enable" "Disabled,Enabled" bitfld.long 0x14 30. " [62] ,FLEXCAN Message Buffer 62 Enable" "Disabled,Enabled" bitfld.long 0x14 29. " [61] ,FLEXCAN Message Buffer 61 Enable" "Disabled,Enabled" bitfld.long 0x14 28. " [60] ,FLEXCAN Message Buffer 60 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " [59] ,FLEXCAN Message Buffer 59 Enable" "Disabled,Enabled" bitfld.long 0x14 26. " [58] ,FLEXCAN Message Buffer 58 Enable" "Disabled,Enabled" bitfld.long 0x14 25. " [57] ,FLEXCAN Message Buffer 57 Enable" "Disabled,Enabled" bitfld.long 0x14 24. " [56] ,FLEXCAN Message Buffer 56 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " [55] ,FLEXCAN Message Buffer 55 Enable" "Disabled,Enabled" bitfld.long 0x14 22. " [54] ,FLEXCAN Message Buffer 54 Enable" "Disabled,Enabled" bitfld.long 0x14 21. " [53] ,FLEXCAN Message Buffer 53 Enable" "Disabled,Enabled" bitfld.long 0x14 20. " [52] ,FLEXCAN Message Buffer 52 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " [51] ,FLEXCAN Message Buffer 51 Enable" "Disabled,Enabled" bitfld.long 0x14 18. " [50] ,FLEXCAN Message Buffer 50 Enable" "Disabled,Enabled" bitfld.long 0x14 17. " [49] ,FLEXCAN Message Buffer 49 Enable" "Disabled,Enabled" bitfld.long 0x14 16. " [48] ,FLEXCAN Message Buffer 48 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " [47] ,FLEXCAN Message Buffer 47 Enable" "Disabled,Enabled" bitfld.long 0x14 14. " [46] ,FLEXCAN Message Buffer 46 Enable" "Disabled,Enabled" bitfld.long 0x14 13. " [45] ,FLEXCAN Message Buffer 45 Enable" "Disabled,Enabled" bitfld.long 0x14 12. " [44] ,FLEXCAN Message Buffer 44 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " [43] ,FLEXCAN Message Buffer 43 Enable" "Disabled,Enabled" bitfld.long 0x14 10. " [42] ,FLEXCAN Message Buffer 42 Enable" "Disabled,Enabled" bitfld.long 0x14 9. " [41] ,FLEXCAN Message Buffer 41 Enable" "Disabled,Enabled" bitfld.long 0x14 8. " [40] ,FLEXCAN Message Buffer 40 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " [39] ,FLEXCAN Message Buffer 39 Enable" "Disabled,Enabled" bitfld.long 0x14 6. " [38] ,FLEXCAN Message Buffer 38 Enable" "Disabled,Enabled" bitfld.long 0x14 5. " [37] ,FLEXCAN Message Buffer 37 Enable" "Disabled,Enabled" bitfld.long 0x14 4. " [36] ,FLEXCAN Message Buffer 36 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " [35] ,FLEXCAN Message Buffer 35 Enable" "Disabled,Enabled" bitfld.long 0x14 2. " [34] ,FLEXCAN Message Buffer 34 Enable" "Disabled,Enabled" bitfld.long 0x14 1. " [33] ,FLEXCAN Message Buffer 33 Enable" "Disabled,Enabled" bitfld.long 0x14 0. " [32] ,FLEXCAN Message Buffer 32 Enable" "Disabled,Enabled" line.long 0x18 "IMASK1,Interrupt Masks 1 Register" bitfld.long 0x18 31. " [31] ,FLEXCAN Message Buffer 31 Enable" "Disabled,Enabled" bitfld.long 0x18 30. " [30] ,FLEXCAN Message Buffer 30 Enable" "Disabled,Enabled" bitfld.long 0x18 29. " [29] ,FLEXCAN Message Buffer 29 Enable" "Disabled,Enabled" bitfld.long 0x18 28. " [28] ,FLEXCAN Message Buffer 28 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 27. " [27] ,FLEXCAN Message Buffer 27 Enable" "Disabled,Enabled" bitfld.long 0x18 26. " [26] ,FLEXCAN Message Buffer 26 Enable" "Disabled,Enabled" bitfld.long 0x18 25. " [25] ,FLEXCAN Message Buffer 25 Enable" "Disabled,Enabled" bitfld.long 0x18 24. " [24] ,FLEXCAN Message Buffer 24 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 23. " [23] ,FLEXCAN Message Buffer 23 Enable" "Disabled,Enabled" bitfld.long 0x18 22. " [22] ,FLEXCAN Message Buffer 22 Enable" "Disabled,Enabled" bitfld.long 0x18 21. " [21] ,FLEXCAN Message Buffer 21 Enable" "Disabled,Enabled" bitfld.long 0x18 20. " [20] ,FLEXCAN Message Buffer 20 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 19. " [19] ,FLEXCAN Message Buffer 19 Enable" "Disabled,Enabled" bitfld.long 0x18 18. " [18] ,FLEXCAN Message Buffer 18 Enable" "Disabled,Enabled" bitfld.long 0x18 17. " [17] ,FLEXCAN Message Buffer 17 Enable" "Disabled,Enabled" bitfld.long 0x18 16. " [16] ,FLEXCAN Message Buffer 16 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 15. " [15] ,FLEXCAN Message Buffer 15 Enable" "Disabled,Enabled" bitfld.long 0x18 14. " [14] ,FLEXCAN Message Buffer 14 Enable" "Disabled,Enabled" bitfld.long 0x18 13. " [13] ,FLEXCAN Message Buffer 13 Enable" "Disabled,Enabled" bitfld.long 0x18 12. " [12] ,FLEXCAN Message Buffer 12 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " [11] ,FLEXCAN Message Buffer 11 Enable" "Disabled,Enabled" bitfld.long 0x18 10. " [10] ,FLEXCAN Message Buffer 10 Enable" "Disabled,Enabled" bitfld.long 0x18 9. " [9] ,FLEXCAN Message Buffer 9 Enable" "Disabled,Enabled" bitfld.long 0x18 8. " [8] ,FLEXCAN Message Buffer 8 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 7. " [7] ,FLEXCAN Message Buffer 7 Enable" "Disabled,Enabled" bitfld.long 0x18 6. " [6] ,FLEXCAN Message Buffer 6 Enable" "Disabled,Enabled" bitfld.long 0x18 5. " [5] ,FLEXCAN Message Buffer 5 Enable" "Disabled,Enabled" bitfld.long 0x18 4. " [4] ,FLEXCAN Message Buffer 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " [3] ,FLEXCAN Message Buffer 3 Enable" "Disabled,Enabled" bitfld.long 0x18 2. " [2] ,FLEXCAN Message Buffer 2 Enable" "Disabled,Enabled" bitfld.long 0x18 1. " [1] ,FLEXCAN Message Buffer 1 Enable" "Disabled,Enabled" bitfld.long 0x18 0. " [0] ,FLEXCAN Message Buffer 0 Enable" "Disabled,Enabled" textline " " line.long 0x1C "IFLAG2,Interrupt Flags 2 Register" bitfld.long 0x1C 31. " BUF_I[63] ,FLEXCAN Message Buffer 63 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 30. " [62] ,FLEXCAN Message Buffer 62 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 29. " [61] ,FLEXCAN Message Buffer 61 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 28. " [60] ,FLEXCAN Message Buffer 60 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 27. " [59] ,FLEXCAN Message Buffer 59 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 26. " [58] ,FLEXCAN Message Buffer 58 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 25. " [57] ,FLEXCAN Message Buffer 57 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 24. " [56] ,FLEXCAN Message Buffer 56 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 23. " [55] ,FLEXCAN Message Buffer 55 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 22. " [54] ,FLEXCAN Message Buffer 54 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 21. " [53] ,FLEXCAN Message Buffer 53 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 20. " [52] ,FLEXCAN Message Buffer 52 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 19. " [51] ,FLEXCAN Message Buffer 51 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 18. " [50] ,FLEXCAN Message Buffer 50 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 17. " [49] ,FLEXCAN Message Buffer 49 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 16. " [48] ,FLEXCAN Message Buffer 48 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 15. " [47] ,FLEXCAN Message Buffer 47 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 14. " [46] ,FLEXCAN Message Buffer 46 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 13. " [45] ,FLEXCAN Message Buffer 45 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 12. " [44] ,FLEXCAN Message Buffer 44 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " [43] ,FLEXCAN Message Buffer 43 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 10. " [42] ,FLEXCAN Message Buffer 42 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 9. " [41] ,FLEXCAN Message Buffer 41 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 8. " [40] ,FLEXCAN Message Buffer 40 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 7. " [39] ,FLEXCAN Message Buffer 39 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 6. " [38] ,FLEXCAN Message Buffer 38 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 5. " [37] ,FLEXCAN Message Buffer 37 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 4. " [36] ,FLEXCAN Message Buffer 36 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 3. " [35] ,FLEXCAN Message Buffer 35 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 2. " [34] ,FLEXCAN Message Buffer 34 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 1. " [33] ,FLEXCAN Message Buffer 33 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 0. " [32] ,FLEXCAN Message Buffer 32 Interrupt" "Disabled,Enabled" line.long 0x20 "IFLAG1,Interrupt Flags 1 Register" bitfld.long 0x20 31. " [31] ,FLEXCAN Message Buffer 31 Interrupt" "Disabled,Enabled" bitfld.long 0x20 30. " [30] ,FLEXCAN Message Buffer 30 Interrupt" "Disabled,Enabled" bitfld.long 0x20 29. " [29] ,FLEXCAN Message Buffer 29 Interrupt" "Disabled,Enabled" bitfld.long 0x20 28. " [28] ,FLEXCAN Message Buffer 28 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 27. " [27] ,FLEXCAN Message Buffer 27 Interrupt" "Disabled,Enabled" bitfld.long 0x20 26. " [26] ,FLEXCAN Message Buffer 26 Interrupt" "Disabled,Enabled" bitfld.long 0x20 25. " [25] ,FLEXCAN Message Buffer 25 Interrupt" "Disabled,Enabled" bitfld.long 0x20 24. " [24] ,FLEXCAN Message Buffer 24 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 23. " [23] ,FLEXCAN Message Buffer 23 Interrupt" "Disabled,Enabled" bitfld.long 0x20 22. " [22] ,FLEXCAN Message Buffer 22 Interrupt" "Disabled,Enabled" bitfld.long 0x20 21. " [21] ,FLEXCAN Message Buffer 21 Interrupt" "Disabled,Enabled" bitfld.long 0x20 20. " [20] ,FLEXCAN Message Buffer 20 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " [19] ,FLEXCAN Message Buffer 19 Interrupt" "Disabled,Enabled" bitfld.long 0x20 18. " [18] ,FLEXCAN Message Buffer 18 Interrupt" "Disabled,Enabled" bitfld.long 0x20 17. " [17] ,FLEXCAN Message Buffer 17 Interrupt" "Disabled,Enabled" bitfld.long 0x20 16. " [16] ,FLEXCAN Message Buffer 16 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " [15] ,FLEXCAN Message Buffer 15 Interrupt" "Disabled,Enabled" bitfld.long 0x20 14. " [14] ,FLEXCAN Message Buffer 14 Interrupt" "Disabled,Enabled" bitfld.long 0x20 13. " [13] ,FLEXCAN Message Buffer 13 Interrupt" "Disabled,Enabled" bitfld.long 0x20 12. " [12] ,FLEXCAN Message Buffer 12 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " [11] ,FLEXCAN Message Buffer 11 Interrupt" "Disabled,Enabled" bitfld.long 0x20 10. " [10] ,FLEXCAN Message Buffer 10 Interrupt" "Disabled,Enabled" bitfld.long 0x20 9. " [9] ,FLEXCAN Message Buffer 9 Interrupt" "Disabled,Enabled" bitfld.long 0x20 8. " [8] ,FLEXCAN Message Buffer 8 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " [7] ,FLEXCAN Message Buffer 7 Interrupt" "Disabled,Enabled" bitfld.long 0x20 6. " [6] ,FLEXCAN Message Buffer 6 Interrupt" "Disabled,Enabled" bitfld.long 0x20 5. " [5] ,FLEXCAN Message Buffer 5 Interrupt" "Disabled,Enabled" bitfld.long 0x20 4. " [4] ,FLEXCAN Message Buffer 4 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 3. " [3] ,FLEXCAN Message Buffer 3 Interrupt" "Disabled,Enabled" bitfld.long 0x20 2. " [2] ,FLEXCAN Message Buffer 2 Interrupt" "Disabled,Enabled" bitfld.long 0x20 1. " [1] ,FLEXCAN Message Buffer 1 Interrupt" "Disabled,Enabled" bitfld.long 0x20 0. " [0] ,FLEXCAN Message Buffer 0 Interrupt" "Disabled,Enabled" textline " " textline "" line.long 0x24 "CTRL2,Control 2 Register" bitfld.long 0x24 28. " WRMFRZ ,Unrestricted write access to FlexCAN memory" "Restricted,Unrestricted" bitfld.long 0x24 24.--27. " RFEN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x24 19.--23. " TASD ,Number of CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 18. " MRP ,Set the matching process start" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x24 17. " RRS ,Remote Request Frame" "Generated,Stored" bitfld.long 0x24 16. " EACEN ,Comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process" "Both compared,IDE only" rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest number inactive Mailbox" bitfld.long 0x00 14. " VPS ,This bit indicates whether IMB and LPTM contents are currently valid or not" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Indicates if any Mailbox is inactive" "No,Yes" textline " " rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,Number of the Mailbox corresponding to the value in TXCRC field" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC value of the last message transmitted" textline " " if ((per.l(ad:0x02094000)&0x01000000)==0x01000000) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" else rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" endif rgroup.long 0x4C++0x03 line.long 0x00 "RXFIR,Rx FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ,Identifier Acceptance Filter hit by the received message that is in the output of the Rx FIFO" group.long 0x880++0x03 line.long 0x00 "RXIMR0_RXIMR63,Rx FIFO Information Register" bitfld.long 0x00 31. " MI[31] ,Mailbox filter 31 and Rx FIFO ID Filter 31 maks" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 and Rx FIFO ID Filter 30 maks" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 and Rx FIFO ID Filter 29 maks" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 and Rx FIFO ID Filter 28 maks" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Mailbox filter 27 and Rx FIFO ID Filter 27 maks" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 and Rx FIFO ID Filter 26 maks" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 and Rx FIFO ID Filter 25 maks" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 and Rx FIFO ID Filter 24 maks" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Mailbox filter 23 and Rx FIFO ID Filter 23 maks" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 and Rx FIFO ID Filter 22 maks" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 and Rx FIFO ID Filter 21 maks" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 and Rx FIFO ID Filter 20 maks" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Mailbox filter 19 and Rx FIFO ID Filter 19 maks" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 and Rx FIFO ID Filter 18 maks" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 and Rx FIFO ID Filter 17 maks" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 and Rx FIFO ID Filter 16 maks" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Mailbox filter 15 and Rx FIFO ID Filter 15 maks" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 and Rx FIFO ID Filter 14 maks" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 and Rx FIFO ID Filter 13 maks" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 and Rx FIFO ID Filter 12 maks" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Mailbox filter 11 and Rx FIFO ID Filter 11 maks" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 and Rx FIFO ID Filter 10 maks" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 and Rx FIFO ID Filter 9 maks" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 and Rx FIFO ID Filter 8 maks" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Mailbox filter 7 and Rx FIFO ID Filter 7 maks" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 and Rx FIFO ID Filter 6 maks" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 and Rx FIFO ID Filter 5 maks" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 and Rx FIFO ID Filter 4 maks" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Mailbox filter 3 and Rx FIFO ID Filter 3 maks" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 and Rx FIFO ID Filter 2 maks" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 and Rx FIFO ID Filter 1 maks" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 and Rx FIFO ID Filter 0 maks" "Masked,Not masked" group.long 0x9E0++0x03 line.long 0x00 "GFWR,Glitch Filter Width Registers" hexmask.long.byte 0x00 0.--7. 1. " GFWR ,Determines the Glitch Filter Width" width 0x0b else base ad:0x42094000 width 16. group.long 0x00++0x0B line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,FLEXCAN disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at ARM level" "Freeze Mode,Not Freeze Mode" bitfld.long 0x00 29. " RFEN ,Rx FIFO feature" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Freeze Mode" "Not requested,Entered" textline " " rbitfld.long 0x00 27. " NOT_RDY ,FLEXCAN current mode" "Disable/Stop/Freeze,Normal/Listen-Only/Loop-Back" bitfld.long 0x00 26. " WAK_MSK ,Wake Up Interrupt generation" "Disabled,Enabled" bitfld.long 0x00 25. " SOFT_RST ,FLEXCAN registers reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped" "Not in Freeze mode,In Freeze mode" textline " " bitfld.long 0x00 23. " SUPV ,This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode" "User,Supervisor" bitfld.long 0x00 22. " SLF_WAK ,FLEXCAN Self Wake Up feature" "Disabled,Enabled" bitfld.long 0x00 21. " WRN_EN ,TWRN_INT and RWRN_INT flags generation in the Error and Status Register" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,FLEXCAN low power mode" "None,Disable/Stop" textline " " bitfld.long 0x00 19. " WAK_SRC ,Low-pass filter to protect the FLEXCAN_RX input from spurious wake up" "Disabled,Enabled" bitfld.long 0x00 17. " SRX_DIS ,Self reception disable" "Enabled,Disabled" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue feature" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIO_EN ,Local Priority" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,Tx abort feature" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,The format of the elements of the Rx FIFO filter table" "A,B,C,D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,The number of the last Message Buffers that will take part in the matching and arbitration processes" line.long 0x04 "CTRL1,Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Ratio between the PE clock frequency and the Serial Clock frequency" bitfld.long 0x04 22.--23. " RJW ,Maximum number of time quanta that a bit time can be changed by one resynchronization" "0,1,2,3" bitfld.long 0x04 19.--21. " PSEG1 ,Length of Phase Buffer Segment 1 in the bit time" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PSEG2 ,Length of Phase Buffer Segment 2 in the bit time" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 15. " BOFF_MSK ,Bus Off Interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " ERR_MSK ,Error Interrupt" "Disabled,Enabled" bitfld.long 0x04 12. " LPB ,Loop-Back Mode" "Disabled,Enabled" bitfld.long 0x04 11. " TWRN_MSK ,Tx Warning Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " RWRN_MSK ,Rx Warning Interrupt" "Disabled,Enabled" bitfld.long 0x04 7. " SMP ,Sampling mode of CAN bits at the FLEXCAN_RX" "1 sample/bit,3 samples/bit" bitfld.long 0x04 6. " BOFF_REC ,FLEXCAN automatic recovery from Bus Off state" "Enabled,Disabled" bitfld.long 0x04 5. " TSYN ,Mechanism that resets the free-running timer each time a message is received in Message Buffer 0" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " LBUF ,Ordering mechanism for Message Buffer transmission" "Highest priority,Lowest number" bitfld.long 0x04 3. " LOM ,Listen Only Mode" "Disabled,Enabled" bitfld.long 0x04 0.--2. " PROP_SEG ,Length of the Propagation Segment in the bit time" "0,1,2,3,4,5,6,7" line.long 0x08 "TIMER,Control 1 Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Timer value" textline " " group.long 0x10++0x27 line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG31 ,Mailbox filter 31 mask" "Masked,Not masked" bitfld.long 0x00 30. " MG30 ,Mailbox filter 30 mask" "Masked,Not masked" bitfld.long 0x00 29. " MG29 ,Mailbox filter 29 mask" "Masked,Not masked" bitfld.long 0x00 28. " MG28 ,Mailbox filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MG27 ,Mailbox filter 27 mask" "Masked,Not masked" bitfld.long 0x00 26. " MG26 ,Mailbox filter 26 mask" "Masked,Not masked" bitfld.long 0x00 25. " MG25 ,Mailbox filter 25 mask" "Masked,Not masked" bitfld.long 0x00 24. " MG24 ,Mailbox filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MG23 ,Mailbox filter 23 mask" "Masked,Not masked" bitfld.long 0x00 22. " MG22 ,Mailbox filter 22 mask" "Masked,Not masked" bitfld.long 0x00 21. " MG21 ,Mailbox filter 21 mask" "Masked,Not masked" bitfld.long 0x00 20. " MG20 ,Mailbox filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MG19 ,Mailbox filter 19 mask" "Masked,Not masked" bitfld.long 0x00 18. " MG18 ,Mailbox filter 18 mask" "Masked,Not masked" bitfld.long 0x00 17. " MG17 ,Mailbox filter 17 mask" "Masked,Not masked" bitfld.long 0x00 16. " MG16 ,Mailbox filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MG15 ,Mailbox filter 15 mask" "Masked,Not masked" bitfld.long 0x00 14. " MG14 ,Mailbox filter 14 mask" "Masked,Not masked" bitfld.long 0x00 13. " MG13 ,Mailbox filter 13 mask" "Masked,Not masked" bitfld.long 0x00 12. " MG12 ,Mailbox filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MG11 ,Mailbox filter 11 mask" "Masked,Not masked" bitfld.long 0x00 10. " MG10 ,Mailbox filter 10 mask" "Masked,Not masked" bitfld.long 0x00 9. " MG9 ,Mailbox filter 9 mask" "Masked,Not masked" bitfld.long 0x00 8. " MG8 ,Mailbox filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MG7 ,Mailbox filter 7 mask" "Masked,Not masked" bitfld.long 0x00 6. " MG6 ,Mailbox filter 6 mask" "Masked,Not masked" bitfld.long 0x00 5. " MG5 ,Mailbox filter 5 mask" "Masked,Not masked" bitfld.long 0x00 4. " MG4 ,Mailbox filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MG3 ,Mailbox filter 3 mask" "Masked,Not masked" bitfld.long 0x00 2. " MG2 ,Mailbox filter 2 mask" "Masked,Not masked" bitfld.long 0x00 1. " MG1 ,Mailbox filter 1 mask" "Masked,Not masked" bitfld.long 0x00 0. " MG0 ,Mailbox filter 0 mask" "Masked,Not masked" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Mailbox 14 filter 31 mask" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Mailbox 14 filter 30 mask" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Mailbox 14 filter 29 mask" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Mailbox 14 filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Mailbox 14 filter 27 mask" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Mailbox 14 filter 26 mask" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Mailbox 14 filter 25 mask" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Mailbox 14 filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Mailbox 14 filter 23 mask" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Mailbox 14 filter 22 mask" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Mailbox 14 filter 21 mask" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Mailbox 14 filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Mailbox 14 filter 19 mask" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Mailbox 14 filter 18 mask" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Mailbox 14 filter 17 mask" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Mailbox 14 filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Mailbox 14 filter 15 mask" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Mailbox 14 filter 14 mask" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Mailbox 14 filter 13 mask" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Mailbox 14 filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Mailbox 14 filter 11 mask" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Mailbox 14 filter 10 mask" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Mailbox 14 filter 9 mask" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Mailbox 14 filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Mailbox 14 filter 7 mask" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Mailbox 14 filter 6 mask" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Mailbox 14 filter 5 mask" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Mailbox 14 filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Mailbox 14 filter 3 mask" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Mailbox 14 filter 2 mask" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Mailbox 14 filter 1 mask" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Mailbox 14 filter 0 mask" "Masked,Not masked" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Mailbox 15 filter 31 mask" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Mailbox 15 filter 30 mask" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Mailbox 15 filter 29 mask" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Mailbox 15 filter 28 mask" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Mailbox 15 filter 27 mask" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Mailbox 15 filter 26 mask" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Mailbox 15 filter 25 mask" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Mailbox 15 filter 24 mask" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Mailbox 15 filter 23 mask" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Mailbox 15 filter 22 mask" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Mailbox 15 filter 21 mask" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Mailbox 15 filter 20 mask" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Mailbox 15 filter 19 mask" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Mailbox 15 filter 18 mask" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Mailbox 15 filter 17 mask" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Mailbox 15 filter 16 mask" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Mailbox 15 filter 15 mask" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Mailbox 15 filter 14 mask" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Mailbox 15 filter 13 mask" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Mailbox 15 filter 12 mask" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Mailbox 15 filter 11 mask" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Mailbox 15 filter 10 mask" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Mailbox 15 filter 9 mask" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Mailbox 15 filter 8 mask" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Mailbox 15 filter 7 mask" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Mailbox 15 filter 6 mask" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Mailbox 15 filter 5 mask" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Mailbox 15 filter 4 mask" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Mailbox 15 filter 3 mask" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Mailbox 15 filter 2 mask" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Mailbox 15 filter 1 mask" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Mailbox 15 filter 0 mask" "Masked,Not masked" textline "" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " Rx_Err_Counter ,Receiver Error Counter" hexmask.long.byte 0x0C 0.--7. 1. " Tx_Err_Counter ,Transmitter Error Counter" line.long 0x10 "ESR1,Error and Status 1 Register" rbitfld.long 0x10 18. " SYNCH ,Synchronization between FLEXCAN and CAN bus" "Not synchronized,Synchronized" bitfld.long 0x10 17. " TWRN_INT ,Tx error counter transition from < 96 to >= 96" "Not occurred,Occurred" bitfld.long 0x10 16. " RWRN_INT ,Rx error counter transition from < 96 to >= 96" "Not occurred,Occurred" bitfld.long 0x10 15. " BIT1_ERR ,Inconsistency between the transmitted and the received bit in a message" "No error,Error" textline " " bitfld.long 0x10 14. " BIT0_ERR ,Inconsistency between the transmitted and the received bit in a message" "No error,Error" bitfld.long 0x10 13. " ACK_ERR ,Acknowledge Error detection by the transmitter node" "No error,Error" bitfld.long 0x10 12. " CRC_ERR ,CRC Error detection by the receiver node" "No error,Error" bitfld.long 0x10 11. " FRM_ERR ,Form Error detection by the receiver node" "No error,Error" textline " " bitfld.long 0x10 10. " STF_ERR ,Stuffing Error detection" "No error,Error" bitfld.long 0x10 9. " TX_WRN ,Repetitive errors during message transmission >= 96" "Not occurred,Occurred" bitfld.long 0x10 8. " RX_WRN ,Repetitive errors during message reception >= 96" "Not occurred,Occurred" bitfld.long 0x10 7. " IDLE ,IDLE state" "Not IDLE,IDLE" textline " " bitfld.long 0x10 6. " TX ,FLEXCAN message" "Receiving,Transmitting" bitfld.long 0x10 4.--5. " FLT_CONF ,Confinement State of the FLEXCAN module" "Error Active,Error Passive,Bus off,Bus off" bitfld.long 0x10 3. " RX ,FLEXCAN message" "Receiving,Transmitting" bitfld.long 0x10 2. " BOFF_INT ,FLEXCAN enters 'Bus Off' state" "Not occurred,Occurred" textline " " bitfld.long 0x10 1. " ERR_INT ,At least one of the Error Bits is set" "Not occurred,Occurred" bitfld.long 0x10 0. " WAK_INT ,Recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode" "Not occurred,Occurred" textline " " line.long 0x14 "IMASK2,Interrupt Masks 2 Register" bitfld.long 0x14 31. " BUF_M[63] ,FLEXCAN Message Buffer 63 Enable" "Disabled,Enabled" bitfld.long 0x14 30. " [62] ,FLEXCAN Message Buffer 62 Enable" "Disabled,Enabled" bitfld.long 0x14 29. " [61] ,FLEXCAN Message Buffer 61 Enable" "Disabled,Enabled" bitfld.long 0x14 28. " [60] ,FLEXCAN Message Buffer 60 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " [59] ,FLEXCAN Message Buffer 59 Enable" "Disabled,Enabled" bitfld.long 0x14 26. " [58] ,FLEXCAN Message Buffer 58 Enable" "Disabled,Enabled" bitfld.long 0x14 25. " [57] ,FLEXCAN Message Buffer 57 Enable" "Disabled,Enabled" bitfld.long 0x14 24. " [56] ,FLEXCAN Message Buffer 56 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " [55] ,FLEXCAN Message Buffer 55 Enable" "Disabled,Enabled" bitfld.long 0x14 22. " [54] ,FLEXCAN Message Buffer 54 Enable" "Disabled,Enabled" bitfld.long 0x14 21. " [53] ,FLEXCAN Message Buffer 53 Enable" "Disabled,Enabled" bitfld.long 0x14 20. " [52] ,FLEXCAN Message Buffer 52 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " [51] ,FLEXCAN Message Buffer 51 Enable" "Disabled,Enabled" bitfld.long 0x14 18. " [50] ,FLEXCAN Message Buffer 50 Enable" "Disabled,Enabled" bitfld.long 0x14 17. " [49] ,FLEXCAN Message Buffer 49 Enable" "Disabled,Enabled" bitfld.long 0x14 16. " [48] ,FLEXCAN Message Buffer 48 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " [47] ,FLEXCAN Message Buffer 47 Enable" "Disabled,Enabled" bitfld.long 0x14 14. " [46] ,FLEXCAN Message Buffer 46 Enable" "Disabled,Enabled" bitfld.long 0x14 13. " [45] ,FLEXCAN Message Buffer 45 Enable" "Disabled,Enabled" bitfld.long 0x14 12. " [44] ,FLEXCAN Message Buffer 44 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " [43] ,FLEXCAN Message Buffer 43 Enable" "Disabled,Enabled" bitfld.long 0x14 10. " [42] ,FLEXCAN Message Buffer 42 Enable" "Disabled,Enabled" bitfld.long 0x14 9. " [41] ,FLEXCAN Message Buffer 41 Enable" "Disabled,Enabled" bitfld.long 0x14 8. " [40] ,FLEXCAN Message Buffer 40 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " [39] ,FLEXCAN Message Buffer 39 Enable" "Disabled,Enabled" bitfld.long 0x14 6. " [38] ,FLEXCAN Message Buffer 38 Enable" "Disabled,Enabled" bitfld.long 0x14 5. " [37] ,FLEXCAN Message Buffer 37 Enable" "Disabled,Enabled" bitfld.long 0x14 4. " [36] ,FLEXCAN Message Buffer 36 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " [35] ,FLEXCAN Message Buffer 35 Enable" "Disabled,Enabled" bitfld.long 0x14 2. " [34] ,FLEXCAN Message Buffer 34 Enable" "Disabled,Enabled" bitfld.long 0x14 1. " [33] ,FLEXCAN Message Buffer 33 Enable" "Disabled,Enabled" bitfld.long 0x14 0. " [32] ,FLEXCAN Message Buffer 32 Enable" "Disabled,Enabled" line.long 0x18 "IMASK1,Interrupt Masks 1 Register" bitfld.long 0x18 31. " [31] ,FLEXCAN Message Buffer 31 Enable" "Disabled,Enabled" bitfld.long 0x18 30. " [30] ,FLEXCAN Message Buffer 30 Enable" "Disabled,Enabled" bitfld.long 0x18 29. " [29] ,FLEXCAN Message Buffer 29 Enable" "Disabled,Enabled" bitfld.long 0x18 28. " [28] ,FLEXCAN Message Buffer 28 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 27. " [27] ,FLEXCAN Message Buffer 27 Enable" "Disabled,Enabled" bitfld.long 0x18 26. " [26] ,FLEXCAN Message Buffer 26 Enable" "Disabled,Enabled" bitfld.long 0x18 25. " [25] ,FLEXCAN Message Buffer 25 Enable" "Disabled,Enabled" bitfld.long 0x18 24. " [24] ,FLEXCAN Message Buffer 24 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 23. " [23] ,FLEXCAN Message Buffer 23 Enable" "Disabled,Enabled" bitfld.long 0x18 22. " [22] ,FLEXCAN Message Buffer 22 Enable" "Disabled,Enabled" bitfld.long 0x18 21. " [21] ,FLEXCAN Message Buffer 21 Enable" "Disabled,Enabled" bitfld.long 0x18 20. " [20] ,FLEXCAN Message Buffer 20 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 19. " [19] ,FLEXCAN Message Buffer 19 Enable" "Disabled,Enabled" bitfld.long 0x18 18. " [18] ,FLEXCAN Message Buffer 18 Enable" "Disabled,Enabled" bitfld.long 0x18 17. " [17] ,FLEXCAN Message Buffer 17 Enable" "Disabled,Enabled" bitfld.long 0x18 16. " [16] ,FLEXCAN Message Buffer 16 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 15. " [15] ,FLEXCAN Message Buffer 15 Enable" "Disabled,Enabled" bitfld.long 0x18 14. " [14] ,FLEXCAN Message Buffer 14 Enable" "Disabled,Enabled" bitfld.long 0x18 13. " [13] ,FLEXCAN Message Buffer 13 Enable" "Disabled,Enabled" bitfld.long 0x18 12. " [12] ,FLEXCAN Message Buffer 12 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " [11] ,FLEXCAN Message Buffer 11 Enable" "Disabled,Enabled" bitfld.long 0x18 10. " [10] ,FLEXCAN Message Buffer 10 Enable" "Disabled,Enabled" bitfld.long 0x18 9. " [9] ,FLEXCAN Message Buffer 9 Enable" "Disabled,Enabled" bitfld.long 0x18 8. " [8] ,FLEXCAN Message Buffer 8 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 7. " [7] ,FLEXCAN Message Buffer 7 Enable" "Disabled,Enabled" bitfld.long 0x18 6. " [6] ,FLEXCAN Message Buffer 6 Enable" "Disabled,Enabled" bitfld.long 0x18 5. " [5] ,FLEXCAN Message Buffer 5 Enable" "Disabled,Enabled" bitfld.long 0x18 4. " [4] ,FLEXCAN Message Buffer 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " [3] ,FLEXCAN Message Buffer 3 Enable" "Disabled,Enabled" bitfld.long 0x18 2. " [2] ,FLEXCAN Message Buffer 2 Enable" "Disabled,Enabled" bitfld.long 0x18 1. " [1] ,FLEXCAN Message Buffer 1 Enable" "Disabled,Enabled" bitfld.long 0x18 0. " [0] ,FLEXCAN Message Buffer 0 Enable" "Disabled,Enabled" textline " " line.long 0x1C "IFLAG2,Interrupt Flags 2 Register" bitfld.long 0x1C 31. " BUF_I[63] ,FLEXCAN Message Buffer 63 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 30. " [62] ,FLEXCAN Message Buffer 62 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 29. " [61] ,FLEXCAN Message Buffer 61 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 28. " [60] ,FLEXCAN Message Buffer 60 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 27. " [59] ,FLEXCAN Message Buffer 59 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 26. " [58] ,FLEXCAN Message Buffer 58 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 25. " [57] ,FLEXCAN Message Buffer 57 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 24. " [56] ,FLEXCAN Message Buffer 56 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 23. " [55] ,FLEXCAN Message Buffer 55 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 22. " [54] ,FLEXCAN Message Buffer 54 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 21. " [53] ,FLEXCAN Message Buffer 53 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 20. " [52] ,FLEXCAN Message Buffer 52 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 19. " [51] ,FLEXCAN Message Buffer 51 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 18. " [50] ,FLEXCAN Message Buffer 50 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 17. " [49] ,FLEXCAN Message Buffer 49 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 16. " [48] ,FLEXCAN Message Buffer 48 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 15. " [47] ,FLEXCAN Message Buffer 47 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 14. " [46] ,FLEXCAN Message Buffer 46 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 13. " [45] ,FLEXCAN Message Buffer 45 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 12. " [44] ,FLEXCAN Message Buffer 44 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " [43] ,FLEXCAN Message Buffer 43 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 10. " [42] ,FLEXCAN Message Buffer 42 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 9. " [41] ,FLEXCAN Message Buffer 41 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 8. " [40] ,FLEXCAN Message Buffer 40 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 7. " [39] ,FLEXCAN Message Buffer 39 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 6. " [38] ,FLEXCAN Message Buffer 38 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 5. " [37] ,FLEXCAN Message Buffer 37 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 4. " [36] ,FLEXCAN Message Buffer 36 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x1C 3. " [35] ,FLEXCAN Message Buffer 35 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 2. " [34] ,FLEXCAN Message Buffer 34 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 1. " [33] ,FLEXCAN Message Buffer 33 Interrupt" "Disabled,Enabled" bitfld.long 0x1C 0. " [32] ,FLEXCAN Message Buffer 32 Interrupt" "Disabled,Enabled" line.long 0x20 "IFLAG1,Interrupt Flags 1 Register" bitfld.long 0x20 31. " [31] ,FLEXCAN Message Buffer 31 Interrupt" "Disabled,Enabled" bitfld.long 0x20 30. " [30] ,FLEXCAN Message Buffer 30 Interrupt" "Disabled,Enabled" bitfld.long 0x20 29. " [29] ,FLEXCAN Message Buffer 29 Interrupt" "Disabled,Enabled" bitfld.long 0x20 28. " [28] ,FLEXCAN Message Buffer 28 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 27. " [27] ,FLEXCAN Message Buffer 27 Interrupt" "Disabled,Enabled" bitfld.long 0x20 26. " [26] ,FLEXCAN Message Buffer 26 Interrupt" "Disabled,Enabled" bitfld.long 0x20 25. " [25] ,FLEXCAN Message Buffer 25 Interrupt" "Disabled,Enabled" bitfld.long 0x20 24. " [24] ,FLEXCAN Message Buffer 24 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 23. " [23] ,FLEXCAN Message Buffer 23 Interrupt" "Disabled,Enabled" bitfld.long 0x20 22. " [22] ,FLEXCAN Message Buffer 22 Interrupt" "Disabled,Enabled" bitfld.long 0x20 21. " [21] ,FLEXCAN Message Buffer 21 Interrupt" "Disabled,Enabled" bitfld.long 0x20 20. " [20] ,FLEXCAN Message Buffer 20 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " [19] ,FLEXCAN Message Buffer 19 Interrupt" "Disabled,Enabled" bitfld.long 0x20 18. " [18] ,FLEXCAN Message Buffer 18 Interrupt" "Disabled,Enabled" bitfld.long 0x20 17. " [17] ,FLEXCAN Message Buffer 17 Interrupt" "Disabled,Enabled" bitfld.long 0x20 16. " [16] ,FLEXCAN Message Buffer 16 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " [15] ,FLEXCAN Message Buffer 15 Interrupt" "Disabled,Enabled" bitfld.long 0x20 14. " [14] ,FLEXCAN Message Buffer 14 Interrupt" "Disabled,Enabled" bitfld.long 0x20 13. " [13] ,FLEXCAN Message Buffer 13 Interrupt" "Disabled,Enabled" bitfld.long 0x20 12. " [12] ,FLEXCAN Message Buffer 12 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " [11] ,FLEXCAN Message Buffer 11 Interrupt" "Disabled,Enabled" bitfld.long 0x20 10. " [10] ,FLEXCAN Message Buffer 10 Interrupt" "Disabled,Enabled" bitfld.long 0x20 9. " [9] ,FLEXCAN Message Buffer 9 Interrupt" "Disabled,Enabled" bitfld.long 0x20 8. " [8] ,FLEXCAN Message Buffer 8 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " [7] ,FLEXCAN Message Buffer 7 Interrupt" "Disabled,Enabled" bitfld.long 0x20 6. " [6] ,FLEXCAN Message Buffer 6 Interrupt" "Disabled,Enabled" bitfld.long 0x20 5. " [5] ,FLEXCAN Message Buffer 5 Interrupt" "Disabled,Enabled" bitfld.long 0x20 4. " [4] ,FLEXCAN Message Buffer 4 Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 3. " [3] ,FLEXCAN Message Buffer 3 Interrupt" "Disabled,Enabled" bitfld.long 0x20 2. " [2] ,FLEXCAN Message Buffer 2 Interrupt" "Disabled,Enabled" bitfld.long 0x20 1. " [1] ,FLEXCAN Message Buffer 1 Interrupt" "Disabled,Enabled" bitfld.long 0x20 0. " [0] ,FLEXCAN Message Buffer 0 Interrupt" "Disabled,Enabled" textline " " textline "" line.long 0x24 "CTRL2,Control 2 Register" bitfld.long 0x24 28. " WRMFRZ ,Unrestricted write access to FlexCAN memory" "Restricted,Unrestricted" bitfld.long 0x24 24.--27. " RFEN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x24 19.--23. " TASD ,Number of CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 18. " MRP ,Set the matching process start" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x24 17. " RRS ,Remote Request Frame" "Generated,Stored" bitfld.long 0x24 16. " EACEN ,Comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process" "Both compared,IDE only" rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest number inactive Mailbox" bitfld.long 0x00 14. " VPS ,This bit indicates whether IMB and LPTM contents are currently valid or not" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Indicates if any Mailbox is inactive" "No,Yes" textline " " rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,Number of the Mailbox corresponding to the value in TXCRC field" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC value of the last message transmitted" textline " " if ((per.l(ad:0x42094000)&0x01000000)==0x01000000) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" else rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" endif rgroup.long 0x4C++0x03 line.long 0x00 "RXFIR,Rx FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ,Identifier Acceptance Filter hit by the received message that is in the output of the Rx FIFO" group.long 0x880++0x03 line.long 0x00 "RXIMR0_RXIMR63,Rx FIFO Information Register" bitfld.long 0x00 31. " MI[31] ,Mailbox filter 31 and Rx FIFO ID Filter 31 maks" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 and Rx FIFO ID Filter 30 maks" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 and Rx FIFO ID Filter 29 maks" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 and Rx FIFO ID Filter 28 maks" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Mailbox filter 27 and Rx FIFO ID Filter 27 maks" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 and Rx FIFO ID Filter 26 maks" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 and Rx FIFO ID Filter 25 maks" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 and Rx FIFO ID Filter 24 maks" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Mailbox filter 23 and Rx FIFO ID Filter 23 maks" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 and Rx FIFO ID Filter 22 maks" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 and Rx FIFO ID Filter 21 maks" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 and Rx FIFO ID Filter 20 maks" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Mailbox filter 19 and Rx FIFO ID Filter 19 maks" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 and Rx FIFO ID Filter 18 maks" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 and Rx FIFO ID Filter 17 maks" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 and Rx FIFO ID Filter 16 maks" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Mailbox filter 15 and Rx FIFO ID Filter 15 maks" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 and Rx FIFO ID Filter 14 maks" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 and Rx FIFO ID Filter 13 maks" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 and Rx FIFO ID Filter 12 maks" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Mailbox filter 11 and Rx FIFO ID Filter 11 maks" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 and Rx FIFO ID Filter 10 maks" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 and Rx FIFO ID Filter 9 maks" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 and Rx FIFO ID Filter 8 maks" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Mailbox filter 7 and Rx FIFO ID Filter 7 maks" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 and Rx FIFO ID Filter 6 maks" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 and Rx FIFO ID Filter 5 maks" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 and Rx FIFO ID Filter 4 maks" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Mailbox filter 3 and Rx FIFO ID Filter 3 maks" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 and Rx FIFO ID Filter 2 maks" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 and Rx FIFO ID Filter 1 maks" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 and Rx FIFO ID Filter 0 maks" "Masked,Not masked" group.long 0x9E0++0x03 line.long 0x00 "GFWR,Glitch Filter Width Registers" hexmask.long.byte 0x00 0.--7. 1. " GFWR ,Determines the Glitch Filter Width" width 0x0b endif tree.end tree.end tree "GIS (General Interrupt Service)" base ad:0x02204000 width 16. tree "Control and configuration registers" group.long 0x00++0x33 line.long 0x00 "CTRL,GIS Control Register" bitfld.long 0x00 31. " SFTRST ,GIS restart" "Normal,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Disabled,Enabled" bitfld.long 0x00 8. " LCDIF1_IRQ_POLARITY ,Polarity of the IRQ assertion level" "Low,High" bitfld.long 0x00 7. " LCDIF0_IRQ_POLARITY ,Polarity of the IRQ assertion level" "Low,High" textline " " bitfld.long 0x00 6. " PXP_IRQ_POLARITY ,Clock gating" "Low,High" bitfld.long 0x00 5. " CS1_IRQ_POLARITY ,Clock gating" "Low,High" bitfld.long 0x00 4. " CS0_IRQ_POLARITY ,Clock gating" "Low,High" textline " " bitfld.long 0x00 3. " CSI_SEL ,Specifies which of the two CSI interfaces to use which interrupt to monitor" "CSI0,CSI1" bitfld.long 0x00 2. " LCDIF_SEL ,Specifies which of the two LCDIF interfaces to use, which interrupt to monitor" "LCDIF0,LCDIF1" bitfld.long 0x00 1. " FB_START ,Specifies which CSI FB finished and caused the first CSI interrupt" "FB0,FB1" bitfld.long 0x00 0. " ENABLE ,Enable the block to process interrupts" "0,1" line.long 0x04 "CTRL_SET,GIS Control Register" bitfld.long 0x04 31. " SFTRST ,GIS restart" "Normal,Reset" bitfld.long 0x04 30. " CLKGATE ,Clock gating" "Disabled,Enabled" bitfld.long 0x04 8. " LCDIF1_IRQ_POLARITY ,Polarity of the IRQ assertion level" "Low,High" bitfld.long 0x04 7. " LCDIF0_IRQ_POLARITY ,Polarity of the IRQ assertion level" "Low,High" textline " " bitfld.long 0x04 6. " PXP_IRQ_POLARITY ,Clock gating" "Low,High" bitfld.long 0x04 5. " CS1_IRQ_POLARITY ,Clock gating" "Low,High" bitfld.long 0x04 4. " CS0_IRQ_POLARITY ,Clock gating" "Low,High" textline " " bitfld.long 0x04 3. " CSI_SEL ,Specifies which of the two CSI interfaces to use which interrupt to monitor" "CSI0,CSI1" bitfld.long 0x04 2. " LCDIF_SEL ,Specifies which of the two LCDIF interfaces to use, which interrupt to monitor" "LCDIF0,LCDIF1" bitfld.long 0x04 1. " FB_START ,Specifies which CSI FB finished and caused the first CSI interrupt" "FB0,FB1" bitfld.long 0x04 0. " ENABLE ,Enable the block to process interrupts" "0,1" line.long 0x08 "CTRL_CLR,GIS Control Register" bitfld.long 0x08 31. " SFTRST ,GIS restart" "Normal,Reset" bitfld.long 0x08 30. " CLKGATE ,Clock gating" "Disabled,Enabled" bitfld.long 0x08 8. " LCDIF1_IRQ_POLARITY ,Polarity of the IRQ assertion level" "Low,High" bitfld.long 0x08 7. " LCDIF0_IRQ_POLARITY ,Polarity of the IRQ assertion level" "Low,High" textline " " bitfld.long 0x08 6. " PXP_IRQ_POLARITY ,Clock gating" "Low,High" bitfld.long 0x08 5. " CS1_IRQ_POLARITY ,Clock gating" "Low,High" bitfld.long 0x08 4. " CS0_IRQ_POLARITY ,Clock gating" "Low,High" textline " " bitfld.long 0x08 3. " CSI_SEL ,Specifies which of the two CSI interfaces to use which interrupt to monitor" "CSI0,CSI1" bitfld.long 0x08 2. " LCDIF_SEL ,Specifies which of the two LCDIF interfaces to use, which interrupt to monitor" "LCDIF0,LCDIF1" bitfld.long 0x08 1. " FB_START ,Specifies which CSI FB finished and caused the first CSI interrupt" "FB0,FB1" bitfld.long 0x08 0. " ENABLE ,Enable the block to process interrupts" "0,1" line.long 0x0C "CTRL_TOG,GIS Control Register" bitfld.long 0x0C 31. " SFTRST ,GIS restart" "Normal,Reset" bitfld.long 0x0C 30. " CLKGATE ,Clock gating" "Disabled,Enabled" bitfld.long 0x0C 8. " LCDIF1_IRQ_POLARITY ,Polarity of the IRQ assertion level" "Low,High" bitfld.long 0x0C 7. " LCDIF0_IRQ_POLARITY ,Polarity of the IRQ assertion level" "Low,High" textline " " bitfld.long 0x0C 6. " PXP_IRQ_POLARITY ,Clock gating" "Low,High" bitfld.long 0x0C 5. " CS1_IRQ_POLARITY ,Clock gating" "Low,High" bitfld.long 0x0C 4. " CS0_IRQ_POLARITY ,Clock gating" "Low,High" textline " " bitfld.long 0x0C 3. " CSI_SEL ,Specifies which of the two CSI interfaces to use which interrupt to monitor" "CSI0,CSI1" bitfld.long 0x0C 2. " LCDIF_SEL ,Specifies which of the two LCDIF interfaces to use, which interrupt to monitor" "LCDIF0,LCDIF1" bitfld.long 0x0C 1. " FB_START ,Specifies which CSI FB finished and caused the first CSI interrupt" "FB0,FB1" bitfld.long 0x0C 0. " ENABLE ,Enable the block to process interrupts" "0,1" textline "" line.long 0x10 "CONFIG0,GIS Configuration 0 Register" bitfld.long 0x10 27.--29. " CH3_NUM ,Number of valid commands to execute for channel 3" "0,1,2,3,4,,," bitfld.long 0x10 24.--26. " CH3_MAPPING ,Command channel2 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x10 19.--21. " CH2_NUM ,Number of valid commands to execute for channel 3" "0,1,2,3,4,,," bitfld.long 0x10 16.--18. " CH2_MAPPING ,Command channel2 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " bitfld.long 0x10 11.--13. " CH1_NUM ,Number of valid commands to execute for channel 1" "0,1,2,3,4,,," bitfld.long 0x10 8.--10. " CH1_MAPPING ,Command channel1 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x10 3.--5. " CH0_NUM ,Number of valid commands to execute for channel 0" "0,1,2,3,4,,," bitfld.long 0x10 0.--2. " CH0_MAPPING ,Command channel0 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" line.long 0x14 "CONFIG0_SET,GIS Configuration 0 Register" bitfld.long 0x14 27.--29. " CH3_NUM ,Number of valid commands to execute for channel 3" "0,1,2,3,4,,," bitfld.long 0x14 24.--26. " CH3_MAPPING ,Command channel2 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x14 19.--21. " CH2_NUM ,Number of valid commands to execute for channel 3" "0,1,2,3,4,,," bitfld.long 0x14 16.--18. " CH2_MAPPING ,Command channel2 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " bitfld.long 0x14 11.--13. " CH1_NUM ,Number of valid commands to execute for channel 1" "0,1,2,3,4,,," bitfld.long 0x14 8.--10. " CH1_MAPPING ,Command channel1 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x14 3.--5. " CH0_NUM ,Number of valid commands to execute for channel 0" "0,1,2,3,4,,," bitfld.long 0x14 0.--2. " CH0_MAPPING ,Command channel0 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " line.long 0x18 "CONFIG0_CLR,GIS Configuration 0 Register" bitfld.long 0x18 27.--29. " CH3_NUM ,Number of valid commands to execute for channel 3" "0,1,2,3,4,,," bitfld.long 0x18 24.--26. " CH3_MAPPING ,Command channel2 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x18 19.--21. " CH2_NUM ,Number of valid commands to execute for channel 3" "0,1,2,3,4,,," bitfld.long 0x18 16.--18. " CH2_MAPPING ,Command channel2 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " bitfld.long 0x18 11.--13. " CH1_NUM ,Number of valid commands to execute for channel 1" "0,1,2,3,4,,," bitfld.long 0x18 8.--10. " CH1_MAPPING ,Command channel1 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x18 3.--5. " CH0_NUM ,Number of valid commands to execute for channel 0" "0,1,2,3,4,,," bitfld.long 0x18 0.--2. " CH0_MAPPING ,Command channel0 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " line.long 0x1C "CONFG0I_TOG,GIS Configuration 0 Register" bitfld.long 0x1C 27.--29. " CH3_NUM ,Number of valid commands to execute for channel 3" "0,1,2,3,4,,," bitfld.long 0x1C 24.--26. " CH3_MAPPING ,Command channel2 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x1C 19.--21. " CH2_NUM ,Number of valid commands to execute for channel 3" "0,1,2,3,4,,," bitfld.long 0x1C 16.--18. " CH2_MAPPING ,Command channel2 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " bitfld.long 0x1C 11.--13. " CH1_NUM ,Number of valid commands to execute for channel 1" "0,1,2,3,4,,," bitfld.long 0x1C 8.--10. " CH1_MAPPING ,Command channel1 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x1C 3.--5. " CH0_NUM ,Number of valid commands to execute for channel 0" "0,1,2,3,4,,," bitfld.long 0x1C 0.--2. " CH0_MAPPING ,Command channel0 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " line.long 0x20 "CONFIG1,GIS Configuration 1 Register" bitfld.long 0x20 11.--13. " CH5_NUM ,Number of valid commands to execute for channel 5" "0,1,2,3,4,,," bitfld.long 0x20 8.--10. " CH5_MAPPING ,Command channel5 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x20 3.--5. " CH4_NUM ,Number of valid commands to execute for channel 4" "0,1,2,3,4,,," bitfld.long 0x20 0.--2. " CH4_MAPPING ,Command channel4 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " line.long 0x24 "CONFIG1_SET,GIS Configuration 1 Register" bitfld.long 0x24 11.--13. " CH5_NUM ,Number of valid commands to execute for channel 5" "0,1,2,3,4,,," bitfld.long 0x24 8.--10. " CH5_MAPPING ,Command channel5 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x24 3.--5. " CH4_NUM ,Number of valid commands to execute for channel 4" "0,1,2,3,4,,," bitfld.long 0x24 0.--2. " CH4_MAPPING ,Command channel4 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " line.long 0x28 "CONFIG1_CLR,GIS Configuration 1 Register" bitfld.long 0x28 11.--13. " CH5_NUM ,Number of valid commands to execute for channel 5" "0,1,2,3,4,,," bitfld.long 0x28 8.--10. " CH5_MAPPING ,Command channel5 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x28 3.--5. " CH4_NUM ,Number of valid commands to execute for channel 4" "0,1,2,3,4,,," bitfld.long 0x28 0.--2. " CH4_MAPPING ,Command channel4 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " line.long 0x2C "CONFG1I_TOG,GIS Configuration 1 Register" bitfld.long 0x2C 11.--13. " CH5_NUM ,Number of valid commands to execute for channel 5" "0,1,2,3,4,,," bitfld.long 0x2C 8.--10. " CH5_MAPPING ,Command channel5 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" bitfld.long 0x2C 3.--5. " CH4_NUM ,Number of valid commands to execute for channel 4" "0,1,2,3,4,,," bitfld.long 0x2C 0.--2. " CH4_MAPPING ,Command channel4 assignment" "CSI_ISR,CSI_FB_UPDATE,PXP_ISR,LCDIF_FB_UPDATE,PXP_KICK,,,UNUSED" textline " " line.long 0x30 "GIS_FB0,Camera Frame Buffer Address 0 Register" group.long 0x40++0x03 line.long 0x00 "GIS_FB1,Camera Frame Buffer Address 1 Register" textline " " group.long 0x50++0x03 line.long 0x00 "PXP_FB0,PXP Frame Buffer Address 0 Register" textline " " group.long 0x60++0x03 line.long 0x00 "PXP_FB1,PXP Frame Buffer Address 1 Register" tree.end tree "Channel 0" group.long (0x70+0x0)++0x23 line.long 0x00 "CH0_CTRL,Control Command Channel 0 Register" bitfld.long 0x00 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x04 "CH0_CTRL_SET,Control Command Channel 0 Register" bitfld.long 0x04 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x08 "CH0_CTRL_CLR,Control Command Channel 0 Register" bitfld.long 0x08 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x0C "CH0_CTRL_TOG,Control Command Channel 0 Register" bitfld.long 0x0C 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " line.long 0x10 "CH0_ADDR0,Channel 0 Command 0 Address Register" bitfld.long 0x10 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x10 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x14 "CH0_ADDR0_SET,Channel 0 Command 0 Address Register" bitfld.long 0x14 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x14 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x14 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x18 "CH0_ADDR0_CLR,Channel 0 Command 0 Address Register" bitfld.long 0x18 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x18 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x18 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x1C "CH0_ADDR0_TOG,Channel 0 Command 0 Address Register" bitfld.long 0x1C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x1C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x1C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x20 "CH0_DATA0,Channel 0 Command 0 Data Register" group.long (0xA0+0x0)++0x13 line.long 0x00 "CH0_ADDR1,Channel 0 Command 1 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH0_ADDR1_SET,Channel 0 Command 1 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH0_ADDR1_CLR,Channel 0 Command 1 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH0_ADDR1_TOG,Channel 0 Command 1 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH0_DATA1,Channel 0 Command 1 Data Register" group.long (0xC0+0x0)++0x13 line.long 0x00 "CH0_ADDR2,Channel 0 Command 2 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH0_ADDR2_SET,Channel 0 Command 2 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH0_ADDR2_CLR,Channel 0 Command 2 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH0_ADDR2_TOG,Channel 0 Command 2 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH0_DATA2,Channel 0 Command 2 Data Register" group.long (0xE0+0x0)++0x13 line.long 0x00 "CH0_ADDR3,Channel 0 Command 3 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH0_ADDR3_SET,Channel 0 Command 3 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH0_ADDR3_CLR,Channel 0 Command 3 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH0_ADDR3_TOG,Channel 0 Command 3 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH0_DATA3,Channel 0 Command 3 Data Register" tree.end tree "Channel 1" group.long (0x70+0x90)++0x23 line.long 0x00 "CH1_CTRL,Control Command Channel 1 Register" bitfld.long 0x00 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x04 "CH1_CTRL_SET,Control Command Channel 1 Register" bitfld.long 0x04 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x08 "CH1_CTRL_CLR,Control Command Channel 1 Register" bitfld.long 0x08 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x0C "CH1_CTRL_TOG,Control Command Channel 1 Register" bitfld.long 0x0C 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " line.long 0x10 "CH1_ADDR0,Channel 1 Command 0 Address Register" bitfld.long 0x10 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x10 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x14 "CH1_ADDR0_SET,Channel 1 Command 0 Address Register" bitfld.long 0x14 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x14 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x14 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x18 "CH1_ADDR0_CLR,Channel 1 Command 0 Address Register" bitfld.long 0x18 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x18 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x18 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x1C "CH1_ADDR0_TOG,Channel 1 Command 0 Address Register" bitfld.long 0x1C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x1C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x1C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x20 "CH1_DATA0,Channel 1 Command 0 Data Register" group.long (0xA0+0x90)++0x13 line.long 0x00 "CH1_ADDR1,Channel 1 Command 1 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH1_ADDR1_SET,Channel 1 Command 1 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH1_ADDR1_CLR,Channel 1 Command 1 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH1_ADDR1_TOG,Channel 1 Command 1 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH1_DATA1,Channel 1 Command 1 Data Register" group.long (0xC0+0x90)++0x13 line.long 0x00 "CH1_ADDR2,Channel 1 Command 2 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH1_ADDR2_SET,Channel 1 Command 2 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH1_ADDR2_CLR,Channel 1 Command 2 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH1_ADDR2_TOG,Channel 1 Command 2 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH1_DATA2,Channel 1 Command 2 Data Register" group.long (0xE0+0x90)++0x13 line.long 0x00 "CH1_ADDR3,Channel 1 Command 3 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH1_ADDR3_SET,Channel 1 Command 3 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH1_ADDR3_CLR,Channel 1 Command 3 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH1_ADDR3_TOG,Channel 1 Command 3 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH1_DATA3,Channel 1 Command 3 Data Register" tree.end tree "Channel 2" group.long (0x70+0x120)++0x23 line.long 0x00 "CH2_CTRL,Control Command Channel 2 Register" bitfld.long 0x00 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x04 "CH2_CTRL_SET,Control Command Channel 2 Register" bitfld.long 0x04 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x08 "CH2_CTRL_CLR,Control Command Channel 2 Register" bitfld.long 0x08 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x0C "CH2_CTRL_TOG,Control Command Channel 2 Register" bitfld.long 0x0C 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " line.long 0x10 "CH2_ADDR0,Channel 2 Command 0 Address Register" bitfld.long 0x10 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x10 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x14 "CH2_ADDR0_SET,Channel 2 Command 0 Address Register" bitfld.long 0x14 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x14 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x14 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x18 "CH2_ADDR0_CLR,Channel 2 Command 0 Address Register" bitfld.long 0x18 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x18 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x18 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x1C "CH2_ADDR0_TOG,Channel 2 Command 0 Address Register" bitfld.long 0x1C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x1C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x1C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x20 "CH2_DATA0,Channel 2 Command 0 Data Register" group.long (0xA0+0x120)++0x13 line.long 0x00 "CH2_ADDR1,Channel 2 Command 1 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH2_ADDR1_SET,Channel 2 Command 1 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH2_ADDR1_CLR,Channel 2 Command 1 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH2_ADDR1_TOG,Channel 2 Command 1 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH2_DATA1,Channel 2 Command 1 Data Register" group.long (0xC0+0x120)++0x13 line.long 0x00 "CH2_ADDR2,Channel 2 Command 2 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH2_ADDR2_SET,Channel 2 Command 2 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH2_ADDR2_CLR,Channel 2 Command 2 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH2_ADDR2_TOG,Channel 2 Command 2 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH2_DATA2,Channel 2 Command 2 Data Register" group.long (0xE0+0x120)++0x13 line.long 0x00 "CH2_ADDR3,Channel 2 Command 3 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH2_ADDR3_SET,Channel 2 Command 3 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH2_ADDR3_CLR,Channel 2 Command 3 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH2_ADDR3_TOG,Channel 2 Command 3 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH2_DATA3,Channel 2 Command 3 Data Register" tree.end tree "Channel 3" group.long (0x70+0x1B0)++0x23 line.long 0x00 "CH3_CTRL,Control Command Channel 3 Register" bitfld.long 0x00 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x04 "CH3_CTRL_SET,Control Command Channel 3 Register" bitfld.long 0x04 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x08 "CH3_CTRL_CLR,Control Command Channel 3 Register" bitfld.long 0x08 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x0C "CH3_CTRL_TOG,Control Command Channel 3 Register" bitfld.long 0x0C 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " line.long 0x10 "CH3_ADDR0,Channel 3 Command 0 Address Register" bitfld.long 0x10 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x10 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x14 "CH3_ADDR0_SET,Channel 3 Command 0 Address Register" bitfld.long 0x14 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x14 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x14 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x18 "CH3_ADDR0_CLR,Channel 3 Command 0 Address Register" bitfld.long 0x18 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x18 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x18 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x1C "CH3_ADDR0_TOG,Channel 3 Command 0 Address Register" bitfld.long 0x1C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x1C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x1C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x20 "CH3_DATA0,Channel 3 Command 0 Data Register" group.long (0xA0+0x1B0)++0x13 line.long 0x00 "CH3_ADDR1,Channel 3 Command 1 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH3_ADDR1_SET,Channel 3 Command 1 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH3_ADDR1_CLR,Channel 3 Command 1 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH3_ADDR1_TOG,Channel 3 Command 1 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH3_DATA1,Channel 3 Command 1 Data Register" group.long (0xC0+0x1B0)++0x13 line.long 0x00 "CH3_ADDR2,Channel 3 Command 2 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH3_ADDR2_SET,Channel 3 Command 2 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH3_ADDR2_CLR,Channel 3 Command 2 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH3_ADDR2_TOG,Channel 3 Command 2 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH3_DATA2,Channel 3 Command 2 Data Register" group.long (0xE0+0x1B0)++0x13 line.long 0x00 "CH3_ADDR3,Channel 3 Command 3 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH3_ADDR3_SET,Channel 3 Command 3 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH3_ADDR3_CLR,Channel 3 Command 3 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH3_ADDR3_TOG,Channel 3 Command 3 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH3_DATA3,Channel 3 Command 3 Data Register" tree.end tree "Channel 4" group.long (0x70+0x240)++0x23 line.long 0x00 "CH4_CTRL,Control Command Channel 4 Register" bitfld.long 0x00 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x04 "CH4_CTRL_SET,Control Command Channel 4 Register" bitfld.long 0x04 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x08 "CH4_CTRL_CLR,Control Command Channel 4 Register" bitfld.long 0x08 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x0C "CH4_CTRL_TOG,Control Command Channel 4 Register" bitfld.long 0x0C 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " line.long 0x10 "CH4_ADDR0,Channel 4 Command 0 Address Register" bitfld.long 0x10 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x10 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x14 "CH4_ADDR0_SET,Channel 4 Command 0 Address Register" bitfld.long 0x14 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x14 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x14 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x18 "CH4_ADDR0_CLR,Channel 4 Command 0 Address Register" bitfld.long 0x18 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x18 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x18 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x1C "CH4_ADDR0_TOG,Channel 4 Command 0 Address Register" bitfld.long 0x1C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x1C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x1C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x20 "CH4_DATA0,Channel 4 Command 0 Data Register" group.long (0xA0+0x240)++0x13 line.long 0x00 "CH4_ADDR1,Channel 4 Command 1 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH4_ADDR1_SET,Channel 4 Command 1 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH4_ADDR1_CLR,Channel 4 Command 1 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH4_ADDR1_TOG,Channel 4 Command 1 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH4_DATA1,Channel 4 Command 1 Data Register" group.long (0xC0+0x240)++0x13 line.long 0x00 "CH4_ADDR2,Channel 4 Command 2 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH4_ADDR2_SET,Channel 4 Command 2 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH4_ADDR2_CLR,Channel 4 Command 2 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH4_ADDR2_TOG,Channel 4 Command 2 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH4_DATA2,Channel 4 Command 2 Data Register" group.long (0xE0+0x240)++0x13 line.long 0x00 "CH4_ADDR3,Channel 4 Command 3 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH4_ADDR3_SET,Channel 4 Command 3 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH4_ADDR3_CLR,Channel 4 Command 3 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH4_ADDR3_TOG,Channel 4 Command 3 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH4_DATA3,Channel 4 Command 3 Data Register" tree.end tree "Channel 5" group.long (0x70+0x2D0)++0x23 line.long 0x00 "CH5_CTRL,Control Command Channel 5 Register" bitfld.long 0x00 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x00 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x00 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x00 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x04 "CH5_CTRL_SET,Control Command Channel 5 Register" bitfld.long 0x04 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x04 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x04 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x04 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x08 "CH5_CTRL_CLR,Control Command Channel 5 Register" bitfld.long 0x08 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x08 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x08 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x08 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," line.long 0x0C "CH5_CTRL_TOG,Control Command Channel 5 Register" bitfld.long 0x0C 31. " CMD3_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 28.--30. " CMD3_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 24.--27. " CMD3_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 23. " CMD2_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 20.--22. " CMD2_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 16.--19. " CMD2_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 15. " CMD1_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 12.--14. " CMD1_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 8.--11. " CMD1_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " bitfld.long 0x0C 7. " CMD0_ACC_NEG ,This bit specifies if the accumulator value should be to negated before it is used in the command" "No negation,Negation specified" bitfld.long 0x0C 4.--6. " CMD0_ALU ,Operation for the ALU when combining the accumulator and the data bits" "AND,OR,XOR,ADD,SUB,,," bitfld.long 0x0C 0.--3. " CMD0_OPCODE ,This field specifies the opcode to go along with the address and data values for this command" "SET_ACC,WR_DATA,WR_ACC,WR_ALU,MOV_ACC,RD_DATA,RD_ALU,WR_FB_CSI,WR_FB_PXP_IN,WR_FB_PXP_OUT,WR_FB_LCDIC,,,,," textline " " line.long 0x10 "CH5_ADDR0,Channel 5 Command 0 Address Register" bitfld.long 0x10 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x10 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x10 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x14 "CH5_ADDR0_SET,Channel 5 Command 0 Address Register" bitfld.long 0x14 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x14 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x14 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x14 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x18 "CH5_ADDR0_CLR,Channel 5 Command 0 Address Register" bitfld.long 0x18 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x18 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x18 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x18 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x1C "CH5_ADDR0_TOG,Channel 5 Command 0 Address Register" bitfld.long 0x1C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x1C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x1C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x1C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x20 "CH5_DATA0,Channel 5 Command 0 Data Register" group.long (0xA0+0x2D0)++0x13 line.long 0x00 "CH5_ADDR1,Channel 5 Command 1 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH5_ADDR1_SET,Channel 5 Command 1 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH5_ADDR1_CLR,Channel 5 Command 1 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH5_ADDR1_TOG,Channel 5 Command 1 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH5_DATA1,Channel 5 Command 1 Data Register" group.long (0xC0+0x2D0)++0x13 line.long 0x00 "CH5_ADDR2,Channel 5 Command 2 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH5_ADDR2_SET,Channel 5 Command 2 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH5_ADDR2_CLR,Channel 5 Command 2 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH5_ADDR2_TOG,Channel 5 Command 2 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH5_DATA2,Channel 5 Command 2 Data Register" group.long (0xE0+0x2D0)++0x13 line.long 0x00 "CH5_ADDR3,Channel 5 Command 3 Address Register" bitfld.long 0x00 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x00 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x00 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x04 "CH5_ADDR3_SET,Channel 5 Command 3 Address Register" bitfld.long 0x04 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x04 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x04 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x08 "CH5_ADDR3_CLR,Channel 5 Command 3 Address Register" bitfld.long 0x08 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x08 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x08 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x0C "CH5_ADDR3_TOG,Channel 5 Command 3 Address Register" bitfld.long 0x0C 31. " LCDIF1_SEL ,LCDIF1 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 30. " LCDIF0_SEL ,LCDIF0 block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 29. " PXP_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " CSI1_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" bitfld.long 0x0C 27. " CSI0_SEL ,PXP block as the target if this command will access the bus" "Disabled,Enabled" hexmask.long 0x0C 0.--26. 1. " ADDR ,32 bit address of command" line.long 0x10 "CH5_DATA3,Channel 5 Command 3 Data Register" tree.end tree "Debug and Info registers" rgroup.long 0x3D0++0x03 line.long 0x00 "DEBUG0,Debug 0 Register" bitfld.long 0x00 28.--29. " CSI_FB_REG ,Current frame buffer register" "0,1,2,3" bitfld.long 0x00 27. " CSI_IRQ ,State of main state machine" "0,1" bitfld.long 0x00 26. " PXP_IRQ ,PXP interrupt pending" "0,1" bitfld.long 0x00 25. " PXP_BUSY ,PXP busy signal" "0,1" textline " " bitfld.long 0x00 21.--24. " CMD_OPCODE ,Opcode for the current command" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F" bitfld.long 0x00 18.--20. " CMD_COUNTER ,Command count for current channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--17. " CHANNEL_CUR ,Current channel executing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--13. 1. " MAIN_STATE ,Main state machine state" hexmask.long.byte 0x00 0.--7. 1. " CMD_STATE ,Command state machine state" rgroup.long 0x3E0++0x03 line.long 0x00 "DEBUG1,Debug 1 Register" bitfld.long 0x00 18.--19. " LCDIF_FB ,Current frame buffer" "0,1,2,3" bitfld.long 0x00 16.--17. " PXP_IN_FB ,Current frame buffer" "0,1,2,3" textline " " hexmask.long.byte 0x00 8.--15. 1. " PXP_OUT_FB ,Current frame buffer" hexmask.long.byte 0x00 0.--7. 1. " CSI_FB ,Current frame buffer" rgroup.long 0x3F0++0x03 line.long 0x00 "VERSION,Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Stepping of the RTL version" tree.end width 12. tree.end tree "GPC (General Power Controller)" tree "GPC (General Power Controller)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020DC000 else base ad:0x420DC000 endif width 8. group.long 0x00++0x17 line.long 0x00 "CNTR,GPC Interface control register" bitfld.long 0x00 22. " L2_PGE ,L2 Cache Power Gate" "Disabled,Enabled" bitfld.long 0x00 21. " GPCIRQM ,GPC interrupt/event masking" "Not masked,Masked" bitfld.long 0x00 18. " VADC_EXT_PWD_N ,VADC power down" "Power down,Power up" bitfld.long 0x00 17. " VADC_ANALOG_OFF ,The analog power to VADC" "Available,Not available" textline " " rbitfld.long 0x00 16. " DVFS0CR ,DVFS0 request for frequency/voltage update" "Not requested,Requested" bitfld.long 0x00 7. " PCIE_PHY_PUP_REQ ,PCIE PHY power up request" "Not requested,Requested" bitfld.long 0x00 6. " PCIE_PHY_PDN_REQ ,PCIE PHY power down request" "Not requested,Requested" bitfld.long 0x00 5. " DISPLAY_PUP_REQ ,Display Power Up request" "Not requested,Requested" textline " " bitfld.long 0x00 4. " DISPLAY_PDN_REQ ,Display Power Down request" "Not requested,Requested" bitfld.long 0x00 3. " MEGA_PUP_REQ ,MEGA domain power up request" "Not requested,Requested" bitfld.long 0x00 2. " MEGA_PDN_REQ ,MEGA domain power down request" "Not requested,Requested" bitfld.long 0x00 1. " GPU_VPU_PUP_REQ ,GPU Power Up request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " GPU_VPU_PDN_REQ ,GPU Power Down request" "Not requested,Requested" line.long 0x04 "PGR,GPC Power Gating Register" bitfld.long 0x04 29.--30. " DRCIC ,Debug ref cir in mux control" "ccm_cosr_1_clk_in,ccm_cosr_2_clk_in,?..." textline "" line.long 0x08 "IMR1,IRQ masking register 1" bitfld.long 0x08 31. " IRQ[63] ,Masking of IRQ 63" "Not masked,Masked" bitfld.long 0x08 30. " [62] ,Masking of IRQ 62" "Not masked,Masked" bitfld.long 0x08 29. " [61] ,Masking of IRQ 61" "Not masked,Masked" bitfld.long 0x08 28. " [60] ,Masking of IRQ 60" "Not masked,Masked" textline " " bitfld.long 0x08 27. " [59] ,Masking of IRQ 59" "Not masked,Masked" bitfld.long 0x08 26. " [58] ,Masking of IRQ 58" "Not masked,Masked" bitfld.long 0x08 25. " [57] ,Masking of IRQ 57" "Not masked,Masked" bitfld.long 0x08 24. " [56] ,Masking of IRQ 56" "Not masked,Masked" textline " " bitfld.long 0x08 23. " [55] ,Masking of IRQ 55" "Not masked,Masked" bitfld.long 0x08 22. " [54] ,Masking of IRQ 54" "Not masked,Masked" bitfld.long 0x08 21. " [53] ,Masking of IRQ 53" "Not masked,Masked" bitfld.long 0x08 20. " [52] ,Masking of IRQ 52" "Not masked,Masked" textline " " bitfld.long 0x08 19. " [51] ,Masking of IRQ 51" "Not masked,Masked" bitfld.long 0x08 18. " [50] ,Masking of IRQ 50" "Not masked,Masked" bitfld.long 0x08 17. " [49] ,Masking of IRQ 49" "Not masked,Masked" bitfld.long 0x08 16. " [48] ,Masking of IRQ 48" "Not masked,Masked" textline " " bitfld.long 0x08 15. " [47] ,Masking of IRQ 47" "Not masked,Masked" bitfld.long 0x08 14. " [46] ,Masking of IRQ 46" "Not masked,Masked" bitfld.long 0x08 13. " [45] ,Masking of IRQ 45" "Not masked,Masked" bitfld.long 0x08 12. " [44] ,Masking of IRQ 44" "Not masked,Masked" textline " " bitfld.long 0x08 11. " [43] ,Masking of IRQ 43" "Not masked,Masked" bitfld.long 0x08 10. " [42] ,Masking of IRQ 42" "Not masked,Masked" bitfld.long 0x08 9. " [41] ,Masking of IRQ 41" "Not masked,Masked" bitfld.long 0x08 8. " [40] ,Masking of IRQ 40" "Not masked,Masked" textline " " bitfld.long 0x08 7. " [39] ,Masking of IRQ 39" "Not masked,Masked" bitfld.long 0x08 6. " [38] ,Masking of IRQ 38" "Not masked,Masked" bitfld.long 0x08 5. " [37] ,Masking of IRQ 37" "Not masked,Masked" bitfld.long 0x08 4. " [36] ,Masking of IRQ 36" "Not masked,Masked" textline " " bitfld.long 0x08 3. " [35] ,Masking of IRQ 35" "Not masked,Masked" bitfld.long 0x08 2. " [34] ,Masking of IRQ 34" "Not masked,Masked" bitfld.long 0x08 1. " [33] ,Masking of IRQ 33" "Not masked,Masked" bitfld.long 0x08 0. " [32] ,Masking of IRQ 32" "Not masked,Masked" line.long 0x0C "IMR2,IRQ masking register 2" bitfld.long 0x0C 31. " [95] ,Masking of IRQ 95" "Not masked,Masked" bitfld.long 0x0C 30. " [94] ,Masking of IRQ 94" "Not masked,Masked" bitfld.long 0x0C 29. " [93] ,Masking of IRQ 93" "Not masked,Masked" bitfld.long 0x0C 28. " [92] ,Masking of IRQ 92" "Not masked,Masked" textline " " bitfld.long 0x0C 27. " [91] ,Masking of IRQ 91" "Not masked,Masked" bitfld.long 0x0C 26. " [90] ,Masking of IRQ 90" "Not masked,Masked" bitfld.long 0x0C 25. " [89] ,Masking of IRQ 89" "Not masked,Masked" bitfld.long 0x0C 24. " [88] ,Masking of IRQ 88" "Not masked,Masked" textline " " bitfld.long 0x0C 23. " [87] ,Masking of IRQ 87" "Not masked,Masked" bitfld.long 0x0C 22. " [86] ,Masking of IRQ 86" "Not masked,Masked" bitfld.long 0x0C 21. " [85] ,Masking of IRQ 85" "Not masked,Masked" bitfld.long 0x0C 20. " [84] ,Masking of IRQ 84" "Not masked,Masked" textline " " bitfld.long 0x0C 19. " [83] ,Masking of IRQ 83" "Not masked,Masked" bitfld.long 0x0C 18. " [82] ,Masking of IRQ 82" "Not masked,Masked" bitfld.long 0x0C 17. " [81] ,Masking of IRQ 81" "Not masked,Masked" bitfld.long 0x0C 16. " [80] ,Masking of IRQ 80" "Not masked,Masked" textline " " bitfld.long 0x0C 15. " [79] ,Masking of IRQ 79" "Not masked,Masked" bitfld.long 0x0C 14. " [78] ,Masking of IRQ 78" "Not masked,Masked" bitfld.long 0x0C 13. " [77] ,Masking of IRQ 77" "Not masked,Masked" bitfld.long 0x0C 12. " [76] ,Masking of IRQ 76" "Not masked,Masked" textline " " bitfld.long 0x0C 11. " [75] ,Masking of IRQ 75" "Not masked,Masked" bitfld.long 0x0C 10. " [74] ,Masking of IRQ 74" "Not masked,Masked" bitfld.long 0x0C 9. " [73] ,Masking of IRQ 73" "Not masked,Masked" bitfld.long 0x0C 8. " [72] ,Masking of IRQ 72" "Not masked,Masked" textline " " bitfld.long 0x0C 7. " [71] ,Masking of IRQ 71" "Not masked,Masked" bitfld.long 0x0C 6. " [70] ,Masking of IRQ 70" "Not masked,Masked" bitfld.long 0x0C 5. " [69] ,Masking of IRQ 69" "Not masked,Masked" bitfld.long 0x0C 4. " [68] ,Masking of IRQ 68" "Not masked,Masked" textline " " bitfld.long 0x0C 3. " [67] ,Masking of IRQ 67" "Not masked,Masked" bitfld.long 0x0C 2. " [66] ,Masking of IRQ 66" "Not masked,Masked" bitfld.long 0x0C 1. " [65] ,Masking of IRQ 65" "Not masked,Masked" bitfld.long 0x0C 0. " [64] ,Masking of IRQ 64" "Not masked,Masked" line.long 0x10 "IMR3,IRQ masking register 3" bitfld.long 0x10 31. " [127] ,Masking of IRQ 127" "Not masked,Masked" bitfld.long 0x10 30. " [126] ,Masking of IRQ 126" "Not masked,Masked" bitfld.long 0x10 29. " [125] ,Masking of IRQ 125" "Not masked,Masked" bitfld.long 0x10 28. " [124] ,Masking of IRQ 124" "Not masked,Masked" textline " " bitfld.long 0x10 27. " [123] ,Masking of IRQ 123" "Not masked,Masked" bitfld.long 0x10 26. " [122] ,Masking of IRQ 122" "Not masked,Masked" bitfld.long 0x10 25. " [121] ,Masking of IRQ 121" "Not masked,Masked" bitfld.long 0x10 24. " [120] ,Masking of IRQ 120" "Not masked,Masked" textline " " bitfld.long 0x10 23. " [119] ,Masking of IRQ 119" "Not masked,Masked" bitfld.long 0x10 22. " [118] ,Masking of IRQ 118" "Not masked,Masked" bitfld.long 0x10 21. " [117] ,Masking of IRQ 117" "Not masked,Masked" bitfld.long 0x10 20. " [116] ,Masking of IRQ 116" "Not masked,Masked" textline " " bitfld.long 0x10 19. " [115 ,Masking of IRQ 115" "Not masked,Masked" bitfld.long 0x10 18. " [114] ,Masking of IRQ 114" "Not masked,Masked" bitfld.long 0x10 17. " [113] ,Masking of IRQ 113" "Not masked,Masked" bitfld.long 0x10 16. " [112] ,Masking of IRQ 112" "Not masked,Masked" textline " " bitfld.long 0x10 15. " [111] ,Masking of IRQ 111" "Not masked,Masked" bitfld.long 0x10 14. " [110] ,Masking of IRQ 110" "Not masked,Masked" bitfld.long 0x10 13. " [109] ,Masking of IRQ 109" "Not masked,Masked" bitfld.long 0x10 12. " [108] ,Masking of IRQ 108" "Not masked,Masked" textline " " bitfld.long 0x10 11. " [107] ,Masking of IRQ 107" "Not masked,Masked" bitfld.long 0x10 10. " [106] ,Masking of IRQ 106" "Not masked,Masked" bitfld.long 0x10 9. " [105] ,Masking of IRQ 105" "Not masked,Masked" bitfld.long 0x10 8. " [104] ,Masking of IRQ 104" "Not masked,Masked" textline " " bitfld.long 0x10 7. " [103] ,Masking of IRQ 103" "Not masked,Masked" bitfld.long 0x10 6. " [102] ,Masking of IRQ 102" "Not masked,Masked" bitfld.long 0x10 5. " [101] ,Masking of IRQ 101" "Not masked,Masked" bitfld.long 0x10 4. " [100] ,Masking of IRQ 100" "Not masked,Masked" textline " " bitfld.long 0x10 3. " [99] ,Masking of IRQ 99" "Not masked,Masked" bitfld.long 0x10 2. " [98] ,Masking of IRQ 98" "Not masked,Masked" bitfld.long 0x10 1. " [97] ,Masking of IRQ 97" "Not masked,Masked" bitfld.long 0x10 0. " [96] ,Masking of IRQ 96" "Not masked,Masked" line.long 0x14 "IMR4,IRQ masking register 4" bitfld.long 0x14 31. " [159] ,Masking of IRQ 159" "Not masked,Masked" bitfld.long 0x14 30. " [158] ,Masking of IRQ 158" "Not masked,Masked" bitfld.long 0x14 29. " [157] ,Masking of IRQ 157" "Not masked,Masked" bitfld.long 0x14 28. " [156] ,Masking of IRQ 156" "Not masked,Masked" textline " " bitfld.long 0x14 27. " [155] ,Masking of IRQ 155" "Not masked,Masked" bitfld.long 0x14 26. " [154] ,Masking of IRQ 154" "Not masked,Masked" bitfld.long 0x14 25. " [153] ,Masking of IRQ 153" "Not masked,Masked" bitfld.long 0x14 24. " [152] ,Masking of IRQ 152" "Not masked,Masked" textline " " bitfld.long 0x14 23. " [151] ,Masking of IRQ 151" "Not masked,Masked" bitfld.long 0x14 22. " [150] ,Masking of IRQ 150" "Not masked,Masked" bitfld.long 0x14 21. " [149] ,Masking of IRQ 149" "Not masked,Masked" bitfld.long 0x14 20. " [148] ,Masking of IRQ 148" "Not masked,Masked" textline " " bitfld.long 0x14 19. " [147] ,Masking of IRQ 147" "Not masked,Masked" bitfld.long 0x14 18. " [146] ,Masking of IRQ 146" "Not masked,Masked" bitfld.long 0x14 17. " [145] ,Masking of IRQ 145" "Not masked,Masked" bitfld.long 0x14 16. " [144] ,Masking of IRQ 144" "Not masked,Masked" textline " " bitfld.long 0x14 15. " [143] ,Masking of IRQ 143" "Not masked,Masked" bitfld.long 0x14 14. " [142] ,Masking of IRQ 142" "Not masked,Masked" bitfld.long 0x14 13. " [141] ,Masking of IRQ 141" "Not masked,Masked" bitfld.long 0x14 12. " [140] ,Masking of IRQ 140" "Not masked,Masked" textline " " bitfld.long 0x14 11. " [139] ,Masking of IRQ 139" "Not masked,Masked" bitfld.long 0x14 10. " [138] ,Masking of IRQ 138" "Not masked,Masked" bitfld.long 0x14 9. " [137] ,Masking of IRQ 137" "Not masked,Masked" bitfld.long 0x14 8. " [136] ,Masking of IRQ 136" "Not masked,Masked" textline " " bitfld.long 0x14 7. " [135] ,Masking of IRQ 135" "Not masked,Masked" bitfld.long 0x14 6. " [134] ,Masking of IRQ 134" "Not masked,Masked" bitfld.long 0x14 5. " [133] ,Masking of IRQ 133" "Not masked,Masked" bitfld.long 0x14 4. " [132] ,Masking of IRQ 132" "Not masked,Masked" textline " " bitfld.long 0x14 3. " [131] ,Masking of IRQ 131" "Not masked,Masked" bitfld.long 0x14 2. " [130] ,Masking of IRQ 130" "Not masked,Masked" bitfld.long 0x14 1. " [129] ,Masking of IRQ 129" "Not masked,Masked" bitfld.long 0x14 0. " [128] ,Masking of IRQ 128" "Not masked,Masked" rgroup.long 0x18++0x1B line.long 0x00 "ISR1,IRQ status resister 1" bitfld.long 0x00 31. " IRQ[63] ,Status of IRQ 63" "0,1" bitfld.long 0x00 30. " [62] ,Status of IRQ 62" "0,1" bitfld.long 0x00 29. " [61] ,Status of IRQ 61" "0,1" bitfld.long 0x00 28. " [60] ,Status of IRQ 60" "0,1" textline " " bitfld.long 0x00 27. " [59] ,Status of IRQ 59" "0,1" bitfld.long 0x00 26. " [58] ,Status of IRQ 58" "0,1" bitfld.long 0x00 25. " [57] ,Status of IRQ 57" "0,1" bitfld.long 0x00 24. " [56] ,Status of IRQ 56" "0,1" textline " " bitfld.long 0x00 23. " [55] ,Status of IRQ 55" "0,1" bitfld.long 0x00 22. " [54] ,Status of IRQ 54" "0,1" bitfld.long 0x00 21. " [53] ,Status of IRQ 53" "0,1" bitfld.long 0x00 20. " [52] ,Status of IRQ 52" "0,1" textline " " bitfld.long 0x00 19. " [51] ,Status of IRQ 51" "0,1" bitfld.long 0x00 18. " [50] ,Status of IRQ 50" "0,1" bitfld.long 0x00 17. " [49] ,Status of IRQ 49" "0,1" bitfld.long 0x00 16. " [48] ,Status of IRQ 48" "0,1" textline " " bitfld.long 0x00 15. " [47] ,Status of IRQ 47" "0,1" bitfld.long 0x00 14. " [46] ,Status of IRQ 46" "0,1" bitfld.long 0x00 13. " [45] ,Status of IRQ 45" "0,1" bitfld.long 0x00 12. " [44] ,Status of IRQ 44" "0,1" textline " " bitfld.long 0x00 11. " [43] ,Status of IRQ 43" "0,1" bitfld.long 0x00 10. " [42] ,Status of IRQ 42" "0,1" bitfld.long 0x00 9. " [41] ,Status of IRQ 41" "0,1" bitfld.long 0x00 8. " [40] ,Status of IRQ 40" "0,1" textline " " bitfld.long 0x00 7. " [39] ,Status of IRQ 39" "0,1" bitfld.long 0x00 6. " [38] ,Status of IRQ 38" "0,1" bitfld.long 0x00 5. " [37] ,Status of IRQ 37" "0,1" bitfld.long 0x00 4. " [36] ,Status of IRQ 36" "0,1" textline " " bitfld.long 0x00 3. " [35] ,Status of IRQ 35" "0,1" bitfld.long 0x00 2. " [34] ,Status of IRQ 34" "0,1" bitfld.long 0x00 1. " [33] ,Status of IRQ 33" "0,1" bitfld.long 0x00 0. " [32] ,Status of IRQ 32" "0,1" line.long 0x04 "ISR2,IRQ status resister 2" bitfld.long 0x04 31. " [95] ,Status of IRQ 95" "0,1" bitfld.long 0x04 30. " [94] ,Status of IRQ 94" "0,1" bitfld.long 0x04 29. " [93] ,Status of IRQ 93" "0,1" bitfld.long 0x04 28. " [92] ,Status of IRQ 92" "0,1" textline " " bitfld.long 0x04 27. " [91] ,Status of IRQ 91" "0,1" bitfld.long 0x04 26. " [90] ,Status of IRQ 90" "0,1" bitfld.long 0x04 25. " [89] ,Status of IRQ 89" "0,1" bitfld.long 0x04 24. " [88] ,Status of IRQ 88" "0,1" textline " " bitfld.long 0x04 23. " [87] ,Status of IRQ 87" "0,1" bitfld.long 0x04 22. " [86] ,Status of IRQ 86" "0,1" bitfld.long 0x04 21. " [85] ,Status of IRQ 85" "0,1" bitfld.long 0x04 20. " [84] ,Status of IRQ 84" "0,1" textline " " bitfld.long 0x04 19. " [83] ,Status of IRQ 83" "0,1" bitfld.long 0x04 18. " [82] ,Status of IRQ 82" "0,1" bitfld.long 0x04 17. " [81] ,Status of IRQ 81" "0,1" bitfld.long 0x04 16. " [80] ,Status of IRQ 80" "0,1" textline " " bitfld.long 0x04 15. " [79] ,Status of IRQ 79" "0,1" bitfld.long 0x04 14. " [78] ,Status of IRQ 78" "0,1" bitfld.long 0x04 13. " [77] ,Status of IRQ 77" "0,1" bitfld.long 0x04 12. " [76] ,Status of IRQ 76" "0,1" textline " " bitfld.long 0x04 11. " [75] ,Status of IRQ 75" "0,1" bitfld.long 0x04 10. " [74] ,Status of IRQ 74" "0,1" bitfld.long 0x04 9. " [73] ,Status of IRQ 73" "0,1" bitfld.long 0x04 8. " [72] ,Status of IRQ 72" "0,1" textline " " bitfld.long 0x04 7. " [71] ,Status of IRQ 71" "0,1" bitfld.long 0x04 6. " [70] ,Status of IRQ 70" "0,1" bitfld.long 0x04 5. " [69] ,Status of IRQ 69" "0,1" bitfld.long 0x04 4. " [68] ,Status of IRQ 68" "0,1" textline " " bitfld.long 0x04 3. " [67] ,Status of IRQ 67" "0,1" bitfld.long 0x04 2. " [66] ,Status of IRQ 66" "0,1" bitfld.long 0x04 1. " [65] ,Status of IRQ 65" "0,1" bitfld.long 0x04 0. " [64] ,Status of IRQ 64" "0,1" line.long 0x08 "ISR3,IRQ status resister 3" bitfld.long 0x08 31. " [127] ,Status of IRQ 127" "0,1" bitfld.long 0x08 30. " [126] ,Status of IRQ 126" "0,1" bitfld.long 0x08 29. " [125] ,Status of IRQ 125" "0,1" bitfld.long 0x08 28. " [124] ,Status of IRQ 124" "0,1" textline " " bitfld.long 0x08 27. " [123] ,Status of IRQ 123" "0,1" bitfld.long 0x08 26. " [122] ,Status of IRQ 122" "0,1" bitfld.long 0x08 25. " [121] ,Status of IRQ 121" "0,1" bitfld.long 0x08 24. " [120] ,Status of IRQ 120" "0,1" textline " " bitfld.long 0x08 23. " [119] ,Status of IRQ 119" "0,1" bitfld.long 0x08 22. " [118] ,Status of IRQ 118" "0,1" bitfld.long 0x08 21. " [117] ,Status of IRQ 117" "0,1" bitfld.long 0x08 20. " [116] ,Status of IRQ 116" "0,1" textline " " bitfld.long 0x08 19. " [115] ,Status of IRQ 115" "0,1" bitfld.long 0x08 18. " [114] ,Status of IRQ 114" "0,1" bitfld.long 0x08 17. " [113] ,Status of IRQ 113" "0,1" bitfld.long 0x08 16. " [112] ,Status of IRQ 112" "0,1" textline " " bitfld.long 0x08 15. " [111] ,Status of IRQ 111" "0,1" bitfld.long 0x08 14. " [110] ,Status of IRQ 110" "0,1" bitfld.long 0x08 13. " [109] ,Status of IRQ 109" "0,1" bitfld.long 0x08 12. " [108] ,Status of IRQ 108" "0,1" textline " " bitfld.long 0x08 11. " [107] ,Status of IRQ 107" "0,1" bitfld.long 0x08 10. " [106] ,Status of IRQ 106" "0,1" bitfld.long 0x08 9. " [105] ,Status of IRQ 105" "0,1" bitfld.long 0x08 8. " [104] ,Status of IRQ 104" "0,1" textline " " bitfld.long 0x08 7. " [103] ,Status of IRQ 103" "0,1" bitfld.long 0x08 6. " [102] ,Status of IRQ 102" "0,1" bitfld.long 0x08 5. " [101] ,Status of IRQ 101" "0,1" bitfld.long 0x08 4. " [100] ,Status of IRQ 100" "0,1" textline " " bitfld.long 0x08 3. " [99] ,Status of IRQ 99" "0,1" bitfld.long 0x08 2. " [98] ,Status of IRQ 98" "0,1" bitfld.long 0x08 1. " [97] ,Status of IRQ 97" "0,1" bitfld.long 0x08 0. " [96] ,Status of IRQ 96" "0,1" line.long 0x0C "ISR4,IRQ status resister 4r" bitfld.long 0x0C 31. " [159] ,Status of IRQ 159" "0,1" bitfld.long 0x0C 30. " [158] ,Status of IRQ 158" "0,1" bitfld.long 0x0C 29. " [157] ,Status of IRQ 157" "0,1" bitfld.long 0x0C 28. " [156] ,Status of IRQ 156" "0,1" textline " " bitfld.long 0x0C 27. " [155] ,Status of IRQ 155" "0,1" bitfld.long 0x0C 26. " [154] ,Status of IRQ 154" "0,1" bitfld.long 0x0C 25. " [153] ,Status of IRQ 153" "0,1" bitfld.long 0x0C 24. " [152] ,Status of IRQ 152" "0,1" textline " " bitfld.long 0x0C 23. " [151] ,Status of IRQ 151" "0,1" bitfld.long 0x0C 22. " [150] ,Status of IRQ 150" "0,1" bitfld.long 0x0C 21. " [149] ,Status of IRQ 149" "0,1" bitfld.long 0x0C 20. " [148] ,Status of IRQ 148" "0,1" textline " " bitfld.long 0x0C 19. " [147] ,Status of IRQ 147" "0,1" bitfld.long 0x0C 18. " [146] ,Status of IRQ 146" "0,1" bitfld.long 0x0C 17. " [145] ,Status of IRQ 145" "0,1" bitfld.long 0x0C 16. " [144] ,Status of IRQ 144" "0,1" textline " " bitfld.long 0x0C 15. " [143] ,Status of IRQ 143" "0,1" bitfld.long 0x0C 14. " [142] ,Status of IRQ 142" "0,1" bitfld.long 0x0C 13. " [141] ,Status of IRQ 141" "0,1" bitfld.long 0x0C 12. " [140] ,Status of IRQ 140" "0,1" textline " " bitfld.long 0x0C 11. " [139] ,Status of IRQ 139" "0,1" bitfld.long 0x0C 10. " [138] ,Status of IRQ 138" "0,1" bitfld.long 0x0C 9. " [137] ,Status of IRQ 137" "0,1" bitfld.long 0x0C 8. " [136] ,Status of IRQ 136" "0,1" textline " " bitfld.long 0x0C 7. " [135] ,Status of IRQ 135" "0,1" bitfld.long 0x0C 6. " [134] ,Status of IRQ 134" "0,1" bitfld.long 0x0C 5. " [133] ,Status of IRQ 133" "0,1" bitfld.long 0x0C 4. " [132] ,Status of IRQ 132" "0,1" textline " " bitfld.long 0x0C 3. " [131] ,Status of IRQ 131" "0,1" bitfld.long 0x0C 2. " [130] ,Status of IRQ 130" "0,1" bitfld.long 0x0C 1. " [129] ,Status of IRQ 129" "0,1" bitfld.long 0x0C 0. " [128] ,Status of IRQ 128" "0,1" textline "" line.long 0x10 "A9_LPSR,A9 Low Power Status Register" bitfld.long 0x10 10. " A9_RST ,Reset status of A9" "Not asserted,Asserted" bitfld.long 0x10 9. " A9_DBG_ACK ,Debug Acknowledge of A9" "Not asserted,Asserted" bitfld.long 0x10 8. " SYSTEM_IN_STOP_MODE ,STOP mode status" "Not STOP,STOP" bitfld.long 0x10 7. " SYSTEM_IN_WAIT_MODE ,WAIT mode status" "Not WAIT,WAIT" textline " " bitfld.long 0x10 6. " A9_CLK_ENABLE ,A9 Clock Enable" "Disabled,Enabled" bitfld.long 0x10 5. " A9_L2CC_IDLE ,A9 L2 Cache idle indication" "Not idle,Idle" bitfld.long 0x10 4. " A9_SCU_IDLE ,A9 SCU idle indication" "Not idle,Idle" bitfld.long 0x10 0. " A9_STANDBY_WFI ,A9 Standby wait for interrupt status" "Not WFI,WFI" line.long 0x14 "M4_LPSR,M4 Low Power Status Register" bitfld.long 0x14 8. " M4_CORE_RESET_B ,Reset status of M4 Core" "Not asserted,Asserted" bitfld.long 0x14 7. " M4_PLATFORM_RESET_B ,Reset status of M4 Platform" "Not asserted,Asserted" bitfld.long 0x14 6. " M4_HALTED ,M4 Halted indication" "Halted,Halted" bitfld.long 0x14 5. " M4_LOCKUP ,M4 lockup indication" "No lockup,Lockup" textline " " bitfld.long 0x14 4. " M4_SLEEPING ,M4 sleeping indication" "Not sleeping,Sleeping" bitfld.long 0x14 3. " M4_SLEEP_DEEP ,M4 deep sleeping indication" "Not deep sleep,Deep sleep" bitfld.long 0x14 2. " M4_GATE_HCLK ,M4 hclk gating status" "Not gated,Gated" bitfld.long 0x14 1. " M4_SLEEP_HOLD_ACK_B ,M4 sleep hold acknowledge" "Asserted,Not asserted" textline " " bitfld.long 0x14 0. " M4_SLEEP_HOLD_REQ_B ,M4 sleep hold request status" "Requested,Not requested" line.long 0x18 "DR,GPC Debug Register" bitfld.long 0x18 20. " IPG_WAIT ,CCM ipg_wait signal indication" "0,1" bitfld.long 0x18 19. " IPG_STOP ,CCM ipg_wait signal indication" "0,1" bitfld.long 0x18 18. " GPC_CPU_ISO ,A9 CPU isolation signal indication" "Disabled,Enabled" bitfld.long 0x18 17. " GPC_CPU_SWITCH_B ,CPU power switch control signal indication" "On,Off" textline " " bitfld.long 0x18 16. " GPC_CPU_RESET_B ,GPC indication to SRC to assert reset for A9 CPU" "Not asserted,Asserted" bitfld.long 0x18 15. " GPC_L2_SWITCH_B ,L2 Cache power switch control signal indication" "On,Off" bitfld.long 0x18 14. " GPC_L2CPU_ISO ,L2 Cache to CPU isolation signal indication" "Disabled,Enabled" bitfld.long 0x18 13. " GPC_L2SOC_ISO ,L2 Cache to SOC isolation signal indication" "Disabled,Enabled" textline " " bitfld.long 0x18 12. " GPC_GPU_ISO ,GPU domain isolation signal indication" "Disabled,Enabled" bitfld.long 0x18 11. " GPC_GPU_SWITCH_B ,GPU domain power switch control signal indication" "On,Off" bitfld.long 0x18 10. " GPC_GPU_RESET_B ,GPC indication to SRC to assert reset for GPU domain" "Asserted,Not asserted" bitfld.long 0x18 9. " GPC_DISP_ISO ,Display domain isolation signal indication" "Disabled,Enabled" textline " " bitfld.long 0x18 8. " GPC_DISP_SWITCH_B ,Display domain power switch control signal indication" "On,Off" bitfld.long 0x18 7. " GPC_DISP_RESET_B ,GPC indication to SRC to assert reset for Display domain" "On,Off" bitfld.long 0x18 6. " GPC_PDN_ACK ,GPC pdn_ack signal indication" "0,1" bitfld.long 0x18 5. " GPC_PUP_ACK ,GPC pun_ack signal indication" "0,1" textline " " bitfld.long 0x18 4. " MEGA_ISO ,MEGA domain isolation signal indication" "Disabled,Enabled" bitfld.long 0x18 3. " MEGA_SWITCH_B ,MEGA domain power switch control signal indication" "On,Off" bitfld.long 0x18 2. " MEGA_RESET_B ,GPC indication to SRC to assert reset for MEGA domain" "Asserted,Not asserted" bitfld.long 0x18 1. " PCIE_PHY_ISO ,PCIE_PHY isolation signal indication" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PCIE_PHY_RESET_B ,PCIE PHY power switch control signal indication" "On,Off" width 0xb tree.end tree "PGC (Power Gating Control)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020DC200 else base ad:0x420DC200 endif width 17. group.long 0x60++0x0F "GPU" line.long 0x00 "GPU_CTRL,PGC Control Register" bitfld.long 0x00 0. " PCR ,Power Control" "On,Off" line.long 0x04 "GPU_PUPSCR,Power Up Sequence Control Register" bitfld.long 0x04 8.--13. " SW2ISO ,Number of IPG clocks to wait between power toggle assertion and negating isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW ,Number of IPG clocks to wait between power-up request and power toggle assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "GPU_PDNSCR,Pull Down Sequence Control Register" bitfld.long 0x08 8.--13. " ISO2SW ,Number of IPG clocks to wait between isolation assertion and power toggle negation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " ISO ,Number of IPG clocks to wait between power-down request and isolation assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "GPU_SR,Power Gating Controller Status Register" bitfld.long 0x0C 0. " PSR ,Indicates whether target subsystem was powered down for the previous power-down request" "Not powered down,Powered down" group.long 0xA0++0x0F "CPU" line.long 0x00 "CPU_CTRL,PGC Control Register" bitfld.long 0x00 0. " PCR ,Power Control" "On,Off" line.long 0x04 "CPU_PUPSCR,Power Up Sequence Control Register" bitfld.long 0x04 8.--13. " SW2ISO ,Number of 32k clocks to wait between bit assertion and negating isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW ,Number of 32k clocks to wait between power-up request and power assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CPU_PDNSCR,Pull Down Sequence Control Register" bitfld.long 0x08 8.--13. " ISO2SW ,Number of IPG clocks to wait between bit assertion and negating power" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " ISO ,Number of IPG clocks to wait between power-down request and isolation assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "CPU_SR,Power Gating Controller Status Register" bitfld.long 0x0C 0. " PSR ,Indicates whether target subsystem was powered down for the previous power-down request" "Not powered down,Powered down" width 0xB tree.end tree "DVFS (Dynamic Voltage & Frequency Scaling)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020DC180 else base ad:0x420DC180 endif width 14. group.long 0x00++0x23 line.long 0x00 "THRS,DVFS Thresholds" bitfld.long 0x00 22.--27. " UPTHR ,Upper threshold for load lacking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DWTHR ,Down threshold for load lacking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " PNCTHR ,Panic threshold for load lacking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "COUN,DVFS Counters thresholds" hexmask.long.byte 0x04 16.--23. 1. " DN_CNT ,Down counter threshold value" hexmask.long.byte 0x04 0.--7. 1. " UPCNT ,UP counter threshold value" line.long 0x08 "SIG1,DVFS general purpose bits weight" bitfld.long 0x08 29.--31. " WSW15 ,General purpose load tracking signal weight dvfs_w_sig[15]" "0,1,2,3,4,5,?..." bitfld.long 0x08 26.--28. " WSW14 ,General purpose load tracking signal weight dvfs_w_sig[14]" "0,1,2,3,4,5,?..." bitfld.long 0x08 23.--25. " WSW13 ,General purpose load tracking signal weight dvfs_w_sig[13]" "0,1,2,3,4,5,?..." bitfld.long 0x08 20.--22. " WSW12 ,General purpose load tracking signal weight dvfs_w_sig[12]" "0,1,2,3,4,5,?..." textline " " bitfld.long 0x08 17.--19. " WSW11 ,General purpose load tracking signal weight dvfs_w_sig[11]" "0,1,2,3,4,5,?..." bitfld.long 0x08 14.--16. " WSW10 ,General purpose load tracking signal weight dvfs_w_sig[10]" "0,1,2,3,4,5,?..." bitfld.long 0x08 11.--13. " WSW9 ,General purpose load tracking signal weight dvfs_w_sig[9]" "0,1,2,3,4,5,?..." bitfld.long 0x08 8.--10. " WSW8 ,General purpose load tracking signal weight dvfs_w_sig[8]" "0,1,2,3,4,5,?..." textline " " bitfld.long 0x08 5.--7. " WSW7 ,General purpose load tracking signal weight dvfs_w_sig[7]" "0,1,2,3,4,5,?..." bitfld.long 0x08 2.--4. " WSW6 ,General purpose load tracking signal weight dvfs_w_sig[6]" "0,1,2,3,4,5,?..." line.long 0x0C "DVFSSIG0,DVFS general purpose bits weight" bitfld.long 0x0C 29.--31. " WSW5 ,General purpose load tracking signal weight dvfs_w_sig[5]" "0,1,2,3,4,5,?..." bitfld.long 0x0C 26.--28. " WSW4 ,General purpose load tracking signal weight dvfs_w_sig[4]" "0,1,2,3,4,5,?..." bitfld.long 0x0C 23.--25. " WSW3 ,General purpose load tracking signal weight dvfs_w_sig[3]" "0,1,2,3,4,5,?..." bitfld.long 0x0C 20.--22. " WSW2 ,General purpose load tracking signal weight dvfs_w_sig[2]" "0,1,2,3,4,5,?..." textline " " bitfld.long 0x0C 6.--11. " WSW1 ,General purpose load tracking signal weight dvfs_w_sig[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " WSW0 ,General purpose load tracking signal weight dvfs_w_sig[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "DVFSGPC0,DVFS general purpose bit 0 weight counter" bitfld.long 0x10 31. " C0STRT ,Counter 0 start" "Counting/Stopped,Started" rbitfld.long 0x10 30. " C0ACT ,Counter 0 active indicator" "Not active,Active" hexmask.long.tbyte 0x10 0.--16. 1. " GPBC0 ,General Purpose bits Counter 0" line.long 0x14 "DVFSGPC1,DVFS general purpose bit 1 weight counter" bitfld.long 0x14 31. " C1STRT ,Counter 1 start" "Counting/Stopped,Started" rbitfld.long 0x14 30. " C1ACT ,Counter 1 active indicator" "Not active,Active" hexmask.long.tbyte 0x14 0.--16. 1. " GPBC1 ,General Purpose bits Counter 1" line.long 0x18 "DVFSGPBT,DVFS general purpose bits enables" bitfld.long 0x18 15. " GPB15 ,General purpose bit 15" "0,1" bitfld.long 0x18 14. " GPB14 ,General purpose bit 14" "0,1" bitfld.long 0x18 13. " GPB13 ,General purpose bit 13" "0,1" bitfld.long 0x18 12. " GPB12 ,General purpose bit 12" "0,1" textline " " bitfld.long 0x18 11. " GPB11 ,General purpose bit 11" "0,1" bitfld.long 0x18 10. " GPB10 ,General purpose bit 10" "0,1" bitfld.long 0x18 9. " GPB9 ,General purpose bit 9" "0,1" bitfld.long 0x18 8. " GPB8 ,General purpose bit 8" "0,1" textline " " bitfld.long 0x18 7. " GPB7 ,General purpose bit 7" "0,1" bitfld.long 0x18 6. " GPB6 ,General purpose bit 6" "0,1" bitfld.long 0x18 5. " GPB5 ,General purpose bit 5" "0,1" bitfld.long 0x18 4. " GPB4 ,General purpose bit 4" "0,1" textline " " bitfld.long 0x18 3. " GPB3 ,General purpose bit 3" "0,1" bitfld.long 0x18 2. " GPB2 ,General purpose bit 2" "0,1" bitfld.long 0x18 1. " GPB1 ,General purpose bit 1" "0,1" bitfld.long 0x18 0. " GPB0 ,General purpose bit 0" "0,1" line.long 0x1C "DVFSEMAC,DVFS EMAC settings" bitfld.long 0x1C 24. " WFIM0 ,DVFS Wait for Interrupt of core 0 mask bit" "Not masked,Masked" rbitfld.long 0x1C 16.--17. " FSVAI0 ,DVFS Frequency adjustment status of core 0" "No change,Increase,Decrease,Increase immediately" bitfld.long 0x1C 9. " DVFEN0 ,DVFS tracking for core 0" "Disabled,Enabled" hexmask.long.word 0x1C 0.--8. 1. " EMAC ,EMA control value" line.long 0x20 "CNTR,DVFS Control" bitfld.long 0x20 29.--31. " DIV3CK ,DIV_3_CLK division ratio inside the DVFS module" "1,4,16,64,246,1024,?..." bitfld.long 0x20 28. " DVFEV ,Always give a DVFS event" "Disabled,Enabled" bitfld.long 0x20 27. " LBMI ,Load buffer full mask interrupt" "Not masked,Masked" bitfld.long 0x20 26. " LBFL1 ,Load buffer 1 - full status bit" "Not full,Full" textline " " bitfld.long 0x20 25. " LBFL0 ,Load buffer 0 - full status bit" "Not full,Full" bitfld.long 0x20 24. " DVFIS ,DVFS Interrupt select" "SDMA,MCU" eventfld.long 0x20 23. " PIRQS ,Pattern IRQ Source" "Not pattern,Pattern" rbitfld.long 0x20 22. " FSVAIM ,DVFS Frequency adjustment interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x20 20.--21. " FSVAI ,DVFS Frequency adjustment interrupt" "No interrupt,Increase,Decrease,Increase immediately" bitfld.long 0x20 18. " MAXF ,Maximum frequency reached" "Not reached,Reached" bitfld.long 0x20 17. " MINF ,Minimum frequency reached" "Not reached,Reached" bitfld.long 0x20 11.--16. " DIV_RATIO ,Divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" textline " " bitfld.long 0x20 9. " PFUE ,Period Frequency Update Enable" "Disabled,Enabled" rbitfld.long 0x20 6.--8. " PFUS ,Periodic Frequency Update Status" "No update,No update,No update,No update,DVFSPT0,DVFSPT1,DVFSPT2,DVFSPT3" bitfld.long 0x20 5. " LTBRSH ,Load Tracking Buffer Register Shift" "Values of [5:2],Values of [4:1]" bitfld.long 0x20 3.--4. " LTBRSR ,Load Tracking Buffer Register Source" "PRE_LD_ADD,LD_ADD,EMA_LD," rgroup.long 0x24++0x0F line.long 0x00 "DVFSLTR0_0,DVFS Load Tracking Register 0, portion 0" bitfld.long 0x00 28.--31. " LTS0_7 ,Core 0 Load Tracking Sample 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " LTS0_6 ,Core 0 Load Tracking Sample 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " LTS0_5 ,Core 0 Load Tracking Sample 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LTS0_4 ,Core 0 Load Tracking Sample 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " LTS0_3 ,Core 0 Load Tracking Sample 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " LTS0_2 ,Core 0 Load Tracking Sample 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " LTS0_1 ,Core 0 Load Tracking Sample 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LTS0_0 ,Core 0 Load Tracking Sample 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DVFSLTR0_1,DVFS Load Tracking Register 0, portion 1" bitfld.long 0x04 28.--31. " LTS0_15 ,Core 0 Load Tracking Sample 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. " LTS0_14 ,Core 0 Load Tracking Sample 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " LTS0_13 ,Core 0 Load Tracking Sample 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " LTS0_12 ,Core 0 Load Tracking Sample 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 12.--15. " LTS0_11 ,Core 0 Load Tracking Sample 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " LTS0_10 ,Core 0 Load Tracking Sample 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " LTS0_9 ,Core 0 Load Tracking Sample 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " LTS0_8 ,Core 0 Load Tracking Sample 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DVFSLTR1_0,DVFS Load Tracking Register 1, portion 0" bitfld.long 0x08 28.--31. " LTS1_7 ,Core 0 Load Tracking Sample 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. " LTS1_6 ,Core 0 Load Tracking Sample 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. " LTS1_5 ,Core 0 Load Tracking Sample 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--19. " LTS1_4 ,Core 0 Load Tracking Sample 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 12.--15. " LTS1_3 ,Core 0 Load Tracking Sample 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " LTS1_2 ,Core 0 Load Tracking Sample 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " LTS1_1 ,Core 0 Load Tracking Sample 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " LTS1_0 ,Core 0 Load Tracking Sample 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "DVFSLTR1_1,DVFS Load Tracking Register 3, portion 1" bitfld.long 0x0C 28.--31. " LTS1_15 ,Core 0 Load Tracking Sample 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 24.--27. " LTS1_14 ,Core 0 Load Tracking Sample 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 20.--23. " LTS1_13 ,Core 0 Load Tracking Sample 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 16.--19. " LTS1_12 ,Core 0 Load Tracking Sample 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0C 12.--15. " LTS1_11 ,Core 0 Load Tracking Sample 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. " LTS1_10 ,Core 0 Load Tracking Sample 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " LTS1_9 ,Core 0 Load Tracking Sample 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " LTS1_8 ,Core 0 Load Tracking Sample 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x0F line.long 0x00 "DVFSPT0,DVFS pattern 0 length" rbitfld.long 0x00 17. " PT0A ,Pattern 0 currently active" "Not active,Active" hexmask.long.tbyte 0x00 0.--16. 1. " FPTN0 ,Frequency pattern 0 counter" line.long 0x04 "DVFSPT1,DVFS pattern 1 length" rbitfld.long 0x04 17. " PT1A ,Pattern 1 currently active" "Not active,Active" hexmask.long.tbyte 0x04 0.--16. 1. " FPTN1 ,Frequency pattern 1 counter" line.long 0x08 "DVFSPT2,DVFS pattern 2 length" hexmask.long.byte 0x08 26.--31. 1. " P2THR ,Pattern 2 Threshold" rbitfld.long 0x08 17. " PT2A ,Pattern 2 currently active" "Not active,Active" hexmask.long.tbyte 0x08 0.--16. 1. " FPTN2 ,Frequency pattern 2 counter" line.long 0x0C "DVFSPT3,DVFS pattern 3 length" rbitfld.long 0x0C 17. " PT3A ,Pattern 3 currently active" "Not active,Active" hexmask.long.tbyte 0x0C 0.--16. 1. " FPTN3 ,Frequency pattern 3 counter" width 0xB tree.end tree.end tree "GPIO (General Purpose Input/Output)" tree "GPIO_1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0209C000 else base ad:0x4209C000 endif width 8. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "0,1" bitfld.long 0x00 30. " DR30 ,Data bit 30" "0,1" bitfld.long 0x00 29. " DR29 ,Data bit 29" "0,1" bitfld.long 0x00 28. " DR28 ,Data bit 28" "0,1" bitfld.long 0x00 27. " DR27 ,Data bit 27" "0,1" bitfld.long 0x00 26. " DR26 ,Data bit 26" "0,1" bitfld.long 0x00 25. " DR25 ,Data bit 25" "0,1" bitfld.long 0x00 24. " DR24 ,Data bit 24" "0,1" textline " " bitfld.long 0x00 23. " DR23 ,Data bit 23" "0,1" bitfld.long 0x00 22. " DR22 ,Data bit 22" "0,1" bitfld.long 0x00 21. " DR21 ,Data bit 21" "0,1" bitfld.long 0x00 20. " DR20 ,Data bit 20" "0,1" bitfld.long 0x00 19. " DR19 ,Data bit 19" "0,1" bitfld.long 0x00 18. " DR18 ,Data bit 18" "0,1" bitfld.long 0x00 17. " DR17 ,Data bit 17" "0,1" bitfld.long 0x00 16. " DR16 ,Data bit 16" "0,1" textline " " bitfld.long 0x00 15. " DR15 ,Data bit 15" "0,1" bitfld.long 0x00 14. " DR14 ,Data bit 14" "0,1" bitfld.long 0x00 13. " DR13 ,Data bit 13" "0,1" bitfld.long 0x00 12. " DR12 ,Data bit 12" "0,1" bitfld.long 0x00 11. " DR11 ,Data bit 11" "0,1" bitfld.long 0x00 10. " DR10 ,Data bit 10" "0,1" bitfld.long 0x00 9. " DR9 ,Data bit 9" "0,1" bitfld.long 0x00 8. " DR8 ,Data bit 8" "0,1" textline " " bitfld.long 0x00 7. " DR7 ,Data bit 7" "0,1" bitfld.long 0x00 6. " DR6 ,Data bit 6" "0,1" bitfld.long 0x00 5. " DR5 ,Data bit 5" "0,1" bitfld.long 0x00 4. " DR4 ,Data bit 4" "0,1" bitfld.long 0x00 3. " DR3 ,Data bit 3" "0,1" bitfld.long 0x00 2. " DR2 ,Data bit 2" "0,1" bitfld.long 0x00 1. " DR1 ,Data bit 1" "0,1" bitfld.long 0x00 0. " DR0 ,Data bit 0" "0,1" line.long 0x04 "GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" textline " " bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" textline " " bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" textline " " bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" textline " " bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "0,1" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "0,1" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "0,1" bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "0,1" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "0,1" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "0,1" bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "0,1" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "0,1" textline " " bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "0,1" bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "0,1" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "0,1" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "0,1" bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "0,1" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "0,1" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "0,1" bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "0,1" textline " " bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "0,1" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "0,1" bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "0,1" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "0,1" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "0,1" bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "0,1" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "0,1" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "0,1" textline " " bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "0,1" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "0,1" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "0,1" bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "0,1" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "0,1" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "0,1" bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "0,1" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "0,1" textline "" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" textline " " bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" textline " " bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" textline " " bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" textline " " bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" textline " " bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" textline "" line.long 0x0C "ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 12. tree.end tree "GPIO_2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020A0000 else base ad:0x420A0000 endif width 8. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "0,1" bitfld.long 0x00 30. " DR30 ,Data bit 30" "0,1" bitfld.long 0x00 29. " DR29 ,Data bit 29" "0,1" bitfld.long 0x00 28. " DR28 ,Data bit 28" "0,1" bitfld.long 0x00 27. " DR27 ,Data bit 27" "0,1" bitfld.long 0x00 26. " DR26 ,Data bit 26" "0,1" bitfld.long 0x00 25. " DR25 ,Data bit 25" "0,1" bitfld.long 0x00 24. " DR24 ,Data bit 24" "0,1" textline " " bitfld.long 0x00 23. " DR23 ,Data bit 23" "0,1" bitfld.long 0x00 22. " DR22 ,Data bit 22" "0,1" bitfld.long 0x00 21. " DR21 ,Data bit 21" "0,1" bitfld.long 0x00 20. " DR20 ,Data bit 20" "0,1" bitfld.long 0x00 19. " DR19 ,Data bit 19" "0,1" bitfld.long 0x00 18. " DR18 ,Data bit 18" "0,1" bitfld.long 0x00 17. " DR17 ,Data bit 17" "0,1" bitfld.long 0x00 16. " DR16 ,Data bit 16" "0,1" textline " " bitfld.long 0x00 15. " DR15 ,Data bit 15" "0,1" bitfld.long 0x00 14. " DR14 ,Data bit 14" "0,1" bitfld.long 0x00 13. " DR13 ,Data bit 13" "0,1" bitfld.long 0x00 12. " DR12 ,Data bit 12" "0,1" bitfld.long 0x00 11. " DR11 ,Data bit 11" "0,1" bitfld.long 0x00 10. " DR10 ,Data bit 10" "0,1" bitfld.long 0x00 9. " DR9 ,Data bit 9" "0,1" bitfld.long 0x00 8. " DR8 ,Data bit 8" "0,1" textline " " bitfld.long 0x00 7. " DR7 ,Data bit 7" "0,1" bitfld.long 0x00 6. " DR6 ,Data bit 6" "0,1" bitfld.long 0x00 5. " DR5 ,Data bit 5" "0,1" bitfld.long 0x00 4. " DR4 ,Data bit 4" "0,1" bitfld.long 0x00 3. " DR3 ,Data bit 3" "0,1" bitfld.long 0x00 2. " DR2 ,Data bit 2" "0,1" bitfld.long 0x00 1. " DR1 ,Data bit 1" "0,1" bitfld.long 0x00 0. " DR0 ,Data bit 0" "0,1" line.long 0x04 "GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" textline " " bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" textline " " bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" textline " " bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" textline " " bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "0,1" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "0,1" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "0,1" bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "0,1" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "0,1" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "0,1" bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "0,1" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "0,1" textline " " bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "0,1" bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "0,1" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "0,1" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "0,1" bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "0,1" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "0,1" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "0,1" bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "0,1" textline " " bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "0,1" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "0,1" bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "0,1" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "0,1" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "0,1" bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "0,1" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "0,1" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "0,1" textline " " bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "0,1" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "0,1" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "0,1" bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "0,1" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "0,1" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "0,1" bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "0,1" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "0,1" textline "" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" textline " " bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" textline " " bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" textline " " bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" textline " " bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" textline " " bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" textline "" line.long 0x0C "ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 12. tree.end tree "GPIO_3" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020A4000 else base ad:0x420A4000 endif width 8. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "0,1" bitfld.long 0x00 30. " DR30 ,Data bit 30" "0,1" bitfld.long 0x00 29. " DR29 ,Data bit 29" "0,1" bitfld.long 0x00 28. " DR28 ,Data bit 28" "0,1" bitfld.long 0x00 27. " DR27 ,Data bit 27" "0,1" bitfld.long 0x00 26. " DR26 ,Data bit 26" "0,1" bitfld.long 0x00 25. " DR25 ,Data bit 25" "0,1" bitfld.long 0x00 24. " DR24 ,Data bit 24" "0,1" textline " " bitfld.long 0x00 23. " DR23 ,Data bit 23" "0,1" bitfld.long 0x00 22. " DR22 ,Data bit 22" "0,1" bitfld.long 0x00 21. " DR21 ,Data bit 21" "0,1" bitfld.long 0x00 20. " DR20 ,Data bit 20" "0,1" bitfld.long 0x00 19. " DR19 ,Data bit 19" "0,1" bitfld.long 0x00 18. " DR18 ,Data bit 18" "0,1" bitfld.long 0x00 17. " DR17 ,Data bit 17" "0,1" bitfld.long 0x00 16. " DR16 ,Data bit 16" "0,1" textline " " bitfld.long 0x00 15. " DR15 ,Data bit 15" "0,1" bitfld.long 0x00 14. " DR14 ,Data bit 14" "0,1" bitfld.long 0x00 13. " DR13 ,Data bit 13" "0,1" bitfld.long 0x00 12. " DR12 ,Data bit 12" "0,1" bitfld.long 0x00 11. " DR11 ,Data bit 11" "0,1" bitfld.long 0x00 10. " DR10 ,Data bit 10" "0,1" bitfld.long 0x00 9. " DR9 ,Data bit 9" "0,1" bitfld.long 0x00 8. " DR8 ,Data bit 8" "0,1" textline " " bitfld.long 0x00 7. " DR7 ,Data bit 7" "0,1" bitfld.long 0x00 6. " DR6 ,Data bit 6" "0,1" bitfld.long 0x00 5. " DR5 ,Data bit 5" "0,1" bitfld.long 0x00 4. " DR4 ,Data bit 4" "0,1" bitfld.long 0x00 3. " DR3 ,Data bit 3" "0,1" bitfld.long 0x00 2. " DR2 ,Data bit 2" "0,1" bitfld.long 0x00 1. " DR1 ,Data bit 1" "0,1" bitfld.long 0x00 0. " DR0 ,Data bit 0" "0,1" line.long 0x04 "GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" textline " " bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" textline " " bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" textline " " bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" textline " " bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "0,1" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "0,1" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "0,1" bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "0,1" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "0,1" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "0,1" bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "0,1" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "0,1" textline " " bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "0,1" bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "0,1" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "0,1" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "0,1" bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "0,1" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "0,1" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "0,1" bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "0,1" textline " " bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "0,1" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "0,1" bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "0,1" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "0,1" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "0,1" bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "0,1" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "0,1" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "0,1" textline " " bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "0,1" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "0,1" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "0,1" bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "0,1" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "0,1" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "0,1" bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "0,1" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "0,1" textline "" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" textline " " bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" textline " " bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" textline " " bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" textline " " bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" textline " " bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" textline "" line.long 0x0C "ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 12. tree.end tree "GPIO_4" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020A8000 else base ad:0x420A8000 endif width 8. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "0,1" bitfld.long 0x00 30. " DR30 ,Data bit 30" "0,1" bitfld.long 0x00 29. " DR29 ,Data bit 29" "0,1" bitfld.long 0x00 28. " DR28 ,Data bit 28" "0,1" bitfld.long 0x00 27. " DR27 ,Data bit 27" "0,1" bitfld.long 0x00 26. " DR26 ,Data bit 26" "0,1" bitfld.long 0x00 25. " DR25 ,Data bit 25" "0,1" bitfld.long 0x00 24. " DR24 ,Data bit 24" "0,1" textline " " bitfld.long 0x00 23. " DR23 ,Data bit 23" "0,1" bitfld.long 0x00 22. " DR22 ,Data bit 22" "0,1" bitfld.long 0x00 21. " DR21 ,Data bit 21" "0,1" bitfld.long 0x00 20. " DR20 ,Data bit 20" "0,1" bitfld.long 0x00 19. " DR19 ,Data bit 19" "0,1" bitfld.long 0x00 18. " DR18 ,Data bit 18" "0,1" bitfld.long 0x00 17. " DR17 ,Data bit 17" "0,1" bitfld.long 0x00 16. " DR16 ,Data bit 16" "0,1" textline " " bitfld.long 0x00 15. " DR15 ,Data bit 15" "0,1" bitfld.long 0x00 14. " DR14 ,Data bit 14" "0,1" bitfld.long 0x00 13. " DR13 ,Data bit 13" "0,1" bitfld.long 0x00 12. " DR12 ,Data bit 12" "0,1" bitfld.long 0x00 11. " DR11 ,Data bit 11" "0,1" bitfld.long 0x00 10. " DR10 ,Data bit 10" "0,1" bitfld.long 0x00 9. " DR9 ,Data bit 9" "0,1" bitfld.long 0x00 8. " DR8 ,Data bit 8" "0,1" textline " " bitfld.long 0x00 7. " DR7 ,Data bit 7" "0,1" bitfld.long 0x00 6. " DR6 ,Data bit 6" "0,1" bitfld.long 0x00 5. " DR5 ,Data bit 5" "0,1" bitfld.long 0x00 4. " DR4 ,Data bit 4" "0,1" bitfld.long 0x00 3. " DR3 ,Data bit 3" "0,1" bitfld.long 0x00 2. " DR2 ,Data bit 2" "0,1" bitfld.long 0x00 1. " DR1 ,Data bit 1" "0,1" bitfld.long 0x00 0. " DR0 ,Data bit 0" "0,1" line.long 0x04 "GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" textline " " bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" textline " " bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" textline " " bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" textline " " bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "0,1" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "0,1" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "0,1" bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "0,1" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "0,1" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "0,1" bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "0,1" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "0,1" textline " " bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "0,1" bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "0,1" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "0,1" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "0,1" bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "0,1" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "0,1" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "0,1" bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "0,1" textline " " bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "0,1" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "0,1" bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "0,1" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "0,1" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "0,1" bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "0,1" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "0,1" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "0,1" textline " " bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "0,1" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "0,1" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "0,1" bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "0,1" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "0,1" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "0,1" bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "0,1" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "0,1" textline "" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" textline " " bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" textline " " bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" textline " " bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" textline " " bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" textline " " bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" textline "" line.long 0x0C "ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 12. tree.end tree "GPIO_5" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020AC000 else base ad:0x420AC000 endif width 8. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "0,1" bitfld.long 0x00 30. " DR30 ,Data bit 30" "0,1" bitfld.long 0x00 29. " DR29 ,Data bit 29" "0,1" bitfld.long 0x00 28. " DR28 ,Data bit 28" "0,1" bitfld.long 0x00 27. " DR27 ,Data bit 27" "0,1" bitfld.long 0x00 26. " DR26 ,Data bit 26" "0,1" bitfld.long 0x00 25. " DR25 ,Data bit 25" "0,1" bitfld.long 0x00 24. " DR24 ,Data bit 24" "0,1" textline " " bitfld.long 0x00 23. " DR23 ,Data bit 23" "0,1" bitfld.long 0x00 22. " DR22 ,Data bit 22" "0,1" bitfld.long 0x00 21. " DR21 ,Data bit 21" "0,1" bitfld.long 0x00 20. " DR20 ,Data bit 20" "0,1" bitfld.long 0x00 19. " DR19 ,Data bit 19" "0,1" bitfld.long 0x00 18. " DR18 ,Data bit 18" "0,1" bitfld.long 0x00 17. " DR17 ,Data bit 17" "0,1" bitfld.long 0x00 16. " DR16 ,Data bit 16" "0,1" textline " " bitfld.long 0x00 15. " DR15 ,Data bit 15" "0,1" bitfld.long 0x00 14. " DR14 ,Data bit 14" "0,1" bitfld.long 0x00 13. " DR13 ,Data bit 13" "0,1" bitfld.long 0x00 12. " DR12 ,Data bit 12" "0,1" bitfld.long 0x00 11. " DR11 ,Data bit 11" "0,1" bitfld.long 0x00 10. " DR10 ,Data bit 10" "0,1" bitfld.long 0x00 9. " DR9 ,Data bit 9" "0,1" bitfld.long 0x00 8. " DR8 ,Data bit 8" "0,1" textline " " bitfld.long 0x00 7. " DR7 ,Data bit 7" "0,1" bitfld.long 0x00 6. " DR6 ,Data bit 6" "0,1" bitfld.long 0x00 5. " DR5 ,Data bit 5" "0,1" bitfld.long 0x00 4. " DR4 ,Data bit 4" "0,1" bitfld.long 0x00 3. " DR3 ,Data bit 3" "0,1" bitfld.long 0x00 2. " DR2 ,Data bit 2" "0,1" bitfld.long 0x00 1. " DR1 ,Data bit 1" "0,1" bitfld.long 0x00 0. " DR0 ,Data bit 0" "0,1" line.long 0x04 "GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" textline " " bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" textline " " bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" textline " " bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" textline " " bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "0,1" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "0,1" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "0,1" bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "0,1" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "0,1" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "0,1" bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "0,1" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "0,1" textline " " bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "0,1" bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "0,1" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "0,1" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "0,1" bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "0,1" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "0,1" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "0,1" bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "0,1" textline " " bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "0,1" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "0,1" bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "0,1" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "0,1" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "0,1" bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "0,1" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "0,1" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "0,1" textline " " bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "0,1" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "0,1" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "0,1" bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "0,1" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "0,1" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "0,1" bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "0,1" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "0,1" textline "" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" textline " " bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" textline " " bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" textline " " bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" textline " " bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" textline " " bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" textline "" line.long 0x0C "ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 12. tree.end tree "GPIO_6" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020B0000 else base ad:0x420B0000 endif width 8. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "0,1" bitfld.long 0x00 30. " DR30 ,Data bit 30" "0,1" bitfld.long 0x00 29. " DR29 ,Data bit 29" "0,1" bitfld.long 0x00 28. " DR28 ,Data bit 28" "0,1" bitfld.long 0x00 27. " DR27 ,Data bit 27" "0,1" bitfld.long 0x00 26. " DR26 ,Data bit 26" "0,1" bitfld.long 0x00 25. " DR25 ,Data bit 25" "0,1" bitfld.long 0x00 24. " DR24 ,Data bit 24" "0,1" textline " " bitfld.long 0x00 23. " DR23 ,Data bit 23" "0,1" bitfld.long 0x00 22. " DR22 ,Data bit 22" "0,1" bitfld.long 0x00 21. " DR21 ,Data bit 21" "0,1" bitfld.long 0x00 20. " DR20 ,Data bit 20" "0,1" bitfld.long 0x00 19. " DR19 ,Data bit 19" "0,1" bitfld.long 0x00 18. " DR18 ,Data bit 18" "0,1" bitfld.long 0x00 17. " DR17 ,Data bit 17" "0,1" bitfld.long 0x00 16. " DR16 ,Data bit 16" "0,1" textline " " bitfld.long 0x00 15. " DR15 ,Data bit 15" "0,1" bitfld.long 0x00 14. " DR14 ,Data bit 14" "0,1" bitfld.long 0x00 13. " DR13 ,Data bit 13" "0,1" bitfld.long 0x00 12. " DR12 ,Data bit 12" "0,1" bitfld.long 0x00 11. " DR11 ,Data bit 11" "0,1" bitfld.long 0x00 10. " DR10 ,Data bit 10" "0,1" bitfld.long 0x00 9. " DR9 ,Data bit 9" "0,1" bitfld.long 0x00 8. " DR8 ,Data bit 8" "0,1" textline " " bitfld.long 0x00 7. " DR7 ,Data bit 7" "0,1" bitfld.long 0x00 6. " DR6 ,Data bit 6" "0,1" bitfld.long 0x00 5. " DR5 ,Data bit 5" "0,1" bitfld.long 0x00 4. " DR4 ,Data bit 4" "0,1" bitfld.long 0x00 3. " DR3 ,Data bit 3" "0,1" bitfld.long 0x00 2. " DR2 ,Data bit 2" "0,1" bitfld.long 0x00 1. " DR1 ,Data bit 1" "0,1" bitfld.long 0x00 0. " DR0 ,Data bit 0" "0,1" line.long 0x04 "GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" textline " " bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" textline " " bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" textline " " bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" textline " " bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "0,1" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "0,1" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "0,1" bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "0,1" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "0,1" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "0,1" bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "0,1" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "0,1" textline " " bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "0,1" bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "0,1" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "0,1" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "0,1" bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "0,1" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "0,1" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "0,1" bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "0,1" textline " " bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "0,1" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "0,1" bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "0,1" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "0,1" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "0,1" bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "0,1" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "0,1" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "0,1" textline " " bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "0,1" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "0,1" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "0,1" bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "0,1" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "0,1" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "0,1" bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "0,1" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "0,1" textline "" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" textline " " bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" textline " " bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" textline " " bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" textline " " bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" textline " " bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" textline "" line.long 0x0C "ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 12. tree.end tree "GPIO_7" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020B4000 else base ad:0x420B4000 endif width 8. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "0,1" bitfld.long 0x00 30. " DR30 ,Data bit 30" "0,1" bitfld.long 0x00 29. " DR29 ,Data bit 29" "0,1" bitfld.long 0x00 28. " DR28 ,Data bit 28" "0,1" bitfld.long 0x00 27. " DR27 ,Data bit 27" "0,1" bitfld.long 0x00 26. " DR26 ,Data bit 26" "0,1" bitfld.long 0x00 25. " DR25 ,Data bit 25" "0,1" bitfld.long 0x00 24. " DR24 ,Data bit 24" "0,1" textline " " bitfld.long 0x00 23. " DR23 ,Data bit 23" "0,1" bitfld.long 0x00 22. " DR22 ,Data bit 22" "0,1" bitfld.long 0x00 21. " DR21 ,Data bit 21" "0,1" bitfld.long 0x00 20. " DR20 ,Data bit 20" "0,1" bitfld.long 0x00 19. " DR19 ,Data bit 19" "0,1" bitfld.long 0x00 18. " DR18 ,Data bit 18" "0,1" bitfld.long 0x00 17. " DR17 ,Data bit 17" "0,1" bitfld.long 0x00 16. " DR16 ,Data bit 16" "0,1" textline " " bitfld.long 0x00 15. " DR15 ,Data bit 15" "0,1" bitfld.long 0x00 14. " DR14 ,Data bit 14" "0,1" bitfld.long 0x00 13. " DR13 ,Data bit 13" "0,1" bitfld.long 0x00 12. " DR12 ,Data bit 12" "0,1" bitfld.long 0x00 11. " DR11 ,Data bit 11" "0,1" bitfld.long 0x00 10. " DR10 ,Data bit 10" "0,1" bitfld.long 0x00 9. " DR9 ,Data bit 9" "0,1" bitfld.long 0x00 8. " DR8 ,Data bit 8" "0,1" textline " " bitfld.long 0x00 7. " DR7 ,Data bit 7" "0,1" bitfld.long 0x00 6. " DR6 ,Data bit 6" "0,1" bitfld.long 0x00 5. " DR5 ,Data bit 5" "0,1" bitfld.long 0x00 4. " DR4 ,Data bit 4" "0,1" bitfld.long 0x00 3. " DR3 ,Data bit 3" "0,1" bitfld.long 0x00 2. " DR2 ,Data bit 2" "0,1" bitfld.long 0x00 1. " DR1 ,Data bit 1" "0,1" bitfld.long 0x00 0. " DR0 ,Data bit 0" "0,1" line.long 0x04 "GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" textline " " bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" textline " " bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" textline " " bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" textline " " bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "0,1" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "0,1" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "0,1" bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "0,1" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "0,1" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "0,1" bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "0,1" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "0,1" textline " " bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "0,1" bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "0,1" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "0,1" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "0,1" bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "0,1" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "0,1" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "0,1" bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "0,1" textline " " bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "0,1" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "0,1" bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "0,1" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "0,1" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "0,1" bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "0,1" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "0,1" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "0,1" textline " " bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "0,1" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "0,1" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "0,1" bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "0,1" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "0,1" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "0,1" bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "0,1" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "0,1" textline "" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" textline " " bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" textline " " bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" textline " " bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" textline " " bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" textline " " bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" textline "" line.long 0x0C "ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" textline " " bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 12. tree.end tree.end tree "GPMI (General Purpose Media Interface)" base ad:0x01806000 width 18. group.long 0x00++0x13 line.long 0x00 "GPMI_CTRL0,GPMI Control Register 0" bitfld.long 0x00 31. " SFTRST ,Soft reset" "Run,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock gate" "Run,Gated" bitfld.long 0x00 29. " RUN ,GPMI busy running" "Idle,Busy" bitfld.long 0x00 28. " DEV_IRQ_EN ,DEV IRQ enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LOCK_CS ,Chip select lock bit" "Disabled,Enabled" bitfld.long 0x00 26. " UDMA ,ATA-Ultra DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x00 23. " WORD_LENGTH ,Data bus mode" "16-bit,8-bit" textline " " bitfld.long 0x00 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,,,,," bitfld.long 0x00 16. " ADDRESS_INCREMENT ,Adress increment" "Not incremented,Incremented" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x04 "GPMI_CTRL0_SET,GPMI Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Soft reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock gate" "No effect,Set" bitfld.long 0x04 29. " RUN ,GPMI busy running" "No effect,Set" bitfld.long 0x04 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Set" textline " " bitfld.long 0x04 27. " TIMEOUT_IRQ_EN ,Timeout interrupt enable" "No effect,Set" bitfld.long 0x04 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Set" bitfld.long 0x04 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x04 23. " WORD_LENGTH ,Data bus mode" "16-bit,8-bit" textline " " bitfld.long 0x04 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x04 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,,,,," bitfld.long 0x04 16. " ADDRESS_INCREMENT ,Adress increment" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x08 "GPMI_CTRL0_CLR,GPMI Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Soft reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Clock gate" "No effect,Clear" bitfld.long 0x08 29. " RUN ,GPMI busy running" "No effect,Clear" bitfld.long 0x08 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " LOCK_CS ,Chip select lock bit" "No effect,Clear" bitfld.long 0x08 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Clear" bitfld.long 0x08 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x08 23. " WORD_LENGTH ,Data bus mode" "16-bit,8-bit" textline " " bitfld.long 0x08 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x08 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,,,,," bitfld.long 0x08 16. " ADDRESS_INCREMENT ,Adress increment" "No effect,Clear" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x0c "GPMI_CTRL0_TOG,GPMI Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Soft reset" "Not toggled,Toggled" bitfld.long 0x0c 30. " CLKGATE ,Clock gate" "Not toggled,Toggled" bitfld.long 0x0c 29. " RUN ,GPMI busy running" "Not toggled,Toggled" bitfld.long 0x0c 28. " DEV_IRQ_EN ,DEV IRQ enable" "Not toggled,Toggled" textline " " bitfld.long 0x0c 27. " LOCK_CS ,Chip select lock bit" "Not toggled,Toggled" bitfld.long 0x0c 26. " UDMA ,ATA-Ultra DMA enable" "Not toggled,Toggled" bitfld.long 0x0c 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x0c 23. " WORD_LENGTH ,Data bus mode" "16-bit,8-bit" textline " " bitfld.long 0x0c 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,,,,," bitfld.long 0x0c 16. " ADDRESS_INCREMENT ,Adress increment" "Not toggled,Toggled" hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x10 "GPMI_COMPARE,GPMI Compare Register Description" hexmask.long.word 0x10 16.--31. 1. " MASK ,16-bit mask which is applied after the read data is XORed with the REFERENCE bit field" hexmask.long.word 0x10 0.--15. 1. " REFERENCE ,16-bit value which is XORed with data read from the NAND device" group.long 0x20++0x13 line.long 0x00 "GPMI_ECCCTRL,GPMI Integrated ECC Control Register" hexmask.long.word 0x00 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x00 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,," bitfld.long 0x00 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Disabled,Enabled" hexmask.long.word 0x00 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x04 "GPMI_ECCCTRL_SET,GPMI Integrated ECC Control Set Register" hexmask.long.word 0x04 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x04 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,," bitfld.long 0x04 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Set" hexmask.long.word 0x04 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x08 "GPMI_ECCCTRL_CLR,GPMI Integrated ECC Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x08 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,," bitfld.long 0x08 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Clear" hexmask.long.word 0x08 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x0c "GPMI_ECCCTRL_TOG,GPMI Integrated ECC Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x0c 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,," bitfld.long 0x0c 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Not toggled,Toggled" hexmask.long.word 0x0c 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x10 "GPMI_ECCCOUNT,GPMI Integrated ECC Transfer Count Register" hexmask.long.byte 0x10 16.--23. 1. " RANDOMIZER_PAGE ,Set NAND page number needed to be randomized" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of bytes to pass through ECC" group.long 0x40++0x03 line.long 0x00 "GPMI_PAYLOAD,GPMI Payload Address" hexmask.long 0x00 2.--31. 0x04 " ADDRESS ,Pointer to an array of one or more 512 byte payload buffers" group.long 0x50++0x03 line.long 0x00 "GPMI_AUXILIARY,GPMI Auxiliary Address Register" hexmask.long 0x00 2.--31. 0x04 " ADDRESS ,Pointer to ECC control structure and meta-data storage" textline "" group.long 0x60++0x13 line.long 0x00 "GPMI_CTRL1,GPMI Control Register 1" bitfld.long 0x00 31. " DEV_CLK_STOP ,Device clock stop" "Not stopped,Stopped" bitfld.long 0x00 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "Not stopped,Stopped" textline " " bitfld.long 0x00 29. " WRITE_CLK_STOP ,Stop clock durning data write" "Not stopped,Stopped" bitfld.long 0x00 28. " TOGGLE_MODE ,Samsung toggle mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " GPMI_CLK_DIV2_EN ,GPMI clk divider enable" "Disabled,Enabled" bitfld.long 0x00 26. " UPDATE_CS ,Force CS value update" "Not updated,Updated" textline " " bitfld.long 0x00 25. " SSYNCMODE ,Asynchronous/synchronous mode" "Async,Sync" bitfld.long 0x00 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "Disabled,Enabled" textline " " bitfld.long 0x00 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "~2ns,~4ns,~6ns,No delay" bitfld.long 0x00 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not forced,Forced" bitfld.long 0x00 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" ",BCH" textline " " bitfld.long 0x00 17. " DLL_ENABLE ,GPMI DLL enable bit" "Disabled,Enabled" bitfld.long 0x00 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--15. " RDN_DELAY ,Delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " DMA2ECC_MODE ,DMA ECC mode" "0,1" textline " " bitfld.long 0x00 10. " DEV_IRQ ,ATA device interrupt received" "Not received,Received" bitfld.long 0x00 9. " TIMEOUT_IRQ ,Interrupt timeout" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " BURST_EN ,4-transfer burst on APB bus enable" "Disabled,Enabled" bitfld.long 0x00 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "Not aborted,Aborted" textline " " bitfld.long 0x00 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DEV_RESET ,Device reset" "No reset,Reset" textline " " bitfld.long 0x00 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Low,High" bitfld.long 0x00 1. " CAMERA_MODE ,CAMERA Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " GPMI_MODE ,GPMI Mode" "NAND,ATA" line.long 0x04 "GPMI_CTRL1_SET,GPMI Control Set Register 1" bitfld.long 0x04 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Set" bitfld.long 0x04 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Set" textline " " bitfld.long 0x04 29. " WRITE_CLK_STOP ,Stop clock durning data write" "No effect,Set" bitfld.long 0x04 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Set" textline " " bitfld.long 0x04 27. " GPMI_CLK_DIV2_EN ,gpmi clk divider enable" "No effect,Set" bitfld.long 0x04 26. " UPDATE_CS ,Force CS value update" "No effect,Set" textline " " bitfld.long 0x04 25. " SSYNCMODE ,Asynchronous/synchronous mode" "Async,Sync" bitfld.long 0x04 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "No effect,Set" textline " " bitfld.long 0x04 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,6-10 ns,7-12 ns,No delay" bitfld.long 0x04 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "No effect,Set" textline " " bitfld.long 0x04 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Set" bitfld.long 0x04 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Set" textline " " bitfld.long 0x04 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Set" bitfld.long 0x04 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Set" textline " " bitfld.long 0x04 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 11. " DMA2ECC_MODE ,DMA ECC mode" "No effect,Set" textline " " bitfld.long 0x04 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Set" bitfld.long 0x04 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Set" textline " " bitfld.long 0x04 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Set" bitfld.long 0x04 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Set" textline " " bitfld.long 0x04 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " DEV_RESET ,Device reset" "No effect,Set" textline " " bitfld.long 0x04 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Set" bitfld.long 0x04 1. " CAMERA_MODE ,CAMERA Mode" "No effect,Set" textline " " bitfld.long 0x04 0. " GPMI_MODE ,GPMI Mode" "No effect,Set" line.long 0x08 "GPMI_CTRL1_CLR,GPMI Control Clear Register 1" bitfld.long 0x08 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Clear" bitfld.long 0x08 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Clear" textline " " bitfld.long 0x08 29. " WRITE_CLK_STOP ,Stop clock durning data write" "No effect,Clear" bitfld.long 0x08 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " GPMI_CLK_DIV2_EN ,gpmi clk divider enable" "No effect,Clear" bitfld.long 0x08 26. " UPDATE_CS ,Force CS value update" "No effect,Clear" textline " " bitfld.long 0x08 25. " SSYNCMODE ,Asynchronous/synchronous mode" "Async,Sync" bitfld.long 0x08 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "No effect,Clear" textline " " bitfld.long 0x08 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,6-10 ns,7-12 ns,No delay" bitfld.long 0x08 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "No effect,Clear" textline " " bitfld.long 0x08 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Clear" bitfld.long 0x08 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Clear" textline " " bitfld.long 0x08 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Clear" bitfld.long 0x08 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Clear" textline " " bitfld.long 0x08 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 11. " DMA2ECC_MODE ,DMA ECC mode" "No effect,Clear" textline " " bitfld.long 0x08 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Clear" bitfld.long 0x08 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Clear" textline " " bitfld.long 0x08 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Clear" bitfld.long 0x08 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Clear" textline " " bitfld.long 0x08 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x08 3. " DEV_RESET ,Device reset" "No effect,Clear" textline " " bitfld.long 0x08 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Clear" bitfld.long 0x08 1. " CAMERA_MODE ,CAMERA Mode" "No effect,Clear" textline " " bitfld.long 0x08 0. " GPMI_MODE ,GPMI Mode" "No effect,Clear" line.long 0x0c "GPMI_CTRL1_TOG,GPMI Control Toggle Register 1" bitfld.long 0x0c 31. " DEV_CLK_STOP ,Device clock stop" "Not toggled,Toggled" bitfld.long 0x0c 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "Not toggled,Toggled" textline " " bitfld.long 0x0c 29. " WRITE_CLK_STOP ,Stop clock durning data write" "Not toggled,Toggled" bitfld.long 0x0c 28. " TOGGLE_MODE ,Samsung toggle mode enable" "Not toggled,Toggled" textline " " bitfld.long 0x0c 27. " GPMI_CLK_DIV2_EN ,gpmi clk divider enable" "Not toggled,Toggled" bitfld.long 0x0c 26. " UPDATE_CS ,Force CS value update" "Not toggled,Toggled" textline " " bitfld.long 0x0c 25. " SSYNCMODE ,Asynchronous/synchronous mode" "Async,Sync" bitfld.long 0x0c 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "Not toggled,Toggled" textline " " bitfld.long 0x0c 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,6-10 ns,7-12 ns,No delay" bitfld.long 0x0c 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "Not toggled,Toggled" textline " " bitfld.long 0x0c 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not toggled,Toggled" bitfld.long 0x0c 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "Not toggled,Toggled" textline " " bitfld.long 0x0c 17. " DLL_ENABLE ,GPMI DLL enable bit" "Not toggled,Toggled" bitfld.long 0x0c 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Not toggled,Toggled" textline " " bitfld.long 0x0c 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0c 11. " DMA2ECC_MODE ,DMA ECC mode" "Not toggled,Toggled" textline " " bitfld.long 0x0c 10. " DEV_IRQ ,ATA device interrupt received" "Not toggled,Toggled" bitfld.long 0x0c 9. " TIMEOUT_IRQ ,Interrupt timeout" "Not toggled,Toggled" textline " " bitfld.long 0x0c 8. " BURST_EN ,4-transfer burst on APB bus enable" "Not toggled,Toggled" bitfld.long 0x0c 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "Not toggled,Toggled" textline " " bitfld.long 0x0c 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 3. " DEV_RESET ,Device reset" "Not toggled,Toggled" textline " " bitfld.long 0x0c 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Not toggled,Toggled" bitfld.long 0x0c 1. " CAMERA_MODE ,CAMERA Mode" "Not toggled,Toggled" textline " " bitfld.long 0x0c 0. " GPMI_MODE ,GPMI Mode" "Not toggled,Toggled" textline "" line.long 0x10 "GPMI_TIMING0,GPMI Timing Register 0" hexmask.long.byte 0x10 16.--23. 1. " ADDRESS_SETUP ,Number of GPMICLK cycles that the CE signals are active before a strobe is asserted" hexmask.long.byte 0x10 8.--15. 1. " DATA_HOLD ,Data bus hold time in GPMICLK cycles" hexmask.long.byte 0x10 0.--7. 1. " DATA_SETUP ,Data bus setup time in GPMICLK cycles" group.long 0x80++0x03 line.long 0x00 "GPMI_TIMING1,GPMI Timing Register 1" hexmask.long.word 0x00 16.--31. 1. " DEVICE_BUSY_TIMEOUT ,Timeout waiting for NAND Ready/Busy" group.long 0x90++0x03 line.long 0x00 "GPMI_TIMING2,GPMI Timing Register 2" bitfld.long 0x00 29.--31. " TRPSTH ,Toggle NAND timing control delay TRPSTH GPMICLK cycles" "8,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " TCR ,Toggle NAND timing control delay (TRC+1) GPMICLK cycles" "0,1,2,3" bitfld.long 0x00 24.--26. " READ_LATENCY ,Read latency" "0,1,2,3,4,5,3,3" bitfld.long 0x00 16.--20. " CE_DELAY ,CE delay" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 12.--15. " PREAMBLE_DELAY ,Pre-amble delay" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " POSTAMBLE_DELAY ,Post-amble delay" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CMDADD_PAUSE ,Delay time from cmd/addr pause to cmd/addr resume in GPMICLK cycles" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DATA_PAUSE ,Delay time from data pause to data resume in GPMICLK cycles" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xa0++0x03 line.long 0x00 "GPMI_DATA,GPMI DMA Data Transfer Register" rgroup.long 0xb0++0x03 line.long 0x00 "GPMI_STAT,GPMI Status Register" hexmask.long.byte 0x00 24.--31. 1. " READY_BUSY ,NAND Ready_Busy Input pins" textline " " bitfld.long 0x00 23. " RDY_TIMEOUT[7] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 22. " [6] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 21. " [5] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 20. " [4] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" textline " " bitfld.long 0x00 19. " [3] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 18. " [2] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 17. " [1] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 16. " [0] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" textline " " bitfld.long 0x00 15. " DEV7_ERROR ,Error condition on NAND Device accessed by DMA channel 7" "No error,Error" bitfld.long 0x00 14. " DEV6_ERROR ,Error condition on NAND Device accessed by DMA channel 6" "No error,Error" bitfld.long 0x00 13. " DEV5_ERROR ,Error condition on NAND Device accessed by DMA channel 5" "No error,Error" bitfld.long 0x00 12. " DEV4_ERROR ,Error condition on NAND Device accessed by DMA channel 4" "No error,Error" textline " " bitfld.long 0x00 11. " DEV3_ERROR ,Error condition on NAND Device accessed by DMA channel 3" "No error,Error" bitfld.long 0x00 10. " DEV2_ERROR ,Error condition on NAND Device accessed by DMA channel 2" "No error,Error" bitfld.long 0x00 9. " DEV1_ERROR ,Error condition on NAND Device accessed by DMA channel 1" "No error,Error" bitfld.long 0x00 8. " DEV0_ERROR ,Error condition on NAND Device accessed by DMA channel 0" "No error,Error" textline " " bitfld.long 0x00 4. " ATA_IRQ ,Status of ATA_IRQ input pin" "Low,High" bitfld.long 0x00 3. " INVALID_BUFFER_MASK ,ECC Buffer Mask" "Not invalid,Invalid" bitfld.long 0x00 2. " FIFO_EMPTY ,Fifo empty" "Not empty,Empty" bitfld.long 0x00 1. " FIFO_FULL ,Fifo full" "Not full,Full" textline " " bitfld.long 0x00 0. " PRESENT ,GPMI present" "Not present,Present" rgroup.long 0xc0++0x03 line.long 0x00 "GPMI_DEBUG,GPMI Debug Information Register" bitfld.long 0x00 31. " WAIT_FOR_READY_END[7] ,WAIT_FOR_READY command end of channel 7" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,WAIT_FOR_READY command end of channel 6" "Not occurred,Occurred" bitfld.long 0x00 29. " [5] ,WAIT_FOR_READY command end of channel 5" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,WAIT_FOR_READY command end of channel 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " [3] ,WAIT_FOR_READY command end of channel 3" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,WAIT_FOR_READY command end of channel 2" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,WAIT_FOR_READY command end of channel 1" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,WAIT_FOR_READY command end of channel 0" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " DMA_SENSE[7] ,Sense state of channel 7" "No effect,Failed/Timeouted" bitfld.long 0x00 22. " [6] ,Sense state of channel 6" "No effect,Failed/Timeouted" bitfld.long 0x00 21. " [5] ,Sense state of channel 5" "No effect,Failed/Timeouted" bitfld.long 0x00 20. " [4] ,Sense state of channel 4" "No effect,Failed/Timeouted" textline " " bitfld.long 0x00 19. " [3] ,Sense state of channel 3" "No effect,Failed/Timeouted" bitfld.long 0x00 18. " [2] ,Sense state of channel 2" "No effect,Failed/Timeouted" bitfld.long 0x00 17. " [1] ,Sense state of channel 1" "No effect,Failed/Timeouted" bitfld.long 0x00 16. " [0] ,Sense state of channel 0" "No effect,Failed/Timeouted" textline " " bitfld.long 0x00 15. " DMAREQ[7] ,DMA request line for channel 7" "Not requested,Requested" bitfld.long 0x00 14. " [6] ,DMA request line for channel 6" "Not requested,Requested" bitfld.long 0x00 13. " [5] ,DMA request line for channel 5" "Not requested,Requested" bitfld.long 0x00 12. " [4] ,DMA request line for channel 4" "Not requested,Requested" textline " " bitfld.long 0x00 11. " [3] ,DMA request line for channel 3" "Not requested,Requested" bitfld.long 0x00 10. " [2] ,DMA request line for channel 2" "Not requested,Requested" bitfld.long 0x00 9. " [1] ,DMA request line for channel 1" "Not requested,Requested" bitfld.long 0x00 8. " [0] ,DMA request line for channel 0" "Not requested,Requested" textline " " bitfld.long 0x00 7. " CMD_END[7] ,Command End toggle to DMA Channel 7" "Not finished,Finished" bitfld.long 0x00 6. " [6] ,Command End toggle to DMA Channel 6" "Not finished,Finished" textline " " bitfld.long 0x00 5. " [5] ,Command End toggle to DMA Channel 5" "Not finished,Finished" bitfld.long 0x00 4. " [4] ,Command End toggle to DMA Channel 4" "Not finished,Finished" bitfld.long 0x00 3. " [3] ,Command End toggle to DMA Channel 3" "Not finished,Finished" bitfld.long 0x00 2. " [2] ,Command End toggle to DMA Channel 2" "Not finished,Finished" textline " " bitfld.long 0x00 1. " [1] ,Command End toggle to DMA Channel 1" "Not finished,Finished" bitfld.long 0x00 0. " [0] ,Command End toggle to DMA Channel 0" "Not finished,Finished" textline "" rgroup.long 0xd0++0x03 line.long 0x00 "GPMI_VERSION,GPMI Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0x0E0++0x03 line.long 0x00 "GPMI_DEBUG2,GPMI Debug2 Information Register" rbitfld.long 0x00 24.--27. " UDMA_STATE ,UDMA state" "USM_IDLE,USM_DMARQ,USM_ACK,USM_FIFO_E,USM_WPAUSE,USM_TSTRB,USM_CAPTUR,USM_DATOUT,USM_CRC,USM_WAIT_R,USM_END,USM_WAIT_S,USM_RPAUSE,USM_RSTOP,USM_WTERM,USM_RTERM" rbitfld.long 0x00 23. " BUSY ,When asserted the GPMI is busy" "Disabled,Enabled" rbitfld.long 0x00 20.--22. " PIN_STATE ,Pin state" "PSM_IDLE,PSM_BYTCNT,PSM_ADDR,PSM_STALL,PSM_STROBE,PSM_ATARDY,PSM_DHOLD,PSM_DONE" rbitfld.long 0x00 16.--19. " MAIN_STATE ,Main state" "MSM_IDLE,MSM_BYTCNT,MSM_WAITFE,MSM_WAITFR,MSM_DMAREQ,MSM_DMAACK,MSM_WAITFF,MSM_LDFIFO,MSM_LDDMAR,MSM_RDCMP,MSM_DONE,,,,," textline " " rbitfld.long 0x00 12.--15. " SYND2GPMI_BE ,Data byte enable Input from BCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 11. " GPMI2SYND_VALID ,Data handshake output to BCH" "Not valid,Valid" rbitfld.long 0x00 10. " GPMI2SYND_READY ,Data handshake output to BCH" "Not ready,Ready" rbitfld.long 0x00 9. " SYND2GPMI_VALID ,Data handshake Input from BCH" "Not valid,Valid" textline " " rbitfld.long 0x00 8. " SYND2GPMI_READY ,Data handshake Input from BCH" "Not ready,Ready" bitfld.long 0x00 7. " VIEW_DELAYED_RDN ,feedback RDN to drive the GPMI_ADDR[0]" "No delay,Delay" rbitfld.long 0x00 6. " UPDATE_WINDOW ,DLL is busy generating the required delay" "No,Yes" rbitfld.long 0x00 0.--5. " RDN_TAP ,This is the DLL tap calculated by the DLL controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x0F0++0x03 line.long 0x00 "GPMI_DEBUG3,GPMI Debug3 Information Register Description" hexmask.long.word 0x00 16.--31. 1. " APB_WORD_CNTR ,Reflects the number of words remains to be transferred on the APB bus" hexmask.long.word 0x00 0.--15. 1. " DEV_WORD_CNTR ,Reflects the number of words remains to be transferred on the ATA/Nand bus" textline "" width 25. group.long 0x0100++0x03 line.long 0x00 "GPMI_READ_DDR_DLL_CTRL,GPMI Double Rate Read DLL Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Update interval of 256 GPMICLK cycles" hexmask.long.byte 0x00 10.--17. 1. " SLV_OVERRIDE_VAL ,Select 1 of 256 physical taps manually" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " REFCLK_ON ,Reference clock" "Off,On" bitfld.long 0x00 7. " GATE_UPDATE ,Slave delay line" "No effect,Not updated" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the read clock" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,16/16" bitfld.long 0x00 2. " SLV_FORCE_UPD ,Slave delay line" "No effect,Updated" textline " " bitfld.long 0x00 1. " RESET ,Reset on DLL" "No effect,Reset" bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" group.long 0x0110++0x03 line.long 0x00 "GPMI_WRITE_DDR_DLL_CTRL,GPMI Double Rate Write DLL Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Update interval of 256 GPMICLK cycles" hexmask.long.byte 0x00 10.--17. 1. " SLV_OVERRIDE_VAL ,Select 1 of 256 physical taps manually" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " REFCLK_ON ,Reference clock" "Off,On" bitfld.long 0x00 7. " GATE_UPDATE ,Slave delay line" "No effect,Not updated" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the read clock" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,16/16" bitfld.long 0x00 2. " SLV_FORCE_UPD ,Slave delay line" "No effect,Updated" textline " " bitfld.long 0x00 1. " RESET ,Reset on DLL" "No effect,Reset" bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" rgroup.long 0x0120++0x03 line.long 0x00 "GPMI_READ_DDR_DLL_STS,GPMI Double Rate Read DLL Status Register" hexmask.long.byte 0x00 17.--24. 1. " REF_SEL ,Reference delay line select status" bitfld.long 0x00 16. " REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" hexmask.long.byte 0x00 1.--8. 1. " SLV_SEL ,Slave delay line select status" bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Unlocked,Locked" rgroup.long 0x0130++0x03 line.long 0x00 "GPMI_WRITE_DDR_DLL_STS,GPMI Double Rate Write DLL Status Register" hexmask.long.byte 0x00 17.--24. 1. " REF_SEL ,Reference delay line select status" bitfld.long 0x00 16. " REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" hexmask.long.byte 0x00 1.--8. 1. " SLV_SEL ,Slave delay line select status" bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Unlocked,Locked" width 0xB tree.end tree "GPT (General Purpose Timer)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02098000 else base ad:0x42098000 endif width 8. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force Output Compare Channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force Output Compare Channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force Output Compare Channel 1" "No effect,Force" textline " " bitfld.long 0x00 26.--28. " OM3 ,Output Compare Channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 23.--25. " OM2 ,Output Compare Channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output Compare Channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" textline " " bitfld.long 0x00 18.--19. " IM2 ,Input Capture Channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input Capture Channel 1 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FRR ,Free-Run or Restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock Source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,," bitfld.long 0x00 5. " STOPEN ,GPT Stop Mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT Doze Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " WAITEN ,GPT Wait Mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENMOD ,GPT Enable mode (Main Counter Value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT Enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover Flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 Flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x08 2. " OF3 ,Output Compare 3 Flag" "Not occurred,Occurred" eventfld.long 0x08 1. " OF2 ,Output Compare 2 Flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output Compare 1 Flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 2. " OF3IE ,Output Compare 3 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0C 1. " OF2IE ,Output Compare 2 Interrupt Enable" "Freeze,Reset" bitfld.long 0x0C 0. " OF1IE ,Output Compare 1 Interrupt Enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 12. tree.end tree "I2C (I2C Controller)" tree "I2C_1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021A0000 else base ad:0x421A0000 endif width 6. group.word 0x00++0x01 line.word 0x00 "IADR,I2C Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "IFDR,I2C Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "/30,/32,/36,/42,/48,/52,/60,/72,/80,/88,/104,/128,/144,/160,/192,/240,/288,/320,/384,/480,/576,/640,/768,/960,/1152,/1280,/1536,/1920,/2304,/2560,/3072,/3840,/22,/24,/26,/28,/32,/36,/40,/44,/48,/56,/64,/72,/80,/96,/112,/128,/160,/192,/224,/256,/320,/384,/448,/512,/640,/768,/896,/1024,/1280,/1536,/1792,/2048" group.word 0x08++0x01 line.word 0x00 "I2CR,I2C Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/slave mode select bit" "Slave,Master" textline " " bitfld.word 0x00 4. " MTX ,Transmit/receive mode select bit" "Receive,Transmit" bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "Enabled,Disabled" bitfld.word 0x00 2. " RSTA ,Repeat start" "No repeat,Repeated" group.word 0x0C++0x01 line.word 0x00 "I2SR,I2C Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "Disabled,Enabled" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Disabled,Enabled" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" textline " " bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" rbitfld.word 0x00 2. " SRW ,Slave read/write" "Receive,Transmit" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" textline " " rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,No ACK" group.word 0x10++0x01 line.word 0x00 "I2DR,I2C Data I/O Register" hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data byte" width 0x0B tree.end tree "I2C_2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021A4000 else base ad:0x421A4000 endif width 6. group.word 0x00++0x01 line.word 0x00 "IADR,I2C Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "IFDR,I2C Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "/30,/32,/36,/42,/48,/52,/60,/72,/80,/88,/104,/128,/144,/160,/192,/240,/288,/320,/384,/480,/576,/640,/768,/960,/1152,/1280,/1536,/1920,/2304,/2560,/3072,/3840,/22,/24,/26,/28,/32,/36,/40,/44,/48,/56,/64,/72,/80,/96,/112,/128,/160,/192,/224,/256,/320,/384,/448,/512,/640,/768,/896,/1024,/1280,/1536,/1792,/2048" group.word 0x08++0x01 line.word 0x00 "I2CR,I2C Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/slave mode select bit" "Slave,Master" textline " " bitfld.word 0x00 4. " MTX ,Transmit/receive mode select bit" "Receive,Transmit" bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "Enabled,Disabled" bitfld.word 0x00 2. " RSTA ,Repeat start" "No repeat,Repeated" group.word 0x0C++0x01 line.word 0x00 "I2SR,I2C Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "Disabled,Enabled" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Disabled,Enabled" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" textline " " bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" rbitfld.word 0x00 2. " SRW ,Slave read/write" "Receive,Transmit" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" textline " " rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,No ACK" group.word 0x10++0x01 line.word 0x00 "I2DR,I2C Data I/O Register" hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data byte" width 0x0B tree.end tree "I2C_3" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021A8000 else base ad:0x421A8000 endif width 6. group.word 0x00++0x01 line.word 0x00 "IADR,I2C Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "IFDR,I2C Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "/30,/32,/36,/42,/48,/52,/60,/72,/80,/88,/104,/128,/144,/160,/192,/240,/288,/320,/384,/480,/576,/640,/768,/960,/1152,/1280,/1536,/1920,/2304,/2560,/3072,/3840,/22,/24,/26,/28,/32,/36,/40,/44,/48,/56,/64,/72,/80,/96,/112,/128,/160,/192,/224,/256,/320,/384,/448,/512,/640,/768,/896,/1024,/1280,/1536,/1792,/2048" group.word 0x08++0x01 line.word 0x00 "I2CR,I2C Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/slave mode select bit" "Slave,Master" textline " " bitfld.word 0x00 4. " MTX ,Transmit/receive mode select bit" "Receive,Transmit" bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "Enabled,Disabled" bitfld.word 0x00 2. " RSTA ,Repeat start" "No repeat,Repeated" group.word 0x0C++0x01 line.word 0x00 "I2SR,I2C Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "Disabled,Enabled" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Disabled,Enabled" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" textline " " bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" rbitfld.word 0x00 2. " SRW ,Slave read/write" "Receive,Transmit" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" textline " " rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,No ACK" group.word 0x10++0x01 line.word 0x00 "I2DR,I2C Data I/O Register" hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data byte" width 0x0B tree.end tree "I2C_4" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021F8000 else base ad:0x421F8000 endif width 6. group.word 0x00++0x01 line.word 0x00 "IADR,I2C Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "IFDR,I2C Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "/30,/32,/36,/42,/48,/52,/60,/72,/80,/88,/104,/128,/144,/160,/192,/240,/288,/320,/384,/480,/576,/640,/768,/960,/1152,/1280,/1536,/1920,/2304,/2560,/3072,/3840,/22,/24,/26,/28,/32,/36,/40,/44,/48,/56,/64,/72,/80,/96,/112,/128,/160,/192,/224,/256,/320,/384,/448,/512,/640,/768,/896,/1024,/1280,/1536,/1792,/2048" group.word 0x08++0x01 line.word 0x00 "I2CR,I2C Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/slave mode select bit" "Slave,Master" textline " " bitfld.word 0x00 4. " MTX ,Transmit/receive mode select bit" "Receive,Transmit" bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "Enabled,Disabled" bitfld.word 0x00 2. " RSTA ,Repeat start" "No repeat,Repeated" group.word 0x0C++0x01 line.word 0x00 "I2SR,I2C Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "Disabled,Enabled" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Disabled,Enabled" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" textline " " bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" rbitfld.word 0x00 2. " SRW ,Slave read/write" "Receive,Transmit" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" textline " " rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,No ACK" group.word 0x10++0x01 line.word 0x00 "I2DR,I2C Data I/O Register" hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data byte" width 0x0B tree.end tree.end tree "IOMUXC (IOMUX Controller)" tree "General Purpose Registers" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020E4000 else base ad:0x420E0000 endif width 7. group.long 0x00++0x0F line.long 0x00 "GPR0,General Purpose Register 0" bitfld.long 0x00 22. " DMAREQ_MUX_SEL22 ,Selects between two possible sources for SDMA_EVENT[30]" "uart3.ipd_uart_tx_dmareq_b," bitfld.long 0x00 21. " DMAREQ_MUX_SEL21 ,Selects between two possible sources for SDMA_EVENT[29]" "uart3.ipd_uart_rx_dmareq_b," bitfld.long 0x00 20. " DMAREQ_MUX_SEL20 ,Selects between two possible sources for SDMA_EVENT[2]" "iomux_top.sdma_events[14],csi2.ipi_csi_int_b" textline " " bitfld.long 0x00 19. " DMAREQ_MUX_SEL19 ,Selects between two possible sources for SDMA_EVENT[47]" "uart6.ipd_uart_tx_dmareq_b," bitfld.long 0x00 18. " DMAREQ_MUX_SEL18 ,Selects between two possible sources for SDMA_EVENT[34]" "uart5.ipd_uart_tx_dmareq_b,sai2.ipd_req_sai_tx" bitfld.long 0x00 17. " DMAREQ_MUX_SEL17 ,Selects between two possible sources for SDMA_EVENT[33]" "uart5.ipd_uart_rx_dmareq_b,sai2.ipd_req_sai_rx" textline " " bitfld.long 0x00 16. " DMAREQ_MUX_SEL16 ,Selects between two possible sources for SDMA_EVENT[32]" "uart4.ipd_uart_tx_dmareq_b,sai1.ipd_req_sai_tx" bitfld.long 0x00 15. " DMAREQ_MUX_SEL15 ,Selects between two possible sources for SDMA_EVENT[31]" "uart4.ipd_uart_rx_dmareq_b,sai1.ipd_req_sai_rx" bitfld.long 0x00 14. " DMAREQ_MUX_SEL14 ,Selects between two possible sources for SDMA_EVENT[23]" "esai.ipd_esai_rx_b,i2c3.ipi_int_b" textline " " bitfld.long 0x00 13. " DMAREQ_MUX_SEL13 ,Selects between two possible sources for SDMA_EVENT[14]" "spdif.drq0_spdif_b,iomux_top.sdma_events[15]" bitfld.long 0x00 12. " DMAREQ_MUX_SEL12 ,Selects between two possible sources for SDMA_EVENT[13]" "adc2.ipd_req,gpt.ipi_int_gpt" bitfld.long 0x00 11. " DMAREQ_MUX_SEL11 ,Selects between two possible sources for SDMA_EVENT[12]" "ecspi5.ipd_req_cspi_tdma_b,lcdif2.lcdif_irq" textline " " bitfld.long 0x00 10. " DMAREQ_MUX_SEL10 ,Selects between two possible sources for SDMA_EVENT[11]" "ecspi5.ipd_req_cspi_rdma_b," bitfld.long 0x00 9. " DMAREQ_MUX_SEL9 ,Selects between two possible sources for SDMA_EVENT[10]" "ecspi4.ipd_req_cspi_tdma_b," bitfld.long 0x00 8. " DMAREQ_MUX_SEL8 ,Selects between two possible sources for SDMA_EVENT[9]" "ecspi4.ipd_req_cspi_rdma_b,epit2.ipi_int_epit_oc" textline " " bitfld.long 0x00 7. " DMAREQ_MUX_SEL7 ,Selects between two possible sources for SDMA_EVENT[8]" "ecspi3.ipd_req_cspi_tdma_b,lcdif1.lcdif_irq" bitfld.long 0x00 6. " DMAREQ_MUX_SEL6 ,Selects between two possible sources for SDMA_EVENT[7]" "ecspi3.ipd_req_cspi_rdma_b,csi1.ipi_csi_int_b" bitfld.long 0x00 5. " DMAREQ_MUX_SEL5 ,Selects between two possible sources for SDMA_EVENT[6]" "ecspi2.ipd_req_cspi_tdma_b,pxp.pxp_irq" textline " " bitfld.long 0x00 4. " DMAREQ_MUX_SEL4 ,Selects between two possible sources for SDMA_EVENT[5]" "ecspi2.ipd_req_cspi_rdma_b,i2c1.ipi_int_b" bitfld.long 0x00 3. " DMAREQ_MUX_SEL3 ,Selects between two possible sources for SDMA_EVENT[4]" "ecspi1.ipd_req_cspi_tdma_b,i2c2.ipi_int_b" bitfld.long 0x00 2. " DMAREQ_MUX_SEL2 ,Selects between two possible sources for SDMA_EVENT[3]" "ecspi1.ipd_req_cspi_rdma_b,i2c3.ipi_int_b" textline " " bitfld.long 0x00 1. " DMAREQ_MUX_SEL1 ,Selects between two possible sources for SDMA_EVENT[1]" "adc1.ipd_req,i2c4.ipi_int_b" bitfld.long 0x00 0. " DMAREQ_MUX_SEL0 ,Selects between two possible sources for SDMA_EVENT[0]" "uart6.ipd_uart_rx_dmareq," textline " " line.long 0x04 "GPR1,General Purpose Register 1" bitfld.long 0x04 27. " ARMA9_IPG_CLK_EN ,ARM A9 platform IPG clock" "Gated,Enabled" bitfld.long 0x04 26. " ARMA9_CLK_AHB_EN ,ARM A9 platform AHB clock enable" "Gated,Enabled" bitfld.long 0x04 25. " ARMA9_CLK_ATB_EN ,ARM A9 platform ATB clock enable" "Gated,Enabled" textline " " bitfld.long 0x04 24. " ARMA9_CLK_APB_DBG_EN ,ARM A9 platform APB clock enable" "Gated,Enabled" bitfld.long 0x04 23. " TZASC1_BOOT_LOCK ,TZASC-1 secure boot lock" "Disabled,Enabled" bitfld.long 0x04 22. " EXC_MON ,Exclusive monitor response select of illegal command" "OKEY,SLVError" textline " " bitfld.long 0x04 20. " VDEC_SW_RST ,Video Decoder Software Reset" "Released,Held" bitfld.long 0x04 19. " VADC_SW_RST ,Video ADC Software Reset" "Released,Held" bitfld.long 0x04 18. " ENET2_TX_CLK_DIR ,ENET2_TX_CLK data direction control when anatop" "Disabled,Enabled" textline " " bitfld.long 0x04 17. " ENET1_TX_CLK_DIR ,ENET1_TX_CLK data direction control when anatop" "Disabled,Enabled" bitfld.long 0x04 16. " ADD_DS ,Drive strength" "10% stronger,Normal" bitfld.long 0x04 15. " USB_EXP_MODE ,USB Exposure mode" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " ENET2_CLK_SEL ,ENET2 reference clock mode select" "REF_ENETPLL0,ENET2_TX_CLK" bitfld.long 0x04 13. " ENET1_CLK_SEL ,ENET1 reference clock mode select" "REF_ENETPLL1,ENET1_TX_CLK" bitfld.long 0x04 12. " GINT ,Global interrupt 0 bit" "Not asserted,Asserted" textline " " bitfld.long 0x04 10.--11. " ADDRS3 ,Address Space 3" "32-MBytes,64-MBytes,128-MBytes," bitfld.long 0x04 9. " ACT_CS3 ,Active Chip 3" "Not activated,Activated" bitfld.long 0x04 7.--8. " ADDRS2 ,Address Space 2" "32-MBytes,64-MBytes,128-MBytes," textline " " bitfld.long 0x04 6. " ACT_CS2 ,Active Chip 2" "Not activated,Activated" bitfld.long 0x04 4.--5. " ADDRS1 ,Address Space 1" "32-MBytes,64-MBytes,128-MBytes," bitfld.long 0x04 3. " ACT_CS1 ,Active Chip 1" "Not activated,Activated" textline " " bitfld.long 0x04 1.--2. " ADDRS0 ,Address Space 0" "32-MBytes,64-MBytes,128-MBytes," bitfld.long 0x04 0. " ACT_CS0 ,Active Chip 0" "Not activated,Activated" line.long 0x08 "GPR2,General Purpose Register 2" bitfld.long 0x08 31. " DRAM_CKE_BYPASS ,Reset value for the LDB counter" "MMDC PHY,GPR2" bitfld.long 0x08 30. " DRAM_CKE1 ,CKE1 Bypass Value" "0,1" bitfld.long 0x08 29. " DRAM_CKE0 ,CKE0 Bypass Value" "0,1" textline " " bitfld.long 0x08 28. " DRAM_RESET ,DRAM Reset Value" "0,1" bitfld.long 0x08 27. " DRAM_RESET_BYPASS ,DRAM Reset Bypass Select" "MMDC,GPR2" bitfld.long 0x08 26. " MQS_OVERSAMPLE ,Used to control the PWM oversampling rate compared with mclk" "32,64" textline " " bitfld.long 0x08 25. " MQS_EN ,MQS enable" "Disabled,Enabled" bitfld.long 0x08 24. " MQS_SW_RST ,MQS software reset" "No reset,Reset" hexmask.long.byte 0x08 16.--23. 1. " MQS_CLK_DIV ,Divider ratio control for mclk from hmclk. mclk frequency" textline " " bitfld.long 0x08 15. " L2_MEM_LIGHTSLEEP ,Light sleep state" "Disabled,Enabled" bitfld.long 0x08 14. " L2_MEM_DEEPSLEEP ,Control how memory enters Deep Sleep mode" "Not forced,Forced" bitfld.long 0x08 13. " L2_MEM_SHUTDOWN ,Shutdown state" "Disabled,Enabled" textline " " bitfld.long 0x08 12. " L2_MEM_EN_POWERSAVING ,Power saving features on L2 memory" "Disabled,Enabled" bitfld.long 0x08 11. " LCDIF2_MEM_LIGHTSLEEP ,Light sleep state" "Disabled,Enabled" bitfld.long 0x08 10. " LCDIF2_MEM_DEEPSLEEP ,Control how memory enters Deep Sleep mode" "Not forced,Forced" textline " " bitfld.long 0x08 9. " LCDIF2_MEM_SHUTDOWN ,Shutdown state" "Disabled,Enabled" bitfld.long 0x08 8. " LCDIF2_MEM_EN_POWERSAVING ,Power saving features on LCDIF memory" "Disabled,Enabled" bitfld.long 0x08 7. " LCDIF1_MEM_LIGHTSLEEP ,Light sleep state" "Disabled,Enabled" textline " " bitfld.long 0x08 6. " LCDIF1_MEM_DEEPSLEEP ,Control how memory enters Deep Sleep mode" "Not forced,Forced" bitfld.long 0x08 5. " LCDIF1_MEM_SHUTDOWN ,Shutdown state" "Disabled,Enabled" bitfld.long 0x08 4. " LCDIF1_MEM_EN_POWERSAVING ,Power saving features on LCDIF memory" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " PXP_MEM_LIGHTSLEEP ,Light sleep state" "Disabled,Enabled" bitfld.long 0x08 2. " PXP_MEM_DEEPSLEEP ,Deep sleep state" "Disabled,Enabled" bitfld.long 0x08 1. " PXP_MEM_SHUTDOWN ,Shutdown state" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PXP_MEM_EN_POWERSAVING ,Power saving features on PXP memory" "Disabled,Enabled" line.long 0x0C "GPR3,General Purpose Register 3" rbitfld.long 0x0C 27. " OCRAM_L2_STATUS[3] ,Write address pipeline status" "Valid,Changed" rbitfld.long 0x0C 26. " OCRAM_L2_STATUS[2] ,Write data pipeline status" "Valid,Changed" rbitfld.long 0x0C 25. " OCRAM_L2_STATUS[1] ,Read address pipeline status" "Valid,Changed" textline " " rbitfld.long 0x0C 24. " OCRAM_L2_STATUS[0] ,Read data pipeline status" "Valid,Changed" rbitfld.long 0x0C 23. " OCRAM_S_STATUS[3] ,Write address pipeline status" "Valid,Changed" rbitfld.long 0x0C 22. " OCRAM_S_STATUS[2] ,Write data pipeline status" "Valid,Changed" textline " " rbitfld.long 0x0C 21. " OCRAM_S_STATUS[1] ,Read address pipeline status" "Valid,Changed" rbitfld.long 0x0C 24. " OCRAM_S_STATUS[0] ,Read data pipeline status" "Valid,Changed" rbitfld.long 0x0C 27. " OCRAM_STATUS[3] ,Write address pipeline status" "Valid,Changed" textline " " rbitfld.long 0x0C 26. " OCRAM_STATUS[2] ,Write data pipeline status" "Valid,Changed" rbitfld.long 0x0C 25. " OCRAM_STATUS[1] ,Read address pipeline status" "Valid,Changed" rbitfld.long 0x0C 24. " OCRAM_STATUS[0] ,Read data pipeline status" "Valid,Changed" textline " " bitfld.long 0x0C 13. " CORE_DBG_ACK_EN ,Mask control of Core debug acknowledge to global debug acknowledge" "Not masked,Masked" bitfld.long 0x0C 11. " OCRAM_L2_CTL_3 ,Write address pipeline control bit 3" "Disabled,Enabled" bitfld.long 0x0C 10. " OCRAM_L2_CTL_2 ,Write address pipeline control bit 2" "Disabled,Enabled" textline " " bitfld.long 0x0C 9. " OCRAM_L2_CTL_1 ,Write address pipeline control bit 1" "Disabled,Enabled" bitfld.long 0x0C 8. " OCRAM_L2_CTL_0 ,Write address pipeline control bit 0" "Disabled,Enabled" bitfld.long 0x0C 7. " OCRAM_S_CTL_3 ,Write address pipeline control bit 3" "Disabled,Enabled" textline " " bitfld.long 0x0C 6. " OCRAM_S_CTL_2 ,Write address pipeline control bit 2" "Disabled,Enabled" bitfld.long 0x0C 5. " OCRAM_S_CTL_1 ,Write address pipeline control bit 1" "Disabled,Enabled" bitfld.long 0x0C 4. " OCRAM_S_CTL_0 ,Write address pipeline control bit 0" "Disabled,Enabled" textline " " bitfld.long 0x0C 3. " OCRAM_S_CTL_3 ,Write address pipeline control bit 3" "Disabled,Enabled" bitfld.long 0x0C 2. " OCRAM_S_CTL_2 ,Write address pipeline control bit 2" "Disabled,Enabled" bitfld.long 0x0C 1. " OCRAM_S_CTL_1 ,Write address pipeline control bit 1" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " OCRAM_S_CTL_0 ,Write address pipeline control bit 0" "Disabled,Enabled" rgroup.long 0x10++0x03 line.long 0x00 "GPR4,General Purpose Register 4" bitfld.long 0x00 31. " ARM_WFE ,ARM A9 WFE event out indication on WFE state of the cores" "Not WFE,WFE" bitfld.long 0x00 30. " ARM_WFI ,ARM A9 WFI event out indicating on WFI state of the cores" "Not WFI,WFI" bitfld.long 0x00 29. " L2_CLK_STOP ,L2 cache clock stop indication" "Running,Stopped" textline " " bitfld.long 0x00 22. " SAI2_STOP_ACK ,SAI2 stop acknowledge" "Not asserted,Asserted" bitfld.long 0x00 21. " SAI1_STOP_ACK ,SAI1 stop acknowledge" "Not asserted,Asserted" bitfld.long 0x00 20. " ENET2_STOP_ACK ,ENET2 stop acknowledge" "Not asserted,Asserted" textline " " bitfld.long 0x00 19. " ENET1_STOP_ACK ,ENET1 stop acknowledge" "Not asserted,Asserted" bitfld.long 0x00 18. " CAN2_STOP_ACK ,CAN2 stop acknowledge" "Not asserted,Asserted" bitfld.long 0x00 17. " CAN1_STOP_ACK ,CAN1 stop acknowledge" "Not asserted,Asserted" textline " " bitfld.long 0x00 16. " SDMA_STOP_ACK ,SDMA stop acknowledge" "Not asserted,Asserted" bitfld.long 0x00 6. " SAI2_STOP_REQ ,SAI2 stop request" "Not asserted,Asserted" bitfld.long 0x00 5. " SAI1_STOP_REQ ,SAI1 stop request" "Not asserted,Asserted" textline " " bitfld.long 0x00 4. " ENET2_STOP_REQ ,ENET2 stop request" "Not asserted,Asserted" bitfld.long 0x00 3. " ENET1_STOP_REQ ,ENET1 stop request" "Not asserted,Asserted" bitfld.long 0x00 2. " CAN2_STOP_REQ ,CAN2 stop request" "Not requested,Requested" textline " " bitfld.long 0x00 1. " CAN1_STOP_REQ ,CAN1 stop request" "Not requested,Requested" bitfld.long 0x00 0. " SDMA_STOP_REQ ,SDMA stop request" "Not requested,Requested" textline " " group.long 0x14++0x0F line.long 0x00 "GPR5,General Purpose Register 5" bitfld.long 0x00 31. " REF_1M_CLK_EPIT2 ,EPIT2 1MHz clock source select" "IPG_PERCLK,1MHz clock" bitfld.long 0x00 30. " REF_1M_CLK_EPIT1 ,EPIT1 1MHz clock source select" "IPG_PERCLK,1MHz clock" bitfld.long 0x00 29. " VREF_1M_CLK_GPT ,GPT 1MHz clock source select" "IPG_PERCLK,1MHz clock" textline " " bitfld.long 0x00 27.--28. " CSI2_MUX_CTRL ,CSI2 input mux control" "External,Video,VADC-CSI,GND" bitfld.long 0x00 26. " VADC_TO_CSI_CAPTURE_EN ,VADC to CSI Capture Circuit Enable" "Disabled,Enabled" bitfld.long 0x00 25. " VADC_TEST_GPR2 ,VADC Test Input Enable" "Test,Normal" textline " " bitfld.long 0x00 24. " VADC_TEST_6SX_GPR5 ,Video Decoder Debug Mux" "0,1" bitfld.long 0x00 23. " VADC_TEST_GPR3 ,Video Decoder Debug Mux select[0]" "0,1" bitfld.long 0x00 22. " LCDIF2_CSI_VSYNC_SEL ,LCDIF2 VSYNC Select" "CSI1,CSI2" textline " " bitfld.long 0x00 21. " LCDIF2_CSI_VSYNC_SEL ,LCDIF1 VSYNC Select" "CSI1,CSI2" bitfld.long 0x00 20. " WDOG3_MASK ,WDOG3 Timeout Mask" "Normal,Masked" bitfld.long 0x00 19. " PCIE_BTNRST ,PCIE_BTNRST" "0,1" textline " " bitfld.long 0x00 18. " PCIE_BTNRST ,PCIE_PERST" "0,1" bitfld.long 0x00 16.--17. " LCDIF_HANDSHAKE_PXP ,PXP Input Handshake Select" "LCDIF1,LCDIF2,GND,GND" bitfld.long 0x00 14.--15. " LCDIF_HANDSHAKE_LCDIF2 ,LCDIF2 Input Handshake Select" "CSI1,CS2,PXP,GND" textline " " bitfld.long 0x00 12.--13. " LCDIF_HANDSHAKE_LCDIF1 ,LCDIF1 Input Handshake Select" "CSI1,CS2,PXP,GND" bitfld.long 0x00 10.--11. " LCDIF_HANDSHAKE_CSI2 ,CSI2 Input Handshake Select" "LCDIF1,LCDIF2,GND,GND" bitfld.long 0x00 8.--9. " LCDIF_HANDSHAKE_CSI1 ,CSI1 Input Handshake Select" "LCDIF1,LCDIF2,GND,GND" textline " " bitfld.long 0x00 7. " WDOG2_MASK ,WDOG2 Timeout Mask" "Normal,Masked" bitfld.long 0x00 6. " WDOG1_MASK ,WDOG1 Timeout Mask" "Normal,Masked" bitfld.long 0x00 4.--5. " CSI1_MUX_CTRL ,CSI1 input mux control" "External,Video,VADC-CSI,GND" textline " " bitfld.long 0x00 3. " DISP_MUX_LDB_CTRL ,LDB Input Select" "LCDIF1,LCDIF2" bitfld.long 0x00 2. " DISP_MUX_DCIC2_CTRL ,DCIC2 Input Select" "LCDIF2,LDB" bitfld.long 0x00 1. " DISP_MUX_DCIC1_CTRL ,DCIC1 Input Select" "LCDIF1,LDB" textline " " bitfld.long 0x00 0. " SVADC_TEST_GPR1 ,VADC Clamp Test Input Enable" "Normal,Test" line.long 0x04 "GPR6,General Purpose Register 6" bitfld.long 0x04 20.--21. " COUNTER_RESET_VAL[10] ,Reset value for the LDB counter which determines when the shift registers are loaded with data" "5,3,4,6" bitfld.long 0x04 16.--18. " LVDS_CLK_SHIFT ,Reset value for the LDB counter which determines when the shift registers are loaded with data" "1100011,1110001,1111000,1000111,0001111,0011111,0111100,1100011" bitfld.long 0x04 9. " LCDIF_VS_POLARITY ,Vsync polarity for LCDIF interface" "High,Low" textline " " bitfld.long 0x04 6. " BIT_MAPPING_CH0 ,Data mapping for LVDS channel 0" "SPWG,JEIDA" bitfld.long 0x04 5. " DATA_WIDTH_CH0 ,Data width for LVDS channel 0" "18 bits,24 bits" bitfld.long 0x04 0.--1. " CH0_MODE ,LVDS channel 0 operation mode" "Disabled,LCDIF,Disabled," line.long 0x08 "GPR7,General Purpose Register 7" bitfld.long 0x08 21. " ASRC_SEL_CLK_C ,ASRC CLK C Select" "spdif_outclock,sai1_tx" bitfld.long 0x08 20. " ASRC_SEL_CLK_9 ,ASRC CLK 9 Select" "asrc_asrck_clock_9_pre_sai,sai1_tx" bitfld.long 0x08 19. " ASRC_SEL_CLK_4 ,ASRC CLK 4 Select" "spdif_srclk,sai1_rx" textline " " bitfld.long 0x08 18. " ASRC_SEL_CLK_1 ,ASRC CLK 1 Select" "asrc_asrck_clock_1_pre_sai,sai1_rx" bitfld.long 0x08 16.--17. " ASRC_SEL_SPDIF_TX ,SPDIF TX_CLK1 select" "asrck_clock_1,asrck_clock_2,asrck_clock_3,GND" bitfld.long 0x08 14.--15. " ASRC_SEL_SSI3_TX ,ASRC ASRCK_CLOCK_B select" "ssi3_tx,din_stck,ssi_stck,tx_bit_clk" textline " " bitfld.long 0x08 12.--13. " ASRC_SEL_SSI3_RX ,ASRC ASRCK_CLOCK_3 select" "ssi3_rx,din_stck,ssi_stck,rx_bit_clk" bitfld.long 0x08 10.--11. " ASRC_SEL_SSI2_TX ,ASRC ASRCK_CLOCK_A select" "ssi2_tx,din_stck,ssi_stck,tx_bit_clk" bitfld.long 0x08 8.--9. " ASRC_SEL_SSI2_RX ,ASRC ASRCK_CLOCK_2 select" "ssi2_rx,din_stck,ssi_stck,rx_bit_clk" textline " " bitfld.long 0x08 6.--7. " ASRC_SEL_SSI1_TX ,ASRC ASRCK_CLOCK_9 select" "ssi1_tx,din_stck,ssi_stck,tx_bit_clk" bitfld.long 0x08 4.--5. " ASRC_SEL_SSI1_RX ,ASRC ASRCK_CLOCK_1 select" "ssi1_rx,din_stck,ssi_stck,rx_bit_clk" bitfld.long 0x08 2.--3. " ASRC_SEL_ESAI_TX ,ASRC ASRCK_CLOCK_8 select" "esai_rx,ipp_ind_sckt,ipp_do_sckt,GND" textline " " bitfld.long 0x08 0.--1. " ASRC_SEL_ESAI_RX ,ASRC ASRCK_CLOCK_0 select" "esai_rx,ipp_ind_sckr,ipp_do_sckr,GND" line.long 0x0C "GPR8,General Purpose Register 8" hexmask.long.byte 0x0C 25.--31. 1. " PCS_TX_SWING_LOW ,PCIe_TX_SWING_LOW" hexmask.long.byte 0x0C 18.--24. 1. " PCS_TX_SWING_FULL ,PCIe_TX_SWING_FULL" bitfld.long 0x0C 12.--17. " PCS_TX_DEEMMPH_GEN2_6DB ,PCS_TX_DEEMMPH_GEN2_6DB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0C 6.--11. " PCS_TX_DEEMPH_GEN2_3P5DB ,PCS_TX_DEEMPH_GEN2_3P5DB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " PCS_TX_DEEMPH_GEN1 ,PCS_TX_DEEMPH_GEN1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x24++0x03 line.long 0x00 "GPR9,General Purpose Register 9" bitfld.long 0x00 0. " TZASC1_BYP ,TZASC-1 bypass/transaction check" "Bypass,Check" textline " " group.long 0x28++0x0F line.long 0x00 "GPR10,General Purpose Register 10" bitfld.long 0x00 11.--15. " OCRAM_TZ_ADDR ,OCRAM TrustZone start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " OCRAM_TZ_EN ,ARM non secure debug OCRAM TrustZone (TZ) enable" "Disabled,Enabled" bitfld.long 0x00 4.--9. " OCRAM_L2_TZ_ADDR ,OCRAM_L2 TrustZone (TZ) start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 3. " OCRAM_L2_TZ_EN ,OCRAM_L2 TrustZone (TZ) enable" "Disabled,Enabled" bitfld.long 0x00 2. " SEC_ERR_RESP ,Security error response enable for all security gaskets" "OKEY,SLVError" bitfld.long 0x00 1. " DBG_CLK_EN ,ARM Debug clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DBG_EN ,ARM non secure (non-invasive) debug enable" "Disabled,Enabled" line.long 0x04 "GPR11,General Purpose Register 11" bitfld.long 0x04 11.--12. " OCRAM_S_TZ_ADDR ,OCRAM_S TrustZone (TZ) start address" "0,1,2,3" bitfld.long 0x04 10. " OCRAM_S_TZ_EN ,OCRAM_S TrustZone (TZ) enable" "Disabled,Enabled" bitfld.long 0x04 1. " OCRAM_L2_EN ,L2 cache as ocram" "Disabled,Enabled" line.long 0x08 "GPR12,General Purpose Register 12" bitfld.long 0x08 31. " PCIE_CTRL_CFG_L1 ,Enabled PCIE_CTRL_CFG_L1 MAC powerdown override to P2" "Disabled,Enabled" bitfld.long 0x08 30. " TEST_POWERDOWN ,Powers down all circuitry in the PHY for IDDQ testing" "Not requested,Requested" bitfld.long 0x08 29. " APP_CLK_REQ_N ,Indicates that application logic is ready to have reference clock removed" "0,1" textline " " bitfld.long 0x08 28. " APP_READY_ENTR_L23 ,Indication from the application that it is ready to enter the L23 state" "Not ready,Ready" bitfld.long 0x08 27. " AUX_CLK_SWITCH_CORE_CLK_GATE_EN ,Enabled Auxillary Clock core switch" "0,1" bitfld.long 0x08 26. " APP_REQ_EXIT_L1 ,Request from the application to exit ASPM state L1" "Not set,Set" textline " " bitfld.long 0x08 25. " APP_REQ_ENTR_L1 ,Request from the application to enter ASPM state L1" "Not set,Set" bitfld.long 0x08 24. " SYS_INT ,PCIe system interrupt request" "Not asserted,Asserted" bitfld.long 0x08 21.--23. " PCIe_CTL_7 ,PCIe control of diagnostic bus select" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 17.--20. " DIAG_STATUS_BUS_SELECT ,used for debug to select what part of diag_status_bus will be reflected on the 32 bits of the iomux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16. " APPS_PM_XMT_TURNOFF ,Request from the application to generate a PM_Turn_Off Message" "0,1" bitfld.long 0x08 12.--15. " DEVICE_TYPE ,Specific type of this PCI Express Function" "EP,,,,RC,?..." textline " " bitfld.long 0x08 11. " APP_INIT_RST ,Request from the application to send a Hot Reset to the downstream device" "0,1" bitfld.long 0x08 10. " APP_LTSSM_ENABLE ,Application ready" "Not ready,Ready" bitfld.long 0x08 9. " APPS_PM_XMT_PME ,Used by application logic to wake up the PMC state machine from a D1, D2 or D3 power state" "0,1" textline " " bitfld.long 0x08 4.--8. " LOS_LEVEL ,Sets the sensitivity level for the Loss-of-Signal detector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--2. " PCIE_RX0_EQ ,Control pcie phy's rx0_eq bits" "0,1,2,3,4,5,6,7" line.long 0x0C "GPR13,General Purpose Register 13" bitfld.long 0x0C 15. " GPR_PCIE_CLK_RST_FIX_PERST_DISABLE ,GPR_PCIE_CLK_RST_FIX_PERST_DISABLE" "0,1" bitfld.long 0x0C 14. " GPR_PCIE_CLK_RST_FIX_LNKRST_DISABLE ,GPR_PCIE_CLK_RST_FIX_LNKRST_DISABLE" "0,1" bitfld.long 0x0C 13. " LCDIF2_RD_CACHE_SEL ,This bit selects the cacheable attribute of LCDIF AXI read transcations" "LCDIF core,LCDIF_RD_CACHE_VAL" textline " " bitfld.long 0x0C 12. " LCDIF1_RD_CACHE_SEL ,This bit selects the cacheable attribute of LCDIF AXI read transcations" "LCDIF core,LCDIF_RD_CACHE_VAL" bitfld.long 0x0C 11. " PCIE_WR_CACHE_SEL ,Cacheable attribute of PCIE AXI write transcations" "PCIE core,PCIE_WR_CACHE_VAL" bitfld.long 0x0C 10. " PCIE_RD_CACHE_SEL ,Cacheable attribute of PCIE AXI read transcations" "PCIE core,PCIE_RD_CACHE_VAL" textline " " bitfld.long 0x0C 9. " PXP_WR_CACHE_SEL ,This bit selects the cacheable attribute of PXP AXI write transcations" "PXP core,PXP_WR_CACHE_VAL" bitfld.long 0x0C 8. " PXP_RD_CACHE_SEL ,This bit selects the cacheable attribute of PXP AXI read transcations" "PXP core,PXP_RD_CACHE_VAL" bitfld.long 0x0C 7. " LCDIF2_RD_CACHE_VAL ,LCDIF block cacheable attribute value of AXI read transactions" "Off,On" textline " " bitfld.long 0x0C 6. " LCDIF1_RD_CACHE_VAL ,LCDIF block cacheable attribute value of AXI read transactions" "Off,On" bitfld.long 0x0C 5. " PCIE_WR_CACHE_VAL ,PCIE block cacheable attribute value of AXI write transactions" "Off,On" bitfld.long 0x0C 4. " PCIE_RD_CACHE_VAL ,PCIE block cacheable attribute value of AXI read transactions" "Off,On" textline " " bitfld.long 0x0C 3. " PXP_WR_CACHE_VAL ,PXP block cacheable attribute value of AXI write transactions" "Off,On" bitfld.long 0x0C 2. " PXP_RD_CACHE_VAL ,PXP block cacheable attribute value of AXI read transactions" "Off,On" bitfld.long 0x0C 1. " USDHC_WR_CACHE_VAL ,USDHC block cacheable attribute value of AXI write transactions" "Off,On" textline " " bitfld.long 0x0C 0. " USDHC_RD_CACHE_VAL ,USDHC block cacheable attribute value of AXI read transactions" "Off,On" width 0xb tree.end tree "IOMUXC Registers" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020E0000 else endif width 12. tree "GPIO_1" group.long 0x014++0x473 line.long 0x00 "GPIO1_IO00,GPIO1_IO00 register" bitfld.long 0x00 4. " SION ,Software Input On Field" "Not forced,Forced" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX Mode Select Field" "I2C1_SCL,SD1_VSELECT,SPDIF_LOCK,,WDOG1_ANY,GPIO1_IO00,SNVS_VIO_5," line.long 0x04 "GPIO1_IO01,GPIO1_IO01 register" bitfld.long 0x04 4. " SION ,Force input path of pad GPIO1_IO01" "Not forced,Forced" bitfld.long 0x04 0.--2. " MUX_MODE ,GPIO1_IO01 MUX Mode" "I2C1_SDA,SD1_RESET_B,SPDIF_SR_CLK,,WDOG3_B,GPIO1_IO01,SNVS_VIO_5_CTL," line.long 0x08 "GPIO1_IO02,GPIO1_IO02 register" bitfld.long 0x08 4. " SION ,Force input path of pad GPIO1_IO02" "Not forced,Forced" bitfld.long 0x08 0.--2. " MUX_MODE ,GPIO1_IO02 MUX Mode" "I2C2_SCL,SD1_CD_B,CSI2_MCLK,,WDOG1_B,GPIO1_IO02,CCM_REF_EN_B," line.long 0x0C "GPIO1_IO03,GPIO1_IO03 register" bitfld.long 0x0C 4. " SION ,Force input path of pad GPIO1_IO03" "Not forced,Forced" bitfld.long 0x0C 0.--2. " MUX_MODE ,GPIO1_IO03 MUX Mode" "I2C2_SDA,SD1_WP,ENET1_REF_CLK_25M,,WDOG2_B,GPIO1_IO03,," line.long 0x10 "GPIO1_IO04,GPIO1_IO04 register" bitfld.long 0x10 4. " SION ,Force input path of pad GPIO1_IO04" "Not forced,Forced" bitfld.long 0x10 0.--2. " MUX_MODE ,GPIO1_IO04 MUX Mode" "UART1_TX_DATA,SD2_RESET_B,ENET1_MDC,,ENET2_REF_CLK2,GPIO1_IO04,," line.long 0x14 "GPIO1_IO05,GPIO1_IO05 register" bitfld.long 0x14 4. " SION ,Force input path of pad GPIO1_IO05" "Not forced,Forced" bitfld.long 0x14 0.--2. " MUX_MODE ,GPIO1_IO05 MUX Mode" "UART1_RX_DATA,SD2_VSELECT,ENET1_MDIO,ASRC_EXT_CLK,ENET1_REF_CLK1,GPIO1_IO05,," line.long 0x18 "GPIO1_IO06,GPIO1_IO06 register" bitfld.long 0x18 4. " SION ,Force input path of pad GPIO1_IO06" "Not forced,Forced" bitfld.long 0x18 0.--2. " MUX_MODE ,GPIO1_IO06 MUX Mode" "UART2_TX_DATA,SD2_CD_B,ENET2_MDC,CSI1_MCLK,UART1_RTS_B,GPIO1_IO06,," line.long 0x1C "GPIO1_IO07,GPIO1_IO07 register" bitfld.long 0x1C 4. " SION ,Force input path of pad GPIO1_IO07" "Not forced,Forced" bitfld.long 0x1C 0.--3. " MUX_MODE ,GPIO1_IO07 MUX Mode" "UART2_RX_DATA,SD2_WP,ENET2_MDIO,AUDIO_CLK_OUT,UART1_CTS_B,GPIO1_IO07,,DCIC2_OUT,?..." line.long 0x20 "GPIO1_IO08,GPIO1_IO08 register" bitfld.long 0x20 4. " SION ,Force input path of pad GPIO1_IO08" "Not forced,Forced" bitfld.long 0x20 0.--3. " MUX_MODE ,GPIO1_IO08 MUX Mode" "USB_OTG1_OC,WDOG1_B,SDMA_EXT_EVENT0,CCM_PMIC_READY,UART2_RTS_B,GPIO1_IO08,,DCIC1_OUT,?..." line.long 0x24 "GPIO1_IO09,GPIO1_IO09 register" bitfld.long 0x24 4. " SION ,Force input path of pad GPIO1_IO09" "Not forced,Forced" bitfld.long 0x24 0.--3. " MUX_MODE ,GPIO1_IO09 MUX Mode" "USB_OTG1_PWR,WDOG2_B,SDMA_EXT_EVENT1,,UART2_CTS_B,GPIO1_IO09,?..." line.long 0x28 "GPIO1_IO10,GPIO1_IO10 register" bitfld.long 0x28 4. " SION ,Force input path of pad GPIO1_IO10" "Not forced,Forced" bitfld.long 0x28 0.--3. " MUX_MODE ,GPIO1_IO10 MUX Mode" "USB_OTG1_ID,SPDIF_EXT_CLK,PWM1_OUT,,CSI1_FIELD,GPIO1_IO10,?..." line.long 0x2C "GPIO1_IO11,GPIO1_IO11 register" bitfld.long 0x2C 4. " SION ,Force input path of pad GPIO1_IO11" "Not forced,Forced" bitfld.long 0x2C 0.--3. " MUX_MODE ,GPIO1_IO11 MUX Mode" "USB_OTG2_OC,SPDIF_IN,PWM2_OUT,CCM_CLKO1,MLB_DATA,GPIO1_IO11,?..." line.long 0x30 "GPIO1_IO12,GPIO1_IO12 register" bitfld.long 0x30 4. " SION ,Force input path of pad GPIO1_IO12" "Not forced,Forced" bitfld.long 0x30 0.--3. " MUX_MODE ,GPIO1_IO12 MUX Mode" "USB_OTG2_PWR,SPDIF_OUT,PWM3_OUT,CCM_CLKO2,MLB_CLK,GPIO1_IO12,?..." line.long 0x34 "GPIO1_IO13,GPIO1_IO13 register" bitfld.long 0x34 4. " SION ,Force input path of pad GPIO1_IO13" "Not forced,Forced" bitfld.long 0x34 0.--3. " MUX_MODE ,GPIO1_IO13 MUX Mode" "WDOG1_ANY,USB_OTG2_ID,PWM4_OUT,,MLB_SIG,GPIO1_IO13,?..." tree.end width 12. tree "CSI" group.long 0x4C++0x2F line.long 0x00 "CSI_DATA00,CSI_DATA00 register" bitfld.long 0x00 4. " SION ,Force input path of pad CSI_DATA00" "Not forced,Forced" bitfld.long 0x00 0.--3. " MUX_MODE ,CSI_DATA00 MUX Mode" "CSI1_DATA02,ESAI_TX_CLK,AUD6_TXC,I2C1_SCL,UART6_RI_B,GPIO1_IO14,EIM_DATA23,SAI1_TX_BCLK,VADC_DATA04,?..." line.long 0x04 "CSI_DATA01,CSI_DATA01 register" bitfld.long 0x04 4. " SION ,Force input path of pad CSI_DATA01" "Not forced,Forced" bitfld.long 0x04 0.--3. " MUX_MODE ,CSI_DATA01 MUX Mode" "CSI1_DATA03,ESAI_TX_FS,AUD6_TXFS,I2C1_SDA,UART6_DSR_B,GPIO1_IO15,EIM_DATA22,SAI1_TX_SYNC,VADC_DATA05,?..." line.long 0x08 "CSI_DATA02,CSI_DATA02 register" bitfld.long 0x08 4. " SION ,Force input path of pad CSI_DATA02" "Not forced,Forced" bitfld.long 0x08 0.--3. " MUX_MODE ,CSI_DATA02 MUX Mode" "CSI1_DATA04,ESAI_RX_CLK,AUD6_RXC,KPP_COL5,UART6_DTR_B,GPIO1_IO16,EIM_DATA21,SAI1_RX_BCLK,VADC_DATA06,?..." line.long 0x0C "CSI_DATA03,CSI_DATA03 register" bitfld.long 0x0C 4. " SION ,Force input path of pad CSI_DATA03" "Not forced,Forced" bitfld.long 0x0C 0.--3. " MUX_MODE ,CSI_DATA03 MUX Mode" "CSI1_DATA05,ESAI_RX_FS,AUD6_RXFS,KPP_ROW5,UART6_DCD_B,GPIO1_IO17,EIM_DATA20,SAI1_RX_SYNC,VADC_DATA07,?..." line.long 0x10 "CSI_DATA04,CSI_DATA04 register" bitfld.long 0x10 4. " SION ,Force input path of pad CSI_DATA04" "Not forced,Forced" bitfld.long 0x10 0.--3. " MUX_MODE ,CSI_DATA04 MUX Mode" "CSI1_DATA06,ESAI_TX1,SPDIF_OUT,KPP_COL6,UART6_RX_DATA,GPIO1_IO18,EIM_DATA19,PWM5_OUT,VADC_DATA08,?..." line.long 0x14 "CSI_DATA05,CSI_DATA05 register" bitfld.long 0x14 4. " SION ,Force input path of pad CSI_DATA05" "Not forced,Forced" bitfld.long 0x14 0.--3. " MUX_MODE ,CSI_DATA05 MUX Mode" "CSI1_DATA07,ESAI_TX4_RX1,SPDIF_IN,KPP_ROW6,UART6_TX_DATA,GPIO1_IO19,EIM_DATA18,PWM6_OUT,VADC_DATA09,?..." line.long 0x18 "CSI_DATA06,CSI_DATA06 register" bitfld.long 0x18 4. " SION ,Force input path of pad CSI_DATA06" "Not forced,Forced" bitfld.long 0x18 0.--3. " MUX_MODE ,CSI_DATA06 MUX Mode" "CSI1_DATA08,ESAI_TX2_RX3,I2C4_SCL,KPP_COL7,UART6_RTS_B,GPIO1_IO20,EIM_DATA17,DCIC2_OUT,VADC_DATA10,?..." line.long 0x1C "CSI_DATA07,CSI_DATA07 register" bitfld.long 0x1C 4. " SION ,Force input path of pad CSI_DATA07" "Not forced,Forced" bitfld.long 0x1C 0.--3. " MUX_MODE ,CSI_DATA07 MUX Mode" "CSI1_DATA09,ESAI_TX3_RX2,I2C4_SDA,KPP_ROW7,UART6_CTS_B,GPIO1_IO21,EIM_DATA16,DCIC1_OUT,VADC_DATA11,?..." line.long 0x20 "CSI_HSYNC,CSI_HSYNC register" bitfld.long 0x20 4. " SION ,Force input path of pad CSI_HSYNC" "Not forced,Forced" bitfld.long 0x20 0.--3. " MUX_MODE ,CSI_HSYNC MUX Mode" "CSI1_HSYNC,ESAI_TX0,AUD6_TXD,UART4_RTS_B,MQS_LEFT,GPIO1_IO22,EIM_DATA25,SAI1_TX_DATA0,VADC_DATA02,?..." line.long 0x24 "CSI_MCLK,CSI_MCLK register" bitfld.long 0x24 4. " SION ,Force input path of pad CSI_MCLK" "Not forced,Forced" bitfld.long 0x24 0.--3. " MUX_MODE ,CSI_MCLK MUX Mode" "CSI1_MCLK,ESAI_TX_HF_CLK,,UART4_RX_DATA,XTALOSC_REF_CLK_32K,GPIO1_IO23,EIM_DATA26,CSI1_FIELD,VADC_DATA01,?..." line.long 0x28 "CSI_PIXCLK,CSI_PIXCLK register" bitfld.long 0x28 4. " SION ,Force input path of pad CSI_PIXCLK" "Not forced,Forced" bitfld.long 0x28 0.--3. " MUX_MODE ,CSI_PIXCLK MUX Mode" "CSI1_PIXCLK,ESAI_RX_HF_CLK,AUDIO_CLK_OUT,UART4_TX_DATA,XTALOSC_REF_CLK_24M,GPIO1_IO24,EIM_DATA27,ESAI_TX_HF_CLK,VADC_CLK,?..." line.long 0x2C "CSI_VSYNC,CSI_VSYNC register" bitfld.long 0x2C 4. " SION ,Force input path of pad CSI_VSYNC" "Not forced,Forced" bitfld.long 0x2C 0.--3. " MUX_MODE ,CSI_VSYNC MUX Mode" "CSI1_VSYNC,ESAI_TX5_RX0,AUD6_RXD,UART4_CTS_B,MQS_RIGHT,GPIO1_IO25,EIM_DATA24,SAI1_RX_DATA0,VADC_DATA03,?..." tree.end width 14. tree "ENETx" group.long 0x7C++0x27 line.long 0x00 "ENET1_COL,ENET1_COL register" bitfld.long 0x00 4. " SION ,Force input path of pad ENET1_COL" "Not forced,Forced" bitfld.long 0x00 0.--3. " MUX_MODE ,ENET1_COL MUX Mode" "ENET1_COL,ENET2_MDC,AUD4_TXC,UART1_RI_B,SPDIF_EXT_CLK,GPIO2_IO00,CSI2_DATA23,LCD2_DATA16,?..." line.long 0x04 "ENET1_CRS,ENET1_CRS register" bitfld.long 0x04 4. " SION ,Force input path of pad ENET1_CRS" "Not forced,Forced" bitfld.long 0x04 0.--3. " MUX_MODE ,ENET1_CRS MUX Mode" "ENET1_CRS,ENET2_MDIO,AUD4_TXD,UART1_DCD_B,SPDIF_LOCK,GPIO2_IO01,CSI2_DATA22,LCD2_DATA17,?..." line.long 0x08 "ENET1_MDC,ENET1_MDC register" bitfld.long 0x08 4. " SION ,Force input path of pad ENET1_MDC" "Not forced,Forced" bitfld.long 0x08 0.--2. " MUX_MODE ,ENET1_MDC MUX Mode" "ENET1_MDC,ENET2_MDC,AUD3_RXFS,XTALOSC_REF_CLK_24M,EPIT2_OUT,GPIO2_IO02,USB_OTG1_PWR,PWM7_OUT" line.long 0x0C "ENET1_MDIO,ENET1_MDIO register" bitfld.long 0x0C 4. " SION ,Force input path of pad ENET1_MDIO" "Not forced,Forced" bitfld.long 0x0C 0.--2. " MUX_MODE ,ENET1_MDIO MUX Mode" "ENET1_MDIO,ENET2_MDIO,AUDIO_CLK_OUT,,EPIT1_OUT,GPIO2_IO03,USB_OTG1_OC,PWM8_OUT" line.long 0x10 "ENET1_RX_CLK,ENET1_RX_CLK register" bitfld.long 0x10 4. " SION ,Force input path of pad ENET1_RX_CLK" "Not forced,Forced" bitfld.long 0x10 0.--3. " MUX_MODE ,ENET1_RX_CLK MUX Mode" "ENET1_RX_CLK,ENET1_REF_CLK_25M,AUD4_TXFS,UART1_DSR_B,SPDIF_OUT,GPIO2_IO04,CSI2_DATA21,LCD2_DATA18,?..." line.long 0x14 "ENET1_TX_CLK,ENET1_TX_CLK register" bitfld.long 0x14 4. " SION ,Force input path of pad ENET1_TX_CLK" "Not forced,Forced" bitfld.long 0x14 0.--3. " MUX_MODE ,ENET1_TX_CLK MUX Mode" "ENET1_TX_CLK,ENET1_REF_CLK1,AUD4_RXD,UART1_DTR_B,SPDIF_SR_CLK,GPIO2_IO05,CSI2_DATA20,LCD2_DATA19,?..." line.long 0x18 "ENET2_COL,ENET2_COL register" bitfld.long 0x18 4. " SION ,Force input path of pad ENET2_COL" "Not forced,Forced" bitfld.long 0x18 0.--3. " MUX_MODE ,ENET2_COL MUX Mode" "ENET2_COL,ENET1_MDC,AUD4_RXC,UART1_RX_DATA,SPDIF_IN,GPIO2_IO06,USB_OTG1_ID,LCD2_DATA20,?..." line.long 0x1C "ENET2_CRS,ENET2_CRS register" bitfld.long 0x1C 4. " SION ,Force input path of pad ENET2_CRS" "Not forced,Forced" bitfld.long 0x1C 0.--3. " MUX_MODE ,ENET2_CRS MUX Mode" "ENET2_CRS,ENET1_MDIO,AUD4_RXFS,UART1_TX_DATA,MLB_SIG,GPIO2_IO07,USB_OTG2_ID,LCD2_DATA21,?..." line.long 0x20 "ENET2_RX_CLK,ENET2_RX_CLK register" bitfld.long 0x20 4. " SION ,Force input path of pad ENET2_RX_CLK" "Not forced,Forced" bitfld.long 0x20 0.--3. " MUX_MODE ,ENET2_RX_CLK MUX Mode" "ENET2_RX_CLK,ENET2_REF_CLK_25M,I2C3_SCL,UART1_RTS_B,MLB_DATA,GPIO2_IO08,USB_OTG2_OC,LCD2_DATA22,?..." line.long 0x24 "ENET2_TX_CLK,ENET2_TX_CLK register" bitfld.long 0x24 4. " SION ,Force input path of pad ENET2_TX_CLK" "Not forced,Forced" bitfld.long 0x24 0.--3. " MUX_MODE ,ENET2_TX_CLK MUX Mode" "ENET2_TX_CLK,ENET2_REF_CLK2,I2C3_SDA,UART1_CTS_B,MLB_CLK,GPIO2_IO09,USB_OTG2_PWR,LCD2_DATA23,?..." tree.end width 10. tree "KEY" group.long 0xA4++0x27 line.long 0x00 "KEY_COL0,KEY_COL0 register" bitfld.long 0x00 4. " SION ,Force input path of pad KEY_COL0" "Not forced,Forced" bitfld.long 0x00 0.--3. " MUX_MODE ,KEY_COL0 MUX Mode" "KPP_COL0,SD3_CD_B,UART6_RTS_B,ECSPI1_SCLK,AUD5_TXC,GPIO2_IO10,SDMA_EXT_EVENT1,SAI2_TX_BCLK,VADC_DATA00,?..." line.long 0x04 "KEY_COL1,KEY_COL1 register" bitfld.long 0x04 4. " SION ,Force input path of pad KEY_COL1" "Not forced,Forced" bitfld.long 0x04 0.--2. " MUX_MODE ,KEY_COL1 MUX Mode" "KPP_COL1,SD3_RESET_B,UART6_TX_DATA,ECSPI1_MISO,AUD5_TXFS,GPIO2_IO11,SD3_RESET,SAI2_TX_SYNC" line.long 0x08 "KEY_COL2,KEY_COL2 register" bitfld.long 0x08 4. " SION ,Force input path of pad KEY_COL2" "Not forced,Forced" bitfld.long 0x08 0.--2. " MUX_MODE ,KEY_COL2 MUX Mode" "KPP_COL2,SD4_CD_B,UART5_RTS_B,CAN1_TX,,GPIO2_IO12,EIM_DATA30,ECSPI1_RDY" line.long 0x0C "KEY_COL3,KEY_COL3 register" bitfld.long 0x0C 4. " SION ,Force input path of pad KEY_COL3" "Not forced,Forced" bitfld.long 0x0C 0.--2. " MUX_MODE ,KEY_COL3 MUX Mode" "KPP_COL3,SD4_LCTL,UART5_TX_DATA,CAN2_TX,,GPIO2_IO13,EIM_DATA28,ECSPI1_SS2" line.long 0x10 "KEY_COL4,KEY_COL4 register" bitfld.long 0x10 4. " SION ,Force input path of pad KEY_COL4" "Not forced,Forced" bitfld.long 0x10 0.--2. " MUX_MODE ,KEY_COL4 MUX Mode" "KPP_COL4,ENET2_MDC,I2C3_SCL,SD2_LCTL,AUD5_RXC,GPIO2_IO14,EIM_CRE,SAI2_RX_BCLK" line.long 0x14 "KEY_ROW0,KEY_ROW0 register" bitfld.long 0x14 4. " SION ,Force input path of pad KEY_ROW0" "Not forced,Forced" bitfld.long 0x14 0.--3. " MUX_MODE ,KEY_ROW0 MUX Mode" "KPP_ROW0,SD3_WP,UART6_CTS_B,ECSPI1_MOSI,AUD5_TXD,GPIO2_IO15,SDMA_EXT_EVENT0,SAI2_TX_DATA0,?..." line.long 0x18 "KEY_ROW1,KEY_ROW1 register" bitfld.long 0x18 4. " SION ,Force input path of pad KEY_ROW1" "Not forced,Forced" bitfld.long 0x18 0.--3. " MUX_MODE ,KEY_ROW1 MUX Mode" "KPP_ROW1,SD4_VSELECT,UART6_RX_DATA,ECSPI1_SS0,AUD5_RXD,GPIO2_IO16,EIM_DATA31,SAI2_RX_DATA0,ARM_M4_NMI,?..." line.long 0x1C "KEY_ROW2,KEY_ROW2 register" bitfld.long 0x1C 4. " SION ,Force input path of pad KEY_ROW2" "Not forced,Forced" bitfld.long 0x1C 0.--2. " MUX_MODE ,KEY_ROW2 MUX Mode" "KPP_ROW2,SD4_WP,UART5_CTS_B,CAN1_RX,,GPIO2_IO17,EIM_DATA29,ECSPI1_SS3" line.long 0x20 "KEY_ROW3,KEY_ROW3 register" bitfld.long 0x20 4. " SION ,Force input path of pad KEY_ROW3" "Not forced,Forced" bitfld.long 0x20 0.--2. " MUX_MODE ,KEY_ROW3 MUX Mode" "KPP_ROW3,SD3_LCTL,UART5_RX_DATA,CAN2_RX,,GPIO2_IO18,EIM_DTACK_B,ECSPI1_SS1" line.long 0x24 "KEY_ROW4,KEY_ROW4 register" bitfld.long 0x24 4. " SION ,Force input path of pad KEY_ROW4" "Not forced,Forced" bitfld.long 0x24 0.--2. " MUX_MODE ,KEY_ROW4 MUX Mode" "KPP_ROW4,ENET2_MDIO,I2C3_SDA,SD1_LCTL,AUD5_RXFS,GPIO2_IO19,EIM_ACLK_FREERUN,SAI2_RX_SYNC" tree.end width 13. tree "LCD1" group.long 0xCC++0x73 line.long 0x00 "LCD1_CLK,LCD1_CLK register" bitfld.long 0x00 4. " SION ,Force input path of pad LCD1_CLK" "Not forced,Forced" bitfld.long 0x00 0.--3. " MUX_MODE ,LCD1_CLK MUX Mode" "LCD1_CLK,LCD1_WR_RWN,AUD3_RXC,ENET1_1588_EVENT2_IN,CSI1_DATA16,GPIO3_IO00,SD1_WP,?..." line.long 0x04 "LCD1_DATA00,LCD1_DATA00 register" bitfld.long 0x04 4. " SION ,Force input path of pad LCD1_DATA00" "Not forced,Forced" bitfld.long 0x04 0.--3. " MUX_MODE ,LCD1_DATA00 MUX Mode" "LCD1_DATA00,EIM_CS1_B,ARM_M4_TRACE0,ARM_A9_TRACE00,CSI1_DATA20,GPIO3_IO01,SRC_BOOT_CFG00,?..." line.long 0x08 "LCD1_DATA01,LCD1_DATA01 register" bitfld.long 0x08 4. " SION ,Force input path of pad LCD1_DATA01" "Not forced,Forced" bitfld.long 0x08 0.--3. " MUX_MODE ,LCD1_DATA01 MUX Mode" "LCD1_DATA01,EIM_CS2_B,ARM_M4_TRACE1,ARM_A9_TRACE01,CSI1_DATA21,GPIO3_IO02,SRC_BOOT_CFG01,?..." line.long 0x0C "LCD1_DATA02,LCD1_DATA02 register" bitfld.long 0x0C 4. " SION ,Force input path of pad LCD1_DATA02" "Not forced,Forced" bitfld.long 0x0C 0.--3. " MUX_MODE ,LCD1_DATA02 MUX Mode" "LCD1_DATA02,EIM_CS3_B,ARM_M4_TRACE2,ARM_A9_TRACE02,CSI1_DATA22,GPIO3_IO03,SRC_BOOT_CFG02,?..." line.long 0x10 "LCD1_DATA03,LCD1_DATA03 register" bitfld.long 0x10 4. " SION ,Force input path of pad LCD1_DATA03" "Not forced,Forced" bitfld.long 0x10 0.--3. " MUX_MODE ,LCD1_DATA03 MUX Mode" "LCD1_DATA03,EIM_ADDR24,ARM_M4_TRACE3,ARM_A9_TRACE03,CSI1_DATA23,GPIO3_IO04,SRC_BOOT_CFG03,?..." line.long 0x14 "LCD1_DATA04,LCD1_DATA04 register" bitfld.long 0x14 4. " SION ,Force input path of pad LCD1_DATA04" "Not forced,Forced" bitfld.long 0x14 0.--3. " MUX_MODE ,LCD1_DATA04 MUX Mode" "LCD1_DATA04,EIM_ADDR25,,ARM_A9_TRACE04,CSI1_VSYNC,GPIO3_IO05,SRC_BOOT_CFG04,?..." line.long 0x18 "LCD1_DATA05,LCD1_DATA05 register" bitfld.long 0x18 4. " SION ,Force input path of pad LCD1_DATA05" "Not forced,Forced" bitfld.long 0x18 0.--3. " MUX_MODE ,LCD1_DATA05 MUX Mode" "LCD1_DATA05,EIM_ADDR26,,ARM_A9_TRACE05,CSI1_HSYNC,GPIO3_IO06,SRC_BOOT_CFG05,?..." line.long 0x1C "LCD1_DATA06,LCD1_DATA06 register" bitfld.long 0x1C 4. " SION ,Force input path of pad LCD1_DATA06" "Not forced,Forced" bitfld.long 0x1C 0.--3. " MUX_MODE ,LCD1_DATA06 MUX Mode" "LCD1_DATA06,EIM_EB2_B,,ARM_A9_TRACE06,CSI1_PIXCLK,GPIO3_IO07,SRC_BOOT_CFG06,?..." line.long 0x20 "LCD1_DATA07,LCD1_DATA07 register" bitfld.long 0x20 4. " SION ,Force input path of pad LCD1_DATA07" "Not forced,Forced" bitfld.long 0x20 0.--3. " MUX_MODE ,LCD1_DATA07 MUX Mode" "LCD1_DATA07,EIM_EB3_B,,ARM_A9_TRACE07,CSI1_MCLK,GPIO3_IO08,SRC_BOOT_CFG07,?..." line.long 0x24 "LCD1_DATA08,LCD1_DATA08 register" bitfld.long 0x24 4. " SION ,Force input path of pad LCD1_DATA08" "Not forced,Forced" bitfld.long 0x24 0.--3. " MUX_MODE ,LCD1_DATA08 MUX Mode" "LCD1_DATA08,EIM_AD08,,ARM_A9_TRACE08,CSI1_DATA09,GPIO3_IO09,SRC_BOOT_CFG08,?..." line.long 0x28 "LCD1_DATA09,LCD1_DATA09 register" bitfld.long 0x28 4. " SION ,Force input path of pad LCD1_DATA09" "Not forced,Forced" bitfld.long 0x28 0.--3. " MUX_MODE ,LCD1_DATA09 MUX Mode" "LCD1_DATA09,EIM_AD09,,ARM_A9_TRACE09,CSI1_DATA08,GPIO3_IO10,SRC_BOOT_CFG09,?..." line.long 0x2C "LCD1_DATA10,LCD1_DATA10 register" bitfld.long 0x2C 4. " SION ,Force input path of pad LCD1_DATA10" "Not forced,Forced" bitfld.long 0x2C 0.--3. " MUX_MODE ,LCD1_DATA10 MUX Mode" "LCD1_DATA10,EIM_AD10,,ARM_A9_TRACE10,CSI1_DATA07,GPIO3_IO11,SRC_BOOT_CFG10,?..." line.long 0x30 "LCD1_DATA11,LCD1_DATA11 register" bitfld.long 0x30 4. " SION ,Force input path of pad LCD1_DATA11" "Not forced,Forced" bitfld.long 0x30 0.--3. " MUX_MODE ,LCD1_DATA11 MUX Mode" "LCD1_DATA11,EIM_AD11,,ARM_A9_TRACE11,CSI1_DATA06,GPIO3_IO12,SRC_BOOT_CFG11,?..." line.long 0x34 "LCD1_DATA12,LCD1_DATA12" bitfld.long 0x34 4. " SION ,Force input path of pad LCD1_DATA12" "Not forced,Forced" bitfld.long 0x34 0.--3. " MUX_MODE ,LCD1_DATA12 MUX Mode" "LCD1_DATA12,EIM_AD12,,ARM_A9_TRACE12,CSI1_DATA05,GPIO3_IO13,SRC_BOOT_CFG12,?..." line.long 0x38 "LCD1_DATA13,LCD1_DATA13" bitfld.long 0x38 4. " SION ,Force input path of pad LCD1_DATA13" "Not forced,Forced" bitfld.long 0x38 0.--3. " MUX_MODE ,LCD1_DATA13 MUX Mode" "LCD1_DATA13,EIM_AD13,,ARM_A9_TRACE13,CSI1_DATA04,GPIO3_IO14,SRC_BOOT_CFG13,?..." line.long 0x3C "LCD1_DATA14,LCD1_DATA14 register" bitfld.long 0x3C 4. " SION ,Force input path of pad LCD1_DATA14" "Not forced,Forced" bitfld.long 0x3C 0.--3. " MUX_MODE ,LCD1_DATA14 MUX Mode" "LCD1_DATA14,EIM_AD14,,ARM_A9_TRACE14,CSI1_DATA03,GPIO3_IO15,SRC_BOOT_CFG14,?..." line.long 0x40 "LCD1_DATA15,LCD1_DATA15 register" bitfld.long 0x40 4. " SION ,Force input path of pad LCD1_DATA15" "Not forced,Forced" bitfld.long 0x40 0.--3. " MUX_MODE ,LCD1_DATA15 MUX Mode" "LCD1_DATA15,EIM_AD15,,ARM_A9_TRACE15,CSI1_DATA02,GPIO3_IO16,SRC_BOOT_CFG15,?..." line.long 0x44 "LCD1_DATA16,LCD1_DATA16 register" bitfld.long 0x44 4. " SION ,Force input path of pad LCD1_DATA16" "Not forced,Forced" bitfld.long 0x44 0.--3. " MUX_MODE ,LCD1_DATA16 MUX Mode" "LCD1_DATA16,EIM_ADDR16,ARM_M4_TRACE_CLK,ARM_A9_TRACE_CLK,CSI1_DATA01,GPIO3_IO17,SRC_BOOT_CFG24,?..." line.long 0x48 "LCD1_DATA17,LCD1_DATA17 register" bitfld.long 0x48 4. " SION ,Force input path of pad LCD1_DATA17" "Not forced,Forced" bitfld.long 0x48 0.--3. " MUX_MODE ,LCD1_DATA17 MUX Mode" "LCD1_DATA17,EIM_ADDR17,,ARM_A9_TRACE_CTL,CSI1_DATA00,GPIO3_IO18,SRC_BOOT_CFG25,?..." line.long 0x4C "LCD1_DATA18,LCD1_DATA18 register" bitfld.long 0x4C 4. " SION ,Force input path of pad LCD1_DATA18" "Not forced,Forced" bitfld.long 0x4C 0.--3. " MUX_MODE ,LCD1_DATA18 MUX Mode" "LCD1_DATA18,EIM_ADDR18,ARM_M4_EVENTO,ARM_A9_EVENTO,CSI1_DATA15,GPIO3_IO19,SRC_BOOT_CFG26,?..." line.long 0x50 "LCD1_DATA19,LCD1_DATA19 register" bitfld.long 0x50 4. " SION ,Force input path of pad LCD1_DATA19" "Not forced,Forced" bitfld.long 0x50 0.--3. " MUX_MODE ,LCD1_DATA19 MUX Mode" "LCD1_DATA19,EIM_ADDR19,ARM_M4_TRACE_SWO,,CSI1_DATA14,GPIO3_IO20,SRC_BOOT_CFG27,?..." line.long 0x54 "LCD1_DATA20,LCD1_DATA20 register" bitfld.long 0x54 4. " SION ,Force input path of pad LCD1_DATA20" "Not forced,Forced" bitfld.long 0x54 0.--3. " MUX_MODE ,LCD1_DATA20 MUX Mode" "LCD1_DATA20,EIM_ADDR20,PWM8_OUT,ENET1_1588_EVENT2_OUT,CSI1_DATA13,GPIO3_IO21,SRC_BOOT_CFG28,?..." line.long 0x58 "LCD1_DATA21,LCD1_DATA21 register" bitfld.long 0x58 4. " SION ,Force input path of pad LCD1_DATA21" "Not forced,Forced" bitfld.long 0x58 0.--3. " MUX_MODE ,LCD1_DATA21 MUX Mode" "LCD1_DATA21,EIM_ADDR21,PWM7_OUT,ENET1_1588_EVENT3_OUT,CSI1_DATA12,GPIO3_IO22,SRC_BOOT_CFG29,?..." line.long 0x5C "LCD1_DATA22,LCD1_DATA22 register" bitfld.long 0x5C 4. " SION ,Force input path of pad LCD1_DATA22" "Not forced,Forced" bitfld.long 0x5C 0.--3. " MUX_MODE ,LCD1_DATA22 MUX Mode" "LCD1_DATA22,EIM_ADDR22,PWM6_OUT,ENET2_1588_EVENT2_OUT,CSI1_DATA11,GPIO3_IO23,SRC_BOOT_CFG30,?..." line.long 0x60 "LCD1_DATA23,LCD1_DATA23 register" bitfld.long 0x60 4. " SION ,Force input path of pad EIM_D24" "Not forced,Forced" bitfld.long 0x60 0.--3. " MUX_MODE ,EIM_D24 MUX Mode" "LCD1_DATA23,EIM_ADDR23,PWM5_OUT,ENET2_1588_EVENT3_OUT,CSI1_DATA10,GPIO3_IO24,SRC_BOOT_CFG31,?..." line.long 0x64 "LCD1_ENABLE,LCD1_ENABLE register" bitfld.long 0x64 4. " SION ,Force input path of pad LCD1_ENABLE" "Not forced,Forced" bitfld.long 0x64 0.--3. " MUX_MODE ,LCD1_ENABLE MUX Mode" "LCD1_ENABLE,LCD1_RD_E,AUD3_TXC,ENET1_1588_EVENT3_IN,CSI1_DATA17,GPIO3_IO25,SD1_CD_B,?..." line.long 0x68 "LCD1_HSYNC,LCD1_HSYNC register" bitfld.long 0x68 4. " SION ,Force input path of pad LCD1_HSYNC" "Not forced,Forced" bitfld.long 0x68 0.--3. " MUX_MODE ,LCD1_HSYNC MUX Mode" "LCD1_HSYNC,LCD1_RS,AUD3_TXD,ENET2_1588_EVENT2_IN,CSI1_DATA18,GPIO3_IO26,SD2_WP,?..." line.long 0x6C "LCD1_RESET,LCD1_RESET register" bitfld.long 0x6C 4. " SION ,Force input path of pad LCD1_RESET." "Not forced,Forced" bitfld.long 0x6C 0.--3. " MUX_MODE ,LCD1_RESET MUX Mode" "LCD1_RESET,LCD1_CS,AUD3_RXD,ARM_A9_EVENTI,ARM_M4_EVENTI,GPIO3_IO27,CCM_PMIC_READY,?..." line.long 0x70 "LCD1_VSYNC,LCD1_VSYNC register" bitfld.long 0x70 4. " SION ,Force input path of pad LCD1_VSYNC." "Not forced,Forced" bitfld.long 0x70 0.--3. " MUX_MODE ,LCD1_VSYNC MUX Mode" "LCD1_VSYNC,LCD1_BUSY,AUD3_TXFS,ENET2_1588_EVENT3_IN,CSI1_DATA19,GPIO3_IO28,SD2_CD_B,?..." tree.end width 14. tree "NAND" group.long 0x140++0x03F line.long 0x00 "NAND_ALE,NAND_ALE register" bitfld.long 0x00 4. " SION ,Force input path of pad NAND_ALE." "Not forced,Forced" bitfld.long 0x00 0.--3. " MUX_MODE ,NAND_ALE MUX Mode" "NAND_ALE,I2C3_SDA,QSPI2A_SS0_B,ECSPI2_SS0,ESAI_TX3_RX2,GPIO4_IO00,EIM_CS0_B,?..." line.long 0x04 "NAND_CE0_B,NAND_CE0_B register" bitfld.long 0x04 4. " SION ,Force input path of pad NAND_CE0_B" "Not forced,Forced" bitfld.long 0x04 0.--3. " MUX_MODE ,NAND_CE0_B MUX Mode" "NAND_CE0_B,SD2_VSELECT,QSPI2A_DATA2,AUD4_TXC,ESAI_TX_CLK,GPIO4_IO01,EIM_LBA_B,?..." line.long 0x08 "NAND_CE1_B,NAND_CE1_B register" bitfld.long 0x08 4. " SION ,Force input path of pad NAND_CE1_B" "Not forced,Forced" bitfld.long 0x08 0.--3. " MUX_MODE ,NAND_CE1_B MUX Mode" "NAND_CE1_B,SD3_RESET_B,QSPI2A_DATA3,AUD4_TXD,ESAI_TX0,GPIO4_IO02,EIM_OE,?..." line.long 0x0C "NAND_CLE,NAND_CLE register" bitfld.long 0x0C 4. " SION ,Force input path of pad NAND_CLE" "Not forced,Forced" bitfld.long 0x0C 0.--3. " MUX_MODE ,NAND_CLE MUX Mode" "NAND_CLE,I2C3_SCL,QSPI2A_SCLK,ECSPI2_SCLK,ESAI_TX2_RX3,GPIO4_IO03,EIM_BCLK,?..." line.long 0x10 "NAND_DATA00,NAND_DATA00 register" bitfld.long 0x10 4. " SION ,Force input path of pad NAND_DATA00" "Not forced,Forced" bitfld.long 0x10 0.--3. " MUX_MODE ,NAND_DATA00 MUX Mode" "NAND_DATA00,SD1_DATA4,QSPI2B_DATA1,ECSPI5_MISO,ESAI_RX_CLK,GPIO4_IO04,EIM_AD00,?..." line.long 0x14 "NAND_DATA01,NAND_DATA01 register" bitfld.long 0x14 4. " SION ,Force input path of pad NAND_DATA01" "Not forced,Forced" bitfld.long 0x14 0.--3. " MUX_MODE ,NAND_DATA01 MUX Mode" "NAND_DATA01,SD1_DATA5,QSPI2B_DATA0,ECSPI5_MOSI,ESAI_RX_FS,GPIO4_IO05,EIM_AD01,?..." line.long 0x18 "NAND_DATA02,NAND_DATA02 register" bitfld.long 0x18 4. " SION ,Force input path of pad NAND_DATA02" "Not forced,Forced" bitfld.long 0x18 0.--3. " MUX_MODE ,NAND_DATA02 MUX Mode" "NAND_DATA02,SD1_DATA6,QSPI2B_SCLK,ECSPI5_SCLK,ESAI_TX_HF_CLK,GPIO4_IO06,EIM_AD02,?..." line.long 0x1C "NAND_DATA03,NAND_DATA03 register" bitfld.long 0x1C 4. " SION ,Force input path of pad NAND_DATA03" "Not forced,Forced" bitfld.long 0x1C 0.--3. " MUX_MODE ,NAND_DATA03 MUX Mode" "NAND_DATA03,SD1_DATA7,QSPI2B_SS0_B,ECSPI5_SS0,ESAI_RX_HF_CLK,GPIO4_IO07,EIM_AD03,?..." line.long 0x20 "NAND_DATA04,NAND_DATA04 register" bitfld.long 0x20 4. " SION ,Force input path of pad NAND_DATA04" "Not forced,Forced" bitfld.long 0x20 0.--3. " MUX_MODE ,NAND_DATA04 MUX Mode" "NAND_DATA04,SD2_DATA4,QSPI2B_SS1_B,UART3_RTS_B,AUD4_RXFS,GPIO4_IO08,EIM_AD04,?..." line.long 0x24 "NAND_DATA05,NAND_DATA05 register" bitfld.long 0x24 4. " SION ,Force input path of pad NAND_DATA05" "Not forced,Forced" bitfld.long 0x24 0.--3. " MUX_MODE ,NAND_DATA05 MUX Mode" "NAND_DATA05,SD2_DATA5,QSPI2B_DQS,UART3_CTS_B,AUD4_RXC,GPIO4_IO09,EIM_AD05,?..." line.long 0x28 "NAND_DATA06,NAND_DATA06 register" bitfld.long 0x28 4. " SION ,Force input path of pad NAND_DATA06" "Not forced,Forced" bitfld.long 0x28 0.--3. " MUX_MODE ,NAND_DATA06 MUX Mode" "NAND_DATA06,SD2_DATA6,QSPI2A_SS1_B,UART3_RX_DATA,PWM3_OUT,GPIO4_IO10,EIM_AD06,?..." line.long 0x2C "NAND_DATA07,NAND_DATA07 register" bitfld.long 0x2C 4. " SION ,Force input path of pad NAND_DATA06" "Not forced,Forced" bitfld.long 0x2C 0.--3. " MUX_MODE ,NAND_DATA06 MUX Mode" "NAND_DATA07,SD2_DATA7,QSPI2A_DQS,UART3_TX_DATA,PWM4_OUT,GPIO4_IO11,EIM_AD07,?..." line.long 0x30 "NAND_RE_B,NAND_RE_B register" bitfld.long 0x30 4. " SION ,Force input path of pad NAND_RE_B" "Not forced,Forced" bitfld.long 0x30 0.--3. " MUX_MODE ,NAND_RE_B MUX Mode" "NAND_RE_B,SD2_RESET_B,QSPI2B_DATA3,AUD4_TXFS,ESAI_TX_FS,GPIO4_IO12,EIM_RW,?..." line.long 0x34 "NAND_READY_B,NAND_READY_B register" bitfld.long 0x34 4. " SION ,Force input path of pad NAND_READY_B" "Not forced,Forced" bitfld.long 0x34 0.--3. " MUX_MODE ,NAND_READY_B MUX Mode" "NAND_READY_B,SD1_VSELECT,QSPI2A_DATA1,ECSPI2_MISO,ESAI_TX1,GPIO4_IO13,EIM_EB1_B,?..." line.long 0x38 "NAND_WE_B,NAND_WE_B register" bitfld.long 0x38 4. " SION ,Force input path of pad NAND_WE_B" "Not forced,Forced" bitfld.long 0x38 0.--3. " MUX_MODE ,NAND_WE_B MUX Mode" "NAND_WE_B,SD4_VSELECT,QSPI2B_DATA2,AUD4_RXD,ESAI_TX5_RX0,GPIO4_IO14,EIM_WAIT,?..." line.long 0x3C "NAND_WP_B,NAND_WP_B register" bitfld.long 0x3C 4. " SION ,Force input path of pad NAND_WP_B" "Not forced,Forced" bitfld.long 0x3C 0.--3. " MUX_MODE ,NAND_WP_B MUX Mode" "NAND_WP_B,SD1_RESET_B,QSPI2A_DATA0,ECSPI2_MOSI,ESAI_TX4_RX1,GPIO4_IO15,EIM_EB0_B,?..." tree.end width 14. tree "QSPI1" group.long 0x180++0x3F line.long 0x00 "QSPI1A_DATA0,QSPI1A_DATA0 register" bitfld.long 0x00 4. " SION ,Force input path of pad QSPI1A_DATA0" "Not forced,Forced" bitfld.long 0x00 0.--3. " MUX_MODE ,QSPI1A_DATA0 MUX Mode" "QSPI1A_DATA0,USB_OTG2_OC,ECSPI1_MOSI,ESAI_TX4_RX1,CSI1_DATA14,GPIO4_IO16,EIM_DATA06,?..." line.long 0x04 "QSPI1A_DATA1,QSPI1A_DATA1 register" bitfld.long 0x04 4. " SION ,Force input path of pad QSPI1A_DATA1" "Not forced,Forced" bitfld.long 0x04 0.--3. " MUX_MODE ,QSPI1A_DATA1 MUX Mode" "QSPI1A_DATA1,USB_OTG1_ID,ECSPI1_MISO,ESAI_TX1,CSI1_DATA13,GPIO4_IO17,EIM_DATA05,?..." line.long 0x08 "QSPI1A_DATA2,QSPI1A_DATA2 register" bitfld.long 0x08 4. " SION ,Force input path of pad QSPI1A_DATA2" "Not forced,Forced" bitfld.long 0x08 0.--3. " MUX_MODE ,QSPI1A_DATA2 MUX Mode" "QSPI1A_DATA2,USB_OTG1_PWR,ECSPI5_SS1,ESAI_TX_CLK,CSI1_DATA12,GPIO4_IO18,EIM_DATA04,?..." line.long 0x0C "QSPI1A_DATA3,QSPI1A_DATA3 register" bitfld.long 0x0C 4. " SION ,Force input path of pad QSPI1A_DATA3" "Not forced,Forced" bitfld.long 0x0C 0.--3. " MUX_MODE ,QSPI1A_DATA3 MUX Mode" "QSPI1A_DATA3,USB_OTG1_OC,ECSPI5_SS2,ESAI_TX0,CSI1_DATA11,GPIO4_IO19,EIM_DATA03,?..." line.long 0x10 "QSPI1A_DQS,QSPI1A_DQS register" bitfld.long 0x10 4. " SION ,Force input path of pad QSPI1A_DQS" "Not forced,Forced" bitfld.long 0x10 0.--3. " MUX_MODE ,QSPI1A_DQS MUX Mode" "QSPI1A_DQS,CAN2_TX,,ECSPI5_MOSI,CSI1_DATA15,GPIO4_IO20,EIM_DATA07,?..." line.long 0x14 "QSPI1A_SCLK,QSPI1A_SCLK register" bitfld.long 0x14 4. " SION ,Force input path of pad QSPI1A_SCLK" "Not forced,Forced" bitfld.long 0x14 0.--3. " MUX_MODE ,QSPI1A_SCLK MUX Mode" "QSPI1A_SCLK,USB_OTG2_ID,ECSPI1_SCLK,ESAI_TX2_RX3,CSI1_DATA01,GPIO4_IO21,EIM_DATA00,?..." line.long 0x18 "QSPI1A_SS0_B,QSPI1A_SS0_B register" bitfld.long 0x18 4. " SION ,Force input path of pad QSPI1A_SS0_B" "Not forced,Forced" bitfld.long 0x18 0.--3. " MUX_MODE ,QSPI1A_SS0_B MUX Mode" "QSPI1A_SS0_B,USB_OTG2_PWR,ECSPI1_SS0,ESAI_TX3_RX2,CSI1_DATA00,GPIO4_IO22,EIM_DATA01,?..." line.long 0x1C "QSPI1A_SS1_B,QSPI1A_SS1_B register" bitfld.long 0x1C 4. " SION ,Force input path of pad QSPI1A_SS1_B" "Not forced,Forced" bitfld.long 0x1C 0.--3. " MUX_MODE ,QSPI1A_SS1_B MUX Mode" "QSPI1A_SS1_B,CAN1_RX,,ECSPI5_MISO,CSI1_DATA10,GPIO4_IO23,EIM_DATA02,?..." line.long 0x20 "QSPI1B_DATA0,QSPI1B_DATA0 register" bitfld.long 0x20 4. " SION ,Force input path of pad QSPI1B_DATA0" "Not forced,Forced" bitfld.long 0x20 0.--2. " MUX_MODE ,QSPI1B_DATA0 MUX Mode" "QSPI1B_DATA0,UART3_CTS_B,ECSPI3_MOSI,ESAI_RX_FS,CSI1_DATA22,GPIO4_IO24,EIM_DATA14," line.long 0x24 "QSPI1B_DATA1,QSPI1B_DATA1 register" bitfld.long 0x24 4. " SION ,Force input path of pad QSPI1B_DATA1" "Not forced,Forced" bitfld.long 0x24 0.--2. " MUX_MODE ,QSPI1B_DATA1 MUX Mode" "QSPI1B_DATA1,UART3_RTS_B,ECSPI3_MISO,ESAI_RX_CLK,CSI1_DATA21,GPIO4_IO25,EIM_DATA13," line.long 0x28 "QSPI1B_DATA2,QSPI1B_DATA2 register" bitfld.long 0x28 4. " SION ,Force input path of pad QSPI1B_DATA2" "Not forced,Forced" bitfld.long 0x28 0.--2. " MUX_MODE ,QSPI1B_DATA2 MUX Mode" "QSPI1B_DATA2,I2C2_SDA,ECSPI5_RDY,ESAI_TX5_RX0,CSI1_DATA20,GPIO4_IO26,EIM_DATA12," line.long 0x2C "QSPI1B_DATA3,QSPI1B_DATA3 register" bitfld.long 0x2C 4. " SION ,Force input path of pad QSPI1B_DATA3" "Not forced,Forced" bitfld.long 0x2C 0.--2. " MUX_MODE ,QSPI1B_DATA3 MUX Mode" "QSPI1B_DATA3,I2C2_SCL,ECSPI5_SS3,ESAI_TX_FS,CSI1_DATA19,GPIO4_IO27,EIM_DATA11," line.long 0x30 "QSPI1B_DQS,QSPI1B_DQS register" bitfld.long 0x30 4. " SION ,Force input path of pad QSPI1B_DQS" "Not forced,Forced" bitfld.long 0x30 0.--2. " MUX_MODE ,QSPI1B_DQS MUX Mode" "QSPI1B_DQS,CAN1_TX,,ECSPI5_SS0,CSI1_DATA23,GPIO4_IO28,EIM_DATA15," line.long 0x34 "QSPI1B_SCLK,QSPI1B_SCLK register" bitfld.long 0x34 4. " SION ,Force input path of pad QSPI1B_SCLK" "Not forced,Forced" bitfld.long 0x34 0.--2. " MUX_MODE ,QSPI1B_SCLK MUX Mode" "QSPI1B_SCLK,UART3_RX_DATA,ECSPI3_SCLK,ESAI_RX_HF_CLK,CSI1_DATA16,GPIO4_IO29,EIM_DATA08," line.long 0x38 "QSPI1B_SS0_B,QSPI1B_SS0_B register" bitfld.long 0x38 4. " SION ,Force input path of pad QSPI1B_SS0_B" "Not forced,Forced" bitfld.long 0x38 0.--2. " MUX_MODE ,QSPI1B_SS0_B MUX Mode" "QSPI1B_SS0_B,UART3_TX_DATA,ECSPI3_SS0,ESAI_TX_HF_CLK,CSI1_DATA17,GPIO4_IO30,EIM_DATA09," line.long 0x3C "QSPI1B_SS1_B,QSPI1B_SS1_B register" bitfld.long 0x3C 4. " SION ,Force input path of pad QSPI1B_SS1_B" "Not forced,Forced" bitfld.long 0x3C 0.--2. " MUX_MODE ,QSPI1B_SS1_B MUX Mode" "QSPI1B_SS1_B,CAN2_RX,,ECSPI5_SCLK,CSI1_DATA18,GPIO4_IO31,EIM_DATA10," tree.end width 15. tree "RGMI" group.long 0x1C0++0x5F line.long 0x00 "RGMII1_RD0,RGMII1_RD0 register" bitfld.long 0x00 4. " SION ,Force input path of pad RGMII1_RD0" "Not forced,Forced" bitfld.long 0x00 0.--3. " MUX_MODE ,RGMII1_RD0 MUX Mode" "ENET1_RX_DATA0,,,,,GPIO5_IO00,CSI2_DATA10,?..." line.long 0x04 "RGMII1_RD1,RGMII1_RD1 register" bitfld.long 0x04 4. " SION ,Force input path of pad RGMII1_RD1" "Not forced,Forced" bitfld.long 0x04 0.--3. " MUX_MODE ,RGMII1_RD1 MUX Mode" "ENET1_RX_DATA1,,,,,GPIO5_IO01,CSI2_DATA11,?..." line.long 0x08 "RGMII1_RD2,RGMII1_RD2 register" bitfld.long 0x08 4. " SION ,Force input path of pad RGMII1_RD2" "Not forced,Forced" bitfld.long 0x08 0.--3. " MUX_MODE ,RGMII1_RD2 MUX Mode" "ENET1_RX_DATA2,,,,,GPIO5_IO02,CSI2_DATA12,?..." line.long 0x0C "RGMII1_RD3,RGMII1_RD3 register" bitfld.long 0x0C 4. " SION ,Force input path of pad RGMII1_RD3" "Not forced,Forced" bitfld.long 0x0C 0.--3. " MUX_MODE ,RGMII1_RD3 MUX Mode" "ENET1_RX_DATA3,,,,,GPIO5_IO03,CSI2_DATA13,?..." line.long 0x10 "RGMII1_RX_CTL,RGMII1_RX_CTL register" bitfld.long 0x10 4. " SION ,Force input path of pad RGMII1_RX_CTL" "Not forced,Forced" bitfld.long 0x10 0.--3. " MUX_MODE ,RGMII1_RX_CTL MUX Mode" "ENET1_RX_EN,,,,,GPIO5_IO04,CSI2_DATA14,?..." line.long 0x14 "RGMII1_RXC,RGMII1_RXC register" bitfld.long 0x14 4. " SION ,Force input path of pad RGMII1_RXC" "Not forced,Forced" bitfld.long 0x14 0.--3. " MUX_MODE ,RGMII1_RXC MUX Mode" "ENET1_RX_CLK,ENET1_RX_ER,,,,GPIO5_IO05,CSI2_DATA15,?..." line.long 0x18 "RGMII1_TD0,RGMII1_TD0 register" bitfld.long 0x18 4. " SION ,Force input path of pad RGMII1_TD0" "Not forced,Forced" bitfld.long 0x18 0.--3. " MUX_MODE ,RGMII1_TD0 MUX Mode" "ENET1_TX_DATA0,,SAI2_RX_SYNC,,,GPIO5_IO06,CSI2_DATA16,?..." line.long 0x1C "RGMII1_TD1,RGMII1_TD1 register" bitfld.long 0x1C 4. " SION ,Force input path of pad RGMII1_TD1" "Not forced,Forced" bitfld.long 0x1C 0.--3. " MUX_MODE ,RGMII1_TD1 MUX Mode" "ENET1_TX_DATA1,,SAI2_RX_BCLK,,,GPIO5_IO07,CSI2_DATA17,?..." line.long 0x20 "RGMII1_TD2,RGMII1_TD2 register" bitfld.long 0x20 4. " SION ,Force input path of pad RGMII1_TD2" "Not forced,Forced" bitfld.long 0x20 0.--3. " MUX_MODE ,RGMII1_TD2 MUX Mode" "ENET1_TX_DATA2,,SAI2_TX_SYNC,,,GPIO5_IO08,CSI2_DATA18,?..." line.long 0x24 "RGMII1_TD3,RGMII1_TD3 register" bitfld.long 0x24 4. " SION ,Force input path of pad RGMII1_TD3" "Not forced,Forced" bitfld.long 0x24 0.--3. " MUX_MODE ,RGMII1_TD3 MUX Mode" "ENET1_TX_DATA3,,SAI2_TX_BCLK,,,GPIO5_IO09,CSI2_DATA19,?..." line.long 0x28 "RGMII1_TX_CTL,RGMII1_TX_CTL register" bitfld.long 0x28 4. " SION ,Force input path of pad RGMII1_TX_CTL" "Not forced,Forced" bitfld.long 0x28 0.--3. " MUX_MODE ,RGMII1_TX_CTL MUX Mode" "ENET1_TX_EN,,SAI2_RX_DATA0,,,GPIO5_IO10,CSI2_DATA20,?..." line.long 0x2C "RGMII1_TXC,RGMII1_TXC register" bitfld.long 0x2C 4. " SION ,Force input path of pad RGMII1_TXC" "Not forced,Forced" bitfld.long 0x2C 0.--3. " MUX_MODE ,RGMII1_TXC MUX Mode" "ENET1_RGMII_TXC,ENET1_TX_ER,SAI2_TX_DATA0,,,GPIO5_IO11,CSI2_DATA01,?..." line.long 0x30 "RGMII2_RD0,RGMII2_RD0 register" bitfld.long 0x30 4. " SION ,Force input path of pad RGMII2_RD0" "Not forced,Forced" bitfld.long 0x30 0.--3. " MUX_MODE ,RGMII2_RD0 MUX Mode" "ENET2_RX_DATA0,,PWM4_OUT,,,GPIO5_IO12,CSI2_DATA02,?..." line.long 0x34 "RGMII2_RD1,RGMII2_RD1 register" bitfld.long 0x34 4. " SION ,Force input path of pad RGMII2_RD1" "Not forced,Forced" bitfld.long 0x34 0.--3. " MUX_MODE ,RGMII2_RD1 MUX Mode" "ENET2_RX_DATA1,,PWM3_OUT,,,GPIO5_IO13,CSI2_DATA03,?..." line.long 0x38 "RGMII2_RD2,RGMII2_RD2 register" bitfld.long 0x38 4. " SION ,Force input path of pad RGMII2_RD2" "Not forced,Forced" bitfld.long 0x38 0.--3. " MUX_MODE ,RGMII2_RD2 MUX Mode" "ENET2_RX_DATA2,,PWM2_OUT,,,GPIO5_IO14,CSI2_DATA04,?..." line.long 0x3C "RGMII2_RD3,RGMII2_RD3 register" bitfld.long 0x3C 4. " SION ,Force input path of pad RGMII2_RD3" "Not forced,Forced" bitfld.long 0x3C 0.--3. " MUX_MODE ,RGMII2_RD3 MUX Mode" "ENET2_RX_DATA3,,PWM1_OUT,,,GPIO5_IO15,CSI2_DATA05,?..." line.long 0x40 "RGMII2_RX_CTL,RGMII2_RX_CTL register" bitfld.long 0x40 4. " SION ,Force input path of pad RGMII2_RX_CTL" "Not forced,Forced" bitfld.long 0x40 0.--3. " MUX_MODE ,RGMII2_RX_CTL MUX Mode" "ENET2_RX_EN,,,,,GPIO5_IO16,CSI2_DATA06,?..." line.long 0x44 "RGMII2_RXC,RGMII2_RXC register" bitfld.long 0x44 4. " SION ,Force input path of pad RGMII2_RXC" "Not forced,Forced" bitfld.long 0x44 0.--3. " MUX_MODE ,RGMII2_RXC MUX Mode" "ENET2_RX_CLK,ENET2_RX_ER,,,,GPIO5_IO17,CSI2_DATA07,?..." line.long 0x48 "RGMII2_TD0,RGMII2_TD0 register" bitfld.long 0x48 4. " SION ,Force input path of pad RGMII2_TD0" "Not forced,Forced" bitfld.long 0x48 0.--3. " MUX_MODE ,RGMII2_TD0 MUX Mode" "ENET2_TX_DATA0,,SAI1_RX_SYNC,PWM8_OUT,,GPIO5_IO18,CSI2_DATA08,?..." line.long 0x4C "RGMII2_TD1,RGMII2_TD1 register" bitfld.long 0x4C 4. " SION ,Force input path of pad RGMII2_TD1" "Not forced,Forced" bitfld.long 0x4C 0.--3. " MUX_MODE ,RGMII2_TD1 MUX Mode" "ENET2_TX_DATA1,,SAI1_RX_BCLK,PWM7_OUT,,GPIO5_IO19,CSI2_DATA09,?..." line.long 0x50 "RGMII2_TD2,RGMII2_TD2 register" bitfld.long 0x50 4. " SION ,Force input path of pad RGMII2_TD2" "Not forced,Forced" bitfld.long 0x50 0.--3. " MUX_MODE ,RGMII2_TD2 MUX Mode" "ENET2_TX_DATA2,,SAI1_TX_SYNC,PWM6_OUT,,GPIO5_IO20,CSI2_VSYNC,?..." line.long 0x54 "RGMII2_TD3,RGMII2_TD3 register" bitfld.long 0x54 4. " SION ,Force input path of pad RGMII2_TD3" "Not forced,Forced" bitfld.long 0x54 0.--3. " MUX_MODE ,RGMII2_TD3 MUX Mode" "ENET2_TX_DATA3,,SAI1_TX_BCLK,PWM5_OUT,,GPIO5_IO21,CSI2_HSYNC,?..." line.long 0x58 "RGMII2_TX_CTL,RGMII2_TX_CTL register" bitfld.long 0x58 4. " SION ,Force input path of pad RGMII2_TX_CTL" "Not forced,Forced" bitfld.long 0x58 0.--3. " MUX_MODE ,RGMII2_TX_CTL MUX Mode" "ENET2_TX_EN,,SAI1_TX_DATA0,,,GPIO5_IO22,CSI2_FIELD,JTAG_DE_B,?..." line.long 0x5C "RGMII2_TXC,RGMII2_TXC register" bitfld.long 0x5C 4. " SION ,Force input path of pad RGMII2_TXC" "Not forced,Forced" bitfld.long 0x5C 0.--3. " MUX_MODE ,RGMII2_TXC MUX Mode" "ENET2_RGMII_TXC,ENET2_TX_ER,SAI1_TX_DATA0,,,GPIO5_IO23,CSI2_PIXCLK,?..." tree.end width 13. tree "SD" group.long 0x220++0x83 line.long 0x00 "SD1_CLK,SD1_CLK register" bitfld.long 0x00 4. " SION ,Force input path of pad SD1_CLK" "Not forced,Forced" bitfld.long 0x00 0.--3. " MUX_MODE ,SD1_CLK MUX Mode" "SD1_CLK,AUD5_RXFS,WDOG2_B,GPT_CLK,WDOG2_RST_B_DEB,GPIO6_IO00,ENET2_1588_EVENT1_OUT,VADC_ADC_PROC_CLK,?..." line.long 0x04 "SD1_CMD,SD1_CMD register" bitfld.long 0x04 4. " SION ,Force input path of pad SD1_CMD" "Not forced,Forced" bitfld.long 0x04 0.--3. " MUX_MODE ,SD1_CMD MUX Mode" "SD1_CMD,AUD5_RXC,WDOG1_B,GPT_COMPARE1,WDOG1_RST_B_DEB,GPIO6_IO01,ENET2_1588_EVENT1_IN,CCM_CLKO1,VADC_EXT_SYSCLK,?..." line.long 0x08 "SD1_DATA0,SD1_DATA0 register" bitfld.long 0x08 4. " SION ,Force input path of pad SD1_DATA0" "Not forced,Forced" bitfld.long 0x08 0.--3. " MUX_MODE ,SD1_DATA0 MUX Mode" "SD1_DATA0,AUD5_RXD,,GPT_CAPTURE1,UART2_RX_DATA,GPIO6_IO02,ENET1_1588_EVENT1_IN,VADC_CLAMP_UP,?..." line.long 0x0C "SD1_DATA1,SD1_DATA1 register" bitfld.long 0x0C 4. " SION ,Force input path of pad SD1_DATA1" "Not forced,Forced" bitfld.long 0x0C 0.--3. " MUX_MODE ,SD1_DATA1 MUX Mode" "SD1_DATA1,AUD5_TXC,PWM4_OUT,GPT_CAPTURE2,UART2_TX_DATA,GPIO6_IO03,ENET1_1588_EVENT1_OUT,CCM_CLKO2,VADC_CLAMP_DOWN,?..." line.long 0x10 "SD1_DATA2,SD1_DATA2 register" bitfld.long 0x10 4. " SION ,Force input path of pad SD1_DATA2" "Not forced,Forced" bitfld.long 0x10 0.--3. " MUX_MODE ,SD1_DATA2 MUX Mode" "SD1_DATA2,AUD5_TXFS,PWM3_OUT,GPT_COMPARE2,UART2_CTS_B,GPIO6_IO04,ECSPI4_RDY,VADC_EXT_PD_N,?..." line.long 0x14 "SD1_DATA3,SD1_DATA3 register" bitfld.long 0x14 4. " SION ,Force input path of pad SD1_DATA3" "Not forced,Forced" bitfld.long 0x14 0.--3. " MUX_MODE ,SD1_DATA3 MUX Mode" "SD1_DATA3,AUD5_TXD,AUD5_RXD,GPT_COMPARE3,UART2_RTS_B,GPIO6_IO05,ECSPI4_SS1,CCM_PMIC_READY,VADC_RST_N,?..." line.long 0x18 "SD2_CLK,SD2_CLK register" bitfld.long 0x18 4. " SION ,Force input path of pad SD2_CLK" "Not forced,Forced" bitfld.long 0x18 0.--3. " MUX_MODE ,SD2_CLK MUX Mode" "SD2_CLK,AUD6_RXFS,KPP_COL5,ECSPI4_SCLK,MLB_SIG,GPIO6_IO06,MQS_RIGHT,WDOG1_ANY,VADC_CLAMP_CURRENT5,?..." line.long 0x1C "SD2_CMD,SD2_CMD register" bitfld.long 0x1C 4. " SION ,Force input path of pad SD2_CMD" "Not forced,Forced" bitfld.long 0x1C 0.--3. " MUX_MODE ,SD2_CMD MUX Mode" "SD2_CMD,AUD6_RXC,KPP_ROW5,ECSPI4_MOSI,MLB_CLK,GPIO6_IO07,MQS_LEFT,WDOG3_B,VADC_CLAMP_CURRENT4,?..." line.long 0x20 "SD2_DATA0,SD2_DATA0 register" bitfld.long 0x20 4. " SION ,Force input path of pad SD2_DATA0" "Not forced,Forced" bitfld.long 0x20 0.--3. " MUX_MODE ,SD2_DATA0 MUX Mode" "SD2_DATA0,AUD6_RXD,KPP_ROW7,PWM1_OUT,I2C4_SDA,GPIO6_IO08,ECSPI4_SS3,UART4_RX_DATA,VADC_CLAMP_CURRENT0,?..." line.long 0x24 "SD2_DATA1,SD2_DATA1 register" bitfld.long 0x24 4. " SION ,Force input path of pad SD2_DATA1" "Not forced,Forced" bitfld.long 0x24 0.--3. " MUX_MODE ,SD2_DATA1 MUX Mode" "SD2_DATA1,AUD6_TXC,KPP_COL7,PWM2_OUT,I2C4_SCL,GPIO6_IO09,ECSPI4_SS2,UART4_TX_DATA,VADC_CLAMP_CURRENT1,?..." line.long 0x28 "SD2_DATA2,SD2_DATA2 register" bitfld.long 0x28 4. " SION ,Force input path of pad SD2_DATA2" "Not forced,Forced" bitfld.long 0x28 0.--3. " MUX_MODE ,SD2_DATA2 MUX Mode" "SD2_DATA2,AUD6_TXFS,KPP_ROW6,ECSPI4_SS0,SDMA_EXT_EVENT0,GPIO6_IO10,SPDIF_OUT,UART6_RX_DATA,VADC_CLAMP_CURRENT2,?..." line.long 0x2C "SD2_DATA3,SD2_DATA3 register" bitfld.long 0x2C 4. " SION ,Force input path of pad SD2_DATA3" "Not forced,Forced" bitfld.long 0x2C 0.--3. " MUX_MODE ,SD2_DATA3 MUX Mode" "SD2_DATA3,AUD6_TXD,KPP_COL6,ECSPI4_MISO,MLB_DATA,GPIO6_IO11,SPDIF_IN,UART6_TX_DATA,VADC_CLAMP_CURRENT3,?..." line.long 0x30 "SD3_CLK,SD3_CLK register" bitfld.long 0x30 4. " SION ,Force input path of pad SD3_CLK" "Not forced,Forced" bitfld.long 0x30 0.--3. " MUX_MODE ,SD3_CLK MUX Mode" "SD3_CLK,UART4_CTS_B,ECSPI4_SCLK,AUD6_RXFS,LCD2_VSYNC,GPIO7_IO00,LCD2_BUSY,?..." line.long 0x34 "SD3_CMD,SD3_CMD register" bitfld.long 0x34 4. " SION ,Force input path of pad SD3_CMD" "Not forced,Forced" bitfld.long 0x34 0.--3. " MUX_MODE ,SD3_CMD MUX Mode" "SD3_CMD,UART4_TX_DATA,ECSPI4_MOSI,AUD6_RXC,LCD2_HSYNC,GPIO7_IO01,LCD2_RS,?..." line.long 0x38 "SD3_DATA0,SD3_DATA0 register" bitfld.long 0x38 4. " SION ,Force input path of pad SD3_DATA0" "Not forced,Forced" bitfld.long 0x38 0.--3. " MUX_MODE ,SD3_DATA0 MUX Mode" "SD3_DATA0,I2C4_SCL,ECSPI2_SS1,AUD6_RXD,LCD2_DATA01,GPIO7_IO02,DCIC1_OUT,?..." line.long 0x3C "SD3_DATA1,SD3_DATA1 register" bitfld.long 0x3C 4. " SION ,Force input path of pad SD3_DATA1" "Not forced,Forced" bitfld.long 0x3C 0.--3. " MUX_MODE ,SD3_DATA1 MUX Mode" "SD3_DATA1,I2C4_SDA,ECSPI2_SS2,AUD6_TXC,LCD2_DATA00,GPIO7_IO03,DCIC2_OUT,?..." line.long 0x40 "SD3_DATA2,SD3_DATA2 register" bitfld.long 0x40 4. " SION ,Force input path of pad SD3_DATA2" "Not forced,Forced" bitfld.long 0x40 0.--3. " MUX_MODE ,SD3_DATA2 MUX Mode" "SD3_DATA2,UART4_RTS_B,ECSPI4_SS0,AUD6_TXFS,LCD2_CLK,GPIO7_IO04,LCD2_WR_RWN,?..." line.long 0x44 "SD3_DATA3,SD3_DATA3 register" bitfld.long 0x44 4. " SION ,Force input path of pad SD3_DATA3" "Not forced,Forced" bitfld.long 0x44 0.--3. " MUX_MODE ,SD3_DATA3 MUX Mode" "SD3_DATA3,UART4_RX_DATA,ECSPI4_MISO,AUD6_TXD,LCD2_ENABLE,GPIO7_IO05,LCD2_RD_E,?..." line.long 0x48 "SD3_DATA4,SD3_DATA4 register" bitfld.long 0x48 4. " SION ,Force input path of pad SD3_DATA4" "Not forced,Forced" bitfld.long 0x48 0.--3. " MUX_MODE ,SD3_DATA4 MUX Mode" "SD3_DATA4,CAN2_RX,,UART3_RX_DATA,LCD2_DATA03,GPIO7_IO06,ENET2_1588_EVENT0_IN,?..." line.long 0x4C "SD3_DATA5,SD3_DATA5 register" bitfld.long 0x4C 4. " SION ,Force input path of pad SD3_DATA5" "Not forced,Forced" bitfld.long 0x4C 0.--3. " MUX_MODE ,SD3_DATA5 MUX Mode" "SD3_DATA5,CAN1_TX,,UART3_TX_DATA,LCD2_DATA02,GPIO7_IO07,ENET2_1588_EVENT0_OUT,?..." line.long 0x50 "SD3_DATA6,SD3_DATA6 register" bitfld.long 0x50 4. " SION ,Force input path of pad SD3_DATA6" "Not forced,Forced" bitfld.long 0x50 0.--3. " MUX_MODE ,SD3_DATA6 MUX Mode" "SD3_DATA6,CAN2_TX,,UART3_RTS_B,LCD2_DATA04,GPIO7_IO08,ENET1_1588_EVENT0_OUT,?..." line.long 0x54 "SD3_DATA7,SD3_DATA7 register" bitfld.long 0x54 4. " SION ,Force input path of pad SD3_DATA7" "Not forced,Forced" bitfld.long 0x54 0.--3. " MUX_MODE ,SD3_DATA7 MUX Mode" "SD3_DATA7,CAN1_RX,,UART3_CTS_B,LCD2_DATA05,GPIO7_IO09,ENET1_1588_EVENT0_IN,?..." line.long 0x58 "SD4_CLK,SD4_CLK register" bitfld.long 0x58 4. " SION ,Force input path of pad SD4_CLK" "Not forced,Forced" bitfld.long 0x58 0.--3. " MUX_MODE ,SD4_CLK MUX Mode" "SD4_CLK,NAND_DATA15,ECSPI2_MISO,AUD3_RXFS,LCD2_DATA13,GPIO6_IO12,ECSPI3_SS2,?..." line.long 0x5C "SD4_CMD,SD4_CMD register" bitfld.long 0x5C 4. " SION ,Force input path of pad SD4_CMD" "Not forced,Forced" bitfld.long 0x5C 0.--3. " MUX_MODE ,SD4_CMD MUX Mode" "SD4_CMD,NAND_DATA14,ECSPI2_MOSI,AUD3_RXC,LCD2_DATA14,GPIO6_IO13,ECSPI3_SS1,?..." line.long 0x60 "SD4_DATA0,SD4_DATA0 register" bitfld.long 0x60 4. " SION ,Force input path of pad SD4_DATA0" "Not forced,Forced" bitfld.long 0x60 0.--3. " MUX_MODE ,SD4_DATA0 MUX Mode" "SD4_DATA0,NAND_DATA10,ECSPI2_SS0,AUD3_RXD,LCD2_DATA12,GPIO6_IO14,ECSPI3_SS3,?..." line.long 0x64 "SD4_DATA1,SD4_DATA1 register" bitfld.long 0x64 4. " SION ,Force input path of pad SD4_DATA1" "Not forced,Forced" bitfld.long 0x64 0.--3. " MUX_MODE ,SD4_DATA1 MUX Mode" "SD4_DATA1,NAND_DATA11,ECSPI2_SCLK,AUD3_TXC,LCD2_DATA11,GPIO6_IO15,ECSPI3_RDY,?..." line.long 0x68 "SD4_DATA2,SD4_DATA2 register" bitfld.long 0x68 4. " SION ,Force input path of pad SD4_DATA2" "Not forced,Forced" bitfld.long 0x68 0.--3. " MUX_MODE ,SD4_DATA2 MUX Mode" "SD4_DATA2,NAND_DATA12,I2C2_SDA,AUD3_TXFS,LCD2_DATA10,GPIO6_IO16,ECSPI2_SS3,?..." line.long 0x6C "SD4_DATA3,SD4_DATA3 register" bitfld.long 0x6C 4. " SION ,Force input path of pad SD4_DATA3" "Not forced,Forced" bitfld.long 0x6C 0.--3. " MUX_MODE ,SD4_DATA3 MUX Mode" "SD4_DATA3,NAND_DATA13,I2C2_SCL,AUD3_TXD,LCD2_DATA09,GPIO6_IO17,ECSPI2_RDY,?..." line.long 0x70 "SD4_DATA4,SD4_DATA4 register" bitfld.long 0x70 4. " SION ,Force input path of pad SD4_DATA4" "Not forced,Forced" bitfld.long 0x70 0.--3. " MUX_MODE ,SD4_DATA4 MUX Mode" "SD4_DATA4,NAND_DATA09,UART5_RX_DATA,ECSPI3_SCLK,LCD2_DATA08,GPIO6_IO18,SPDIF_OUT,,USB_OTG_HOST_MODE,?..." line.long 0x74 "SD4_DATA5,SD4_DATA5 register" bitfld.long 0x74 4. " SION ,Force input path of pad SD4_DATA5" "Not forced,Forced" bitfld.long 0x74 0.--3. " MUX_MODE ,SD4_DATA5 MUX Mode" "SD4_DATA5,NAND_CE2_B,UART5_TX_DATA,ECSPI3_MOSI,LCD2_DATA07,GPIO6_IO19,SPDIF_IN,?..." line.long 0x78 "SD4_DATA6,SD4_DATA6 register" bitfld.long 0x78 4. " SION ,Force input path of pad SD4_DATA6" "Not forced,Forced" bitfld.long 0x78 0.--3. " MUX_MODE ,SD4_DATA6 MUX Mode" "SD4_DATA6,NAND_CE3_B,UART5_RTS_B,ECSPI3_MISO,LCD2_DATA06,GPIO6_IO20,SD4_WP,?..." line.long 0x7C "SD4_DATA7,SD4_DATA7 register" bitfld.long 0x7C 4. " SION ,Force input path of pad SD4_DATA7" "Not forced,Forced" bitfld.long 0x7C 0.--3. " MUX_MODE ,SD4_DATA7 MUX Mode" "SD4_DATA7,NAND_DATA08,UART5_CTS_B,ECSPI3_SS0,LCD2_DATA15,GPIO6_IO21,SD4_CD_B,,USB_OTG_PWR_WAKE,?..." line.long 0x80 "SD4_RESET_B,SD4_RESET_B register" bitfld.long 0x80 4. " SION ,Force input path of pad SD4_RESET_B" "Not forced,Forced" bitfld.long 0x80 0.--3. " MUX_MODE ,SD4_RESET_B MUX Mode" "SD4_RESET_B,NAND_DQS,SD4_RESET,AUDIO_CLK_OUT,LCD2_RESET,GPIO6_IO22,LCD2_CS,?..." tree.end width 14. tree "USB_H" group.long 0x2A4++0x07 line.long 0x00 "USB_H_DATA,USB_H_DATA register" bitfld.long 0x00 4. " SION ,Force input path of pad USB_H_DATA" "Not forced,Forced" bitfld.long 0x00 0.--2. " MUX_MODE ,USB_H_DATA MUX Mode" "USB_H_DATA,PWM2_OUT,XTALOSC_REF_CLK_24M,I2C4_SDA,WDOG3_B,GPIO7_IO10,..." line.long 0x04 "USB_H_STROBE,USB_H_STROBE register" rbitfld.long 0x04 4. " SION ,Force input path of pad USB_H_STROBE" "Not forced,Forced" bitfld.long 0x04 0.--2. " MUX_MODE ,USB_H_STROBE MUX Mode" "USB_H_STROBE,PWM1_OUT,XTALOSC_REF_CLK_32K,I2C4_SCL,WDOG3_RST_B_DEB,GPIO7_IO11,..." tree.end width 13. tree "DRAM" group.long 0x2AC++0x97 line.long 0x00 "DRAM_ADDR00,DRAM_ADDR00 register" rbitfld.long 0x00 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x00 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x00 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x00 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x00 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x00 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" line.long 0x04 "DRAM_ADDR01,DRAM_ADDR01 register" rbitfld.long 0x04 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x04 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x04 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x04 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x04 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x04 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x04 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x04 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x04 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" line.long 0x08 "DRAM_ADDR02,DRAM_ADDR02 register" rbitfld.long 0x08 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x08 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x08 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x08 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x08 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x08 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x08 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x08 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x08 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" line.long 0x0C "DRAM_ADDR03,DRAM_ADDR03 register" rbitfld.long 0x0C 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x0C 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x0C 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x0C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x0C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x0C 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x0C 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x0C 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x0C 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" line.long 0x10 "DRAM_ADDR04,DRAM_ADDR04 register" rbitfld.long 0x10 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x10 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x10 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x10 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" line.long 0x14 "DRAM_ADDR05,DRAM_ADDR05 register" rbitfld.long 0x14 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x14 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x14 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x14 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" line.long 0x18 "DRAM_ADDR06,DRAM_ADDR06 register" rbitfld.long 0x18 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x18 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x18 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x18 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" line.long 0x1C "DRAM_ADDR07,DRAM_ADDR07 register" rbitfld.long 0x1C 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x1C 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x1C 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x1C 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" line.long 0x20 "DRAM_ADDR08,DRAM_ADDR08 register" rbitfld.long 0x20 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x20 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x20 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x20 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x24 "DRAM_ADDR09,DRAM_ADDR09 register" rbitfld.long 0x24 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x24 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x24 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x24 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x28 "DRAM_ADDR10,DRAM_ADDR10 register" bitfld.long 0x28 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x28 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x28 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x28 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x28 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x28 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x28 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x28 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x28 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x2C "DRAM_ADDR11,DRAM_ADDR11 register" bitfld.long 0x2C 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x2C 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x2C 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x2C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x2C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x2C 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x2C 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x2C 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x2C 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x30 "DRAM_ADDR12,DRAM_ADDR12 register" bitfld.long 0x30 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x30 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x30 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x30 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x30 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x30 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x30 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x30 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x30 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x34 "DRAM_ADDR13,DRAM_ADDR13 register" bitfld.long 0x34 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x34 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x34 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x34 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x34 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x34 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x34 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x34 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x34 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x38 "DRAM_ADDR14,DRAM_ADDR14 register" bitfld.long 0x38 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x38 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x38 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x38 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x38 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x38 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x38 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x38 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x38 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x3C "DRAM_ADDR15,DRAM_ADDR15 register" bitfld.long 0x3C 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x3C 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x3C 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x3C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x3C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x3C 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x3C 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x3C 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x3C 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x40 "DRAM_DQM0,DRAM_DQM0 register" rbitfld.long 0x40 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x40 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x40 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x40 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x40 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x40 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x40 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x40 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x40 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x44 "DRAM_DQM1,DRAM_DQM1 register" rbitfld.long 0x44 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x44 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x44 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x44 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x44 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x44 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x44 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x44 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x44 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x48 "DRAM_DQM2,DRAM_DQM2 register" rbitfld.long 0x48 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x48 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x48 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x48 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x48 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x48 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x48 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x48 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x48 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x4C "DRAM_DQM3,DRAM_DQM3 register" rbitfld.long 0x4C 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x4C 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x4C 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x4C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x4C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x4C 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x4C 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x4C 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x4C 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x50 "DRAM_RAS_B,DRAM_RAS_B register" bitfld.long 0x50 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x50 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x50 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x50 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x50 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x50 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x50 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x50 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x50 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x54 "DRAM_CAS_B,DRAM_CAS_B register" bitfld.long 0x54 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x54 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x54 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x54 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x54 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x54 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x54 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x54 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x54 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x58 "DRAM_CS0_B,DRAM_CS0_B register" bitfld.long 0x58 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x58 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x58 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x58 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x58 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x58 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x58 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x58 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x58 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x5C "DRAM_CS1_B,DRAM_CS1_B register" bitfld.long 0x5C 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x5C 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x5C 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x5C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x5C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x5C 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x5C 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x5C 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x5C 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x60 "DRAM_SDWE_B,DRAM_SDWE_B register" bitfld.long 0x60 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x60 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x60 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x60 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x60 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x60 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x60 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x60 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x60 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x64 "DRAM_ODT0,DRAM_ODT0 register" bitfld.long 0x64 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x64 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x64 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x64 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " bitfld.long 0x64 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x64 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x64 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x64 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x64 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x68 "DRAM_ODT1,DRAM_ODT1 register" bitfld.long 0x68 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x68 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x68 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x68 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " bitfld.long 0x68 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x68 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x68 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x68 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x68 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x6C "DRAM_SDBA0,DRAM_SDBA0 register" bitfld.long 0x6C 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x6C 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x6C 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x6C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x6C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x6C 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x6C 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x6C 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x6C 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x70 "DRAM_SDBA1,DRAM_SDBA1 register" bitfld.long 0x70 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x70 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x70 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x70 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x70 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x70 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x70 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x70 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x70 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x74 "DRAM_SDBA2,DRAM_SDBA2 register" bitfld.long 0x74 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x74 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x74 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x74 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x74 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x74 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x74 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x74 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x74 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x78 "DRAM_SDCKE0,DRAM_SDCKE0 register" bitfld.long 0x78 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x78 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x78 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x78 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " bitfld.long 0x78 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x78 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x78 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x78 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x78 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x7C "DRAM_SDCKE1,DRAM_SDCKE1 register" bitfld.long 0x7C 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x7C 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x7C 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x7C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " bitfld.long 0x7C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x7C 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x7C 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x7C 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " rbitfld.long 0x7C 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x80 "DRAM_SDCKE1,DRAM_SDCKE1 register" bitfld.long 0x80 24.--25. " DO_TRIM_PADN ,DO Trim PADN Field" "Min,50ps,100ps,150ps" bitfld.long 0x80 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x80 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x80 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x80 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " rbitfld.long 0x80 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x80 13. " PUE ,Pull / Keep Select Field" "0,1" rbitfld.long 0x80 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x80 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x80 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x84 "DRAM_SDQS0_P,DRAM_SDQS0_P register" bitfld.long 0x84 24.--25. " DO_TRIM_PADN ,DO Trim PADN Field" "Min,50ps,100ps,150ps" bitfld.long 0x84 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x84 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" rbitfld.long 0x84 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" textline " " rbitfld.long 0x84 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x84 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x84 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x84 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x84 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" bitfld.long 0x84 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x88 "DRAM_SDQS1_P,DRAM_SDQS1_P register" bitfld.long 0x88 24.--25. " DO_TRIM_PADN ,DO Trim PADN Field" "Min,50ps,100ps,150ps" bitfld.long 0x88 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x88 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" rbitfld.long 0x88 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" textline " " rbitfld.long 0x88 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x88 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x88 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x88 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x88 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" bitfld.long 0x88 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x8C "DRAM_SDQS2_P,DRAM_SDQS2_P register" bitfld.long 0x8C 24.--25. " DO_TRIM_PADN ,DO Trim PADN Field" "Min,50ps,100ps,150ps" bitfld.long 0x8C 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x8C 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" rbitfld.long 0x8C 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" textline " " rbitfld.long 0x8C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x8C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x8C 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x8C 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x8C 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" bitfld.long 0x8C 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x90 "DRAM_SDQS2_P,DRAM_SDQS2_P register" bitfld.long 0x90 24.--25. " DO_TRIM_PADN ,DO Trim PADN Field" "Min,50ps,100ps,150ps" bitfld.long 0x90 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" rbitfld.long 0x90 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" rbitfld.long 0x90 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" textline " " rbitfld.long 0x90 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x90 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x90 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x90 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x90 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" bitfld.long 0x90 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x94 "DRAM_RESET,DRAM_RESET register" bitfld.long 0x94 20.--21. " DO_TRIM ,DO Trim Field" "0,1,2,3" bitfld.long 0x94 18.--19. " DDR_SEL ,DDR Select Field" "0,1,2,3" bitfld.long 0x94 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" bitfld.long 0x94 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" textline " " bitfld.long 0x94 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" bitfld.long 0x94 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x94 12. " PKE ,Pull / Keep Enable Field" "0,1" bitfld.long 0x94 8.--10. " ODT ,On Die Termination Field" "Disabled,120_OHM,60_OHM,40_OHM,30_OHM,24_OHM,20_OHM,17_OHM" textline " " bitfld.long 0x94 3.--5. " DSE ,Drive Strength Field" "HI-Z,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" tree.end width 13. tree "JTAG" group.long 0x344++0x017 line.long 0x00 "JTAG_MOD,JTAG_MOD register" bitfld.long 0x00 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x00 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Ohm Down,47K Ohm Up,100K Ohm Up,22K Ohm Up" rbitfld.long 0x00 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x00 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x00 11. " ODE ,Open Drain Enable Field" "0,1" rbitfld.long 0x00 6.--7. " SPEED ,Speed Field" "0,1,2,3" rbitfld.long 0x00 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x04 "JTAG_TCK,JTAG_TCK register" bitfld.long 0x04 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x04 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Ohm Down,47K Ohm Up,100K Ohm Up,22K Ohm Up" rbitfld.long 0x04 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x04 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x04 11. " ODE ,Open Drain Enable Field" "0,1" rbitfld.long 0x04 6.--7. " SPEED ,Speed Field" "0,1,2,3" rbitfld.long 0x04 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x08 "JTAG_TDI,JTAG_TDI register" bitfld.long 0x08 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x08 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Ohm Down,47K Ohm Up,100K Ohm Up,22K Ohm Up" rbitfld.long 0x08 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x08 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x08 11. " ODE ,Open Drain Enable Field" "0,1" rbitfld.long 0x08 6.--7. " SPEED ,Speed Field" "0,1,2,3" rbitfld.long 0x08 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" rbitfld.long 0x08 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x0C "JTAG_TDO,JTAG_TDO register" rbitfld.long 0x0C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" rbitfld.long 0x0C 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x0C 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x0C 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x0C 11. " ODE ,Open Drain Enable Field" "0,1" rbitfld.long 0x0C 6.--7. " SPEED ,Speed Field" "0,1,2,3" rbitfld.long 0x0C 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 0. " SRE ,Slew Rate Field" "0,1" line.long 0x10 "JTAG_TMS,JTAG_TMS register" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Ohm Down,47K Ohm Up,100K Ohm Up,22K Ohm Up" rbitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "0,1" rbitfld.long 0x10 6.--7. " SPEED ,Speed Field" "0,1,2,3" rbitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 0. " SRE ,Slew Rate Field" "0,1" line.long 0x14 "JTAG_TRST_B,JTAG_TRST_B register" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "0,1,2,3" rbitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "0,1" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "0,1" textline " " rbitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "0,1" rbitfld.long 0x14 6.--7. " SPEED ,Speed Field" "0,1,2,3" rbitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "0,1,2,3,4,5,6,7" rbitfld.long 0x14 0. " SRE ,Slew Rate Field" "Slow,Fast" tree.end width 13. tree "GPIO" group.long 0x35C++0x037 line.long 0x0 "GPIO1_IO00,GPIO1_IO00 register" bitfld.long 0x0 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x0 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x0 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x0 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x0 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x0 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x0 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x4 "GPIO1_IO01,GPIO1_IO01 register" bitfld.long 0x4 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x4 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x4 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x4 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x4 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x4 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x4 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x4 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x8 "GPIO1_IO02,GPIO1_IO02 register" bitfld.long 0x8 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x8 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x8 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x8 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x8 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x8 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x8 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x8 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0xC "GPIO1_IO03,GPIO1_IO03 register" bitfld.long 0xC 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0xC 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0xC 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0xC 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0xC 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0xC 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0xC 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0xC 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x10 "GPIO1_IO04,GPIO1_IO04 register" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x10 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x14 "GPIO1_IO05,GPIO1_IO05 register" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x14 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x18 "GPIO1_IO06,GPIO1_IO06 register" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x18 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x1C "GPIO1_IO07,GPIO1_IO07 register" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x20 "GPIO1_IO08,GPIO1_IO08 register" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x20 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x24 "GPIO1_IO09,GPIO1_IO09 register" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x24 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x28 "GPIO1_IO10,GPIO1_IO10 register" bitfld.long 0x28 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x28 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x28 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x28 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x28 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x28 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x2C "GPIO1_IO11,GPIO1_IO11 register" bitfld.long 0x2C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x2C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x2C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x2C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x2C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x2C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x2C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x2C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x30 "GPIO1_IO12,GPIO1_IO12 register" bitfld.long 0x30 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x30 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x30 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x30 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x30 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x30 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x30 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x30 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x34 "GPIO1_IO13,GPIO1_IO13 register" bitfld.long 0x34 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x34 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x34 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x34 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x34 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x34 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x34 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x34 0. " SRE ,Slew Rate Field" "Slow,Fast" tree.end width 13. tree "CSI" group.long 0x390++0x2F line.long 0x0 "CSI_DATA00,CSI_DATA00 register" bitfld.long 0x0 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x0 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x0 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x0 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x0 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x0 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x0 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x4 "CSI_DATA01,CSI_DATA01 register" bitfld.long 0x4 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x4 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x4 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x4 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x4 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x4 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x4 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x4 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x8 "CSI_DATA02,CSI_DATA02 register" bitfld.long 0x8 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x8 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x8 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x8 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x8 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x8 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x8 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x8 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0xC "CSI_DATA03,CSI_DATA03 register" bitfld.long 0xC 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0xC 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0xC 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0xC 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0xC 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0xC 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0xC 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0xC 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x10 "CSI_DATA04,CSI_DATA04 register" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x10 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x14 "CSI_DATA05,CSI_DATA05 register" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x14 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x18 "CSI_DATA06,CSI_DATA06 register" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x18 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x1C "CSI_DATA07,CSI_DATA07 register" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x20 "CSI_HSYNC,CSI_HSYNC register" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x20 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x24 "CSI_MCLK,CSI_MCLK register" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x24 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x28 "CSI_PIXCLK,CSI_PIXCLK register" bitfld.long 0x28 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x28 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x28 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x28 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x28 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x28 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x2C "CSI_VSYNC,CSI_VSYNC register" bitfld.long 0x2C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x2C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x2C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x2C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x2C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x2C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x2C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x2C 0. " SRE ,Slew Rate Field" "Slow,Fast" tree.end width 14. tree "ENET" group.long 0x3C4++0x027 line.long 0x00 "ENET1_COL,ENET1_COL register" bitfld.long 0x00 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x00 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x00 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x00 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x00 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x04 "ENET1_CRS,ENET1_CRS register" bitfld.long 0x04 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x04 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x04 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x04 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x04 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x08 "ENET1_MDC,ENET1_MDC register" bitfld.long 0x08 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x08 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x08 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x08 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x08 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x08 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x08 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x0C "ENET1_MDIO,ENET1_MDIO register" bitfld.long 0x0C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x0C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x0C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x0C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x0C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x0C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x0C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x0C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x10 "ENET1_RX_CLK,ENET1_RX_CLK register" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x10 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x14 "ENET1_TX_CLK,ENET1_TX_CLK register" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x14 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x18 "ENET2_COL,ENET2_COL register" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x18 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x1C "ENET2_CRS,ENET2_CRS register" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x20 "ENET2_RX_CLK,ENET2_RX_CLK register" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x20 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x24 "ENET2_TX_CLK,ENET2_TX_CLK register" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x24 0. " SRE ,Slew Rate Field" "Slow,Fast" tree.end width 10. tree "KEY" group.long 0x3EC++0x27 line.long 0x0 "KEY_COL0,KEY_COL0 register" bitfld.long 0x0 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x0 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x0 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x0 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x0 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x0 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x0 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x4 "KEY_COL1,KEY_COL1 register" bitfld.long 0x4 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x4 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x4 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x4 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x4 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x4 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x4 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x4 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x8 "KEY_COL2,KEY_COL2 register" bitfld.long 0x8 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x8 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x8 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x8 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x8 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x8 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x8 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x8 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0xC "KEY_COL3,KEY_COL3 register" bitfld.long 0xC 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0xC 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0xC 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0xC 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0xC 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0xC 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0xC 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0xC 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x10 "KEY_COL4,KEY_COL4 register" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x10 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x14 "KEY_ROW0,KEY_ROW0 register" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x14 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x18 "KEY_ROW1,KEY_ROW1 register" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x18 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x1C "KEY_ROW2,KEY_ROW2 register" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x20 "KEY_ROW3,KEY_ROW3 register" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x20 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x24 "KEY_ROW4,KEY_ROW4 register" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x24 0. " SRE ,Slew Rate Field" "Slow,Fast" tree.end width 13. tree "LCD1" group.long 0x414++0x77 line.long 0x00 "LCD1_CLK,LCD1_CLK register" bitfld.long 0x00 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x00 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x00 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x00 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x00 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x4 "LCD1_DATA00,LCD1_DATA00 register" bitfld.long 0x4 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x4 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x4 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x4 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x4 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x4 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x4 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x4 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x8 "LCD1_DATA01,LCD1_DATA01 register" bitfld.long 0x8 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x8 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x8 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x8 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x8 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x8 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x8 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x8 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0xC "LCD1_DATA02,LCD1_DATA02 register" bitfld.long 0xC 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0xC 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0xC 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0xC 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0xC 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0xC 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0xC 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0xC 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x10 "LCD1_DATA03,LCD1_DATA03 register" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x10 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x14 "LCD1_DATA04,LCD1_DATA04 register" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x14 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x18 "LCD1_DATA05,LCD1_DATA05 register" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x18 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x1C "LCD1_DATA06,LCD1_DATA06 register" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x20 "LCD1_DATA07,LCD1_DATA07 register" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x20 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x24 "LCD1_DATA08,LCD1_DATA08 register" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x24 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x28 "LCD1_DATA09,LCD1_DATA09 register" bitfld.long 0x28 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x28 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x28 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x28 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x28 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x28 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x2C "LCD1_DATA10,LCD1_DATA10 register" bitfld.long 0x2C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x2C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x2C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x2C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x2C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x2C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x2C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x2C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x30 "LCD1_DATA11,LCD1_DATA11 register" bitfld.long 0x30 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x30 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x30 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x30 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x30 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x30 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x30 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x30 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x34 "LCD1_DATA12,LCD1_DATA12 register" bitfld.long 0x34 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x34 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x34 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x34 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x34 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x34 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x34 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x34 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x38 "LCD1_DATA13,LCD1_DATA13 register" bitfld.long 0x38 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x38 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x38 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x38 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x38 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x38 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x38 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x38 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x3C "LCD1_DATA14,LCD1_DATA14 register" bitfld.long 0x3C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x3C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x3C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x3C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x3C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x3C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x3C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x3C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x40 "LCD1_DATA15,LCD1_DATA15 register" bitfld.long 0x40 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x40 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x40 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x40 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x40 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x40 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x40 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x40 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x44 "LCD1_DATA16,LCD1_DATA16 register" bitfld.long 0x44 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x44 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x44 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x44 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x44 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x44 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x44 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x44 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x48 "LCD1_DATA17,LCD1_DATA17 register" bitfld.long 0x48 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x48 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x48 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x48 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x48 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x48 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x48 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x48 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x4C "LCD1_DATA18,LCD1_DATA18 register" bitfld.long 0x4C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x4C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x4C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x4C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x4C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x4C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x4C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x4C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x50 "LCD1_DATA19,LCD1_DATA19 register" bitfld.long 0x50 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x50 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x50 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x50 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x50 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x50 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x50 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x50 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x58 "LCD1_DATA20,LCD1_DATA20 register" bitfld.long 0x58 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x58 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x58 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x58 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x58 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x58 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x58 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x58 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x5C "LCD1_DATA21,LCD1_DATA21 register" bitfld.long 0x5C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x5C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x5C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x5C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x5C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x5C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x5C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x5C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x60 "LCD1_DATA22,LCD1_DATA22 register" bitfld.long 0x60 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x60 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x60 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x60 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x60 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x60 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x60 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x60 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x64 "LCD1_DATA23,LCD1_DATA23 register" bitfld.long 0x64 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x64 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x64 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x64 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x64 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x64 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x64 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x64 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x68 "LCD1_ENABLE,LCD1_ENABLE register" bitfld.long 0x68 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x68 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x68 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x68 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x68 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x68 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x68 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x68 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x6C "LCD1_HSYNC,LCD1_HSYNC register" bitfld.long 0x6C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x6C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x6C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x6C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x6C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x6C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x6C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x6C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x70 "LCD1_RESET,LCD1_RESET register" bitfld.long 0x70 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x70 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x70 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x70 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x70 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x70 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x70 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x70 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x74 "LCD1_VSYNC,LCD1_VSYNC register" bitfld.long 0x74 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x74 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x74 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x74 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x74 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x74 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x74 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x74 0. " SRE ,Slew Rate Field" "Slow,Fast" tree.end width 14. tree "NAND registers" group.long 0x488++0x3F line.long 0x00 "NAND_ALE,NAND_ALE register" bitfld.long 0x00 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x00 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x00 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x00 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x00 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x04 "NAND_CE0_B,NAND_CE0_B register" bitfld.long 0x04 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x04 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x04 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x04 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x04 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x08 "NAND_CE1_B,NAND_CE1_B register" bitfld.long 0x08 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x08 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x08 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x08 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x08 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x08 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x08 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x0C "NAND_CLE,NAND_CLE register" bitfld.long 0x0C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x0C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x0C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x0C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x0C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x0C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x0C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x0C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x10 "NAND_DATA00,NAND_DATA00 register" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x10 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x14 "NAND_DATA01,NAND_DATA01 register" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x14 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x18 "NAND_DATA02,NAND_DATA02 register" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x18 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x1C "NAND_DATA03,NAND_DATA03 register" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x20 "NAND_DATA04,NAND_DATA04 register" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x20 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x24 "NAND_DATA05,NAND_DATA05 register" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x24 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x28 "NAND_DATA06,NAND_DATA06 register" bitfld.long 0x28 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x28 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x28 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x28 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x28 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x28 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x2C "NAND_DATA07,NAND_DATA07 register" bitfld.long 0x2C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x2C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x2C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x2C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x2C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x2C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x2C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x2C 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x30 "NAND_RE_B,NAND_RE_B register" bitfld.long 0x30 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x30 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x30 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x30 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x30 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x30 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x30 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x30 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x34 "NAND_READY_B,NAND_READY_B register" bitfld.long 0x34 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x34 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x34 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x34 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x34 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x34 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x34 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x34 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x38 "NAND_WE_B,NAND_WE_B register" bitfld.long 0x38 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x38 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x38 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x38 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x38 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x38 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x38 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x38 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x3C "NAND_WP_B,NAND_WP_B register" bitfld.long 0x3C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x3C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x3C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x3C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x3C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x3C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x3C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x3C 0. " SRE ,Slew Rate Field" "SLOW,FAST" tree.end width 14. tree "QSPI1x" group.long 0x4C8++0x03F line.long 0x0 "QSPI1A_DATA0,QSPI1A_DATA0 register" bitfld.long 0x0 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x0 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x0 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x0 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x0 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x0 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x0 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x4 "QSPI1A_DATA1,QSPI1A_DATA1 register" bitfld.long 0x4 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x4 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x4 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x4 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x4 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x4 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x4 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x4 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x8 "QSPI1A_DATA2,QSPI1A_DATA2 register" bitfld.long 0x8 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x8 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x8 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x8 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x8 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x8 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x8 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x8 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0xC "QSPI1A_DATA3,QSPI1A_DATA3 register" bitfld.long 0xC 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0xC 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0xC 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0xC 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0xC 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0xC 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0xC 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0xC 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x10 "QSPI1A_DQS,QSPI1A_DQS register" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x10 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x14 "QSPI1A_SCLK,QSPI1A_SCLK register" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x14 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x18 "QSPI1A_SS0_B,QSPI1A_SS0_B register" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x18 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x1C "QSPI1A_SS1_B,QSPI1A_SS1_B register" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x20 "QSPI1B_DATA0,QSPI1B_DATA0 register" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x20 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x24 "QSPI1B_DATA1,QSPI1B_DATA1 register" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x24 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x28 "QSPI1B_DATA2,QSPI1B_DATA2 register" bitfld.long 0x28 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x28 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x28 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x28 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x28 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x28 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x2C "QSPI1B_DATA3,QSPI1B_DATA3 register" bitfld.long 0x2C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x2C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x2C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x2C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x2C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x2C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x2C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x2C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x30 "QSPI1B_DQS,QSPI1B_DQS register" bitfld.long 0x30 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x30 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x30 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x30 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x30 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x30 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x30 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x30 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x34 "QSPI1B_SCLK,QSPI1B_SCLK register" bitfld.long 0x34 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x34 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x34 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x34 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x34 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x34 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x34 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x34 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x38 "QSPI1B_SS0_B,QSPI1A_SS0_B register" bitfld.long 0x38 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x38 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x38 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x38 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x38 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x38 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x38 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x38 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x3C "QSPI1B_SS1_B,QSPI1A_SS1_B register" bitfld.long 0x3C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x3C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x3C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x3C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x3C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x3C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x3C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x3C 0. " SRE ,Slew Rate Field" "Slow,Fast" tree.end width 15. tree "RGMIIx registers" group.long 0x508++0x5F line.long 0x0 "RGMII1_RD0,RGMII1_RD0 registers" bitfld.long 0x0 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x0 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x0 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x0 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x0 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x0 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x0 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x4 "RGMII1_RD1,RGMII1_RD1 registers" bitfld.long 0x4 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x4 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x4 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x4 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x4 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x4 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x4 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x4 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x8 "RGMII1_RD2,RGMII1_RD2 registers" bitfld.long 0x8 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x8 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x8 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x8 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x8 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x8 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x8 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x8 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0xC "RGMII1_RD3,RGMII1_RD3 registers" bitfld.long 0xC 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0xC 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0xC 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0xC 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0xC 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0xC 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0xC 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0xC 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x10 "RGMII1_RX_CTL,RGMII1_RX_CTL registers" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x10 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x14 "RGMII1_RXC,RGMII1_RXC registers" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x14 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x18 "RGMII1_RD0,RGMII1_TD0 registers" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x18 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x1C "RGMII1_RD1,RGMII1_TD1 registers" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x20 "RGMII1_RD2,RGMII1_TD2 registers" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x20 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x24 "RGMII1_RD3,RGMII1_TD3 registers" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x24 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x28 "RGMII1_TX_CTL,RGMII1_TX_CTL registers" bitfld.long 0x28 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x28 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x28 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x28 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x28 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x28 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x2C "RGMII1_TXC,RGMII1_TXC registers" bitfld.long 0x2C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x2C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x2C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x2C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x2C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x2C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x2C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x2C 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x30 "RGMII2_RD0,RGMII2_RD0 registers" bitfld.long 0x30 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x30 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x30 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x30 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x30 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x30 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x30 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x30 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x34 "RGMII2_RD1,RGMII2_RD1 registers" bitfld.long 0x34 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x34 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x34 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x34 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x34 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x34 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x34 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x34 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x38 "RGMII2_RD2,RGMII2_RD2 registers" bitfld.long 0x38 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x38 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x38 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x38 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x38 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x38 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x38 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x38 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x3C "RGMII2_RD3,RGMII2_RD3 registers" bitfld.long 0x3C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x3C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x3C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x3C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x3C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x3C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x3C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x3C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x40 "RGMII2_RX_CTL,RGMII2_RX_CTL registers" bitfld.long 0x40 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x40 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x40 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x40 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x40 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x40 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x40 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x40 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x44 "RGMII2_RXC,RGMII2_RXC registers" bitfld.long 0x44 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x44 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x44 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x44 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x44 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x44 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x44 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x44 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x48 "RGMII2_TD0,RGMII2_TD0 registers" bitfld.long 0x48 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x48 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x48 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x48 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x48 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x48 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x48 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x48 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x4C "RGMII2_TD1,RGMII2_TD1 registers" bitfld.long 0x4C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x4C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x4C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x4C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x4C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x4C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x4C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x4C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x50 "RGMII2_TD2,RGMII2_TD2 registers" bitfld.long 0x50 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x50 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x50 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x50 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x50 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x50 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x50 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x50 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x54 "RGMII2_TD3,RGMII2_TD3 registers" bitfld.long 0x54 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x54 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x54 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x54 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x54 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x54 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x54 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x54 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x58 "RGMII2_TX_CTL,RGMII2_TX_CTL registers" bitfld.long 0x58 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x58 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x58 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x58 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x58 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x58 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x58 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x58 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x5C "RGMII2_TXC,RGMII2_TXC registers" bitfld.long 0x5C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x5C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x5C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x5C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x5C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x5C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x5C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x5C 0. " SRE ,Slew Rate Field" "Slow,Fast" tree.end width 13. tree "SDx" group.long 0x568++0x83 line.long 0x00 "SD1_CLK,SD1_CLK registers" bitfld.long 0x00 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x00 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x00 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x00 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x00 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x04 "SD1_CMD,SD1_CMD registers" bitfld.long 0x04 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x04 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x04 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x04 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x04 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x8 "SD1_DATA0,SD1_DATA0 registers" bitfld.long 0x8 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x8 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x8 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x8 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x8 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x8 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x8 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x8 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0xC "SD1_DATA1,SD1_DATA1 registers" bitfld.long 0xC 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0xC 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0xC 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0xC 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0xC 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0xC 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0xC 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0xC 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x10 "SD1_DATA2,SD1_DATA2 registers" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x10 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x10 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x10 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x10 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x14 "SD1_DATA3,SD1_DATA3 registers" bitfld.long 0x14 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x14 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x14 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x14 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x14 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x18 "SD2_CLK,SD2_CLK registers" bitfld.long 0x18 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x18 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x18 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x18 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x1C "SD2_CMD,SD2_CMD registers" bitfld.long 0x1C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x1C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x1C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x20 "SD1_DATA0,SD1_DATA0 registers" bitfld.long 0x20 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x20 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x20 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x20 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x24 "SD1_DATA1,SD1_DATA1 registers" bitfld.long 0x24 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x24 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x24 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x24 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x24 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x28 "SD1_DATA2,SD1_DATA2 registers" bitfld.long 0x28 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x28 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x28 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x28 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x28 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x28 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x2C "SD1_DATA3,SD1_DATA3 registers" bitfld.long 0x2C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x2C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x2C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x2C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x2C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x2C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x2C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x2C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x30 "SD3_CLK,SD3_CLK registers" bitfld.long 0x30 22. " LVE ,Low Voltage Enable Field" "High,Low" bitfld.long 0x30 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x30 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x30 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x30 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x30 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x30 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x30 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x30 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x34 "SD3_CMD,SD3_CMD registers" bitfld.long 0x34 22. " LVE ,Low Voltage Enable Field" "High,Low" bitfld.long 0x34 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x34 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x34 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x34 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x34 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x34 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x34 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x34 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x38 "SD3_DATA0,SD3_DATA0 registers" bitfld.long 0x38 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x38 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x38 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x38 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x38 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x38 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x38 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x38 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x3C "SD3_DATA1,SD3_DATA1 registers" bitfld.long 0x3C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x3C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x3C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x3C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x3C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x3C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x3C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x3C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x40 "SD3_DATA2,SD3_DATA2 registers" bitfld.long 0x40 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x40 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x40 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x40 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x40 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x40 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x40 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x40 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x44 "SD3_DATA3,SD3_DATA3 registers" bitfld.long 0x44 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x44 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x44 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x44 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x44 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x44 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x44 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x44 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x48 "SD3_DATA4,SD3_DATA4 registers" bitfld.long 0x48 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x48 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x48 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x48 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x48 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x48 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x48 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x48 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x4C "SD3_DATA5,SD3_DATA5 registers" bitfld.long 0x4C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x4C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x4C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x4C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x4C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x4C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x4C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x4C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x50 "SD3_DATA6,SD3_DATA6 registers" bitfld.long 0x50 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x50 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x50 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x50 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x50 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x50 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x50 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x50 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x54 "SD3_DATA7,SD3_DATA7 registers" bitfld.long 0x54 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x54 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x54 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x54 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x54 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x54 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x54 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x54 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x58 "SD4_CLK,SD4_CLK registers" bitfld.long 0x58 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x58 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x58 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x58 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x58 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x58 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x58 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x58 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x5C "SD4_CMD,SD3_CMD registers" bitfld.long 0x5C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x5C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x5C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x5C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x5C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x5C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x5C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x5C 0. " SRE ,Slew Rate Field" "SLOW,FAST" line.long 0x60 "SD4_DATA0,SD4_DATA0 registers" bitfld.long 0x60 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x60 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x60 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x60 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x60 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x60 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x60 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x60 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x64 "SD4_DATA1,SD4_DATA1 registers" bitfld.long 0x64 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x64 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x64 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x64 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x64 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x64 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x64 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x64 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x68 "SD4_DATA2,SD4_DATA2 registers" bitfld.long 0x68 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x68 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x68 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x68 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x68 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x68 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x68 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x68 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x6C "SD4_DATA3,SD4_DATA3 registers" bitfld.long 0x6C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x6C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x6C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x6C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x6C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x6C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x6C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x6C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x70 "SD4_DATA4,SD4_DATA4 registers" bitfld.long 0x70 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x70 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x70 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x70 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x70 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x70 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x70 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x70 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x74 "SD4_DATA5,SD4_DATA5 registers" bitfld.long 0x74 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x74 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x74 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x74 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x74 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x74 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x74 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x74 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x78 "SD4_DATA6,SD4_DATA6 registers" bitfld.long 0x78 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x78 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x78 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x78 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x78 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x78 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x78 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x78 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x7C "SD4_DATA7,SD4_DATA7 registers" bitfld.long 0x7C 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x7C 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x7C 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x7C 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x7C 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x7C 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x7C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x7C 0. " SRE ,Slew Rate Field" "Slow,Fast" line.long 0x80 "SD4_RESET_B,SD4_RESET_B registers" bitfld.long 0x80 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x80 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x80 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x80 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x80 11. " ODE ,Open Drain Enable Field" "Disabled,Enabled" bitfld.long 0x80 6.--7. " SPEED ,Speed Field" "50MHZ,100MHZ,100MHZ,200MHZ" bitfld.long 0x80 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" bitfld.long 0x80 0. " SRE ,Slew Rate Field" "Slow,Fast" tree.end width 14. tree "USB_H" group.long 0x5EC++0x007 line.long 0x00 "USB_H_DATA,USB_H_DATA register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO Trim Field" "Min,50ps,100ps,150ps" bitfld.long 0x00 18.--19. " DDR_SEL ,DDR Select Field" ",,LPDDR2,DDR3" rbitfld.long 0x00 17. " DDR_INPUT ,DDR/CMOS Input Mode Field" "0,1" textline " " bitfld.long 0x00 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x00 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" bitfld.long 0x00 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--10. " ODT ,On Die Termination Field" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x04 "USB_H_STROBE,USB_H_STROBE register" bitfld.long 0x04 20.--21. " DO_TRIM ,DO Trim Field" "Min,50ps,100ps,150ps" bitfld.long 0x04 18.--19. " DDR_SEL ,DDR Select Field" ",,LPDDR2,DDR3" bitfld.long 0x04 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "0,1" bitfld.long 0x04 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" bitfld.long 0x04 14.--15. " PUS ,Pull Up / Down Configuration Field" "100K Pull Down,47K Pull Up,100K Pull Up,22K Pull Up" textline " " bitfld.long 0x04 13. " PUE ,Pull / Keep Select Field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled" bitfld.long 0x04 8.--10. " ODT ,On Die Termination Field" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x04 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" tree.end width 14. tree "GRP" group.long 0x5F4++0x02F line.long 0x00 "GRP_ADDDS,GRP_ADDDS register" bitfld.long 0x00 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x04 "DDRMODE_CTL,DDRMODE_CTL register" bitfld.long 0x04 17. " DDR_INPUT ,DDR/CMOS Input Mode Field" "CMOS,Differential" line.long 0x08 "GRP_DDRPKE,GRP_DDRPKE register" bitfld.long 0x08 12. " PKE ,Pull/Keep Enable Field" "Disabled,Enabled" line.long 0x0C "GRP_DDRPK,GRP_DDRPK register" bitfld.long 0x0C 13. " PUE ,Pull/Keep Enable Field" "Keep,Pull" line.long 0x10 "GRP_DDRHYS,GRP_DDRHYS register" bitfld.long 0x10 16. " HYS ,Hysteresis Enable Field" "CMOS,Schmitt" line.long 0x14 "GRP_DDRMODE,GRP_DDRMODE register" bitfld.long 0x14 17. " DDR_INPUT ,DDR/CMOS Input Mode Field" "CMOS,Differential" line.long 0x18 "GRP_B0DS,GRP_B0DS register" bitfld.long 0x18 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x1C "GRP_B1DS,GRP_B1DS register" bitfld.long 0x1C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x20 "GRP_CTLDS,GRP_CTLDS register" bitfld.long 0x20 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x24 "GRP_DDR_TYPE,GRP_DDR_TYPE register" bitfld.long 0x24 18.--19. " DDR_SEL ,DDR Select Field" ",,LPDDR2,DDR3" line.long 0x28 "GRP_B2DS,GRP_B2DS register" bitfld.long 0x28 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" line.long 0x2C "GRP_B3DS,GRP_B3DS register" bitfld.long 0x2C 3.--5. " DSE ,Drive Strength Field" "HIZ,260_OHM,130_OHM,87_OHM,65_OHM,52_OHM,43_OHM,37_OHM" tree.end width 21. tree "Anatop USB" group.long 0x624++0x07 line.long 0x00 "OTG_ID_SELECT_INPUT,OTG_ID_SELECT_INPUT register" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO10_ALT0,ENET2_COL_ALT6,QSPI1A_DATA1_ALT1," line.long 0x04 "UH1_ID_SELECT_INPUT,UH1_ID_SELECT_INPUT register" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO13_ALT1,ENET2_CRS_ALT6,QSPI1A_SCLK_ALT1," tree.end width 24. tree "AUDMUX" tree "P3 Input" group.long 0x62C++0x17 line.long 0x00 "DA_AMX_SELECT_INPUT,DA_AMX_SELECT_INPUT register" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA0_ALT3,LCD1_RESET_ALT2" line.long 0x04 "DB_AMX_SELECT_INPUT,DB_AMX_SELECT_INPUT register" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA3_ALT3,LCD1_HSYNC_ALT2" line.long 0x08 "RXCLK_AMX_SELECT_INPUT,RXCLK_AMX_SELECT_INPUT register" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "SD4_CMD_ALT3,LCD1_CLK_ALT2" line.long 0x0C "RXFS_AMX_SELECT_INPUT,RXFS_AMX_SELECT_INPUT register" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "SD4_CLK_ALT3,ENET1_MDC_ALT2" line.long 0x10 "TXCLK_AMX_SELECT_INPUT,TXCLK_AMX_SELECT_INPUT register" bitfld.long 0x10 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA1_ALT3,LCD1_ENABLE_ALT2" line.long 0x14 "TXFS_AMX_SELECT_INPUT,TXFS_AMX_SELECT_INPUT register" bitfld.long 0x14 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA2_ALT3,LCD1_VSYNC_ALT2" tree.end tree "P4 Input" group.long 0x644++0x17 line.long 0x00 "DA_AMX_SELECT_INPUT,DA_AMX_SELECT_INPUT register" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "NAND_WE_B_ALT3,ENET1_TX_CLK_ALT2" line.long 0x04 "DB_AMX_SELECT_INPUT,DB_AMX_SELECT_INPUT register" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "NAND_CE1_B_ALT3,ENET1_CRS_ALT2" line.long 0x08 "RXCLK_AMX_SELECT_INPUT,RXCLK_AMX_SELECT_INPUT register" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "NAND_DATA05_ALT4,ENET2_COL_ALT2" line.long 0x0C "RXFS_AMX_SELECT_INPUT,RXFS_AMX_SELECT_INPUT register" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "NAND_DATA04_ALT4,ENET2_CRS_ALT2" line.long 0x10 "TXCLK_AMX_SELECT_INPUT,TXCLK_AMX_SELECT_INPUT register" bitfld.long 0x10 0. " DAISY ,Input Select (DAISY) Field" "NAND_CE0_B_ALT3,ENET1_COL_ALT2" line.long 0x14 "TXFS_AMX_SELECT_INPUT,TXFS_AMX_SELECT_INPUT register" bitfld.long 0x14 0. " DAISY ,Input Select (DAISY) Field" "NAND_RE_B_ALT3,ENET1_RX_CLK_ALT2" tree.end tree "P5 Input" group.long 0x65C++0x17 line.long 0x00 "DA_AMX_SELECT_INPUT,DA_AMX_SELECT_INPUT register" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "KEY_ROW1_ALT4,SD1_DATA0_ALT1,SD1_DATA3_ALT2," line.long 0x04 "DB_AMX_SELECT_INPUT,DB_AMX_SELECT_INPUT register" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "KEY_ROW0_ALT4,SD1_DATA3_ALT1" line.long 0x08 "RXCLK_AMX_SELECT_INPUT,RXCLK_AMX_SELECT_INPUT register" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "KEY_COL4_ALT4,SD1_CMD_ALT1" line.long 0x0C "RXFS_AMX_SELECT_INPUT,RXFS_AMX_SELECT_INPUT register" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "KEY_ROW4_ALT4,SD1_CLK_ALT1" line.long 0x10 "TXCLK_AMX_SELECT_INPUT,TXCLK_AMX_SELECT_INPUT register" bitfld.long 0x10 0. " DAISY ,Input Select (DAISY) Field" "KEY_COL0_ALT4,SD1_DATA1_ALT1" line.long 0x14 "TXFS_AMX_SELECT_INPUT,TXFS_AMX_SELECT_INPUT register" bitfld.long 0x14 0. " DAISY ,Input Select (DAISY) Field" "KEY_COL1_ALT4,SD1_DATA2_ALT1" tree.end tree "P6 Input" group.long 0x674++0x17 line.long 0x00 "DA_AMX_SELECT_INPUT,DA_AMX_SELECT_INPUT register" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA0_ALT3,CSI_VSYNC_ALT2,SD2_DATA0_ALT1," line.long 0x04 "DB_AMX_SELECT_INPUT,DB_AMX_SELECT_INPUT register" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA3_ALT3,CSI_HSYNC_ALT2,SD2_DATA3_ALT1," line.long 0x08 "RXCLK_AMX_SELECT_INPUT,RXCLK_AMX_SELECT_INPUT register" bitfld.long 0x08 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_CMD_ALT3,CSI_DATA02_ALT2,SD2_CMD_ALT1," line.long 0x0C "RXFS_AMX_SELECT_INPUT,RXFS_AMX_SELECT_INPUT register" bitfld.long 0x0C 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_CLK_ALT3,CSI_DATA03_ALT2,SD2_CLK_ALT1," line.long 0x10 "TXCLK_AMX_SELECT_INPUT,TXCLK_AMX_SELECT_INPUT register" bitfld.long 0x10 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA1_ALT3,CSI_DATA00_ALT2,SD2_DATA1_ALT1," line.long 0x14 "TXFS_AMX_SELECT_INPUT,TXFS_AMX_SELECT_INPUT register" bitfld.long 0x14 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA2_ALT3,CSI_DATA01_ALT2,SD2_DATA2_ALT1," tree.end tree.end width 23. tree "CAN" group.long 0x68C++0x0F line.long 0x00 "CANRX1_SELECT_INPUT,IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA7_ALT1,KEY_ROW2_ALT3,QSPI1A_SS1_B_ALT1," line.long 0x04 "CANRX2_SELECT_INPUT,IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA4_ALT1,KEY_ROW3_ALT3,QSPI1B_SS1_B_ALT1," line.long 0x08 "CAN_0_RX_SELECT_INPUT,IOMUXC_CANFD_IPD_M_CAN_0_RX_SELECT_INPUT" bitfld.long 0x08 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA7_ALT2,KEY_ROW2_ALT4,QSPI1A_SS1_B_ALT2," line.long 0x0C "CAN_1_RX_SELECT_INPUT,IOMUXC_CANFD_IPD_M_CAN_1_RX_SELECT_INPUT" bitfld.long 0x0C 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA4_ALT2,KEY_ROW3_ALT4,QSPI1B_SS1_B_ALT2," tree.end width 19. tree "CCM" group.long 0x69C++0x03 line.long 0x00 "CCM_PMIC_VFUNCIONAL,IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "LCD1_RESET_ALT6,GPIO1_IO08_ALT3,SD1_DATA3_ALT7," tree.end width 20. tree "CSI1_IPP" tree "CSI_D" group.long 0x6A0++0x27 line.long 0x00 "SELECT_INPUT_0,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA17_ALT4,QSPI1A_SS0_B_ALT4" line.long 0x04 "SELECT_INPUT_1,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA16_ALT4,QSPI1A_SCLK_ALT4" line.long 0x08 "SELECT_INPUT_2,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA00_ALT0,LCD1_DATA15_ALT4" line.long 0x0C "SELECT_INPUT_3,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA01_ALT0,LCD1_DATA14_ALT4" line.long 0x10 "SELECT_INPUT_4,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4" bitfld.long 0x10 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA02_ALT0,LCD1_DATA13_ALT4" line.long 0x14 "SELECT_INPUT_5,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5" bitfld.long 0x14 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA03_ALT0,LCD1_DATA12_ALT4" line.long 0x18 "SELECT_INPUT_6,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6" bitfld.long 0x18 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA04_ALT0,LCD1_DATA11_ALT4" line.long 0x1C "SELECT_INPUT_7,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7" bitfld.long 0x1C 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA05_ALT0,LCD1_DATA10_ALT4" line.long 0x20 "SELECT_INPUT_8,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8" bitfld.long 0x20 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA06_ALT0,LCD1_DATA09_ALT4" line.long 0x24 "SELECT_INPUT_9,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9" bitfld.long 0x24 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA07_ALT0,LCD1_DATA08_ALT4" group.long 0x6CC++0x37 line.long 0x34 "SELECT_INPUT_10,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10" bitfld.long 0x34 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA23_ALT4,QSPI1A_SS1_B_ALT4" line.long 0x00 "SELECT_INPUT_11,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA22_ALT4,QSPI1A_DATA3_ALT4" line.long 0x04 "SELECT_INPUT_12,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA21_ALT4,QSPI1A_DATA2_ALT4" line.long 0x08 "SELECT_INPUT_13,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA20_ALT4,QSPI1A_DATA1_ALT4" line.long 0x0C "SELECT_INPUT_14,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA19_ALT4,QSPI1A_DATA0_ALT4" line.long 0x10 "SELECT_INPUT_15,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15" bitfld.long 0x10 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA18_ALT4,QSPI1A_DQS_ALT4" line.long 0x14 "SELECT_INPUT_16,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16" bitfld.long 0x14 0. " DAISY ,Input Select (DAISY) Field" "LCD1_CLK_ALT4,QSPI1B_SCLK_ALT4" line.long 0x18 "SELECT_INPUT_17,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17" bitfld.long 0x18 0. " DAISY ,Input Select (DAISY) Field" "LCD1_ENABLE_ALT4,QSPI1B_SS0_B_ALT4" line.long 0x1C "SELECT_INPUT_18,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18" bitfld.long 0x1C 0. " DAISY ,Input Select (DAISY) Field" "LCD1_HSYNC_ALT4,QSPI1B_SS1_B_ALT4" line.long 0x20 "SELECT_INPUT_19,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19" bitfld.long 0x20 0. " DAISY ,Input Select (DAISY) Field" "LCD1_VSYNC_ALT4,QSPI1B_DATA3_ALT4" line.long 0x24 "SELECT_INPUT_20,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20" bitfld.long 0x24 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA00_ALT4,QSPI1B_DATA2_ALT4" line.long 0x28 "SELECT_INPUT_21,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21" bitfld.long 0x28 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA01_ALT4,QSPI1B_DATA1_ALT4" line.long 0x2C "SELECT_INPUT_22,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22" bitfld.long 0x2C 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA02_ALT4,QSPI1B_DATA0_ALT4" line.long 0x30 "SELECT_INPUT_23,IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23" bitfld.long 0x30 0. " DAISY ,Input Select (DAISY) Field" "LCD1_DATA03_ALT4,QSPI1B_DQS_ALT4" tree.end group.long 0x700++0x0F line.long 0x00 "HSYNC_SELECT,IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "CSI_HSYNC_ALT0,LCD1_DATA05_ALT4" line.long 0x04 "PIXCLK_SELECT,IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "CSI_PIXCLK_ALT0,LCD1_DATA06_ALT4" line.long 0x08 "VSYNC_SELECT,IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "CSI_VSYNC_ALT0,LCD1_DATA04_ALT4" line.long 0x0C "TVDECODER_IN_FIELD,IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "CSI_MCLK_ALT7,GPIO1_IO10_ALT4" tree.end width 13. tree "ECSPIx_IPP" tree "ECSPI1" group.long 0x710++0x0F line.long 0x00 "CSPI_CLK_IN,IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "KEY_COL0_ALT3,QSPI1A_SCLK_ALT2" line.long 0x04 "IND_MISO,IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "KEY_COL1_ALT3,QSPI1A_DATA1_ALT2" line.long 0x08 "IND_MOSI,IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "KEY_ROW0_ALT3,QSPI1A_DATA0_ALT2" line.long 0x0C "IND_SS_B_0,IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "KEY_ROW1_ALT3,QSPI1A_SS0_B_ALT2" tree.end tree "ECSPI2" group.long 0x720++0x0F line.long 0x00 "CSPI_CLK_IN,IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "NAND_CLE_ALT3,SD4_DATA1_ALT2" line.long 0x04 "IND_MISO,IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "NAND_READY_B_ALT3,SD4_CLK_ALT2" line.long 0x08 "IND_MOSI,IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "NAND_WP_B_ALT3,SD4_CMD_ALT2" line.long 0x0C "IND_SS_B_0,IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "NAND_ALE_ALT3,SD4_DATA0_ALT2" tree.end tree "ECSPI3" group.long 0x730++0x0F line.long 0x00 "CSPI_CLK_IN,IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA4_ALT3,QSPI1B_SCLK_ALT2" line.long 0x04 "IND_MISO,IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA6_ALT3,QSPI1B_DATA1_ALT2" line.long 0x08 "IND_MOSI,IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA5_ALT3,QSPI1B_DATA0_ALT2" line.long 0x0C "IND_SS_B_0,IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA7_ALT3,QSPI1B_SS0_B_ALT2" tree.end tree "ECSPI4" group.long 0x740++0x0F line.long 0x00 "CSPI_CLK_IN,IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "SD3_CLK_ALT2,SD2_CLK_ALT3" line.long 0x04 "IND_MISO,IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "SD3_DATA3_ALT2,SD2_DATA3_ALT3" line.long 0x08 "IND_MOSI,IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "SD3_CMD_ALT2,SD2_CMD_ALT3" line.long 0x0C "IND_SS_B_0,IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "SD3_DATA2_ALT2,SD2_DATA2_ALT3" tree.end tree "ECSPI5" group.long 0x750++0x0F line.long 0x00 "CSPI_CLK_IN,IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "NAND_DATA02_ALT3,QSPI1B_SS1_B_ALT3" line.long 0x04 "IND_MISO,IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "NAND_DATA00_ALT3,QSPI1A_SS1_B_ALT3" line.long 0x08 "IND_MOSI,IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "NAND_DATA01_ALT3,QSPI1A_DQS_ALT3" line.long 0x0C "IND_SS_B_0,IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "NAND_DATA03_ALT3,QSPI1B_DQS_ALT3" tree.end tree.end width 19. tree "ENETx" tree "ENET1" group.long 0x760++0x0B line.long 0x00 "IPG_CLK_RMII,IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO05_ALT4,ENET1_TX_CLK_ALT1" line.long 0x04 "IPP_IND_MAC0_MDIO,IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO05_ALT2,ENET1_MDIO_ALT0,ENET2_CRS_ALT1," line.long 0x08 "IND_MAC0_RXCLK,IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "ENET1_RX_CLK_ALT0,RGMII1_RXC_ALT0" tree.end tree "ENET2" group.long 0x76C++0x0B line.long 0x00 "IPG_CLK_RMII,IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO04_ALT4,ENET2_TX_CLK_ALT1" line.long 0x04 "IPP_IND_MAC0_MDIO,IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO07_ALT2,ENET1_CRS_ALT1,ENET1_MDIO_ALT1,KEY_ROW4_ALT1" line.long 0x08 "IND_MAC0_RXCLK,IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "ENET2_RX_CLK_ALT0,RGMII2_RXC_ALT0" tree.end tree.end width 15. tree "ESAI_IPP" group.long 0x778++0x02B line.long 0x00 "IND_FSR,IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_DATA01_ALT4,CSI_DATA03_ALT1,QSPI1B_DATA0_ALT3," line.long 0x04 "IND_FST,IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_RE_B_ALT4,CSI_DATA01_ALT1,QSPI1B_DATA3_ALT3," line.long 0x08 "IND_HCKR,IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT" bitfld.long 0x08 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_DATA03_ALT4,CSI_PIXCLK_ALT1,QSPI1B_SCLK_ALT3," line.long 0x0C "IND_HCKT,IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT" bitfld.long 0x0C 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_DATA02_ALT4,CSI_MCLK_ALT1,CSI_PIXCLK_ALT7,QSPI1B_SS0_B_ALT3" line.long 0x10 "IND_SCKR,IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT" bitfld.long 0x10 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_DATA00_ALT4,CSI_DATA02_ALT1,QSPI1B_DATA1_ALT3," line.long 0x14 "IND_SCKT,IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT" bitfld.long 0x14 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_CE0_B_ALT4,CSI_DATA00_ALT1,QSPI1A_DATA2_ALT3," line.long 0x18 "IND_SDO0,IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT" bitfld.long 0x18 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_CE1_B_ALT4,CSI_HSYNC_ALT1,QSPI1A_DATA3_ALT3," line.long 0x1C "IND_SDO2_SDI3,IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT" bitfld.long 0x1C 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_CLE_ALT4,CSI_DATA06_ALT1,QSPI1A_SCLK_ALT3," line.long 0x20 "IND_SDO3_SDI2,IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT" bitfld.long 0x20 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_ALE_ALT4,CSI_DATA07_ALT1,QSPI1A_SS0_B_ALT3," line.long 0x24 "IND_SDO4_SDI1,IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT" bitfld.long 0x24 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_WP_B_ALT4,CSI_DATA05_ALT1,QSPI1A_DATA0_ALT3," line.long 0x28 "IND_SDO5_SDI0,IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT" bitfld.long 0x28 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_WE_B_ALT4,CSI_VSYNC_ALT1,QSPI1B_DATA2_ALT3," tree.end width 8. tree "I2Cx_IPP" tree "I2C_1" group.long 0x7A8++0x007 line.long 0x00 "SCL_IN,IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA00_ALT3,GPIO1_IO00_ALT0" line.long 0x04 "SDA_IN,IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA01_ALT3,GPIO1_IO01_ALT0" tree.end tree "I2C_2" group.long 0x7B0++0x007 line.long 0x00 "SCL_IN,IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "SD4_DATA3_ALT2,GPIO1_IO02_ALT0,QSPI1B_DATA3_ALT1," line.long 0x04 "SDA_IN,IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "SD4_DATA2_ALT2,GPIO1_IO03_ALT0,QSPI1B_DATA2_ALT1," tree.end tree "I2C_3" group.long 0x7B8++0x007 line.long 0x00 "SCL_IN,IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_CLE_ALT1,ENET2_RX_CLK_ALT2,KEY_COL4_ALT2," line.long 0x04 "SDA_IN,IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "NAND_ALE_ALT1,ENET2_TX_CLK_ALT2,KEY_ROW4_ALT2," tree.end tree "I2C_4" group.long 0x7C0++0x007 line.long 0x00 "SCL_IN,IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA0_ALT1,USB_H_STROBE_ALT3,CSI_DATA06_ALT2,SD2_DATA1_ALT4" line.long 0x04 "SDA_IN,IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_DATA1_ALT1,USB_H_DATA_ALT3,CSI_DATA07_ALT2,SD2_DATA0_ALT4" tree.end tree.end width 11. tree "KPP_IPP" group.long 0x7C8++0x17 line.long 0x00 "IND_COL_5,IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA02_ALT3,SD2_CLK_ALT2" line.long 0x04 "IND_COL_6,IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA04_ALT3,SD2_DATA3_ALT2" line.long 0x08 "IND_COL_7,IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA06_ALT3,SD2_DATA1_ALT2" line.long 0x0C "IND_ROW_5,IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA03_ALT3,SD2_CMD_ALT2" line.long 0x10 "IND_ROW_6,IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6" bitfld.long 0x10 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA05_ALT3,SD2_DATA2_ALT2" line.long 0x14 "IND_ROW_7,IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7" bitfld.long 0x14 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA07_ALT3,SD2_DATA0_ALT2" tree.end width 11. tree "LCD" group.long 0x7E0++0x07 line.long 0x00 "LCD1_BUSY,IOMUXC_LCD1_BUSY_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "LCD1_HSYNC_ALT0,LCD1_VSYNC_ALT1" line.long 0x04 "LCD2_BUSY,IOMUXC_LCD2_BUSY_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "SD3_CLK_ALT6,SD3_CMD_ALT4" tree.end width 13. tree "MLB" group.long 0x7E0++0x0B line.long 0x00 "MLB_CLK_IN,IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO12_ALT4,ENET2_TX_CLK_ALT4,SD2_CMD_ALT4," line.long 0x04 "MLB_DATA_IN,IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO11_ALT4,ENET2_RX_CLK_ALT4,SD2_DATA3_ALT4," line.long 0x08 "MLB_SIG_IN,IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT" bitfld.long 0x08 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO13_ALT4,ENET2_CRS_ALT4,SD2_CLK_ALT4," tree.end width 8. tree "SAIx_IPP_IND_SAI" tree "SAI_1" group.long 0x7F4++0x13 line.long 0x00 "RXBCLK,IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA02_ALT7,RGMII2_TD1_ALT2" line.long 0x04 "RXDATA,IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "CSI_VSYNC_ALT7,RGMII2_TX_CTL_ALT2" line.long 0x08 "RXSYNC,IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA03_ALT7,RGMII2_TD0_ALT2" line.long 0x0C "TXBCLK,IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA00_ALT7,RGMII2_TD3_ALT2" line.long 0x10 "TXSYNC,IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT" bitfld.long 0x10 0. " DAISY ,Input Select (DAISY) Field" "CSI_DATA01_ALT7,RGMII2_TD2_ALT2" tree.end tree "SAI_2" group.long 0x808++0x13 line.long 0x00 "RXBCLK,IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "KEY_COL4_ALT7,RGMII1_TD1_ALT2" line.long 0x04 "RXDATA,IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "KEY_ROW1_ALT7,RGMII1_TX_CTL_ALT2" line.long 0x08 "RXSYNC,IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT" bitfld.long 0x08 0. " DAISY ,Input Select (DAISY) Field" "KEY_ROW4_ALT7,RGMII2_TD0_ALT2" line.long 0x0C "TXBCLK,IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT)" bitfld.long 0x0C 0. " DAISY ,Input Select (DAISY) Field" "KEY_COL0_ALT7,RGMII1_TD3_ALT2" line.long 0x10 "TXSYNC,IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT)" bitfld.long 0x10 0. " DAISY ,Input Select (DAISY) Field" "KEY_COL1_ALT7,RGMII1_TD2_ALT2" tree.end tree.end width 10. tree "SPDIF" group.long 0x81C++0x07 line.long 0x00 "SEL_IN14,IOMUXC_SDMA_EVENTS_SELECT_INPUT_14" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO08_ALT2,KEY_ROW0_ALT6,SD2_DATA2_ALT4," line.long 0x04 "SEL_IN14,IOMUXC_SDMA_EVENTS_SELECT_INPUT_15" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO09_ALT2,COL0" tree.end width 11. tree "SPDIF" group.long 0x824++0x07 line.long 0x00 "SPDIF_IN1,IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT" bitfld.long 0x00 0.--2. " DAISY ,Input Select (DAISY) Field" "SD4_DATA5_ALT6,CSI_DATA05_ALT2,GPIO1_IO11_ALT1,ENET2_COL_ALT4,SD2_DATA3_ALT6,,," line.long 0x04 "TX_CLK2,IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO10_ALT1,ENET1_COL_ALT4" tree.end width 14. tree "UARTx_IPP" tree "UART_1" group.long 0x82C++0x07 line.long 0x00 "UART_RTS_B,IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO06_ALT4,GPIO1_IO07_ALT4,ENET2_RX_CLK_ALT3,ENET2_TX_CLK_ALT3" line.long 0x04 "UART_RXD_MUX,IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO04_ALT0,GPIO1_IO05_ALT0,ENET2_COL_ALT3,ENET2_CRS_ALT3" tree.end tree "UART_2" group.long 0x834++0x07 line.long 0x00 "UART_RTS_B,IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO08_ALT4,GPIO1_IO09_ALT4,SD1_DATA2_ALT4,SD1_DATA3_ALT4" line.long 0x04 "UART_RXD_MUX,IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO06_ALT0,GPIO1_IO07_ALT0,SD1_DATA0_ALT4,SD1_DATA1_ALT4" tree.end tree "UART_3" group.long 0x83C++0x07 line.long 0x00 "UART_RTS_B,IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT" bitfld.long 0x00 0.--2. " DAISY ,Input Select (DAISY) Field" "NAND_DATA04_ALT3,NAND_DATA05_ALT3,SD3_DATA6_ALT3,SD3_DATA7_ALT3,QSPI1B_DATA0_ALT1,QSPI1B_DATA1_ALT1,," line.long 0x04 "UART_RXD_MUX,IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT" bitfld.long 0x04 0.--2. " DAISY ,Input Select (DAISY) Field" "NAND_DATA06_ALT3,NAND_DATA07_ALT3,SD3_DATA4_ALT3,SD3_DATA5_ALT3,QSPI1B_SCLK_ALT1,QSPI1B_SS0_B_ALT1,," tree.end tree "UART_4" group.long 0x844++0x07 line.long 0x00 "UART_RTS_B,IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "SD3_CLK_ALT1,SD3_DATA2_ALT1,CSI_HSYNC_ALT3,CSI_VSYNC_ALT3" line.long 0x04 "UART_RXD_MUX,IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT" bitfld.long 0x04 0.--2. " DAISY ,Input Select (DAISY) Field" "SD3_CMD_ALT1,SD3_DATA3_ALT1,CSI_MCLK_ALT3,CSI_PIXCLK_ALT3,SD2_DATA0_ALT7,SD2_DATA1_ALT7,," tree.end tree "UART_5" group.long 0x84C++0x07 line.long 0x00 "UART_RTS_B,IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "SD4_DATA6_ALT2,SD4_DATA7_ALT2,KEY_COL2_ALT2,KEY_ROW2_ALT2" line.long 0x04 "UART_RXD_MUX,IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "SD4_DATA4_ALT2,SD4_DATA5_ALT2,KEY_COL3_ALT2,KEY_ROW3_ALT2" tree.end tree "UART_6" group.long 0x854++0x07 line.long 0x00 "UART_RTS_B,IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "CSI_DATA06_ALT4,CSI_DATA07_ALT4,KEY_COL0_ALT2,KEY_ROW0_ALT2" line.long 0x04 "UART_RXD_MUX,IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT" bitfld.long 0x04 0.--2. " DAISY ,Input Select (DAISY) Field" "CSI_DATA04_ALT4,CSI_DATA05_ALT4,KEY_COL1_ALT2,KEY_ROW1_ALT2,SD2_DATA2_ALT7,SD2_DATA3_ALT7,?..." tree.end tree.end width 9. tree "USB_IPP" group.long 0x85C++0x07 line.long 0x00 "OTG2_OC,IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT" bitfld.long 0x00 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO11_ALT0,ENET2_RX_CLK_ALT6,QSPI1A_DATA0_ALT1," line.long 0x04 "OTG_OC,IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT" bitfld.long 0x04 0.--1. " DAISY ,Input Select (DAISY) Field" "GPIO1_IO08_ALT0,ENET1_MDIO_ALT6,QSPI1A_DATA3_ALT1," tree.end width 10. tree "USDHCx_IPP" tree "USDHC_1" group.long 0x864++0x07 line.long 0x00 "CARD_DET,IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "LCD1_ENABLE_ALT6,GPIO1_IO02_ALT1" line.long 0x04 "WP_ON,IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "LCD1_CLK_ALT6,GPIO1_IO03_ALT1" tree.end tree "USDHC_2" group.long 0x86C++0x07 line.long 0x00 "CARD_DET,IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "LCD1_VSYNC_ALT6,GPIO1_IO06_ALT1" line.long 0x04 "WP_ON,IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "LCD1_HSYNC_ALT6,GPIO1_IO07_ALT1" tree.end tree "USDHC_4" group.long 0x86C++0x07 line.long 0x00 "CARD_DET,IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT" bitfld.long 0x00 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA7_ALT6,KEY_COL2_ALT1" line.long 0x04 "WP_ON,IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT" bitfld.long 0x04 0. " DAISY ,Input Select (DAISY) Field" "SD4_DATA6_ALT6,KEY_ROW2_ALT1" tree.end tree.end width 0xb tree.end tree.end tree "KPP (Keypad Port Registers)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020B8000 else base ad:0x420B8000 endif width 10. group.word 0x00++0x07 line.word 0x00 "KPP_KPCR,Keypad Control Register" bitfld.word 0x00 15. " KCO_7 ,Keypad column strobe Open-Drain enable 7" "Totem pole,Open drain" bitfld.word 0x00 14. " KCO_6 ,Keypad column strobe Open-Drain enable 6" "Totem pole,Open drain" bitfld.word 0x00 13. " KCO_5 ,Keypad column strobe Open-Drain enable 5" "Totem pole,Open drain" bitfld.word 0x00 12. " KCO_4 ,Keypad column strobe Open-Drain enable 4" "Totem pole,Open drain" textline " " bitfld.word 0x00 11. " KCO_3 ,Keypad column strobe Open-Drain enable 3" "Totem pole,Open drain" bitfld.word 0x00 10. " KCO_2 ,Keypad column strobe Open-Drain enable 2" "Totem pole,Open drain" bitfld.word 0x00 9. " KCO_1 ,Keypad column strobe Open-Drain enable 1" "Totem pole,Open drain" bitfld.word 0x00 8. " KCO_0 ,Keypad column strobe Open-Drain enable 0" "Totem pole,Open drain" textline " " bitfld.word 0x00 7. " KRE_7 ,Keypad row enable 7" "Not included,Included" bitfld.word 0x00 6. " KRE_6 ,Keypad row enable 6" "Not included,Included" bitfld.word 0x00 5. " KRE_5 ,Keypad row enable 5" "Not included,Included" bitfld.word 0x00 4. " KRE_4 ,Keypad row enable 4" "Not included,Included" textline " " bitfld.word 0x00 3. " KRE_3 ,Keypad row enable 3" "Not included,Included" bitfld.word 0x00 2. " KRE_2 ,Keypad row enable 2" "Not included,Included" bitfld.word 0x00 1. " KRE_1 ,Keypad row enable 1" "Not included,Included" bitfld.word 0x00 0. " KRE_0 ,Keypad row enable 0" "Not included,Included" line.word 0x02 "KPP_KPSR,Keypad Status Register" bitfld.word 0x02 9. " KRIE ,Keypad release interrupt enable" "No interrupt,Interrupted" bitfld.word 0x02 8. " KDIE ,Keypad key depress interrupt enable" "No interrupt,Interrupted" bitfld.word 0x02 3. " KRSS ,Key release synchronizer set" "No effect,Release" bitfld.word 0x02 2. " KDSC ,Key depress synchronizer clear" "No effect,Clear" textline " " eventfld.word 0x02 1. " KPKR ,Keypad key release" "Not released,Released" eventfld.word 0x02 0. " KPKD ,Keypad key depress" "Not pressed,Depressed" line.word 0x04 "KPP_KDDR,Keypad Data Direction Register" bitfld.word 0x04 15. " KCCD_7 ,Keypad column data direction register 7" "Input,Output" bitfld.word 0x04 14. " KCCD_6 ,Keypad column data direction register 6" "Input,Output" bitfld.word 0x04 13. " KCCD_5 ,Keypad column data direction register 5" "Input,Output" bitfld.word 0x04 12. " KCCD_4 ,Keypad column data direction register 4" "Input,Output" textline " " bitfld.word 0x04 11. " KCCD_3 ,Keypad column data direction register 3" "Input,Output" bitfld.word 0x04 10. " KCCD_2 ,Keypad column data direction register 2" "Input,Output" bitfld.word 0x04 9. " KCCD_1 ,Keypad column data direction register 1" "Input,Output" bitfld.word 0x04 8. " KCCD_0 ,Keypad column data direction register 0" "Input,Output" textline " " bitfld.word 0x04 7. " KRDD_7 ,Keypad row data direction 7" "Input,Output" bitfld.word 0x04 6. " KRDD_6 ,Keypad row data direction 6" "Input,Output" bitfld.word 0x04 5. " KRDD_5 ,Keypad row data direction 5" "Input,Output" bitfld.word 0x04 4. " KRDD_4 ,Keypad row data direction 4" "Input,Output" textline " " bitfld.word 0x04 3. " KRDD_3 ,Keypad row data direction 3" "Input,Output" bitfld.word 0x04 2. " KRDD_2 ,Keypad row data direction 2" "Input,Output" bitfld.word 0x04 1. " KRDD_1 ,Keypad row data direction 1" "Input,Output" bitfld.word 0x04 0. " KRDD_0 ,Keypad row data direction 0" "Input,Output" line.word 0x06 "KPP_KPDR,Keypad Data Register" bitfld.word 0x06 15. " KCD_7 ,Keypad column data 7" "0,1" bitfld.word 0x06 14. " KCD_6 ,Keypad column data 6" "0,1" bitfld.word 0x06 13. " KCD_5 ,Keypad column data 5" "0,1" bitfld.word 0x06 12. " KCD_4 ,Keypad column data 4" "0,1" textline " " bitfld.word 0x06 11. " KCD_3 ,Keypad column data 3" "0,1" bitfld.word 0x06 10. " KCD_2 ,Keypad column data 2" "0,1" bitfld.word 0x06 9. " KCD_1 ,Keypad column data 1" "0,1" bitfld.word 0x06 8. " KCD_0 ,Keypad column data 0" "0,1" textline " " bitfld.word 0x06 7. " KRD_7 ,Keypad row data 7" "0,1" bitfld.word 0x06 6. " KRD_6 ,Keypad row data 6" "0,1" bitfld.word 0x06 5. " KRD_5 ,Keypad row data 5" "0,1" bitfld.word 0x06 4. " KRD_4 ,Keypad row data 4" "0,1" textline " " bitfld.word 0x06 3. " KRD_3 ,Keypad row data 3" "0,1" bitfld.word 0x06 2. " KRD_2 ,Keypad row data 2" "0,1" bitfld.word 0x06 1. " KRD_1 ,Keypad row data 1" "0,1" bitfld.word 0x06 0. " KRD_0 ,Keypad row data 0" "0,1" width 0x0B tree.end tree "eLCDIF(Enhanced LCD Interface)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02220000 else base ad:0x42220000 endif width 18. tree "Control registers" group.long 0x00++0x2F line.long 0x00 "LCDIF1_CTRL,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the eLCDIF" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,YCbCr 422" textline " " bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,Mode" "0,1" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" textline " " bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command Mode polarity bit" "Command,Data" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big Endinan,Hafl-words,Bytes/Half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big Endian,Half-words,Bytes/Half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between eLCDIF and ePXP" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " MASTER ,eLCDIF mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" textline " " bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "All valid,Drop 2 bits" bitfld.long 0x00 0. " RUN ,Transferring data between the SoC and the display" "Not running,Running" line.long 0x04 "LCDIF1_CTRL_SET,eLCDIF General Control Register" bitfld.long 0x04 31. " SFTRST ,Operation of the eLCDIF" "Normal operation,Block level reset" bitfld.long 0x04 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x04 29. " YCBCR422_INPUT ,Color format" "RGB,YCbCr 422" textline " " bitfld.long 0x04 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x04 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x04 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x04 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20. " DVI_MODE ,Mode" "0,1" bitfld.long 0x04 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" textline " " bitfld.long 0x04 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x04 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x04 16. " DATA_SELECT ,Command Mode polarity bit" "Command,Data" textline " " bitfld.long 0x04 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big Endinan,Hafl-words,Bytes/Half-word" bitfld.long 0x04 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big Endian,Half-words,Bytes/Half-word" bitfld.long 0x04 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x04 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x04 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x04 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between eLCDIF and ePXP" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " MASTER ,eLCDIF mode" "PIO,Bus master" bitfld.long 0x04 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x04 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" textline " " bitfld.long 0x04 1. " DATA_FORMAT_24_BIT ,24bit data format" "All valid,Drop 2 bits" bitfld.long 0x04 0. " RUN ,Transferring data between the SoC and the display" "Not running,Running" line.long 0x08 "LCDIF1_CTRL_CLR,eLCDIF General Control Register" bitfld.long 0x08 31. " SFTRST ,Operation of the eLCDIF" "Normal operation,Block level reset" bitfld.long 0x08 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x08 29. " YCBCR422_INPUT ,Color format" "RGB,YCbCr 422" textline " " bitfld.long 0x08 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x08 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x08 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x08 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20. " DVI_MODE ,Mode" "0,1" bitfld.long 0x08 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" textline " " bitfld.long 0x08 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x08 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x08 16. " DATA_SELECT ,Command Mode polarity bit" "Command,Data" textline " " bitfld.long 0x08 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big Endinan,Hafl-words,Bytes/Half-word" bitfld.long 0x08 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big Endian,Half-words,Bytes/Half-word" bitfld.long 0x08 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x08 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x08 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x08 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between eLCDIF and ePXP" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " MASTER ,eLCDIF mode" "PIO,Bus master" bitfld.long 0x08 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x08 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" textline " " bitfld.long 0x08 1. " DATA_FORMAT_24_BIT ,24bit data format" "All valid,Drop 2 bits" bitfld.long 0x08 0. " RUN ,Transferring data between the SoC and the display" "Not running,Running" line.long 0x0C "LCDIF1_CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x0C 31. " SFTRST ,Operation of the eLCDIF" "Normal operation,Block level reset" bitfld.long 0x0C 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x0C 29. " YCBCR422_INPUT ,Color format" "RGB,YCbCr 422" textline " " bitfld.long 0x0C 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x0C 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "0,1" bitfld.long 0x0C 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x0C 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 20. " DVI_MODE ,Mode" "0,1" bitfld.long 0x0C 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" textline " " bitfld.long 0x0C 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x0C 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x0C 16. " DATA_SELECT ,Command Mode polarity bit" "Command,Data" textline " " bitfld.long 0x0C 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big Endinan,Hafl-words,Bytes/Half-word" bitfld.long 0x0C 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big Endian,Half-words,Bytes/Half-word" bitfld.long 0x0C 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16 bit,8 bit,18 bit,24 bit" textline " " bitfld.long 0x0C 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x0C 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x0C 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between eLCDIF and ePXP" "Disabled,Enabled" textline " " bitfld.long 0x0C 5. " MASTER ,eLCDIF mode" "PIO,Bus master" bitfld.long 0x0C 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x0C 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" textline " " bitfld.long 0x0C 1. " DATA_FORMAT_24_BIT ,24bit data format" "All valid,Drop 2 bits" bitfld.long 0x0C 0. " RUN ,Transferring data between the SoC and the display" "Not running,Running" line.long 0x10 "LCDIF1_CTRL1,eLCDIF General Control1 Register" bitfld.long 0x10 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWn/LCD_RD_E,LCD_WR_RWn" bitfld.long 0x10 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" bitfld.long 0x10 25. " BM_ERROR_IRQ ,Interrupt request by the eLCDIF block" "Not requested,Requested" textline " " bitfld.long 0x10 24. " RECOVER_ON_UNDERFLOW ,eLCDIF block recovery in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x10 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by eLCDIF block" "Not required,Required" bitfld.long 0x10 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" textline " " bitfld.long 0x10 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x10 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x10 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" textline " " bitfld.long 0x10 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x10 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x10 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" textline " " bitfld.long 0x10 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x10 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x10 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" textline " " bitfld.long 0x10 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x10 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x10 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the eLCDIF block when" "Not requested,Requested" textline " " bitfld.long 0x10 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the eLCDIF block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x10 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the eLCDIF block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x10 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x10 0. " RESET ,Reset bit for the external LCD controller" "LCDRESET_LOW,LCDRESET_HIGH" line.long 0x14 "LCDIF1_CTRL1_SET,eLCDIF General Control1 Register" bitfld.long 0x14 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWn/LCD_RD_E,LCD_WR_RWn" bitfld.long 0x14 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" bitfld.long 0x14 25. " BM_ERROR_IRQ ,Interrupt request by the eLCDIF block" "Not requested,Requested" textline " " bitfld.long 0x14 24. " RECOVER_ON_UNDERFLOW ,eLCDIF block recovery in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x14 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by eLCDIF block" "Not required,Required" bitfld.long 0x14 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" textline " " bitfld.long 0x14 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x14 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x14 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" textline " " bitfld.long 0x14 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x14 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x14 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" textline " " bitfld.long 0x14 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x14 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x14 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" textline " " bitfld.long 0x14 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x14 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x14 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the eLCDIF block when" "Not requested,Requested" textline " " bitfld.long 0x14 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the eLCDIF block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x14 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the eLCDIF block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x14 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x14 0. " RESET ,Reset bit for the external LCD controller" "LCDRESET_LOW,LCDRESET_HIGH" line.long 0x18 "LCDIF1_CTRL1_CLR,eLCDIF General Control1 Register" bitfld.long 0x18 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWn/LCD_RD_E,LCD_WR_RWn" bitfld.long 0x18 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" bitfld.long 0x18 25. " BM_ERROR_IRQ ,Interrupt request by the eLCDIF block" "Not requested,Requested" textline " " bitfld.long 0x18 24. " RECOVER_ON_UNDERFLOW ,eLCDIF block recovery in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x18 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by eLCDIF block" "Not required,Required" bitfld.long 0x18 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" textline " " bitfld.long 0x18 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x18 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x18 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" textline " " bitfld.long 0x18 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x18 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x18 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" textline " " bitfld.long 0x18 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x18 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x18 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" textline " " bitfld.long 0x18 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x18 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x18 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the eLCDIF block when" "Not requested,Requested" textline " " bitfld.long 0x18 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the eLCDIF block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x18 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the eLCDIF block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x18 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x18 0. " RESET ,Reset bit for the external LCD controller" "LCDRESET_LOW,LCDRESET_HIGH" line.long 0x1C "LCDIF1_CTRL1_TOG,eLCDIF General Control1 Register" bitfld.long 0x1C 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWn/LCD_RD_E,LCD_WR_RWn" bitfld.long 0x1C 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" bitfld.long 0x1C 25. " BM_ERROR_IRQ ,Interrupt request by the eLCDIF block" "Not requested,Requested" textline " " bitfld.long 0x1C 24. " RECOVER_ON_UNDERFLOW ,eLCDIF block recovery in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x1C 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by eLCDIF block" "Not required,Required" bitfld.long 0x1C 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" textline " " bitfld.long 0x1C 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x1C 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x1C 19. " BYTE_PACKING_FORMAT_3 ,Bitfield is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" textline " " bitfld.long 0x1C 18. " BYTE_PACKING_FORMAT_2 ,Bitfield is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x1C 17. " BYTE_PACKING_FORMAT_1 ,Bitfield is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x1C 16. " BYTE_PACKING_FORMAT_0 ,Bitfield is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" textline " " bitfld.long 0x1C 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x1C 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x1C 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" textline " " bitfld.long 0x1C 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x1C 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x1C 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the eLCDIF block when" "Not requested,Requested" textline " " bitfld.long 0x1C 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the eLCDIF block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x1C 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the eLCDIF block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x1C 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x1C 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x1C 0. " RESET ,Reset bit for the external LCD controller" "LCDRESET_LOW,LCDRESET_HIGH" textline " " line.long 0x20 "LCDIF1_CTRL2,eLCDIF General Control2 Register" bitfld.long 0x20 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,,," bitfld.long 0x20 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x20 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,," textline " " bitfld.long 0x20 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,," bitfld.long 0x20 10. " READ_PACK_DIR ,Direction of reading data bits" "Little Endian,Big Endian" bitfld.long 0x20 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data conversion to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" textline " " bitfld.long 0x20 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x20 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,,," bitfld.long 0x20 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x24 "LCDIF1_CTRL2_SET,eLCDIF General Control2 Register" bitfld.long 0x24 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,,," bitfld.long 0x24 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x24 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,," textline " " bitfld.long 0x24 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,," bitfld.long 0x24 10. " READ_PACK_DIR ,Direction of reading data bits" "Little Endian,Big Endian" bitfld.long 0x24 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data conversion to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" textline " " bitfld.long 0x24 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x24 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,,," bitfld.long 0x24 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x28 "LCDIF1_CTRL2_CLR,eLCDIF General Control2 Register" bitfld.long 0x28 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,,," bitfld.long 0x28 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x28 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,," textline " " bitfld.long 0x28 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,," bitfld.long 0x28 10. " READ_PACK_DIR ,Direction of reading data bits" "Little Endian,Big Endian" bitfld.long 0x28 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data conversion to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" textline " " bitfld.long 0x28 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x28 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,,," bitfld.long 0x28 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x2C "LCDIF1_CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x2C 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,,," bitfld.long 0x2C 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x2C 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,," textline " " bitfld.long 0x2C 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,," bitfld.long 0x2C 10. " READ_PACK_DIR ,Direction of reading data bits" "Little Endian,Big Endian" bitfld.long 0x2C 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data conversion to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" textline " " bitfld.long 0x2C 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x2C 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,,," bitfld.long 0x2C 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" tree.end textline "" width 23. group.long 0x030++0x03 line.long 0x00 "LCDIF1_TRANSFER_COUNT,eLCDIF Horizontal and Vertical Valid Data Count Register" hexmask.long.word 0x00 16.--31. 1. " V_COUNT ,Number of horizontal lines per frame which contain valid data" hexmask.long.word 0x00 0.--15. 1. " H_COUNT ,Total valid data (pixels) in each horizontal line" group.long 0x040++0x03 line.long 0x00 "LCDIF1_CUR_BUF,LCD Interface Current Buffer Address Register" group.long 0x050++0x03 line.long 0x00 "LCDIF1_NEXT_BUF,LCD Interface Next Buffer Address Register" group.long 0x060++0x03 line.long 0x00 "LCDIF1_TIMING,LCD Interface Timing Register" hexmask.long.byte 0x00 24.--31. 1. " CMD_HOLD ,Number of CLK_DIS_LCDIFn cycles that the DCn signal is active after CEn is deasserted" hexmask.long.byte 0x00 16.--23. 1. " CMD_SETUP ,Number of CLK_DIS_LCDIFn cycles that the DCn signal is active before CEn is asserted" hexmask.long.byte 0x00 8.--15. 1. " DATA_HOLD ,Data bus hold time in CLK_DIS_LCDIFn cycles" hexmask.long.byte 0x00 0.--7. 1. " DATA_SETUP ,Data bus setup time in CLK_DIS_LCDIFn cycles" tree "VDCTRL" width 20. group.long 0x070++0x00F line.long 0x00 "LCDIF1_VDCTRL0,eLCDIF VSYNC Mode and Dotclk Mode Control Register0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "0,1" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" textline " " bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity [launched/caputerd]" "Negative/Positive,Positive/Negitve" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "0,1" bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" textline " " bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x04 "LCDIF1_VDCTRL0_SET,eLCDIF VSYNC Mode and Dotclk Mode Control Register0" bitfld.long 0x04 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x04 28. " ENABLE_PRESENT ,Enable present" "0,1" bitfld.long 0x04 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x04 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" textline " " bitfld.long 0x04 25. " DOTCLK_POL ,DOTCLK polarity [launched/caputerd]" "Negative/Positive,Positive/Negitve" bitfld.long 0x04 24. " ENABLE_POL ,Enable polarity" "0,1" bitfld.long 0x04 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x04 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" textline " " bitfld.long 0x04 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x04 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x04 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x08 "LCDIF1_VDCTRL0_CLR,eLCDIF VSYNC Mode and Dotclk Mode Control Register0" bitfld.long 0x08 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x08 28. " ENABLE_PRESENT ,Enable present" "0,1" bitfld.long 0x08 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x08 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" textline " " bitfld.long 0x08 25. " DOTCLK_POL ,DOTCLK polarity [launched/caputerd]" "Negative/Positive,Positive/Negitve" bitfld.long 0x08 24. " ENABLE_POL ,Enable polarity" "0,1" bitfld.long 0x08 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x08 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" textline " " bitfld.long 0x08 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x08 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x08 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x0C "LCDIF1_VDCTRL0_TOG,eLCDIF VSYNC Mode and Dotclk Mode Control Register0" bitfld.long 0x0C 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x0C 28. " ENABLE_PRESENT ,Enable present" "0,1" bitfld.long 0x0C 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x0C 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" textline " " bitfld.long 0x0C 25. " DOTCLK_POL ,DOTCLK polarity [launched/caputerd]" "Negative/Positive,Positive/Negitve" bitfld.long 0x0C 24. " ENABLE_POL ,Enable polarity" "0,1" bitfld.long 0x0C 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x0C 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" textline " " bitfld.long 0x0C 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" bitfld.long 0x0C 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x0C 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" group.long 0x80++0x03 line.long 0x00 "LCDIF1_VDCTRL1,eLCDIF VSYNC Mode and Dotclk Mode Control Register1" group.long 0x90++0x03 line.long 0x00 "LCDIF1_VDCTRL2,eLCDIF VSYNC Mode and Dotclk Mode Control Register2" hexmask.long.word 0x00 18.--31. 1. " HSYNC_PULSE_WIDTH ,Number of CLK_DIS_LCDIFn cycles for which HSYNC signal is active" hexmask.long.tbyte 0x00 0.--17. 1. " HSYNC_PERIOD ,Total number of CLK_DIS_LCDIFn cycles between two positive or two negative edges of the HSYNC signal" group.long 0xA0++0x03 line.long 0x00 "LCDIF1_VDCTRL3,eLCDIF VSYNC Mode and Dotclk Mode Control Register3" bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Internally multiplexed signals" "Separated,Multiplexed" bitfld.long 0x00 28. " VSYNC_ONLY ,Mode of operation" "DOTCLK,VSYNC" hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,Wait for this number of clocks from edge" hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Wait for this number of CLK_DIS_LCDIFn cycles from the VSYNC edge before starting LCD transactions" group.long 0xB0++0x03 line.long 0x00 "LCDIF1_VDCTRL4,eLCDIF VSYNC Mode and Dotclk Mode Control Register4" bitfld.long 0x00 29.--31. " DOTCLK_DLY_SEL ,Amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin" "2ns,4ns,6ns,8ns,,,," bitfld.long 0x00 18. " SYNC_SIGNALS_ON ,VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end" "0,1" hexmask.long.tbyte 0x00 0.--17. 1. " DOTCLK_H_VALID_DATA_CNT ,Total number of CLK_DIS_LCDIFn cycles on each horizontal line that carry valid data in DOTCLK mode" tree.end width 17. tree "DVICTRLx registers" group.long 0xC0++0x03 line.long 0x00 "LCDIF1_DVICTRL0,Digital Video Interface Control 0 Register" hexmask.long.word 0x00 16.--27. 1. " H_ACTIVE_CNT ,Number of active video samples to be transmitted" hexmask.long.word 0x00 0.--11. 1. " H_BLANKING_CNT ,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval" group.long 0xD0++0x03 line.long 0x00 "LCDIF1_DVICTRL1,Digital Video Interface Control 1 Register" hexmask.long.word 0x00 20.--29. 1. " F1_START_LINE ,Vertical line number from which Field 1 begins" hexmask.long.word 0x00 10.--19. 1. " F1_END_LINE ,Vertical line number at which Field 1 ends" hexmask.long.word 0x00 0.--9. 1. " F2_START_LINE ,Vertical line number from which Field 2 begins" group.long 0xE0++0x03 line.long 0x00 "LCDIF1_DVICTRL2,Digital Video Interface Control 2 Register" hexmask.long.word 0x00 20.--29. 1. " F2_END_LINE ,Vertical line number at which Field 2 ends" hexmask.long.word 0x00 10.--19. 1. " V1_BLANK_START_LINE ,Vertical line number towards the end of Field1 where first Vertical Blanking interval starts" hexmask.long.word 0x00 0.--9. 1. " V1_BLANK_END_LINE ,Vertical line number in the beginning part of Field2 where first Vertical Blanking interval ends" group.long 0xF0++0x03 line.long 0x00 "LCDIF1_DVICTRL3,Digital Video Interface Control 3 Register" hexmask.long.word 0x00 20.--29. 1. " V2_BLANK_START_LINE ,Vertical line number towards the end of Field2 where second Vertical Blanking interval starts" hexmask.long.word 0x00 10.--19. 1. " V2_BLANK_END_LINE ,Vertical line number in the beginning part of Field1 where second Vertical Blanking interval ends" hexmask.long.word 0x00 0.--9. 1. " V_LINES_CNT ,Total number of vertical lines per frame" group.long 0x100++0x03 line.long 0x00 "LCDIF1_DVICTRL4,Digital Video Interface Control 4 Register" hexmask.long.byte 0x00 24.--31. 1. " Y_FILL_VALUE ,Value of Y component of filler data" hexmask.long.byte 0x00 16.--23. 1. " CB_FILL_VALUE ,Value of CB component of filler data" hexmask.long.byte 0x00 8.--15. 1. " CR_FILL_VALUE ,Value of CR component of filler data" hexmask.long.byte 0x00 0.--7. 1. " H_FILL_CNT ,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval" tree.end width 19. tree "COEFFx registers" group.long 0x110++0x03 line.long 0x00 "LCDIF1_CSC_COEFF0,RGB to YCbCr 4:2:2 CSC Coefficient0 Register" hexmask.long.word 0x00 16.--25. 1. " C0 ,Two's complement red multiplier coefficient for Y" bitfld.long 0x00 0.--1. " CSC_SUBSAMPLE_FILTER ,Filtering and subsampling scheme to be performed on the chroma components in order to convert from YCbCr 4:4:4 to YCbCr 4:2:2 space" "Sample/Hold,,INTERSTITIAL,COSITED" group.long 0x120++0x03 line.long 0x00 "LCDIF1_CSC_COEFF1,RGB to YCbCr 4:2:2 CSC Coefficient1 Register" hexmask.long.word 0x00 16.--25. 1. " C2 ,Two's complement blue multiplier coefficient for Y" hexmask.long.word 0x00 0.--9. 1. " C1 ,Two's complement green multiplier coefficient for Y" group.long 0x130++0x03 line.long 0x00 "LCDIF1_CSC_COEFF2,RGB to YCbCr 4:2:2 CSC Coefficient2 Register" hexmask.long.word 0x00 16.--25. 1. " C4 ,Two's complement green multiplier coefficient for Cb" hexmask.long.word 0x00 0.--9. 1. " C3 ,Two's complement red multiplier coefficient for Cb" group.long 0x140++0x03 line.long 0x00 "LCDIF1_CSC_COEFF3,RGB to YCbCr 4:2:2 CSC Coefficient3 Register" hexmask.long.word 0x00 16.--25. 1. " C6 ,Two's complement red multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C5 ,Two's complement blue multiplier coefficient for Cb" group.long 0x150++0x03 line.long 0x00 "LCDIF1_CSC_COEFF4,RGB to YCbCr 4:2:2 CSC Coefficient4 Register" hexmask.long.word 0x00 16.--25. 1. " C8 ,Two's complement blue multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C7 ,Two's complement green multiplier coefficient for Cr" tree.end textline "" width 22. group.long 0x160++0x03 line.long 0x00 "LCDIF1_CSC_OFFSET,RGB to YCbCr 4:2:2 CSC Offset Register" hexmask.long.word 0x00 16.--24. 1. " CBCR_OFFSET ,Two's complement offset for the Cb and Cr components" hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two's complement offset for the Y component" group.long 0x170++0x03 line.long 0x00 "LCDIF1_CSC_LIMIT,RGB to YCbCr 4:2:2 CSC Limit Register" hexmask.long.byte 0x00 24.--31. 1. " CBCR_MIN ,Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 16.--23. 1. " CBCR_MAX ,Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 8.--15. 1. " Y_MIN ,Lower limit of Y after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 0.--7. 1. " Y_MAX ,Upper limit of Y after RGB to 4:2:2 YCbCr conversion" group.long 0x180++0x03 line.long 0x00 "LCDIF1_DATA,LCD Interface Data Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_THREE ,Byte 3 (most significant byte) of data written to LCDIF" hexmask.long.byte 0x00 16.--23. 1. " DATA_TWO ,Byte 2 of data written to eLCDIF" hexmask.long.byte 0x00 8.--15. 1. " DATA_ONE ,Byte 1 of data written to eLCDIF" hexmask.long.byte 0x00 0.--7. 1. " DATA_ZERO ,Byte 0 (least significant byte) of data written to eLCDIF" group.long 0x190++0x03 line.long 0x00 "LCDIFx_BM_ERROR_STAT,Bus Master Error Status Register" group.long 0x1A0++0x03 line.long 0x00 "LCDIFx_CRC_STAT,CRC Status Register" rgroup.long 0x1B0++0x03 line.long 0x00 "LCDIFx_STAT,LCD Interface Status Register" bitfld.long 0x00 31. " PRESENT ,eLCDIF presence" "Not present,Present" bitfld.long 0x00 29. " LFIFO_FULL ,Indicates that LCD read datapath FIFO is full" "Not full,Full" bitfld.long 0x00 28. " LFIFO_EMPTY ,Indicates that LCD read datapath FIFO is empty" "Not empty,Empty" bitfld.long 0x00 27. " TXFIFO_FULL ,Indicates that LCD write datapath FIFO is full" "Not full,Full" textline " " bitfld.long 0x00 26. " TXFIFO_EMPTY ,Indicates that LCD write datapath FIFO is empty" "Not empty,Empty" bitfld.long 0x00 25. " BUSY ,View of the input busy signal from the external LCD controller" "Not busy,Busy" bitfld.long 0x00 24. " DVI_CURRENT_FIELD ,View of the current field being transmitted" "Field 1,Field 2" hexmask.long.word 0x00 0.--8. 1. " LFIFO_COUNT ,Current count in Latency buffer" rgroup.long 0x1C0++0x03 line.long 0x00 "LCDIFx_VERSION,LCD Interface Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,MINOR field of RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Stepping of RTL version" width 15. tree "Debug registers" rgroup.long 0x1D0++0x03 line.long 0x00 "LCDIFx_DEBUG0,LCD Interface Debug0 Register" bitfld.long 0x00 31. " STREAMING_END_DETECTED ,DOTCLK_MODE or DVI_MODE bit going from 1 to 0" "0,1" bitfld.long 0x00 30. " WAIT_FOR_VSYNC_EDGE_OUT ,WAIT_FOR_VSYNC_EDGE bit in the VSYNC mode after it comes out of the TXFIFO" "0,1" bitfld.long 0x00 29. " SYNC_SIGNALS_ON_REG ,Read only view of internal sync_signals_on_reg signal" "0,1" bitfld.long 0x00 27. " ENABLE ,Read only view of ENABLE signal" "0,1" textline " " bitfld.long 0x00 26. " HSYNC ,Read only view of HSYNC signal" "0,1" bitfld.long 0x00 25. " VSYNC ,Read only view of VSYNC signal" "0,1" bitfld.long 0x00 24. " CUR_FRAME_TX ,Indicates that the current frame is being transmitted in the VSYNC mode" "0,1" bitfld.long 0x00 23. " EMPTY_WORD ,Indicates that the current word is empty" "0,1" textline " " hexmask.long.byte 0x00 16.--22. 1. " CUR_STATE ,View of the current state machine state in the current mode of operation" bitfld.long 0x00 15. " PXP_LCDIF_B0_READY ,Buffer0 ready signal issued by ePXP" "0,1" bitfld.long 0x00 14. " PXP_B0_DONE ,Buffer0 done signal issued by eLCDIF" "0,1" bitfld.long 0x00 13. " PXP_LCDIF_B1_READY ,Buffer1 ready signal issued by ePXP" "0,1" bitfld.long 0x00 12. " PXP_B1_DONE ,Buffer1 done signal issued by eLCDIF" "0,1" textline " " bitfld.long 0x00 10.--11. " CUR_REQ_STATE ,Read only view of the request state machine" "0,1,2,3" bitfld.long 0x00 9. " MST_AVALID ,MST_AVALID signal issued by the AXI bus master" "0,1" bitfld.long 0x00 4.--8. " MST_OUTSTANDING_REQS ,Current outstanding requests issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " MST_WORDS ,Current bursts issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1E0++0x03 line.long 0x00 "LCDIFx_DEBUG1,LCD Interface Debug1 Register" hexmask.long.word 0x00 16.--31. 1. " H_DATA_COUNT ,Horizontal data counter" hexmask.long.word 0x00 0.--15. 1. " V_DATA_COUNT ,Vertical data counter" rgroup.long 0x1F0++0x03 line.long 0x00 "LCDIFx_DEBUG2,LCD Interface Debug2 Register" rgroup.long 0x270++0x03 line.long 0x00 "LCDIFx_DEBUG3,eLCDIF Interface Debug3 Register" bitfld.long 0x00 10.--11. " CUR_REQ_STATE ,Request state machine" "0,1,2,3" bitfld.long 0x00 9. " MST_AVALID ,MST_AVALID signal issued by the AXI bus master" "0,1" bitfld.long 0x00 4.--8. " MST_OUTSTANDING_REQS ,Current outstanding requests issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " MST_WORDS ,Current bursts issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x280++0x03 line.long 0x00 "LCDIFx_DEBUG4,eLCDIF Interface Debug4 Register" hexmask.long.word 0x00 16.--31. 1. " H_DATA_COUNT ,Current AS state of the horizontal data counter" hexmask.long.word 0x00 0.--15. 1. " V_DATA_COUNT ,Current AS state of the vertical data counter" rgroup.long 0x290++0x03 line.long 0x00 "LCDIFx_DEBUG5,eLCDIF Interface Debug5 Register" tree.end width 22. tree "AS registers" group.long 0x200++0x03 line.long 0x00 "LCDIF1_THRES,eLCDIF Threshold Register" hexmask.long.word 0x00 16.--24. 1. " FASTCLOCK ,This value should be set to a value of pixels from 0 to 511" hexmask.long.word 0x00 0.--8. 1. " PANIC ,Panic level" group.long 0x210++0x03 line.long 0x00 "LCDIF1_AS_CTRL,eLCDIF AS Buffer Control Register" bitfld.long 0x00 31. " CSI_VSYNC_ENABLE ,LCDIF work as sync mode with CSI input" "Disabled,Enabled" bitfld.long 0x00 30. " CSI_VSYNC_POL ,CSI VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 29. " CSI_VSYNC_MODE ,Vsync generate mode" "Internal,External" bitfld.long 0x00 28. " CSI_SYNC_ON_IRQ_EN ,Interrupt when LCDIF lock with CSI vsync input" "Enabled,Disabled" textline " " bitfld.long 0x00 27. " CSI_SYNC_ON_IRQ ,Vsync generate mode" "Internal,External" bitfld.long 0x00 23. " PS_DISABLE ,LCDIF will disable PS buffer data" "No,Yes" bitfld.long 0x00 21.--22. " INPUT_DATA_SWIZZLE ,How to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF" "No swap,Big Endinan,Hafl-words,Bytes/Half-word" bitfld.long 0x00 20. " ALPHA_INVERT ,Alpha value inversion" "Unaffected,Inverted" textline " " bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "MASKAS,MASKNOTAS,MASKASNOT,MERGEAS,MERGENOTAS,MERGEASNOT,NOTCOPYAS,NOT,NOTMASKAS,NOTMERGEAS,XORAS,NOTXORAS,,,," hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL" bitfld.long 0x00 4.--7. " FORMAT ,Indicates the input buffer format for AS" "ARGB8888,,,,RGB888,,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565," bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality for alpha surface" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CTRL ,Alpha value construction" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " AS_ENABLE ,Fetching AS buffer data in bus master mode and combine it with another buffer" "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "LCDIF1_AS_BUF,Alpha Surface Buffer Pointer" group.long 0x230++0x03 line.long 0x00 "LCDIF1_AS_NEXT_BUF,LCDIF1_AS_NEXT_BUF" group.long 0x240++0x03 line.long 0x00 "LCDIF1_AS_CLRKEYLOW,eLCDIF Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x250++0x03 line.long 0x00 "LCDIF1_AS_CLRKEYHIGH,eLCDIF Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x260++0x03 line.long 0x00 "LCDIF1_AS_CLRKEYHIGH,eLCDIF Overlay Color Key High" hexmask.long.word 0x00 16.--31. 1. " V_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" hexmask.long.word 0x00 0.--15. 1. " H_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" tree.end width 0x0b tree.end tree "LDB (LVDS Display Bridge register)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020E4018 else base ad:0x420E0014 endif width 10. group.long 0x00++0x03 line.long 0x00 "LDB_CTRL,LDB Control Register" bitfld.long 0x00 20.--21. " COUNTER_RESET_VAL ,Reset value for the LDB counter which determines when the shift registers are loaded with data" "5,3,4,6" bitfld.long 0x00 16.--18. " LVDS_CLK_SHIFT ,Shifts the LVDS output clock in relation to the data" "1100011,1110001,1111000,1000111,0001111,0011111,0111100,1100011" bitfld.long 0x00 9. " LCDIF1_VS_POLARITY ,Vsync polarity for lcdif1 interface" "High,Low" textline " " bitfld.long 0x00 6. " BIT_MAPPING_CH0 ,Data mapping for LVDS channel 0" "SPWG,JEIDA" bitfld.long 0x00 5. " DATA_WIDTH_CH0 ,Data width for LVDS channel 0" "18 bits,24 bits" bitfld.long 0x00 0.--1. " CH0_MODE ,LVDS channel 0 operation mode" "Disabled,LCDIF1,Disabled,LCDIF2" width 0x0b tree.end ; Module not descripted in newest reference manual! tree "M_CAN (Modular CAN registers)" tree "M_CAN_1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020E8000 else base ad:0x420E8000 endif width 10. rgroup.long 0x00++0x07 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " YEAR ,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " MON ,Time Stamp Month" hexmask.long.byte 0x00 0.--7. 1. " DAY ,Time Stamp Day" line.long 0x04 "ENDN,Endian Register" group.long 0x0C++0x23 line.long 0x00 "FBTP,Fast Bit Timing and Prescaler Register" bitfld.long 0x00 24.--28. " TDCO ,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " TDC ,Transceiver Delay Compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " FBRP ,Fast Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " FTSEG1 ,Fast time segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--6. " FTSEG2 ,Fast time segment after sample point" ",1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " FSJW ,Fast (Re) Synchronization Jump Width" "0,1,2,3" line.long 0x04 "TEST,Test Register" hexmask.long.byte 0x04 8.--13. 1. " TDCV ,Transceiver Delay Compensation Value" rbitfld.long 0x04 7. " RX ,Receive Pin" "Dominant,Recessive" bitfld.long 0x04 5.--6. " TX ,Control of Transmit Pin" "M_CAN,Sample Point,Dominant,Recessive" bitfld.long 0x04 4. " LBCK ,Loopback mode" "Disabled,Enabled" line.long 0x08 "RWD,RAM Watchdog Register" hexmask.long.byte 0x08 8.--15. 1. " WDV ,Actual Message RAM Watchdog Counter Value" hexmask.long.byte 0x08 0.--7. 1. " WDC ,Start value of the Message RAM Watchdog Counter" line.long 0x0C "CCCR,CC Control Register" bitfld.long 0x0C 14. " TXP ,Transmit Pause" "Disabled,Enabled" rbitfld.long 0x0C 13. " FDBS ,CAN FD Bit Rate Switching" "No frames,All frames" rbitfld.long 0x0C 12. " FDO ,CAN FD Operation" "ISO11898-1,CAN FD" bitfld.long 0x0C 10.--11. " CMR ,CAN Mode Request" "Unchanged,CAN FD,CAN FD bitrate,ISO11898-1" textline " " bitfld.long 0x0C 8.--9. " CME ,CAN Mode Enable" "ISO11898-1,CAN FD,CAN FD bitrate,CAN FD bitrate" bitfld.long 0x0C 7. " TEST ,Test Mode Enable" "Disabled,Enabled" bitfld.long 0x0C 6. " DAR ,Disable Automatic Retransmission" "No,Yes" bitfld.long 0x0C 5. " MON ,Bus Monitoring Mode" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " CSR ,Clock Stop Request" "No request,Requested" bitfld.long 0x0C 3. " CSA ,Clock Stop Acknowledge" "No Acknowledge,Acknowledge" bitfld.long 0x0C 2. " ASM ,Restricted Operation Mode" "Disabled,Enabled" bitfld.long 0x0C 1. " CCE ,Configuration Change Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " INIT ,Initialization" "Normal operation,Initialization" line.long 0x10 "BTP,Bit Timing and Prescaler Register" hexmask.long.word 0x10 16.--25. 0x02 " BRP ,Baud Rate Prescaler" hexmask.long.byte 0x10 8.--13. 1. " TSEG1 ,Time segment before sample point" bitfld.long 0x10 4.--7. " TSEG2 ,Time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " SJW ,Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x14 16.--19. " TCP ,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--1. " TSS ,Timestamp Select" "Always 0,Increment (TCP),External,Always 0" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. " TSC ,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. " TOP ,Timeout Period" bitfld.long 0x1C 1.--2. " TOS ,Timeout Select" "Continuous,Tx Event FIFO,Rx FIFO 0,Rx FIFO 1" bitfld.long 0x1C 0. " ETOC ,Enable Timeout Counter" "Disabled,Enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. " TOC ,Timeout Counter" rgroup.long 0x40++0x07 line.long 0x00 "ECR,Error Counter Register" hexmask.long.byte 0x00 16.--23. 1. " CEL ,CAN Error Logging" bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached" hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter" line.long 0x04 "PSR,Protocol Status Register" bitfld.long 0x04 13. " REDL ,Received a CAN FD Message" "Not received,Received" bitfld.long 0x04 12. " RBRS ,BRS flag of last received CAN FD Message" "Not set,Set" bitfld.long 0x04 11. " RESI ,ESI flag of last received CAN FD Message" "Not set,Set" bitfld.long 0x04 8.--10. " FLEC ,Fast Last Error Code" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 7. " BO ,Bus_Off Status" "Not Bus_Off,Bus_Off" bitfld.long 0x04 6. " EW ,Warning Status" "Below level,Level reached" bitfld.long 0x04 5. " EP ,Error Passive" "Error_Active,Error_Passive" bitfld.long 0x04 3.--4. " ACT ,Activity" "Synchronizing,Idle,Receiver,Transmitter" textline " " bitfld.long 0x04 0.--2. " LEC ,Last Error Code" "Error,Stuff,Form,Ack,Bit1,Bit0,CRC,NoChange" group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 31. " STE ,Stuff Error" "Not occurred,Occurred" eventfld.long 0x00 30. " FOE ,Format Error" "Not occurred,Occurred" eventfld.long 0x00 29. " ACKE ,Acknowledge Error" "Not occurred,Occurred" eventfld.long 0x00 28. " BE ,Bit Error" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " CRCE ,CRC Error" "Not occurred,Occurred" eventfld.long 0x00 26. " WDI ,Watchdog Interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " BO ,Bus_Off Status" "Not changed,Changed" eventfld.long 0x00 24. " EW ,Warning Status" "Not changed,Changed" textline " " eventfld.long 0x00 23. " EP ,Error passive" "Not changed,Changed" eventfld.long 0x00 22. " ELO ,Error Logging Overflow" "Not occurred,Occurred" eventfld.long 0x00 21. " BEU ,Bit Error Uncorrected" "Not detected,Detected" eventfld.long 0x00 20. " BEC ,Bit Error Corrected" "Not detected,Detected" textline " " eventfld.long 0x00 19. " DRX ,Message stored to Dedicated Rx Buffer" "Not stored,Stored" eventfld.long 0x00 18. " TOO ,Timeout" "Not occurred,Occurred" eventfld.long 0x00 17. " MRAF ,Message RAM Access Failure" "Not occurred,Occurred" eventfld.long 0x00 16. " TSW ,Timestamp Wraparound" "Not wrapped,Wrapped" textline " " eventfld.long 0x00 15. " TEFL ,Tx Event FIFO Element Lost" "Not lost,Lost" eventfld.long 0x00 14. " TEFF ,Tx Event FIFO Full" "Not full,Full" eventfld.long 0x00 13. " TEFW ,Tx Event FIFO Watermark Reached" "Below,Reached" eventfld.long 0x00 12. " TEFN ,Tx Event FIFO New Entry" "Unchanged,Written" textline " " eventfld.long 0x00 11. " TFE ,Tx FIFO Empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission Cancellation Finished" "Not finished,Finished" eventfld.long 0x00 9. " TC ,Transmission Completed" "Not completed,Completed" eventfld.long 0x00 8. " HPM ,High Priority Message" "Not received,Received" textline " " eventfld.long 0x00 7. " RF1L ,Rx FIFO 1 Message Lost" "Not lost,Lost" eventfld.long 0x00 6. " RF1F ,Rx FIFO 1 Full" "Not full,Full" eventfld.long 0x00 5. " RF1W ,Rx FIFO 1 Watermark Reached" "Below,Reached" eventfld.long 0x00 4. " RF1N ,Rx FIFO 1 New Message" "Not written,Written" textline " " eventfld.long 0x00 3. " RF0L ,Rx FIFO 0 Message Lost" "Not lost,Lost" eventfld.long 0x00 2. " RF0F ,Rx FIFO 0 Full" "Not full,Full" eventfld.long 0x00 1. " RF0W ,Rx FIFO 0 Watermark Reached" "Below,Reached" eventfld.long 0x00 0. " RF0N ,Rx FIFO 0 New Message" "Not written,Written" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 31. " STEE ,Stuff Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 30. " FOEE ,Format Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 29. " ACKEE ,Acknowledge Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 28. " BEE ,Bit Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " CRCEE ,CRC Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 26. " WDIE ,Watchdog Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning Status Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " EPE ,Error Passive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error Logging Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit Error Uncorrected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 20. " BECE ,Bit Error Corrected Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " DRXE ,Message stored to Dedicated Rx Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout Occurred Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 17. " MRAFE ,Message RAM Access Failure Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp Wraparound Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TEFLE ,Tx Event FIFO Element Lost Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 14. " TEFFE ,Tx Event FIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,Tx Event FIFO Watermark Reached Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,Tx Event FIFO New Entry Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " TFEE ,Tx FIFO Empty Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission Cancellation Finished Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission Completed Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 8. " HPME ,High Priority Message Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " RF1LE ,Rx FIFO 1 Message Lost Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,Rx FIFO 1 Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " RF1WE ,Rx FIFO 1 Watermark Reached Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,Rx FIFO 1 New Message Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " RF0LE ,Rx FIFO 0 Message Lost Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " RF0FE ,Rx FIFO 0 Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,Rx FIFO 0 Watermark Reached Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,Rx FIFO 0 New Message Interrupt Enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 31. " STEL ,Stuff Error Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 30. " FOEL ,Format Error Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 29. " ACKEL ,Acknowledge Error Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 28. " BEL ,Bit Error Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 27. " CRCEL ,CRC Error Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 26. " WDIL ,Watchdog Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 25. " BOL ,Bus_Off Status Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 24. " EWL ,Warning Status Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 23. " EPL ,Error Passive Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 22. " ELOL ,Error Logging Overflow Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 21. " BEUL ,Bit Error Uncorrected Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 20. " BECL ,Bit Error Corrected Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 19. " DRXL ,Message stored to Dedicated Rx Buffer Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 18. " TOOL ,Timeout Occurred Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 17. " MRAFL ,Message RAM Access Failure Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 16. " TSWL ,Timestamp Wraparound Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 15. " TEFLL ,Tx Event FIFO Element Lost Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 14. " TEFFL ,Tx Event FIFO Full Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 13. " TEFWL ,Tx Event FIFO Watermark Reached Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 12. " TEFNL ,Tx Event FIFO New Entry Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 11. " TFEL ,Tx FIFO Empty Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 10. " TCFL ,Transmission Cancellation Finished Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 9. " TCL ,Transmission Completed Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 8. " HPML ,High Priority Message Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 7. " RF1LL ,Rx FIFO 1 Message Lost Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 6. " RF1FL ,Rx FIFO 1 Full Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 5. " RF1WL ,Rx FIFO 1 Watermark Reached Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 4. " RF1NL ,Rx FIFO 1 New Message Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 3. " RF0LL ,Rx FIFO 0 Message Lost Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 2. " RF0FL ,Rx FIFO 0 Full Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 1. " RF0WL ,Rx FIFO 0 Watermark Reached Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 0. " RF0NL ,Rx FIFO 0 New Message Interrupt Line" "Line 0,Line 1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable Interrupt Line 0" "Disabled,Enabled" group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept Non-matching Frames Standard" "Rx FIFO 0,Rx FIFO 1,Rejected,Rejected" bitfld.long 0x00 2.--3. " ANFE ,Accept Non-matching Frames Extended" "Rx FIFO 0,Rx FIFO 1,Rejected,Rejected" bitfld.long 0x00 1. " RRFS ,Reject Remote Frames Standard" "Filtered,Rejected" bitfld.long 0x00 0. " RRFE ,Reject Remote Frames Extended" "Filtered,Rejected" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List Size Standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter List Standard Start Address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List Size Extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter List Extended Start Address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID and Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID Mask" rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter List" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter Index" bitfld.long 0x00 6.--7. " MSI ,Message Storage Indicator" "No FIFO,Message lost,FIFO 0,FIFO 1" hexmask.long.byte 0x00 0.--5. 1. " BIDX ,Buffer Index" group.long 0x98++0x0B line.long 0x00 "NDAT1,New Data 1 Register" bitfld.long 0x00 31. " ND[31] ,New Data Rx Buffer 31" "Not updated,Updated" bitfld.long 0x00 30. " ND[30] ,New Data Rx Buffer 30" "Not updated,Updated" bitfld.long 0x00 29. " ND[29] ,New Data Rx Buffer 29" "Not updated,Updated" bitfld.long 0x00 28. " ND[28] ,New Data Rx Buffer 28" "Not updated,Updated" textline " " bitfld.long 0x00 27. " ND[27] ,New Data Rx Buffer 27" "Not updated,Updated" bitfld.long 0x00 26. " ND[26] ,New Data Rx Buffer 26" "Not updated,Updated" bitfld.long 0x00 25. " ND[25] ,New Data Rx Buffer 25" "Not updated,Updated" bitfld.long 0x00 24. " ND[24] ,New Data Rx Buffer 24" "Not updated,Updated" textline " " bitfld.long 0x00 23. " ND[23] ,New Data Rx Buffer 23" "Not updated,Updated" bitfld.long 0x00 22. " ND[22] ,New Data Rx Buffer 22" "Not updated,Updated" bitfld.long 0x00 21. " ND[21] ,New Data Rx Buffer 21" "Not updated,Updated" bitfld.long 0x00 20. " ND[20] ,New Data Rx Buffer 20" "Not updated,Updated" textline " " bitfld.long 0x00 19. " ND[19] ,New Data Rx Buffer 19" "Not updated,Updated" bitfld.long 0x00 18. " ND[18] ,New Data Rx Buffer 18" "Not updated,Updated" bitfld.long 0x00 17. " ND[17] ,New Data Rx Buffer 17" "Not updated,Updated" bitfld.long 0x00 16. " ND[16] ,New Data Rx Buffer 16" "Not updated,Updated" textline " " bitfld.long 0x00 15. " ND[15] ,New Data Rx Buffer 15" "Not updated,Updated" bitfld.long 0x00 14. " ND[14] ,New Data Rx Buffer 14" "Not updated,Updated" bitfld.long 0x00 13. " ND[13] ,New Data Rx Buffer 13" "Not updated,Updated" bitfld.long 0x00 12. " ND[12] ,New Data Rx Buffer 12" "Not updated,Updated" textline " " bitfld.long 0x00 11. " ND[11] ,New Data Rx Buffer 11" "Not updated,Updated" bitfld.long 0x00 10. " ND[10] ,New Data Rx Buffer 10" "Not updated,Updated" bitfld.long 0x00 9. " ND[9] ,New Data Rx Buffer 9" "Not updated,Updated" bitfld.long 0x00 8. " ND[8] ,New Data Rx Buffer 8" "Not updated,Updated" textline " " bitfld.long 0x00 7. " ND[7] ,New Data Rx Buffer 7" "Not updated,Updated" bitfld.long 0x00 6. " ND[6] ,New Data Rx Buffer 6" "Not updated,Updated" bitfld.long 0x00 5. " ND[5] ,New Data Rx Buffer 5" "Not updated,Updated" bitfld.long 0x00 4. " ND[4] ,New Data Rx Buffer 4" "Not updated,Updated" textline " " bitfld.long 0x00 3. " ND[3] ,New Data Rx Buffer 3" "Not updated,Updated" bitfld.long 0x00 2. " ND[2] ,New Data Rx Buffer 2" "Not updated,Updated" bitfld.long 0x00 1. " ND[1] ,New Data Rx Buffer 1" "Not updated,Updated" bitfld.long 0x00 0. " ND[0] ,New Data Rx Buffer 0" "Not updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" bitfld.long 0x04 31. " ND[63] ,New Data Rx Buffer 63" "Not updated,Updated" bitfld.long 0x04 30. " ND[62] ,New Data Rx Buffer 62" "Not updated,Updated" bitfld.long 0x04 29. " ND[61] ,New Data Rx Buffer 61" "Not updated,Updated" bitfld.long 0x04 28. " ND[60] ,New Data Rx Buffer 60" "Not updated,Updated" textline " " bitfld.long 0x04 27. " ND[59] ,New Data Rx Buffer 59" "Not updated,Updated" bitfld.long 0x04 26. " ND[58] ,New Data Rx Buffer 58" "Not updated,Updated" bitfld.long 0x04 25. " ND[57] ,New Data Rx Buffer 57" "Not updated,Updated" bitfld.long 0x04 24. " ND[56] ,New Data Rx Buffer 56" "Not updated,Updated" textline " " bitfld.long 0x04 23. " ND[55] ,New Data Rx Buffer 55" "Not updated,Updated" bitfld.long 0x04 22. " ND[54] ,New Data Rx Buffer 54" "Not updated,Updated" bitfld.long 0x04 21. " ND[53] ,New Data Rx Buffer 53" "Not updated,Updated" bitfld.long 0x04 20. " ND[52] ,New Data Rx Buffer 52" "Not updated,Updated" textline " " bitfld.long 0x04 19. " ND[51] ,New Data Rx Buffer 51" "Not updated,Updated" bitfld.long 0x04 18. " ND[50] ,New Data Rx Buffer 50" "Not updated,Updated" bitfld.long 0x04 17. " ND[49] ,New Data Rx Buffer 49" "Not updated,Updated" bitfld.long 0x04 16. " ND[48] ,New Data Rx Buffer 48" "Not updated,Updated" textline " " bitfld.long 0x04 15. " ND[47] ,New Data Rx Buffer 47" "Not updated,Updated" bitfld.long 0x04 14. " ND[46] ,New Data Rx Buffer 46" "Not updated,Updated" bitfld.long 0x04 13. " ND[45] ,New Data Rx Buffer 45" "Not updated,Updated" bitfld.long 0x04 12. " ND[44] ,New Data Rx Buffer 44" "Not updated,Updated" textline " " bitfld.long 0x04 11. " ND[43] ,New Data Rx Buffer 43" "Not updated,Updated" bitfld.long 0x04 10. " ND[42] ,New Data Rx Buffer 42" "Not updated,Updated" bitfld.long 0x04 9. " ND[41] ,New Data Rx Buffer 41" "Not updated,Updated" bitfld.long 0x04 8. " ND[40] ,New Data Rx Buffer 40" "Not updated,Updated" textline " " bitfld.long 0x04 7. " ND[39] ,New Data Rx Buffer 39" "Not updated,Updated" bitfld.long 0x04 6. " ND[38] ,New Data Rx Buffer 38" "Not updated,Updated" bitfld.long 0x04 5. " ND[37] ,New Data Rx Buffer 37" "Not updated,Updated" bitfld.long 0x04 4. " ND[36] ,New Data Rx Buffer 36" "Not updated,Updated" textline " " bitfld.long 0x04 3. " ND[35] ,New Data Rx Buffer 35" "Not updated,Updated" bitfld.long 0x04 2. " ND[34] ,New Data Rx Buffer 34" "Not updated,Updated" bitfld.long 0x04 1. " ND[33] ,New Data Rx Buffer 33" "Not updated,Updated" bitfld.long 0x04 0. " ND[32] ,New Data Rx Buffer 32" "Not updated,Updated" line.long 0x08 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x08 31. " F0OM ,FIFO 0 Operation Mode" "Blocking,Overwrite" hexmask.long.byte 0x08 24.--30. 1. " F0WM ,Rx FIFO 0 Watermark" hexmask.long.byte 0x08 16.--21. 1. " F0S ,Rx FIFO 0 Size" hexmask.long.word 0x08 2.--15. 0x04 " F0SA ,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,Rx FIFO 0 Message Lost" "Not lost,Lost" bitfld.long 0x00 24. " F0F ,Rx FIFO 0 Full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 8.--13. " F0GI ,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,Rx FIFO 0 Fill Level" group.long 0xA8++0x0B line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x04 2.--15. 0x04 " RBSA ,Rx Buffer Start Address" line.long 0x08 "RXF1C,Rx FIFO 1 Configuration Register" rbitfld.long 0x08 31. " F1OM ,FIFO 1 Operation Mode" "Blocking,Overwrite" hexmask.long.byte 0x08 24.--30. 1. " F1WM ,Rx FIFO 1 Watermark" hexmask.long.byte 0x08 16.--22. 1. " F1S ,Rx FIFO 1 Size" hexmask.long.word 0x08 2.--15. 0x04 " F1SA ,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug Message Status" "Idle,A received,A/B received,A/B/C received" bitfld.long 0x00 25. " RF1L ,Rx FIFO 1 Message Lost" "Not lost,Lost" bitfld.long 0x00 24. " F1F ,Rx FIFO 1 Full" "Not full,Full" bitfld.long 0x00 16.--21. " F1PI ,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 8.--13. " F1GI ,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,Rx FIFO 1 Fill Level" group.long 0xB8++0x0B line.long 0x00 "RXF1A,Rx FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "RXESC,Rx Buffer / FIFO Element Size Configuration Register" bitfld.long 0x04 8.--10. " RBDS ,Rx Buffer Data Field Size" "8 byte,12 byte,16 byte,20 byte,24 byte,32 byte,48 byte,64 byte" bitfld.long 0x04 4.--6. " F1DS ,Rx FIFO 1 Data Field Size" "8 byte,12 byte,16 byte,20 byte,24 byte,32 byte,48 byte,64 byte" bitfld.long 0x04 0.--2. " F0DS ,Rx FIFO 0 Data Field Size" "8 byte,12 byte,16 byte,20 byte,24 byte,32 byte,48 byte,64 byte" line.long 0x08 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x08 30. " TFQM ,Rx FIFO 0 Data Field Size" "FIFO,Queue" bitfld.long 0x08 24.--29. " TFQS ,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x08 16.--21. " NDTB ,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x08 2.--15. 0x04 " TBSA ,Tx Buffers Start Address" rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,Tx FIFO/Queue Full" "Not full,Full" bitfld.long 0x00 16.--20. " TFQPI ,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,Tx FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TFFl ,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x0C8++0x03 line.long 0x00 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x00 0.--2. " TBDS ,Tx Buffer Data Field Size" "8 byte,12 byte,16 byte,20 byte,24 byte,32 byte,48 byte,64 byte" rgroup.long 0x0CC++0x03 line.long 0x00 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission Request Pending Tx Buffer 31" "Not pending,Pending" bitfld.long 0x00 30. " TRP[30] ,Transmission Request Pending Tx Buffer 30" "Not pending,Pending" bitfld.long 0x00 29. " TRP[29] ,Transmission Request Pending Tx Buffer 29" "Not pending,Pending" bitfld.long 0x00 28. " TRP[28] ,Transmission Request Pending Tx Buffer 28" "Not pending,Pending" textline " " bitfld.long 0x00 27. " TRP[27] ,Transmission Request Pending Tx Buffer 27" "Not pending,Pending" bitfld.long 0x00 26. " TRP[26] ,Transmission Request Pending Tx Buffer 26" "Not pending,Pending" bitfld.long 0x00 25. " TRP[25] ,Transmission Request Pending Tx Buffer 25" "Not pending,Pending" bitfld.long 0x00 24. " TRP[24] ,Transmission Request Pending Tx Buffer 24" "Not pending,Pending" textline " " bitfld.long 0x00 23. " TRP[23] ,Transmission Request Pending Tx Buffer 23" "Not pending,Pending" bitfld.long 0x00 22. " TRP[22] ,Transmission Request Pending Tx Buffer 22" "Not pending,Pending" bitfld.long 0x00 21. " TRP[21] ,Transmission Request Pending Tx Buffer 21" "Not pending,Pending" bitfld.long 0x00 20. " TRP[20] ,Transmission Request Pending Tx Buffer 20" "Not pending,Pending" textline " " bitfld.long 0x00 19. " TRP[19] ,Transmission Request Pending Tx Buffer 19" "Not pending,Pending" bitfld.long 0x00 18. " TRP[18] ,Transmission Request Pending Tx Buffer 18" "Not pending,Pending" bitfld.long 0x00 17. " TRP[17] ,Transmission Request Pending Tx Buffer 17" "Not pending,Pending" bitfld.long 0x00 16. " TRP[16] ,Transmission Request Pending Tx Buffer 16" "Not pending,Pending" textline " " bitfld.long 0x00 15. " TRP[15] ,Transmission Request Pending Tx Buffer 15" "Not pending,Pending" bitfld.long 0x00 14. " TRP[14] ,Transmission Request Pending Tx Buffer 14" "Not pending,Pending" bitfld.long 0x00 13. " TRP[13] ,Transmission Request Pending Tx Buffer 13" "Not pending,Pending" bitfld.long 0x00 12. " TRP[12] ,Transmission Request Pending Tx Buffer 12" "Not pending,Pending" textline " " bitfld.long 0x00 11. " TRP[11] ,Transmission Request Pending Tx Buffer 11" "Not pending,Pending" bitfld.long 0x00 10. " TRP[10] ,Transmission Request Pending Tx Buffer 10" "Not pending,Pending" bitfld.long 0x00 9. " TRP[9] ,Transmission Request Pending Tx Buffer 9" "Not pending,Pending" bitfld.long 0x00 8. " TRP[8] ,Transmission Request Pending Tx Buffer 8" "Not pending,Pending" textline " " bitfld.long 0x00 7. " TRP[7] ,Transmission Request Pending Tx Buffer 7" "Not pending,Pending" bitfld.long 0x00 6. " TRP[6] ,Transmission Request Pending Tx Buffer 6" "Not pending,Pending" bitfld.long 0x00 5. " TRP[5] ,Transmission Request Pending Tx Buffer 5" "Not pending,Pending" bitfld.long 0x00 4. " TRP[4] ,Transmission Request Pending Tx Buffer 4" "Not pending,Pending" textline " " bitfld.long 0x00 3. " TRP[3] ,Transmission Request Pending Tx Buffer 3" "Not pending,Pending" bitfld.long 0x00 2. " TRP[2] ,Transmission Request Pending Tx Buffer 2" "Not pending,Pending" bitfld.long 0x00 1. " TRP[1] ,Transmission Request Pending Tx Buffer 1" "Not pending,Pending" bitfld.long 0x00 0. " TRP[0] ,Transmission Request Pending Tx Buffer 0" "Not pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request Tx Buffer 31" "Not requested,Requested" bitfld.long 0x00 30. " AR[30] ,Add request Tx Buffer 30" "Not requested,Requested" bitfld.long 0x00 29. " AR[29] ,Add request Tx Buffer 29" "Not requested,Requested" bitfld.long 0x00 28. " AR[28] ,Add request Tx Buffer 28" "Not requested,Requested" textline " " bitfld.long 0x00 27. " AR[27] ,Add request Tx Buffer 27" "Not requested,Requested" bitfld.long 0x00 26. " AR[26] ,Add request Tx Buffer 26" "Not requested,Requested" bitfld.long 0x00 25. " AR[25] ,Add request Tx Buffer 25" "Not requested,Requested" bitfld.long 0x00 24. " AR[24] ,Add request Tx Buffer 24" "Not requested,Requested" textline " " bitfld.long 0x00 23. " AR[23] ,Add request Tx Buffer 23" "Not requested,Requested" bitfld.long 0x00 22. " AR[22] ,Add request Tx Buffer 22" "Not requested,Requested" bitfld.long 0x00 21. " AR[21] ,Add request Tx Buffer 21" "Not requested,Requested" bitfld.long 0x00 20. " AR[20] ,Add request Tx Buffer 20" "Not requested,Requested" textline " " bitfld.long 0x00 19. " AR[19] ,Add request Tx Buffer 19" "Not requested,Requested" bitfld.long 0x00 18. " AR[18] ,Add request Tx Buffer 18" "Not requested,Requested" bitfld.long 0x00 17. " AR[17] ,Add request Tx Buffer 17" "Not requested,Requested" bitfld.long 0x00 16. " AR[16] ,Add request Tx Buffer 16" "Not requested,Requested" textline " " bitfld.long 0x00 15. " AR[15] ,Add request Tx Buffer 15" "Not requested,Requested" bitfld.long 0x00 14. " AR[14] ,Add request Tx Buffer 14" "Not requested,Requested" bitfld.long 0x00 13. " AR[13] ,Add request Tx Buffer 13" "Not requested,Requested" bitfld.long 0x00 12. " AR[12] ,Add request Tx Buffer 12" "Not requested,Requested" textline " " bitfld.long 0x00 11. " AR[11] ,Add request Tx Buffer 11" "Not requested,Requested" bitfld.long 0x00 10. " AR[10] ,Add request Tx Buffer 10" "Not requested,Requested" bitfld.long 0x00 9. " AR[9] ,Add request Tx Buffer 9" "Not requested,Requested" bitfld.long 0x00 8. " AR[8] ,Add request Tx Buffer 8" "Not requested,Requested" textline " " bitfld.long 0x00 7. " AR[7] ,Add request Tx Buffer 7" "Not requested,Requested" bitfld.long 0x00 6. " AR[6] ,Add request Tx Buffer 6" "Not requested,Requested" bitfld.long 0x00 5. " AR[5] ,Add request Tx Buffer 5" "Not requested,Requested" bitfld.long 0x00 4. " AR[4] ,Add request Tx Buffer 4" "Not requested,Requested" textline " " bitfld.long 0x00 3. " AR[3] ,Add request Tx Buffer 3" "Not requested,Requested" bitfld.long 0x00 2. " AR[2] ,Add request Tx Buffer 2" "Not requested,Requested" bitfld.long 0x00 1. " AR[1] ,Add request Tx Buffer 1" "Not requested,Requested" bitfld.long 0x00 0. " AR[0] ,Add request Tx Buffer 0" "Not requested,Requested" line.long 0x04 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request Tx Buffer 31" "Not requested,Requested" bitfld.long 0x04 30. " CR[30] ,Cancellation request Tx Buffer 30" "Not requested,Requested" bitfld.long 0x04 29. " CR[29] ,Cancellation request Tx Buffer 29" "Not requested,Requested" bitfld.long 0x04 28. " CR[28] ,Cancellation request Tx Buffer 28" "Not requested,Requested" textline " " bitfld.long 0x04 27. " CR[27] ,Cancellation request Tx Buffer 27" "Not requested,Requested" bitfld.long 0x04 26. " CR[26] ,Cancellation request Tx Buffer 26" "Not requested,Requested" bitfld.long 0x04 25. " CR[25] ,Cancellation request Tx Buffer 25" "Not requested,Requested" bitfld.long 0x04 24. " CR[24] ,Cancellation request Tx Buffer 24" "Not requested,Requested" textline " " bitfld.long 0x04 23. " CR[23] ,Cancellation request Tx Buffer 23" "Not requested,Requested" bitfld.long 0x04 22. " CR[22] ,Cancellation request Tx Buffer 22" "Not requested,Requested" bitfld.long 0x04 21. " CR[21] ,Cancellation request Tx Buffer 21" "Not requested,Requested" bitfld.long 0x04 20. " CR[20] ,Cancellation request Tx Buffer 20" "Not requested,Requested" textline " " bitfld.long 0x04 19. " CR[19] ,Cancellation request Tx Buffer 19" "Not requested,Requested" bitfld.long 0x04 18. " CR[18] ,Cancellation request Tx Buffer 18" "Not requested,Requested" bitfld.long 0x04 17. " CR[17] ,Cancellation request Tx Buffer 17" "Not requested,Requested" bitfld.long 0x04 16. " CR[16] ,Cancellation request Tx Buffer 16" "Not requested,Requested" textline " " bitfld.long 0x04 15. " CR[15] ,Cancellation request Tx Buffer 15" "Not requested,Requested" bitfld.long 0x04 14. " CR[14] ,Cancellation request Tx Buffer 14" "Not requested,Requested" bitfld.long 0x04 13. " CR[13] ,Cancellation request Tx Buffer 13" "Not requested,Requested" bitfld.long 0x04 12. " CR[12] ,Cancellation request Tx Buffer 12" "Not requested,Requested" textline " " bitfld.long 0x04 11. " CR[11] ,Cancellation request Tx Buffer 11" "Not requested,Requested" bitfld.long 0x04 10. " CR[10] ,Cancellation request Tx Buffer 10" "Not requested,Requested" bitfld.long 0x04 9. " CR[9] ,Cancellation request Tx Buffer 9" "Not requested,Requested" bitfld.long 0x04 8. " CR[8] ,Cancellation request Tx Buffer 8" "Not requested,Requested" textline " " bitfld.long 0x04 7. " CR[7] ,Cancellation request Tx Buffer 7" "Not requested,Requested" bitfld.long 0x04 6. " CR[6] ,Cancellation request Tx Buffer 6" "Not requested,Requested" bitfld.long 0x04 5. " CR[5] ,Cancellation request Tx Buffer 5" "Not requested,Requested" bitfld.long 0x04 4. " CR[4] ,Cancellation request Tx Buffer 4" "Not requested,Requested" textline " " bitfld.long 0x04 3. " CR[3] ,Cancellation request Tx Buffer 3" "Not requested,Requested" bitfld.long 0x04 2. " CR[2] ,Cancellation request Tx Buffer 2" "Not requested,Requested" bitfld.long 0x04 1. " CR[1] ,Cancellation request Tx Buffer 1" "Not requested,Requested" bitfld.long 0x04 0. " CR[0] ,Cancellation request Tx Buffer 0" "Not requested,Requested" rgroup.long 0xD8++0x07 line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission Occurred Tx Buffer 31" "Not occurred,Occurred" bitfld.long 0x00 30. " TO[30] ,Transmission Occurred Tx Buffer 30" "Not occurred,Occurred" bitfld.long 0x00 29. " TO[29] ,Transmission Occurred Tx Buffer 29" "Not occurred,Occurred" bitfld.long 0x00 28. " TO[28] ,Transmission Occurred Tx Buffer 28" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " TO[27] ,Transmission Occurred Tx Buffer 27" "Not occurred,Occurred" bitfld.long 0x00 26. " TO[26] ,Transmission Occurred Tx Buffer 26" "Not occurred,Occurred" bitfld.long 0x00 25. " TO[25] ,Transmission Occurred Tx Buffer 25" "Not occurred,Occurred" bitfld.long 0x00 24. " TO[24] ,Transmission Occurred Tx Buffer 24" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " TO[23] ,Transmission Occurred Tx Buffer 23" "Not occurred,Occurred" bitfld.long 0x00 22. " TO[22] ,Transmission Occurred Tx Buffer 22" "Not occurred,Occurred" bitfld.long 0x00 21. " TO[21] ,Transmission Occurred Tx Buffer 21" "Not occurred,Occurred" bitfld.long 0x00 20. " TO[20] ,Transmission Occurred Tx Buffer 20" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " TO[19] ,Transmission Occurred Tx Buffer 19" "Not occurred,Occurred" bitfld.long 0x00 18. " TO[18] ,Transmission Occurred Tx Buffer 18" "Not occurred,Occurred" bitfld.long 0x00 17. " TO[17] ,Transmission Occurred Tx Buffer 17" "Not occurred,Occurred" bitfld.long 0x00 16. " TO[16] ,Transmission Occurred Tx Buffer 16" "Not occurred,Occurred" textline " " bitfld.long 0x00 15. " TO[15] ,Transmission Occurred Tx Buffer 15" "Not occurred,Occurred" bitfld.long 0x00 14. " TO[14] ,Transmission Occurred Tx Buffer 14" "Not occurred,Occurred" bitfld.long 0x00 13. " TO[13] ,Transmission Occurred Tx Buffer 13" "Not occurred,Occurred" bitfld.long 0x00 12. " TO[12] ,Transmission Occurred Tx Buffer 12" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " TO[11] ,Transmission Occurred Tx Buffer 11" "Not occurred,Occurred" bitfld.long 0x00 10. " TO[10] ,Transmission Occurred Tx Buffer 10" "Not occurred,Occurred" bitfld.long 0x00 9. " TO[9] ,Transmission Occurred Tx Buffer 9" "Not occurred,Occurred" bitfld.long 0x00 8. " TO[8] ,Transmission Occurred Tx Buffer 8" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " TO[7] ,Transmission Occurred Tx Buffer 7" "Not occurred,Occurred" bitfld.long 0x00 6. " TO[6] ,Transmission Occurred Tx Buffer 6" "Not occurred,Occurred" bitfld.long 0x00 5. " TO[5] ,Transmission Occurred Tx Buffer 5" "Not occurred,Occurred" bitfld.long 0x00 4. " TO[4] ,Transmission Occurred Tx Buffer 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " TO[3] ,Transmission Occurred Tx Buffer 3" "Not occurred,Occurred" bitfld.long 0x00 2. " TO[2] ,Transmission Occurred Tx Buffer 2" "Not occurred,Occurred" bitfld.long 0x00 1. " TO[1] ,Transmission Occurred Tx Buffer 1" "Not occurred,Occurred" bitfld.long 0x00 0. " TO[0] ,Transmission Occurred Tx Buffer 0" "Not occurred,Occurred" line.long 0x04 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation Finished Tx Buffer 31" "Not finished,Finished" bitfld.long 0x04 30. " CF[30] ,Cancellation Finished Tx Buffer 30" "Not finished,Finished" bitfld.long 0x04 29. " CF[29] ,Cancellation Finished Tx Buffer 29" "Not finished,Finished" bitfld.long 0x04 28. " CF[28] ,Cancellation Finished Tx Buffer 28" "Not finished,Finished" textline " " bitfld.long 0x04 27. " CF[27] ,Cancellation Finished Tx Buffer 27" "Not finished,Finished" bitfld.long 0x04 26. " CF[26] ,Cancellation Finished Tx Buffer 26" "Not finished,Finished" bitfld.long 0x04 25. " CF[25] ,Cancellation Finished Tx Buffer 25" "Not finished,Finished" bitfld.long 0x04 24. " CF[24] ,Cancellation Finished Tx Buffer 24" "Not finished,Finished" textline " " bitfld.long 0x04 23. " CF[23] ,Cancellation Finished Tx Buffer 23" "Not finished,Finished" bitfld.long 0x04 22. " CF[22] ,Cancellation Finished Tx Buffer 22" "Not finished,Finished" bitfld.long 0x04 21. " CF[21] ,Cancellation Finished Tx Buffer 21" "Not finished,Finished" bitfld.long 0x04 20. " CF[20] ,Cancellation Finished Tx Buffer 20" "Not finished,Finished" textline " " bitfld.long 0x04 19. " CF[19] ,Cancellation Finished Tx Buffer 19" "Not finished,Finished" bitfld.long 0x04 18. " CF[18] ,Cancellation Finished Tx Buffer 18" "Not finished,Finished" bitfld.long 0x04 17. " CF[17] ,Cancellation Finished Tx Buffer 17" "Not finished,Finished" bitfld.long 0x04 16. " CF[16] ,Cancellation Finished Tx Buffer 16" "Not finished,Finished" textline " " bitfld.long 0x04 15. " CF[15] ,Cancellation Finished Tx Buffer 15" "Not finished,Finished" bitfld.long 0x04 14. " CF[14] ,Cancellation Finished Tx Buffer 14" "Not finished,Finished" bitfld.long 0x04 13. " CF[13] ,Cancellation Finished Tx Buffer 13" "Not finished,Finished" bitfld.long 0x04 12. " CF[12] ,Cancellation Finished Tx Buffer 12" "Not finished,Finished" textline " " bitfld.long 0x04 11. " CF[11] ,Cancellation Finished Tx Buffer 11" "Not finished,Finished" bitfld.long 0x04 10. " CF[10] ,Cancellation Finished Tx Buffer 10" "Not finished,Finished" bitfld.long 0x04 9. " CF[9] ,Cancellation Finished Tx Buffer 9" "Not finished,Finished" bitfld.long 0x04 8. " CF[8] ,Cancellation Finished Tx Buffer 8" "Not finished,Finished" textline " " bitfld.long 0x04 7. " CF[7] ,Cancellation Finished Tx Buffer 7" "Not finished,Finished" bitfld.long 0x04 6. " CF[6] ,Cancellation Finished Tx Buffer 6" "Not finished,Finished" bitfld.long 0x04 5. " CF[5] ,Cancellation Finished Tx Buffer 5" "Not finished,Finished" bitfld.long 0x04 4. " CF[4] ,Cancellation Finished Tx Buffer 4" "Not finished,Finished" textline " " bitfld.long 0x04 3. " CF[3] ,Cancellation Finished Tx Buffer 3" "Not finished,Finished" bitfld.long 0x04 2. " CF[2] ,Cancellation Finished Tx Buffer 2" "Not finished,Finished" bitfld.long 0x04 1. " CF[1] ,Cancellation Finished Tx Buffer 1" "Not finished,Finished" bitfld.long 0x04 0. " CF[0] ,Cancellation Finished Tx Buffer 0" "Not finished,Finished" group.long 0xE0++0x07 line.long 0x00 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x00 31. " TIE[31] ,Transmission Interrupt Enable Tx Buffer 31" "Disabled,Enabled" bitfld.long 0x00 30. " TIE[30] ,Transmission Interrupt Enable Tx Buffer 30" "Disabled,Enabled" bitfld.long 0x00 29. " TIE[29] ,Transmission Interrupt Enable Tx Buffer 29" "Disabled,Enabled" bitfld.long 0x00 28. " TIE[28] ,Transmission Interrupt Enable Tx Buffer 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " TIE[27] ,Transmission Interrupt Enable Tx Buffer 27" "Disabled,Enabled" bitfld.long 0x00 26. " TIE[26] ,Transmission Interrupt Enable Tx Buffer 26" "Disabled,Enabled" bitfld.long 0x00 25. " TIE[25] ,Transmission Interrupt Enable Tx Buffer 25" "Disabled,Enabled" bitfld.long 0x00 24. " TIE[24] ,Transmission Interrupt Enable Tx Buffer 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " TIE[23] ,Transmission Interrupt Enable Tx Buffer 23" "Disabled,Enabled" bitfld.long 0x00 22. " TIE[22] ,Transmission Interrupt Enable Tx Buffer 22" "Disabled,Enabled" bitfld.long 0x00 21. " TIE[21] ,Transmission Interrupt Enable Tx Buffer 21" "Disabled,Enabled" bitfld.long 0x00 20. " TIE[20] ,Transmission Interrupt Enable Tx Buffer 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " TIE[19] ,Transmission Interrupt Enable Tx Buffer 19" "Disabled,Enabled" bitfld.long 0x00 18. " TIE[18] ,Transmission Interrupt Enable Tx Buffer 18" "Disabled,Enabled" bitfld.long 0x00 17. " TIE[17] ,Transmission Interrupt Enable Tx Buffer 17" "Disabled,Enabled" bitfld.long 0x00 16. " TIE[16] ,Transmission Interrupt Enable Tx Buffer 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " TIE[15] ,Transmission Interrupt Enable Tx Buffer 15" "Disabled,Enabled" bitfld.long 0x00 14. " TIE[14] ,Transmission Interrupt Enable Tx Buffer 14" "Disabled,Enabled" bitfld.long 0x00 13. " TIE[13] ,Transmission Interrupt Enable Tx Buffer 13" "Disabled,Enabled" bitfld.long 0x00 12. " TIE[12] ,Transmission Interrupt Enable Tx Buffer 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TIE[11] ,Transmission Interrupt Enable Tx Buffer 11" "Disabled,Enabled" bitfld.long 0x00 10. " TIE[10] ,Transmission Interrupt Enable Tx Buffer 10" "Disabled,Enabled" bitfld.long 0x00 9. " TIE[9] ,Transmission Interrupt Enable Tx Buffer 9" "Disabled,Enabled" bitfld.long 0x00 8. " TIE[8] ,Transmission Interrupt Enable Tx Buffer 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TIE[7] ,Transmission Interrupt Enable Tx Buffer 7" "Disabled,Enabled" bitfld.long 0x00 6. " TIE[6] ,Transmission Interrupt Enable Tx Buffer 6" "Disabled,Enabled" bitfld.long 0x00 5. " TIE[5] ,Transmission Interrupt Enable Tx Buffer 5" "Disabled,Enabled" bitfld.long 0x00 4. " TIE[4] ,Transmission Interrupt Enable Tx Buffer 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TIE[3] ,Transmission Interrupt Enable Tx Buffer 3" "Disabled,Enabled" bitfld.long 0x00 2. " TIE[2] ,Transmission Interrupt Enable Tx Buffer 2" "Disabled,Enabled" bitfld.long 0x00 1. " TIE[1] ,Transmission Interrupt Enable Tx Buffer 1" "Disabled,Enabled" bitfld.long 0x00 0. " TIE[0] ,Transmission Interrupt Enable Tx Buffer 0" "Disabled,Enabled" line.long 0x04 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x04 31. " CFIE[31] ,Cancellation Finished Interrupt Enable Tx Buffer 31" "Disabled,Enabled" bitfld.long 0x04 30. " CFIE[30] ,Cancellation Finished Interrupt Enable Tx Buffer 30" "Disabled,Enabled" bitfld.long 0x04 29. " CFIE[29] ,Cancellation Finished Interrupt Enable Tx Buffer 29" "Disabled,Enabled" bitfld.long 0x04 28. " CFIE[28] ,Cancellation Finished Interrupt Enable Tx Buffer 28" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " CFIE[27] ,Cancellation Finished Interrupt Enable Tx Buffer 27" "Disabled,Enabled" bitfld.long 0x04 26. " CFIE[26] ,Cancellation Finished Interrupt Enable Tx Buffer 26" "Disabled,Enabled" bitfld.long 0x04 25. " CFIE[25] ,Cancellation Finished Interrupt Enable Tx Buffer 25" "Disabled,Enabled" bitfld.long 0x04 24. " CFIE[24] ,Cancellation Finished Interrupt Enable Tx Buffer 24" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " CFIE[23] ,Cancellation Finished Interrupt Enable Tx Buffer 23" "Disabled,Enabled" bitfld.long 0x04 22. " CFIE[22] ,Cancellation Finished Interrupt Enable Tx Buffer 22" "Disabled,Enabled" bitfld.long 0x04 21. " CFIE[21] ,Cancellation Finished Interrupt Enable Tx Buffer 21" "Disabled,Enabled" bitfld.long 0x04 20. " CFIE[20] ,Cancellation Finished Interrupt Enable Tx Buffer 20" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " CFIE[19] ,Cancellation Finished Interrupt Enable Tx Buffer 19" "Disabled,Enabled" bitfld.long 0x04 18. " CFIE[18] ,Cancellation Finished Interrupt Enable Tx Buffer 18" "Disabled,Enabled" bitfld.long 0x04 17. " CFIE[17] ,Cancellation Finished Interrupt Enable Tx Buffer 17" "Disabled,Enabled" bitfld.long 0x04 16. " CFIE[16] ,Cancellation Finished Interrupt Enable Tx Buffer 16" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " CFIE[15] ,Cancellation Finished Interrupt Enable Tx Buffer 15" "Disabled,Enabled" bitfld.long 0x04 14. " CFIE[14] ,Cancellation Finished Interrupt Enable Tx Buffer 14" "Disabled,Enabled" bitfld.long 0x04 13. " CFIE[13] ,Cancellation Finished Interrupt Enable Tx Buffer 13" "Disabled,Enabled" bitfld.long 0x04 12. " CFIE[12] ,Cancellation Finished Interrupt Enable Tx Buffer 12" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " CFIE[11] ,Cancellation Finished Interrupt Enable Tx Buffer 11" "Disabled,Enabled" bitfld.long 0x04 10. " CFIE[10] ,Cancellation Finished Interrupt Enable Tx Buffer 10" "Disabled,Enabled" bitfld.long 0x04 9. " CFIE[9] ,Cancellation Finished Interrupt Enable Tx Buffer 9" "Disabled,Enabled" bitfld.long 0x04 8. " CFIE[8] ,Cancellation Finished Interrupt Enable Tx Buffer 8" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " CFIE[7] ,Cancellation Finished Interrupt Enable Tx Buffer 7" "Disabled,Enabled" bitfld.long 0x04 6. " CFIE[6] ,Cancellation Finished Interrupt Enable Tx Buffer 6" "Disabled,Enabled" bitfld.long 0x04 5. " CFIE[5] ,Cancellation Finished Interrupt Enable Tx Buffer 5" "Disabled,Enabled" bitfld.long 0x04 4. " CFIE[4] ,Cancellation Finished Interrupt Enable Tx Buffer 4" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " CFIE[3] ,Cancellation Finished Interrupt Enable Tx Buffer 3" "Disabled,Enabled" bitfld.long 0x04 2. " CFIE[2] ,Cancellation Finished Interrupt Enable Tx Buffer 2" "Disabled,Enabled" bitfld.long 0x04 1. " CFIE[1] ,Cancellation Finished Interrupt Enable Tx Buffer 1" "Disabled,Enabled" bitfld.long 0x04 0. " CFIE[0] ,Cancellation Finished Interrupt Enable Tx Buffer 0" "Disabled,Enabled" group.long 0xF0++0x03 line.long 0x00 "TXEFC,Tx Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x00 16.--21. " EFS ,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO Size Address" rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,Tx Event FIFO Element Lost" "Not lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO Full" "Not full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " EFGI ,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" group.long 0xF8++0x03 line.long 0x00 "TXEFA,Tx Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0b tree.end tree "M_CAN_2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020F0000 else base ad:0x420F0000 endif width 10. rgroup.long 0x00++0x07 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " YEAR ,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " MON ,Time Stamp Month" hexmask.long.byte 0x00 0.--7. 1. " DAY ,Time Stamp Day" line.long 0x04 "ENDN,Endian Register" group.long 0x0C++0x23 line.long 0x00 "FBTP,Fast Bit Timing and Prescaler Register" bitfld.long 0x00 24.--28. " TDCO ,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " TDC ,Transceiver Delay Compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " FBRP ,Fast Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " FTSEG1 ,Fast time segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--6. " FTSEG2 ,Fast time segment after sample point" ",1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " FSJW ,Fast (Re) Synchronization Jump Width" "0,1,2,3" line.long 0x04 "TEST,Test Register" hexmask.long.byte 0x04 8.--13. 1. " TDCV ,Transceiver Delay Compensation Value" rbitfld.long 0x04 7. " RX ,Receive Pin" "Dominant,Recessive" bitfld.long 0x04 5.--6. " TX ,Control of Transmit Pin" "M_CAN,Sample Point,Dominant,Recessive" bitfld.long 0x04 4. " LBCK ,Loopback mode" "Disabled,Enabled" line.long 0x08 "RWD,RAM Watchdog Register" hexmask.long.byte 0x08 8.--15. 1. " WDV ,Actual Message RAM Watchdog Counter Value" hexmask.long.byte 0x08 0.--7. 1. " WDC ,Start value of the Message RAM Watchdog Counter" line.long 0x0C "CCCR,CC Control Register" bitfld.long 0x0C 14. " TXP ,Transmit Pause" "Disabled,Enabled" rbitfld.long 0x0C 13. " FDBS ,CAN FD Bit Rate Switching" "No frames,All frames" rbitfld.long 0x0C 12. " FDO ,CAN FD Operation" "ISO11898-1,CAN FD" bitfld.long 0x0C 10.--11. " CMR ,CAN Mode Request" "Unchanged,CAN FD,CAN FD bitrate,ISO11898-1" textline " " bitfld.long 0x0C 8.--9. " CME ,CAN Mode Enable" "ISO11898-1,CAN FD,CAN FD bitrate,CAN FD bitrate" bitfld.long 0x0C 7. " TEST ,Test Mode Enable" "Disabled,Enabled" bitfld.long 0x0C 6. " DAR ,Disable Automatic Retransmission" "No,Yes" bitfld.long 0x0C 5. " MON ,Bus Monitoring Mode" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " CSR ,Clock Stop Request" "No request,Requested" bitfld.long 0x0C 3. " CSA ,Clock Stop Acknowledge" "No Acknowledge,Acknowledge" bitfld.long 0x0C 2. " ASM ,Restricted Operation Mode" "Disabled,Enabled" bitfld.long 0x0C 1. " CCE ,Configuration Change Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " INIT ,Initialization" "Normal operation,Initialization" line.long 0x10 "BTP,Bit Timing and Prescaler Register" hexmask.long.word 0x10 16.--25. 0x02 " BRP ,Baud Rate Prescaler" hexmask.long.byte 0x10 8.--13. 1. " TSEG1 ,Time segment before sample point" bitfld.long 0x10 4.--7. " TSEG2 ,Time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " SJW ,Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x14 16.--19. " TCP ,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--1. " TSS ,Timestamp Select" "Always 0,Increment (TCP),External,Always 0" line.long 0x18 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x18 0.--15. 1. " TSC ,Timestamp Counter" line.long 0x1C "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x1C 16.--31. 1. " TOP ,Timeout Period" bitfld.long 0x1C 1.--2. " TOS ,Timeout Select" "Continuous,Tx Event FIFO,Rx FIFO 0,Rx FIFO 1" bitfld.long 0x1C 0. " ETOC ,Enable Timeout Counter" "Disabled,Enabled" line.long 0x20 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x20 0.--15. 1. " TOC ,Timeout Counter" rgroup.long 0x40++0x07 line.long 0x00 "ECR,Error Counter Register" hexmask.long.byte 0x00 16.--23. 1. " CEL ,CAN Error Logging" bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached" hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter" line.long 0x04 "PSR,Protocol Status Register" bitfld.long 0x04 13. " REDL ,Received a CAN FD Message" "Not received,Received" bitfld.long 0x04 12. " RBRS ,BRS flag of last received CAN FD Message" "Not set,Set" bitfld.long 0x04 11. " RESI ,ESI flag of last received CAN FD Message" "Not set,Set" bitfld.long 0x04 8.--10. " FLEC ,Fast Last Error Code" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 7. " BO ,Bus_Off Status" "Not Bus_Off,Bus_Off" bitfld.long 0x04 6. " EW ,Warning Status" "Below level,Level reached" bitfld.long 0x04 5. " EP ,Error Passive" "Error_Active,Error_Passive" bitfld.long 0x04 3.--4. " ACT ,Activity" "Synchronizing,Idle,Receiver,Transmitter" textline " " bitfld.long 0x04 0.--2. " LEC ,Last Error Code" "Error,Stuff,Form,Ack,Bit1,Bit0,CRC,NoChange" group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 31. " STE ,Stuff Error" "Not occurred,Occurred" eventfld.long 0x00 30. " FOE ,Format Error" "Not occurred,Occurred" eventfld.long 0x00 29. " ACKE ,Acknowledge Error" "Not occurred,Occurred" eventfld.long 0x00 28. " BE ,Bit Error" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " CRCE ,CRC Error" "Not occurred,Occurred" eventfld.long 0x00 26. " WDI ,Watchdog Interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " BO ,Bus_Off Status" "Not changed,Changed" eventfld.long 0x00 24. " EW ,Warning Status" "Not changed,Changed" textline " " eventfld.long 0x00 23. " EP ,Error passive" "Not changed,Changed" eventfld.long 0x00 22. " ELO ,Error Logging Overflow" "Not occurred,Occurred" eventfld.long 0x00 21. " BEU ,Bit Error Uncorrected" "Not detected,Detected" eventfld.long 0x00 20. " BEC ,Bit Error Corrected" "Not detected,Detected" textline " " eventfld.long 0x00 19. " DRX ,Message stored to Dedicated Rx Buffer" "Not stored,Stored" eventfld.long 0x00 18. " TOO ,Timeout" "Not occurred,Occurred" eventfld.long 0x00 17. " MRAF ,Message RAM Access Failure" "Not occurred,Occurred" eventfld.long 0x00 16. " TSW ,Timestamp Wraparound" "Not wrapped,Wrapped" textline " " eventfld.long 0x00 15. " TEFL ,Tx Event FIFO Element Lost" "Not lost,Lost" eventfld.long 0x00 14. " TEFF ,Tx Event FIFO Full" "Not full,Full" eventfld.long 0x00 13. " TEFW ,Tx Event FIFO Watermark Reached" "Below,Reached" eventfld.long 0x00 12. " TEFN ,Tx Event FIFO New Entry" "Unchanged,Written" textline " " eventfld.long 0x00 11. " TFE ,Tx FIFO Empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission Cancellation Finished" "Not finished,Finished" eventfld.long 0x00 9. " TC ,Transmission Completed" "Not completed,Completed" eventfld.long 0x00 8. " HPM ,High Priority Message" "Not received,Received" textline " " eventfld.long 0x00 7. " RF1L ,Rx FIFO 1 Message Lost" "Not lost,Lost" eventfld.long 0x00 6. " RF1F ,Rx FIFO 1 Full" "Not full,Full" eventfld.long 0x00 5. " RF1W ,Rx FIFO 1 Watermark Reached" "Below,Reached" eventfld.long 0x00 4. " RF1N ,Rx FIFO 1 New Message" "Not written,Written" textline " " eventfld.long 0x00 3. " RF0L ,Rx FIFO 0 Message Lost" "Not lost,Lost" eventfld.long 0x00 2. " RF0F ,Rx FIFO 0 Full" "Not full,Full" eventfld.long 0x00 1. " RF0W ,Rx FIFO 0 Watermark Reached" "Below,Reached" eventfld.long 0x00 0. " RF0N ,Rx FIFO 0 New Message" "Not written,Written" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 31. " STEE ,Stuff Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 30. " FOEE ,Format Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 29. " ACKEE ,Acknowledge Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 28. " BEE ,Bit Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " CRCEE ,CRC Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 26. " WDIE ,Watchdog Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning Status Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " EPE ,Error Passive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error Logging Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit Error Uncorrected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 20. " BECE ,Bit Error Corrected Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " DRXE ,Message stored to Dedicated Rx Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout Occurred Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 17. " MRAFE ,Message RAM Access Failure Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp Wraparound Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " TEFLE ,Tx Event FIFO Element Lost Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 14. " TEFFE ,Tx Event FIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,Tx Event FIFO Watermark Reached Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,Tx Event FIFO New Entry Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " TFEE ,Tx FIFO Empty Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission Cancellation Finished Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission Completed Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 8. " HPME ,High Priority Message Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " RF1LE ,Rx FIFO 1 Message Lost Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,Rx FIFO 1 Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " RF1WE ,Rx FIFO 1 Watermark Reached Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,Rx FIFO 1 New Message Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " RF0LE ,Rx FIFO 0 Message Lost Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " RF0FE ,Rx FIFO 0 Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,Rx FIFO 0 Watermark Reached Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,Rx FIFO 0 New Message Interrupt Enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 31. " STEL ,Stuff Error Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 30. " FOEL ,Format Error Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 29. " ACKEL ,Acknowledge Error Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 28. " BEL ,Bit Error Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 27. " CRCEL ,CRC Error Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 26. " WDIL ,Watchdog Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 25. " BOL ,Bus_Off Status Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 24. " EWL ,Warning Status Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 23. " EPL ,Error Passive Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 22. " ELOL ,Error Logging Overflow Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 21. " BEUL ,Bit Error Uncorrected Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 20. " BECL ,Bit Error Corrected Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 19. " DRXL ,Message stored to Dedicated Rx Buffer Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 18. " TOOL ,Timeout Occurred Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 17. " MRAFL ,Message RAM Access Failure Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 16. " TSWL ,Timestamp Wraparound Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 15. " TEFLL ,Tx Event FIFO Element Lost Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 14. " TEFFL ,Tx Event FIFO Full Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 13. " TEFWL ,Tx Event FIFO Watermark Reached Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 12. " TEFNL ,Tx Event FIFO New Entry Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 11. " TFEL ,Tx FIFO Empty Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 10. " TCFL ,Transmission Cancellation Finished Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 9. " TCL ,Transmission Completed Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 8. " HPML ,High Priority Message Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 7. " RF1LL ,Rx FIFO 1 Message Lost Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 6. " RF1FL ,Rx FIFO 1 Full Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 5. " RF1WL ,Rx FIFO 1 Watermark Reached Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 4. " RF1NL ,Rx FIFO 1 New Message Interrupt Line" "Line 0,Line 1" textline " " bitfld.long 0x08 3. " RF0LL ,Rx FIFO 0 Message Lost Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 2. " RF0FL ,Rx FIFO 0 Full Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 1. " RF0WL ,Rx FIFO 0 Watermark Reached Interrupt Line" "Line 0,Line 1" bitfld.long 0x08 0. " RF0NL ,Rx FIFO 0 New Message Interrupt Line" "Line 0,Line 1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable Interrupt Line 0" "Disabled,Enabled" group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept Non-matching Frames Standard" "Rx FIFO 0,Rx FIFO 1,Rejected,Rejected" bitfld.long 0x00 2.--3. " ANFE ,Accept Non-matching Frames Extended" "Rx FIFO 0,Rx FIFO 1,Rejected,Rejected" bitfld.long 0x00 1. " RRFS ,Reject Remote Frames Standard" "Filtered,Rejected" bitfld.long 0x00 0. " RRFE ,Reject Remote Frames Extended" "Filtered,Rejected" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List Size Standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter List Standard Start Address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List Size Extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter List Extended Start Address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID and Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID Mask" rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter List" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter Index" bitfld.long 0x00 6.--7. " MSI ,Message Storage Indicator" "No FIFO,Message lost,FIFO 0,FIFO 1" hexmask.long.byte 0x00 0.--5. 1. " BIDX ,Buffer Index" group.long 0x98++0x0B line.long 0x00 "NDAT1,New Data 1 Register" bitfld.long 0x00 31. " ND[31] ,New Data Rx Buffer 31" "Not updated,Updated" bitfld.long 0x00 30. " ND[30] ,New Data Rx Buffer 30" "Not updated,Updated" bitfld.long 0x00 29. " ND[29] ,New Data Rx Buffer 29" "Not updated,Updated" bitfld.long 0x00 28. " ND[28] ,New Data Rx Buffer 28" "Not updated,Updated" textline " " bitfld.long 0x00 27. " ND[27] ,New Data Rx Buffer 27" "Not updated,Updated" bitfld.long 0x00 26. " ND[26] ,New Data Rx Buffer 26" "Not updated,Updated" bitfld.long 0x00 25. " ND[25] ,New Data Rx Buffer 25" "Not updated,Updated" bitfld.long 0x00 24. " ND[24] ,New Data Rx Buffer 24" "Not updated,Updated" textline " " bitfld.long 0x00 23. " ND[23] ,New Data Rx Buffer 23" "Not updated,Updated" bitfld.long 0x00 22. " ND[22] ,New Data Rx Buffer 22" "Not updated,Updated" bitfld.long 0x00 21. " ND[21] ,New Data Rx Buffer 21" "Not updated,Updated" bitfld.long 0x00 20. " ND[20] ,New Data Rx Buffer 20" "Not updated,Updated" textline " " bitfld.long 0x00 19. " ND[19] ,New Data Rx Buffer 19" "Not updated,Updated" bitfld.long 0x00 18. " ND[18] ,New Data Rx Buffer 18" "Not updated,Updated" bitfld.long 0x00 17. " ND[17] ,New Data Rx Buffer 17" "Not updated,Updated" bitfld.long 0x00 16. " ND[16] ,New Data Rx Buffer 16" "Not updated,Updated" textline " " bitfld.long 0x00 15. " ND[15] ,New Data Rx Buffer 15" "Not updated,Updated" bitfld.long 0x00 14. " ND[14] ,New Data Rx Buffer 14" "Not updated,Updated" bitfld.long 0x00 13. " ND[13] ,New Data Rx Buffer 13" "Not updated,Updated" bitfld.long 0x00 12. " ND[12] ,New Data Rx Buffer 12" "Not updated,Updated" textline " " bitfld.long 0x00 11. " ND[11] ,New Data Rx Buffer 11" "Not updated,Updated" bitfld.long 0x00 10. " ND[10] ,New Data Rx Buffer 10" "Not updated,Updated" bitfld.long 0x00 9. " ND[9] ,New Data Rx Buffer 9" "Not updated,Updated" bitfld.long 0x00 8. " ND[8] ,New Data Rx Buffer 8" "Not updated,Updated" textline " " bitfld.long 0x00 7. " ND[7] ,New Data Rx Buffer 7" "Not updated,Updated" bitfld.long 0x00 6. " ND[6] ,New Data Rx Buffer 6" "Not updated,Updated" bitfld.long 0x00 5. " ND[5] ,New Data Rx Buffer 5" "Not updated,Updated" bitfld.long 0x00 4. " ND[4] ,New Data Rx Buffer 4" "Not updated,Updated" textline " " bitfld.long 0x00 3. " ND[3] ,New Data Rx Buffer 3" "Not updated,Updated" bitfld.long 0x00 2. " ND[2] ,New Data Rx Buffer 2" "Not updated,Updated" bitfld.long 0x00 1. " ND[1] ,New Data Rx Buffer 1" "Not updated,Updated" bitfld.long 0x00 0. " ND[0] ,New Data Rx Buffer 0" "Not updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" bitfld.long 0x04 31. " ND[63] ,New Data Rx Buffer 63" "Not updated,Updated" bitfld.long 0x04 30. " ND[62] ,New Data Rx Buffer 62" "Not updated,Updated" bitfld.long 0x04 29. " ND[61] ,New Data Rx Buffer 61" "Not updated,Updated" bitfld.long 0x04 28. " ND[60] ,New Data Rx Buffer 60" "Not updated,Updated" textline " " bitfld.long 0x04 27. " ND[59] ,New Data Rx Buffer 59" "Not updated,Updated" bitfld.long 0x04 26. " ND[58] ,New Data Rx Buffer 58" "Not updated,Updated" bitfld.long 0x04 25. " ND[57] ,New Data Rx Buffer 57" "Not updated,Updated" bitfld.long 0x04 24. " ND[56] ,New Data Rx Buffer 56" "Not updated,Updated" textline " " bitfld.long 0x04 23. " ND[55] ,New Data Rx Buffer 55" "Not updated,Updated" bitfld.long 0x04 22. " ND[54] ,New Data Rx Buffer 54" "Not updated,Updated" bitfld.long 0x04 21. " ND[53] ,New Data Rx Buffer 53" "Not updated,Updated" bitfld.long 0x04 20. " ND[52] ,New Data Rx Buffer 52" "Not updated,Updated" textline " " bitfld.long 0x04 19. " ND[51] ,New Data Rx Buffer 51" "Not updated,Updated" bitfld.long 0x04 18. " ND[50] ,New Data Rx Buffer 50" "Not updated,Updated" bitfld.long 0x04 17. " ND[49] ,New Data Rx Buffer 49" "Not updated,Updated" bitfld.long 0x04 16. " ND[48] ,New Data Rx Buffer 48" "Not updated,Updated" textline " " bitfld.long 0x04 15. " ND[47] ,New Data Rx Buffer 47" "Not updated,Updated" bitfld.long 0x04 14. " ND[46] ,New Data Rx Buffer 46" "Not updated,Updated" bitfld.long 0x04 13. " ND[45] ,New Data Rx Buffer 45" "Not updated,Updated" bitfld.long 0x04 12. " ND[44] ,New Data Rx Buffer 44" "Not updated,Updated" textline " " bitfld.long 0x04 11. " ND[43] ,New Data Rx Buffer 43" "Not updated,Updated" bitfld.long 0x04 10. " ND[42] ,New Data Rx Buffer 42" "Not updated,Updated" bitfld.long 0x04 9. " ND[41] ,New Data Rx Buffer 41" "Not updated,Updated" bitfld.long 0x04 8. " ND[40] ,New Data Rx Buffer 40" "Not updated,Updated" textline " " bitfld.long 0x04 7. " ND[39] ,New Data Rx Buffer 39" "Not updated,Updated" bitfld.long 0x04 6. " ND[38] ,New Data Rx Buffer 38" "Not updated,Updated" bitfld.long 0x04 5. " ND[37] ,New Data Rx Buffer 37" "Not updated,Updated" bitfld.long 0x04 4. " ND[36] ,New Data Rx Buffer 36" "Not updated,Updated" textline " " bitfld.long 0x04 3. " ND[35] ,New Data Rx Buffer 35" "Not updated,Updated" bitfld.long 0x04 2. " ND[34] ,New Data Rx Buffer 34" "Not updated,Updated" bitfld.long 0x04 1. " ND[33] ,New Data Rx Buffer 33" "Not updated,Updated" bitfld.long 0x04 0. " ND[32] ,New Data Rx Buffer 32" "Not updated,Updated" line.long 0x08 "RXF0C,Rx FIFO 0 Configuration Register" bitfld.long 0x08 31. " F0OM ,FIFO 0 Operation Mode" "Blocking,Overwrite" hexmask.long.byte 0x08 24.--30. 1. " F0WM ,Rx FIFO 0 Watermark" hexmask.long.byte 0x08 16.--21. 1. " F0S ,Rx FIFO 0 Size" hexmask.long.word 0x08 2.--15. 0x04 " F0SA ,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,Rx FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,Rx FIFO 0 Message Lost" "Not lost,Lost" bitfld.long 0x00 24. " F0F ,Rx FIFO 0 Full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 8.--13. " F0GI ,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,Rx FIFO 0 Fill Level" group.long 0xA8++0x0B line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "RXBC,Rx Buffer Configuration Register" hexmask.long.word 0x04 2.--15. 0x04 " RBSA ,Rx Buffer Start Address" line.long 0x08 "RXF1C,Rx FIFO 1 Configuration Register" rbitfld.long 0x08 31. " F1OM ,FIFO 1 Operation Mode" "Blocking,Overwrite" hexmask.long.byte 0x08 24.--30. 1. " F1WM ,Rx FIFO 1 Watermark" hexmask.long.byte 0x08 16.--22. 1. " F1S ,Rx FIFO 1 Size" hexmask.long.word 0x08 2.--15. 0x04 " F1SA ,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,Rx FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug Message Status" "Idle,A received,A/B received,A/B/C received" bitfld.long 0x00 25. " RF1L ,Rx FIFO 1 Message Lost" "Not lost,Lost" bitfld.long 0x00 24. " F1F ,Rx FIFO 1 Full" "Not full,Full" bitfld.long 0x00 16.--21. " F1PI ,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 8.--13. " F1GI ,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,Rx FIFO 1 Fill Level" group.long 0xB8++0x0B line.long 0x00 "RXF1A,Rx FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "RXESC,Rx Buffer / FIFO Element Size Configuration Register" bitfld.long 0x04 8.--10. " RBDS ,Rx Buffer Data Field Size" "8 byte,12 byte,16 byte,20 byte,24 byte,32 byte,48 byte,64 byte" bitfld.long 0x04 4.--6. " F1DS ,Rx FIFO 1 Data Field Size" "8 byte,12 byte,16 byte,20 byte,24 byte,32 byte,48 byte,64 byte" bitfld.long 0x04 0.--2. " F0DS ,Rx FIFO 0 Data Field Size" "8 byte,12 byte,16 byte,20 byte,24 byte,32 byte,48 byte,64 byte" line.long 0x08 "TXBC,Tx Buffer Configuration Register" bitfld.long 0x08 30. " TFQM ,Rx FIFO 0 Data Field Size" "FIFO,Queue" bitfld.long 0x08 24.--29. " TFQS ,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x08 16.--21. " NDTB ,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x08 2.--15. 0x04 " TBSA ,Tx Buffers Start Address" rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,Tx FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,Tx FIFO/Queue Full" "Not full,Full" bitfld.long 0x00 16.--20. " TFQPI ,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,Tx FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TFFl ,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x0C8++0x03 line.long 0x00 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x00 0.--2. " TBDS ,Tx Buffer Data Field Size" "8 byte,12 byte,16 byte,20 byte,24 byte,32 byte,48 byte,64 byte" rgroup.long 0x0CC++0x03 line.long 0x00 "TXBRP,Tx Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission Request Pending Tx Buffer 31" "Not pending,Pending" bitfld.long 0x00 30. " TRP[30] ,Transmission Request Pending Tx Buffer 30" "Not pending,Pending" bitfld.long 0x00 29. " TRP[29] ,Transmission Request Pending Tx Buffer 29" "Not pending,Pending" bitfld.long 0x00 28. " TRP[28] ,Transmission Request Pending Tx Buffer 28" "Not pending,Pending" textline " " bitfld.long 0x00 27. " TRP[27] ,Transmission Request Pending Tx Buffer 27" "Not pending,Pending" bitfld.long 0x00 26. " TRP[26] ,Transmission Request Pending Tx Buffer 26" "Not pending,Pending" bitfld.long 0x00 25. " TRP[25] ,Transmission Request Pending Tx Buffer 25" "Not pending,Pending" bitfld.long 0x00 24. " TRP[24] ,Transmission Request Pending Tx Buffer 24" "Not pending,Pending" textline " " bitfld.long 0x00 23. " TRP[23] ,Transmission Request Pending Tx Buffer 23" "Not pending,Pending" bitfld.long 0x00 22. " TRP[22] ,Transmission Request Pending Tx Buffer 22" "Not pending,Pending" bitfld.long 0x00 21. " TRP[21] ,Transmission Request Pending Tx Buffer 21" "Not pending,Pending" bitfld.long 0x00 20. " TRP[20] ,Transmission Request Pending Tx Buffer 20" "Not pending,Pending" textline " " bitfld.long 0x00 19. " TRP[19] ,Transmission Request Pending Tx Buffer 19" "Not pending,Pending" bitfld.long 0x00 18. " TRP[18] ,Transmission Request Pending Tx Buffer 18" "Not pending,Pending" bitfld.long 0x00 17. " TRP[17] ,Transmission Request Pending Tx Buffer 17" "Not pending,Pending" bitfld.long 0x00 16. " TRP[16] ,Transmission Request Pending Tx Buffer 16" "Not pending,Pending" textline " " bitfld.long 0x00 15. " TRP[15] ,Transmission Request Pending Tx Buffer 15" "Not pending,Pending" bitfld.long 0x00 14. " TRP[14] ,Transmission Request Pending Tx Buffer 14" "Not pending,Pending" bitfld.long 0x00 13. " TRP[13] ,Transmission Request Pending Tx Buffer 13" "Not pending,Pending" bitfld.long 0x00 12. " TRP[12] ,Transmission Request Pending Tx Buffer 12" "Not pending,Pending" textline " " bitfld.long 0x00 11. " TRP[11] ,Transmission Request Pending Tx Buffer 11" "Not pending,Pending" bitfld.long 0x00 10. " TRP[10] ,Transmission Request Pending Tx Buffer 10" "Not pending,Pending" bitfld.long 0x00 9. " TRP[9] ,Transmission Request Pending Tx Buffer 9" "Not pending,Pending" bitfld.long 0x00 8. " TRP[8] ,Transmission Request Pending Tx Buffer 8" "Not pending,Pending" textline " " bitfld.long 0x00 7. " TRP[7] ,Transmission Request Pending Tx Buffer 7" "Not pending,Pending" bitfld.long 0x00 6. " TRP[6] ,Transmission Request Pending Tx Buffer 6" "Not pending,Pending" bitfld.long 0x00 5. " TRP[5] ,Transmission Request Pending Tx Buffer 5" "Not pending,Pending" bitfld.long 0x00 4. " TRP[4] ,Transmission Request Pending Tx Buffer 4" "Not pending,Pending" textline " " bitfld.long 0x00 3. " TRP[3] ,Transmission Request Pending Tx Buffer 3" "Not pending,Pending" bitfld.long 0x00 2. " TRP[2] ,Transmission Request Pending Tx Buffer 2" "Not pending,Pending" bitfld.long 0x00 1. " TRP[1] ,Transmission Request Pending Tx Buffer 1" "Not pending,Pending" bitfld.long 0x00 0. " TRP[0] ,Transmission Request Pending Tx Buffer 0" "Not pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,Tx Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request Tx Buffer 31" "Not requested,Requested" bitfld.long 0x00 30. " AR[30] ,Add request Tx Buffer 30" "Not requested,Requested" bitfld.long 0x00 29. " AR[29] ,Add request Tx Buffer 29" "Not requested,Requested" bitfld.long 0x00 28. " AR[28] ,Add request Tx Buffer 28" "Not requested,Requested" textline " " bitfld.long 0x00 27. " AR[27] ,Add request Tx Buffer 27" "Not requested,Requested" bitfld.long 0x00 26. " AR[26] ,Add request Tx Buffer 26" "Not requested,Requested" bitfld.long 0x00 25. " AR[25] ,Add request Tx Buffer 25" "Not requested,Requested" bitfld.long 0x00 24. " AR[24] ,Add request Tx Buffer 24" "Not requested,Requested" textline " " bitfld.long 0x00 23. " AR[23] ,Add request Tx Buffer 23" "Not requested,Requested" bitfld.long 0x00 22. " AR[22] ,Add request Tx Buffer 22" "Not requested,Requested" bitfld.long 0x00 21. " AR[21] ,Add request Tx Buffer 21" "Not requested,Requested" bitfld.long 0x00 20. " AR[20] ,Add request Tx Buffer 20" "Not requested,Requested" textline " " bitfld.long 0x00 19. " AR[19] ,Add request Tx Buffer 19" "Not requested,Requested" bitfld.long 0x00 18. " AR[18] ,Add request Tx Buffer 18" "Not requested,Requested" bitfld.long 0x00 17. " AR[17] ,Add request Tx Buffer 17" "Not requested,Requested" bitfld.long 0x00 16. " AR[16] ,Add request Tx Buffer 16" "Not requested,Requested" textline " " bitfld.long 0x00 15. " AR[15] ,Add request Tx Buffer 15" "Not requested,Requested" bitfld.long 0x00 14. " AR[14] ,Add request Tx Buffer 14" "Not requested,Requested" bitfld.long 0x00 13. " AR[13] ,Add request Tx Buffer 13" "Not requested,Requested" bitfld.long 0x00 12. " AR[12] ,Add request Tx Buffer 12" "Not requested,Requested" textline " " bitfld.long 0x00 11. " AR[11] ,Add request Tx Buffer 11" "Not requested,Requested" bitfld.long 0x00 10. " AR[10] ,Add request Tx Buffer 10" "Not requested,Requested" bitfld.long 0x00 9. " AR[9] ,Add request Tx Buffer 9" "Not requested,Requested" bitfld.long 0x00 8. " AR[8] ,Add request Tx Buffer 8" "Not requested,Requested" textline " " bitfld.long 0x00 7. " AR[7] ,Add request Tx Buffer 7" "Not requested,Requested" bitfld.long 0x00 6. " AR[6] ,Add request Tx Buffer 6" "Not requested,Requested" bitfld.long 0x00 5. " AR[5] ,Add request Tx Buffer 5" "Not requested,Requested" bitfld.long 0x00 4. " AR[4] ,Add request Tx Buffer 4" "Not requested,Requested" textline " " bitfld.long 0x00 3. " AR[3] ,Add request Tx Buffer 3" "Not requested,Requested" bitfld.long 0x00 2. " AR[2] ,Add request Tx Buffer 2" "Not requested,Requested" bitfld.long 0x00 1. " AR[1] ,Add request Tx Buffer 1" "Not requested,Requested" bitfld.long 0x00 0. " AR[0] ,Add request Tx Buffer 0" "Not requested,Requested" line.long 0x04 "TXBCR,Tx Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request Tx Buffer 31" "Not requested,Requested" bitfld.long 0x04 30. " CR[30] ,Cancellation request Tx Buffer 30" "Not requested,Requested" bitfld.long 0x04 29. " CR[29] ,Cancellation request Tx Buffer 29" "Not requested,Requested" bitfld.long 0x04 28. " CR[28] ,Cancellation request Tx Buffer 28" "Not requested,Requested" textline " " bitfld.long 0x04 27. " CR[27] ,Cancellation request Tx Buffer 27" "Not requested,Requested" bitfld.long 0x04 26. " CR[26] ,Cancellation request Tx Buffer 26" "Not requested,Requested" bitfld.long 0x04 25. " CR[25] ,Cancellation request Tx Buffer 25" "Not requested,Requested" bitfld.long 0x04 24. " CR[24] ,Cancellation request Tx Buffer 24" "Not requested,Requested" textline " " bitfld.long 0x04 23. " CR[23] ,Cancellation request Tx Buffer 23" "Not requested,Requested" bitfld.long 0x04 22. " CR[22] ,Cancellation request Tx Buffer 22" "Not requested,Requested" bitfld.long 0x04 21. " CR[21] ,Cancellation request Tx Buffer 21" "Not requested,Requested" bitfld.long 0x04 20. " CR[20] ,Cancellation request Tx Buffer 20" "Not requested,Requested" textline " " bitfld.long 0x04 19. " CR[19] ,Cancellation request Tx Buffer 19" "Not requested,Requested" bitfld.long 0x04 18. " CR[18] ,Cancellation request Tx Buffer 18" "Not requested,Requested" bitfld.long 0x04 17. " CR[17] ,Cancellation request Tx Buffer 17" "Not requested,Requested" bitfld.long 0x04 16. " CR[16] ,Cancellation request Tx Buffer 16" "Not requested,Requested" textline " " bitfld.long 0x04 15. " CR[15] ,Cancellation request Tx Buffer 15" "Not requested,Requested" bitfld.long 0x04 14. " CR[14] ,Cancellation request Tx Buffer 14" "Not requested,Requested" bitfld.long 0x04 13. " CR[13] ,Cancellation request Tx Buffer 13" "Not requested,Requested" bitfld.long 0x04 12. " CR[12] ,Cancellation request Tx Buffer 12" "Not requested,Requested" textline " " bitfld.long 0x04 11. " CR[11] ,Cancellation request Tx Buffer 11" "Not requested,Requested" bitfld.long 0x04 10. " CR[10] ,Cancellation request Tx Buffer 10" "Not requested,Requested" bitfld.long 0x04 9. " CR[9] ,Cancellation request Tx Buffer 9" "Not requested,Requested" bitfld.long 0x04 8. " CR[8] ,Cancellation request Tx Buffer 8" "Not requested,Requested" textline " " bitfld.long 0x04 7. " CR[7] ,Cancellation request Tx Buffer 7" "Not requested,Requested" bitfld.long 0x04 6. " CR[6] ,Cancellation request Tx Buffer 6" "Not requested,Requested" bitfld.long 0x04 5. " CR[5] ,Cancellation request Tx Buffer 5" "Not requested,Requested" bitfld.long 0x04 4. " CR[4] ,Cancellation request Tx Buffer 4" "Not requested,Requested" textline " " bitfld.long 0x04 3. " CR[3] ,Cancellation request Tx Buffer 3" "Not requested,Requested" bitfld.long 0x04 2. " CR[2] ,Cancellation request Tx Buffer 2" "Not requested,Requested" bitfld.long 0x04 1. " CR[1] ,Cancellation request Tx Buffer 1" "Not requested,Requested" bitfld.long 0x04 0. " CR[0] ,Cancellation request Tx Buffer 0" "Not requested,Requested" rgroup.long 0xD8++0x07 line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission Occurred Tx Buffer 31" "Not occurred,Occurred" bitfld.long 0x00 30. " TO[30] ,Transmission Occurred Tx Buffer 30" "Not occurred,Occurred" bitfld.long 0x00 29. " TO[29] ,Transmission Occurred Tx Buffer 29" "Not occurred,Occurred" bitfld.long 0x00 28. " TO[28] ,Transmission Occurred Tx Buffer 28" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " TO[27] ,Transmission Occurred Tx Buffer 27" "Not occurred,Occurred" bitfld.long 0x00 26. " TO[26] ,Transmission Occurred Tx Buffer 26" "Not occurred,Occurred" bitfld.long 0x00 25. " TO[25] ,Transmission Occurred Tx Buffer 25" "Not occurred,Occurred" bitfld.long 0x00 24. " TO[24] ,Transmission Occurred Tx Buffer 24" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " TO[23] ,Transmission Occurred Tx Buffer 23" "Not occurred,Occurred" bitfld.long 0x00 22. " TO[22] ,Transmission Occurred Tx Buffer 22" "Not occurred,Occurred" bitfld.long 0x00 21. " TO[21] ,Transmission Occurred Tx Buffer 21" "Not occurred,Occurred" bitfld.long 0x00 20. " TO[20] ,Transmission Occurred Tx Buffer 20" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " TO[19] ,Transmission Occurred Tx Buffer 19" "Not occurred,Occurred" bitfld.long 0x00 18. " TO[18] ,Transmission Occurred Tx Buffer 18" "Not occurred,Occurred" bitfld.long 0x00 17. " TO[17] ,Transmission Occurred Tx Buffer 17" "Not occurred,Occurred" bitfld.long 0x00 16. " TO[16] ,Transmission Occurred Tx Buffer 16" "Not occurred,Occurred" textline " " bitfld.long 0x00 15. " TO[15] ,Transmission Occurred Tx Buffer 15" "Not occurred,Occurred" bitfld.long 0x00 14. " TO[14] ,Transmission Occurred Tx Buffer 14" "Not occurred,Occurred" bitfld.long 0x00 13. " TO[13] ,Transmission Occurred Tx Buffer 13" "Not occurred,Occurred" bitfld.long 0x00 12. " TO[12] ,Transmission Occurred Tx Buffer 12" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " TO[11] ,Transmission Occurred Tx Buffer 11" "Not occurred,Occurred" bitfld.long 0x00 10. " TO[10] ,Transmission Occurred Tx Buffer 10" "Not occurred,Occurred" bitfld.long 0x00 9. " TO[9] ,Transmission Occurred Tx Buffer 9" "Not occurred,Occurred" bitfld.long 0x00 8. " TO[8] ,Transmission Occurred Tx Buffer 8" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " TO[7] ,Transmission Occurred Tx Buffer 7" "Not occurred,Occurred" bitfld.long 0x00 6. " TO[6] ,Transmission Occurred Tx Buffer 6" "Not occurred,Occurred" bitfld.long 0x00 5. " TO[5] ,Transmission Occurred Tx Buffer 5" "Not occurred,Occurred" bitfld.long 0x00 4. " TO[4] ,Transmission Occurred Tx Buffer 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " TO[3] ,Transmission Occurred Tx Buffer 3" "Not occurred,Occurred" bitfld.long 0x00 2. " TO[2] ,Transmission Occurred Tx Buffer 2" "Not occurred,Occurred" bitfld.long 0x00 1. " TO[1] ,Transmission Occurred Tx Buffer 1" "Not occurred,Occurred" bitfld.long 0x00 0. " TO[0] ,Transmission Occurred Tx Buffer 0" "Not occurred,Occurred" line.long 0x04 "TXBCF,Tx Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation Finished Tx Buffer 31" "Not finished,Finished" bitfld.long 0x04 30. " CF[30] ,Cancellation Finished Tx Buffer 30" "Not finished,Finished" bitfld.long 0x04 29. " CF[29] ,Cancellation Finished Tx Buffer 29" "Not finished,Finished" bitfld.long 0x04 28. " CF[28] ,Cancellation Finished Tx Buffer 28" "Not finished,Finished" textline " " bitfld.long 0x04 27. " CF[27] ,Cancellation Finished Tx Buffer 27" "Not finished,Finished" bitfld.long 0x04 26. " CF[26] ,Cancellation Finished Tx Buffer 26" "Not finished,Finished" bitfld.long 0x04 25. " CF[25] ,Cancellation Finished Tx Buffer 25" "Not finished,Finished" bitfld.long 0x04 24. " CF[24] ,Cancellation Finished Tx Buffer 24" "Not finished,Finished" textline " " bitfld.long 0x04 23. " CF[23] ,Cancellation Finished Tx Buffer 23" "Not finished,Finished" bitfld.long 0x04 22. " CF[22] ,Cancellation Finished Tx Buffer 22" "Not finished,Finished" bitfld.long 0x04 21. " CF[21] ,Cancellation Finished Tx Buffer 21" "Not finished,Finished" bitfld.long 0x04 20. " CF[20] ,Cancellation Finished Tx Buffer 20" "Not finished,Finished" textline " " bitfld.long 0x04 19. " CF[19] ,Cancellation Finished Tx Buffer 19" "Not finished,Finished" bitfld.long 0x04 18. " CF[18] ,Cancellation Finished Tx Buffer 18" "Not finished,Finished" bitfld.long 0x04 17. " CF[17] ,Cancellation Finished Tx Buffer 17" "Not finished,Finished" bitfld.long 0x04 16. " CF[16] ,Cancellation Finished Tx Buffer 16" "Not finished,Finished" textline " " bitfld.long 0x04 15. " CF[15] ,Cancellation Finished Tx Buffer 15" "Not finished,Finished" bitfld.long 0x04 14. " CF[14] ,Cancellation Finished Tx Buffer 14" "Not finished,Finished" bitfld.long 0x04 13. " CF[13] ,Cancellation Finished Tx Buffer 13" "Not finished,Finished" bitfld.long 0x04 12. " CF[12] ,Cancellation Finished Tx Buffer 12" "Not finished,Finished" textline " " bitfld.long 0x04 11. " CF[11] ,Cancellation Finished Tx Buffer 11" "Not finished,Finished" bitfld.long 0x04 10. " CF[10] ,Cancellation Finished Tx Buffer 10" "Not finished,Finished" bitfld.long 0x04 9. " CF[9] ,Cancellation Finished Tx Buffer 9" "Not finished,Finished" bitfld.long 0x04 8. " CF[8] ,Cancellation Finished Tx Buffer 8" "Not finished,Finished" textline " " bitfld.long 0x04 7. " CF[7] ,Cancellation Finished Tx Buffer 7" "Not finished,Finished" bitfld.long 0x04 6. " CF[6] ,Cancellation Finished Tx Buffer 6" "Not finished,Finished" bitfld.long 0x04 5. " CF[5] ,Cancellation Finished Tx Buffer 5" "Not finished,Finished" bitfld.long 0x04 4. " CF[4] ,Cancellation Finished Tx Buffer 4" "Not finished,Finished" textline " " bitfld.long 0x04 3. " CF[3] ,Cancellation Finished Tx Buffer 3" "Not finished,Finished" bitfld.long 0x04 2. " CF[2] ,Cancellation Finished Tx Buffer 2" "Not finished,Finished" bitfld.long 0x04 1. " CF[1] ,Cancellation Finished Tx Buffer 1" "Not finished,Finished" bitfld.long 0x04 0. " CF[0] ,Cancellation Finished Tx Buffer 0" "Not finished,Finished" group.long 0xE0++0x07 line.long 0x00 "TXBTIE,Tx Buffer Transmission Interrupt Enable Register" bitfld.long 0x00 31. " TIE[31] ,Transmission Interrupt Enable Tx Buffer 31" "Disabled,Enabled" bitfld.long 0x00 30. " TIE[30] ,Transmission Interrupt Enable Tx Buffer 30" "Disabled,Enabled" bitfld.long 0x00 29. " TIE[29] ,Transmission Interrupt Enable Tx Buffer 29" "Disabled,Enabled" bitfld.long 0x00 28. " TIE[28] ,Transmission Interrupt Enable Tx Buffer 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " TIE[27] ,Transmission Interrupt Enable Tx Buffer 27" "Disabled,Enabled" bitfld.long 0x00 26. " TIE[26] ,Transmission Interrupt Enable Tx Buffer 26" "Disabled,Enabled" bitfld.long 0x00 25. " TIE[25] ,Transmission Interrupt Enable Tx Buffer 25" "Disabled,Enabled" bitfld.long 0x00 24. " TIE[24] ,Transmission Interrupt Enable Tx Buffer 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " TIE[23] ,Transmission Interrupt Enable Tx Buffer 23" "Disabled,Enabled" bitfld.long 0x00 22. " TIE[22] ,Transmission Interrupt Enable Tx Buffer 22" "Disabled,Enabled" bitfld.long 0x00 21. " TIE[21] ,Transmission Interrupt Enable Tx Buffer 21" "Disabled,Enabled" bitfld.long 0x00 20. " TIE[20] ,Transmission Interrupt Enable Tx Buffer 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " TIE[19] ,Transmission Interrupt Enable Tx Buffer 19" "Disabled,Enabled" bitfld.long 0x00 18. " TIE[18] ,Transmission Interrupt Enable Tx Buffer 18" "Disabled,Enabled" bitfld.long 0x00 17. " TIE[17] ,Transmission Interrupt Enable Tx Buffer 17" "Disabled,Enabled" bitfld.long 0x00 16. " TIE[16] ,Transmission Interrupt Enable Tx Buffer 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " TIE[15] ,Transmission Interrupt Enable Tx Buffer 15" "Disabled,Enabled" bitfld.long 0x00 14. " TIE[14] ,Transmission Interrupt Enable Tx Buffer 14" "Disabled,Enabled" bitfld.long 0x00 13. " TIE[13] ,Transmission Interrupt Enable Tx Buffer 13" "Disabled,Enabled" bitfld.long 0x00 12. " TIE[12] ,Transmission Interrupt Enable Tx Buffer 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TIE[11] ,Transmission Interrupt Enable Tx Buffer 11" "Disabled,Enabled" bitfld.long 0x00 10. " TIE[10] ,Transmission Interrupt Enable Tx Buffer 10" "Disabled,Enabled" bitfld.long 0x00 9. " TIE[9] ,Transmission Interrupt Enable Tx Buffer 9" "Disabled,Enabled" bitfld.long 0x00 8. " TIE[8] ,Transmission Interrupt Enable Tx Buffer 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TIE[7] ,Transmission Interrupt Enable Tx Buffer 7" "Disabled,Enabled" bitfld.long 0x00 6. " TIE[6] ,Transmission Interrupt Enable Tx Buffer 6" "Disabled,Enabled" bitfld.long 0x00 5. " TIE[5] ,Transmission Interrupt Enable Tx Buffer 5" "Disabled,Enabled" bitfld.long 0x00 4. " TIE[4] ,Transmission Interrupt Enable Tx Buffer 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TIE[3] ,Transmission Interrupt Enable Tx Buffer 3" "Disabled,Enabled" bitfld.long 0x00 2. " TIE[2] ,Transmission Interrupt Enable Tx Buffer 2" "Disabled,Enabled" bitfld.long 0x00 1. " TIE[1] ,Transmission Interrupt Enable Tx Buffer 1" "Disabled,Enabled" bitfld.long 0x00 0. " TIE[0] ,Transmission Interrupt Enable Tx Buffer 0" "Disabled,Enabled" line.long 0x04 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x04 31. " CFIE[31] ,Cancellation Finished Interrupt Enable Tx Buffer 31" "Disabled,Enabled" bitfld.long 0x04 30. " CFIE[30] ,Cancellation Finished Interrupt Enable Tx Buffer 30" "Disabled,Enabled" bitfld.long 0x04 29. " CFIE[29] ,Cancellation Finished Interrupt Enable Tx Buffer 29" "Disabled,Enabled" bitfld.long 0x04 28. " CFIE[28] ,Cancellation Finished Interrupt Enable Tx Buffer 28" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " CFIE[27] ,Cancellation Finished Interrupt Enable Tx Buffer 27" "Disabled,Enabled" bitfld.long 0x04 26. " CFIE[26] ,Cancellation Finished Interrupt Enable Tx Buffer 26" "Disabled,Enabled" bitfld.long 0x04 25. " CFIE[25] ,Cancellation Finished Interrupt Enable Tx Buffer 25" "Disabled,Enabled" bitfld.long 0x04 24. " CFIE[24] ,Cancellation Finished Interrupt Enable Tx Buffer 24" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " CFIE[23] ,Cancellation Finished Interrupt Enable Tx Buffer 23" "Disabled,Enabled" bitfld.long 0x04 22. " CFIE[22] ,Cancellation Finished Interrupt Enable Tx Buffer 22" "Disabled,Enabled" bitfld.long 0x04 21. " CFIE[21] ,Cancellation Finished Interrupt Enable Tx Buffer 21" "Disabled,Enabled" bitfld.long 0x04 20. " CFIE[20] ,Cancellation Finished Interrupt Enable Tx Buffer 20" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " CFIE[19] ,Cancellation Finished Interrupt Enable Tx Buffer 19" "Disabled,Enabled" bitfld.long 0x04 18. " CFIE[18] ,Cancellation Finished Interrupt Enable Tx Buffer 18" "Disabled,Enabled" bitfld.long 0x04 17. " CFIE[17] ,Cancellation Finished Interrupt Enable Tx Buffer 17" "Disabled,Enabled" bitfld.long 0x04 16. " CFIE[16] ,Cancellation Finished Interrupt Enable Tx Buffer 16" "Disabled,Enabled" textline " " bitfld.long 0x04 15. " CFIE[15] ,Cancellation Finished Interrupt Enable Tx Buffer 15" "Disabled,Enabled" bitfld.long 0x04 14. " CFIE[14] ,Cancellation Finished Interrupt Enable Tx Buffer 14" "Disabled,Enabled" bitfld.long 0x04 13. " CFIE[13] ,Cancellation Finished Interrupt Enable Tx Buffer 13" "Disabled,Enabled" bitfld.long 0x04 12. " CFIE[12] ,Cancellation Finished Interrupt Enable Tx Buffer 12" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " CFIE[11] ,Cancellation Finished Interrupt Enable Tx Buffer 11" "Disabled,Enabled" bitfld.long 0x04 10. " CFIE[10] ,Cancellation Finished Interrupt Enable Tx Buffer 10" "Disabled,Enabled" bitfld.long 0x04 9. " CFIE[9] ,Cancellation Finished Interrupt Enable Tx Buffer 9" "Disabled,Enabled" bitfld.long 0x04 8. " CFIE[8] ,Cancellation Finished Interrupt Enable Tx Buffer 8" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " CFIE[7] ,Cancellation Finished Interrupt Enable Tx Buffer 7" "Disabled,Enabled" bitfld.long 0x04 6. " CFIE[6] ,Cancellation Finished Interrupt Enable Tx Buffer 6" "Disabled,Enabled" bitfld.long 0x04 5. " CFIE[5] ,Cancellation Finished Interrupt Enable Tx Buffer 5" "Disabled,Enabled" bitfld.long 0x04 4. " CFIE[4] ,Cancellation Finished Interrupt Enable Tx Buffer 4" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " CFIE[3] ,Cancellation Finished Interrupt Enable Tx Buffer 3" "Disabled,Enabled" bitfld.long 0x04 2. " CFIE[2] ,Cancellation Finished Interrupt Enable Tx Buffer 2" "Disabled,Enabled" bitfld.long 0x04 1. " CFIE[1] ,Cancellation Finished Interrupt Enable Tx Buffer 1" "Disabled,Enabled" bitfld.long 0x04 0. " CFIE[0] ,Cancellation Finished Interrupt Enable Tx Buffer 0" "Disabled,Enabled" group.long 0xF0++0x03 line.long 0x00 "TXEFC,Tx Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x00 16.--21. " EFS ,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO Size Address" rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,Tx Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,Tx Event FIFO Element Lost" "Not lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO Full" "Not full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " EFGI ,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" group.long 0xF8++0x03 line.long 0x00 "TXEFA,Tx Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0b tree.end tree.end tree "MLB (MediaLB register)" tree "MediaLB Block Registers" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0218C000 else base ad:0x4218C000 endif width 10. group.long 0x00++0x03 line.long 0x00 "MLBC0,MediaLB Control 0 Register" bitfld.long 0x00 15.--17. " FCNT[2:0] ,The number of frames per sub-buffer for synchronous channels" "1,2,4,8,16,32,64," bitfld.long 0x00 14. " CTLRETRY ,Control Tx packet retry" "Skipped,Retransmitted" bitfld.long 0x00 12. " ASYRETRY ,Asynchronous Tx packet retry" "Skipped,Retransmitted" rbitfld.long 0x00 7. " MLBLK ,MediaLB lock status" "Unlocked,Locked" textline " " bitfld.long 0x00 2.--4. " MLBCLK[2:0] ,MediaLB clock speed select" "256xFs,512xFs,1024xFs,..." bitfld.long 0x00 0. " MLBEN ,MediaLB enable" "Disabled,Enabled" rgroup.long 0x0C++0x0B line.long 0x00 "MS0,MediaLB Channel Status 0 Register" bitfld.long 0x00 31. " MCS31 ,MediaLB channel status bit 31" "Low,High" bitfld.long 0x00 30. " MCS30 ,MediaLB channel status bit 30" "Low,High" bitfld.long 0x00 29. " MCS29 ,MediaLB channel status bit 29" "Low,High" bitfld.long 0x00 28. " MCS28 ,MediaLB channel status bit 28" "Low,High" textline " " bitfld.long 0x00 27. " MCS27 ,MediaLB channel status bit 27" "Low,High" bitfld.long 0x00 26. " MCS26 ,MediaLB channel status bit 26" "Low,High" bitfld.long 0x00 25. " MCS25 ,MediaLB channel status bit 25" "Low,High" bitfld.long 0x00 24. " MCS24 ,MediaLB channel status bit 24" "Low,High" textline " " bitfld.long 0x00 23. " MCS23 ,MediaLB channel status bit 23" "Low,High" bitfld.long 0x00 22. " MCS22 ,MediaLB channel status bit 22" "Low,High" bitfld.long 0x00 21. " MCS21 ,MediaLB channel status bit 21" "Low,High" bitfld.long 0x00 20. " MCS20 ,MediaLB channel status bit 20" "Low,High" textline " " bitfld.long 0x00 19. " MCS19 ,MediaLB channel status bit 19" "Low,High" bitfld.long 0x00 18. " MCS18 ,MediaLB channel status bit 18" "Low,High" bitfld.long 0x00 17. " MCS17 ,MediaLB channel status bit 17" "Low,High" bitfld.long 0x00 16. " MCS16 ,MediaLB channel status bit 16" "Low,High" textline " " bitfld.long 0x00 15. " MCS15 ,MediaLB channel status bit 15" "Low,High" bitfld.long 0x00 14. " MCS14 ,MediaLB channel status bit 14" "Low,High" bitfld.long 0x00 13. " MCS13 ,MediaLB channel status bit 13" "Low,High" bitfld.long 0x00 12. " MCS12 ,MediaLB channel status bit 12" "Low,High" textline " " bitfld.long 0x00 11. " MCS11 ,MediaLB channel status bit 11" "Low,High" bitfld.long 0x00 10. " MCS10 ,MediaLB channel status bit 10" "Low,High" bitfld.long 0x00 9. " MCS9 ,MediaLB channel status bit 9" "Low,High" bitfld.long 0x00 8. " MCS8 ,MediaLB channel status bit 8" "Low,High" textline " " bitfld.long 0x00 7. " MCS7 ,MediaLB channel status bit 7" "Low,High" bitfld.long 0x00 6. " MCS6 ,MediaLB channel status bit 6" "Low,High" bitfld.long 0x00 5. " MCS5 ,MediaLB channel status bit 5" "Low,High" bitfld.long 0x00 4. " MCS4 ,MediaLB channel status bit 4" "Low,High" textline " " bitfld.long 0x00 3. " MCS3 ,MediaLB channel status bit 3" "Low,High" bitfld.long 0x00 2. " MCS2 ,MediaLB channel status bit 2" "Low,High" bitfld.long 0x00 1. " MCS1 ,MediaLB channel status bit 1" "Low,High" bitfld.long 0x00 0. " MCS0 ,MediaLB channel status bit 0" "Low,High" line.long 0x04 "MLBPC2,MediaLB 6-pin Control 2 Register" bitfld.long 0x04 15. " MORCE ,Output reference clock (for SPDIF and ASRC) enable" "Enabled,Disabled" hexmask.long.byte 0x04 8.--14. 0x01 " MORCD ,Divider factor of MLB output reference clock" bitfld.long 0x04 0. " SDOPC ,MLB 3-pin interface: Signal/Data output phase control" "Rising edge,Falling edge" line.long 0x08 "MS1,MediaLB Channel Status1 Register" bitfld.long 0x08 31. " MCS63 ,MediaLB channel status bit 31" "Low,High" bitfld.long 0x08 30. " MCS62 ,MediaLB channel status bit 30" "Low,High" bitfld.long 0x08 29. " MCS61 ,MediaLB channel status bit 29" "Low,High" bitfld.long 0x08 28. " MCS60 ,MediaLB channel status bit 28" "Low,High" textline " " bitfld.long 0x08 27. " MCS59 ,MediaLB channel status bit 27" "Low,High" bitfld.long 0x08 26. " MCS58 ,MediaLB channel status bit 26" "Low,High" bitfld.long 0x08 25. " MCS57 ,MediaLB channel status bit 25" "Low,High" bitfld.long 0x08 24. " MCS56 ,MediaLB channel status bit 24" "Low,High" textline " " bitfld.long 0x08 23. " MCS55 ,MediaLB channel status bit 23" "Low,High" bitfld.long 0x08 22. " MCS54 ,MediaLB channel status bit 22" "Low,High" bitfld.long 0x08 21. " MCS53 ,MediaLB channel status bit 21" "Low,High" bitfld.long 0x08 20. " MCS52 ,MediaLB channel status bit 20" "Low,High" textline " " bitfld.long 0x08 19. " MCS51 ,MediaLB channel status bit 19" "Low,High" bitfld.long 0x08 18. " MCS50 ,MediaLB channel status bit 18" "Low,High" bitfld.long 0x08 17. " MCS49 ,MediaLB channel status bit 17" "Low,High" bitfld.long 0x08 16. " MCS48 ,MediaLB channel status bit 16" "Low,High" textline " " bitfld.long 0x08 15. " MCS47 ,MediaLB channel status bit 15" "Low,High" bitfld.long 0x08 14. " MCS46 ,MediaLB channel status bit 14" "Low,High" bitfld.long 0x08 13. " MCS45 ,MediaLB channel status bit 13" "Low,High" bitfld.long 0x08 12. " MCS44 ,MediaLB channel status bit 12" "Low,High" textline " " bitfld.long 0x08 11. " MCS43 ,MediaLB channel status bit 11" "Low,High" bitfld.long 0x08 10. " MCS42 ,MediaLB channel status bit 10" "Low,High" bitfld.long 0x08 9. " MCS41 ,MediaLB channel status bit 9" "Low,High" bitfld.long 0x08 8. " MCS40 ,MediaLB channel status bit 8" "Low,High" textline " " bitfld.long 0x08 7. " MCS39 ,MediaLB channel status bit 7" "Low,High" bitfld.long 0x08 6. " MC38 ,MediaLB channel status bit 6" "Low,High" bitfld.long 0x08 5. " MCS37 ,MediaLB channel status bit 5" "Low,High" bitfld.long 0x08 4. " MCS36 ,MediaLB channel status bit 4" "Low,High" textline " " bitfld.long 0x08 3. " MCS35 ,MediaLB channel status bit 3" "Low,High" bitfld.long 0x08 2. " MCS34 ,MediaLB channel status bit 2" "Low,High" bitfld.long 0x08 1. " MCS33 ,MediaLB channel status bit 1" "Low,High" bitfld.long 0x08 0. " MCS32 ,MediaLB channel status bit 0" "Low,High" group.long 0x020++0x03 line.long 0x00 "MSS,MediaLB System Status Register" bitfld.long 0x00 5. " SERVREQ ,Service request enabled" "Disabled,Enabled" rbitfld.long 0x00 4. " SWSYSCMD ,Software system command detected" "Not detected,Detected" rbitfld.long 0x00 3. " CSSYSCMD ,Channel scan system command detected" "Not detected,Detected" rbitfld.long 0x00 2. " ULKSYSCMD ,Network unlock system command detected" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " LKSYSCMD ,Network lock system command detected" "Not detected,Detected" rbitfld.long 0x00 0. " RSTSYSCMD ,Reset system command detected" "Not detected,Detected" rgroup.long 0x24++0x03 line.long 0x00 "MSD,MediaLB System Data Register" hexmask.long.byte 0x00 24.--31. 1. " SD3[7:0] ,System data (byte 3)" hexmask.long.byte 0x00 16.--23. 1. " SD2[7:0] ,System data (byte 2)" hexmask.long.byte 0x00 8.--15. 1. " SD1[7:0] ,System data (byte 1)" hexmask.long.byte 0x00 0.--7. 1. " SD0[7:0] ,System data (byte 0)" group.long 0x2C++0x03 line.long 0x00 "MIEN,MediaLB Interrupt Enable Register" bitfld.long 0x00 29. " CTX_BREAK ,Control Tx break enable" "Disabled,Enabled" bitfld.long 0x00 28. " CTX_PE ,Control Tx protocol error enable" "Disabled,Enabled" bitfld.long 0x00 27. " CTX_DONE ,Control Tx packet done enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " CRX_BREAK ,Control Rx break enable" "Disabled,Enabled" bitfld.long 0x00 25. " CRX_PE ,Control Rx protocol error enable" "Disabled,Enabled" bitfld.long 0x00 24. " CRX_DONE ,Control Rx packet done enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " ATX_BREAK ,Asynchronous Tx break enable" "Disabled,Enabled" bitfld.long 0x00 21. " ATX_PE ,Asynchronous Tx protocol error enable" "Disabled,Enabled" bitfld.long 0x00 20. " ATX_DONE ,Asynchronous Tx packet done enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " ARX_BREAK ,Asynchronous Rx break enable" "Disabled,Enabled" bitfld.long 0x00 18. " ARX_PE ,Asynchronous Rx protocol error enable" "Disabled,Enabled" bitfld.long 0x00 17. " ARX_DONE ,Asynchronous Rx done enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SYNC_PE ,Synchronous protocol error enable" "Disabled,Enabled" bitfld.long 0x00 1. " ISOC_BUFO ,Isochronous Rx buffer overflow enable" "Disabled,Enabled" bitfld.long 0x00 0. " ISOC_PE ,Isochronous Rx protocol error enable" "Disabled,Enabled" group.long 0x3C++0x03 line.long 0x00 "MLBC1,MediaLB Control 1 Register" hexmask.long.byte 0x00 8.--15. 1. " NDA[7:0] ,Node device address" rbitfld.long 0x00 7. " CLKM ,MediaLB clock missing status" "Toggled,Not toggled" rbitfld.long 0x00 6. " LOCK ,MediaLB lock error status" "Locked,Unlocked" width 12. tree.end tree "Internal HBI Registers" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0218C000 else base ad:0x4218C000 endif width 10. group.long 0x80++0x03 line.long 0x00 "HCTL,HBI Control Register" bitfld.long 0x00 15. " EN ,HBI enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST1 ,AGU1 software reset" "Active,Reset" bitfld.long 0x00 0. " RST0 ,AGU0 software reset" "Active,Reset" group.long 0x88++0x07 line.long 0x00 "HCMR0,HBI Channel Mask 0 Register" bitfld.long 0x00 31. " CHM31 ,Channel mask 31 bit" "Masked,Unmasked" bitfld.long 0x00 30. " CHM30 ,Channel mask 30 bit" "Masked,Unmasked" bitfld.long 0x00 29. " CHM29 ,Channel mask 29 bit" "Masked,Unmasked" bitfld.long 0x00 28. " CHM28 ,Channel mask 28 bit" "Masked,Unmasked" textline " " bitfld.long 0x00 27. " CHM27 ,Channel mask 27 bit" "Masked,Unmasked" bitfld.long 0x00 26. " CHM26 ,Channel mask 26 bit" "Masked,Unmasked" bitfld.long 0x00 25. " CHM25 ,Channel mask 25 bit" "Masked,Unmasked" bitfld.long 0x00 24. " CHM24 ,Channel mask 24 bit" "Masked,Unmasked" textline " " bitfld.long 0x00 23. " CHM23 ,Channel mask 23 bit" "Masked,Unmasked" bitfld.long 0x00 22. " CHM22 ,Channel mask 22 bit" "Masked,Unmasked" bitfld.long 0x00 21. " CHM21 ,Channel mask 21 bit" "Masked,Unmasked" bitfld.long 0x00 20. " CHM20 ,Channel mask 20 bit" "Masked,Unmasked" textline " " bitfld.long 0x00 19. " CHM19 ,Channel mask 19 bit" "Masked,Unmasked" bitfld.long 0x00 18. " CHM18 ,Channel mask 18 bit" "Masked,Unmasked" bitfld.long 0x00 17. " CHM17 ,Channel mask 17 bit" "Masked,Unmasked" bitfld.long 0x00 16. " CHM16 ,Channel mask 16 bit" "Masked,Unmasked" textline " " bitfld.long 0x00 15. " CHM15 ,Channel mask 15 bit" "Masked,Unmasked" bitfld.long 0x00 14. " CHM14 ,Channel mask 14 bit" "Masked,Unmasked" bitfld.long 0x00 13. " CHM13 ,Channel mask 13 bit" "Masked,Unmasked" bitfld.long 0x00 12. " CHM12 ,Channel mask 12 bit" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " CHM11 ,Channel mask 11 bit" "Masked,Unmasked" bitfld.long 0x00 10. " CHM10 ,Channel mask 10 bit" "Masked,Unmasked" bitfld.long 0x00 9. " CHM9 ,Channel mask 9 bit" "Masked,Unmasked" bitfld.long 0x00 8. " CHM8 ,Channel mask 8 bit" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " CHM7 ,Channel mask 7 bit" "Masked,Unmasked" bitfld.long 0x00 6. " CHM6 ,Channel mask 6 bit" "Masked,Unmasked" bitfld.long 0x00 5. " CHM5 ,Channel mask 5 bit" "Masked,Unmasked" bitfld.long 0x00 4. " CHM4 ,Channel mask 4 bit" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " CHM3 ,Channel mask 3 bit" "Masked,Unmasked" bitfld.long 0x00 2. " CHM2 ,Channel mask 2 bit" "Masked,Unmasked" bitfld.long 0x00 1. " CHM1 ,Channel mask 1 bit" "Masked,Unmasked" bitfld.long 0x00 0. " CHM0 ,Channel mask 0 bit" "Masked,Unmasked" line.long 0x04 "HCMR1,HBI Channel Mask 1 Register" bitfld.long 0x04 31. " CHM63 ,Channel mask 63 bit" "Masked,Unmasked" bitfld.long 0x04 30. " CHM62 ,Channel mask 62 bit" "Masked,Unmasked" bitfld.long 0x04 29. " CHM61 ,Channel mask 61 bit" "Masked,Unmasked" bitfld.long 0x04 28. " CHM60 ,Channel mask 60 bit" "Masked,Unmasked" textline " " bitfld.long 0x04 27. " CHM59 ,Channel mask 59 bit" "Masked,Unmasked" bitfld.long 0x04 26. " CHM58 ,Channel mask 58 bit" "Masked,Unmasked" bitfld.long 0x04 25. " CHM57 ,Channel mask 57 bit" "Masked,Unmasked" bitfld.long 0x04 24. " CHM56 ,Channel mask 56 bit" "Masked,Unmasked" textline " " bitfld.long 0x04 23. " CHM55 ,Channel mask 55 bit" "Masked,Unmasked" bitfld.long 0x04 22. " CHM54 ,Channel mask 54 bit" "Masked,Unmasked" bitfld.long 0x04 21. " CHM53 ,Channel mask 53 bit" "Masked,Unmasked" bitfld.long 0x04 20. " CHM52 ,Channel mask 52 bit" "Masked,Unmasked" textline " " bitfld.long 0x04 19. " CHM51 ,Channel mask 51 bit" "Masked,Unmasked" bitfld.long 0x04 18. " CHM50 ,Channel mask 50 bit" "Masked,Unmasked" bitfld.long 0x04 17. " CHM49 ,Channel mask 49 bit" "Masked,Unmasked" bitfld.long 0x04 16. " CHM48 ,Channel mask 48 bit" "Masked,Unmasked" textline " " bitfld.long 0x04 15. " CHM47 ,Channel mask 47 bit" "Masked,Unmasked" bitfld.long 0x04 14. " CHM46 ,Channel mask 46 bit" "Masked,Unmasked" bitfld.long 0x04 13. " CHM45 ,Channel mask 45 bit" "Masked,Unmasked" bitfld.long 0x04 12. " CHM44 ,Channel mask 44 bit" "Masked,Unmasked" textline " " bitfld.long 0x04 11. " CHM43 ,Channel mask 43 bit" "Masked,Unmasked" bitfld.long 0x04 10. " CHM42 ,Channel mask 42 bit" "Masked,Unmasked" bitfld.long 0x04 9. " CHM41 ,Channel mask 41 bit" "Masked,Unmasked" bitfld.long 0x04 8. " CHM40 ,Channel mask 40 bit" "Masked,Unmasked" textline " " bitfld.long 0x04 7. " CHM39 ,Channel mask 39 bit" "Masked,Unmasked" bitfld.long 0x04 6. " CHM38 ,Channel mask 38 bit" "Masked,Unmasked" bitfld.long 0x04 5. " CHM37 ,Channel mask 37 bit" "Masked,Unmasked" bitfld.long 0x04 4. " CHM36 ,Channel mask 36 bit" "Masked,Unmasked" textline " " bitfld.long 0x04 3. " CHM35 ,Channel mask 35 bit" "Masked,Unmasked" bitfld.long 0x04 2. " CHM34 ,Channel mask 34 bit" "Masked,Unmasked" bitfld.long 0x04 1. " CHM33 ,Channel mask 33 bit" "Masked,Unmasked" bitfld.long 0x04 0. " CHM32 ,Channel mask 32 bit" "Masked,Unmasked" rgroup.long 0x90++0x0F line.long 0x00 "HCER0,HBI Channel Error 0 Register" bitfld.long 0x00 31. " CERR31 ,Channel error 31 bit" "0,1" bitfld.long 0x00 30. " CERR30 ,Channel error 30 bit" "0,1" bitfld.long 0x00 29. " CERR29 ,Channel error 29 bit" "0,1" bitfld.long 0x00 28. " CERR28 ,Channel error 28 bit" "0,1" textline " " bitfld.long 0x00 27. " CERR27 ,Channel error 27 bit" "0,1" bitfld.long 0x00 26. " CERR26 ,Channel error 26 bit" "0,1" bitfld.long 0x00 25. " CERR25 ,Channel error 25 bit" "0,1" bitfld.long 0x00 24. " CERR24 ,Channel error 24 bit" "0,1" textline " " bitfld.long 0x00 23. " CERR23 ,Channel error 23 bit" "0,1" bitfld.long 0x00 22. " CERR22 ,Channel error 22 bit" "0,1" bitfld.long 0x00 21. " CERR21 ,Channel error 21 bit" "0,1" bitfld.long 0x00 20. " CERR20 ,Channel error 20 bit" "0,1" textline " " bitfld.long 0x00 19. " CERR19 ,Channel error 19 bit" "0,1" bitfld.long 0x00 18. " CERR18 ,Channel error 18 bit" "0,1" bitfld.long 0x00 17. " CERR17 ,Channel error 17 bit" "0,1" bitfld.long 0x00 16. " CERR16 ,Channel error 16 bit" "0,1" textline " " bitfld.long 0x00 15. " CERR15 ,Channel error 15 bit" "0,1" bitfld.long 0x00 14. " CERR14 ,Channel error 14 bit" "0,1" bitfld.long 0x00 13. " CERR13 ,Channel error 13 bit" "0,1" bitfld.long 0x00 12. " CERR12 ,Channel error 12 bit" "0,1" textline " " bitfld.long 0x00 11. " CERR11 ,Channel error 11 bit" "0,1" bitfld.long 0x00 10. " CERR10 ,Channel error 10 bit" "0,1" bitfld.long 0x00 9. " CERR9 ,Channel error 9 bit" "0,1" bitfld.long 0x00 8. " CERR8 ,Channel error 8 bit" "0,1" textline " " bitfld.long 0x00 7. " CERR7 ,Channel error 7 bit" "0,1" bitfld.long 0x00 6. " CERR6 ,Channel error 6 bit" "0,1" bitfld.long 0x00 5. " CERR5 ,Channel error 5 bit" "0,1" bitfld.long 0x00 4. " CERR4 ,Channel error 4 bit" "0,1" textline " " bitfld.long 0x00 3. " CERR3 ,Channel error 3 bit" "0,1" bitfld.long 0x00 2. " CERR2 ,Channel error 2 bit" "0,1" bitfld.long 0x00 1. " CERR1 ,Channel error 1 bit" "0,1" bitfld.long 0x00 0. " CERR0 ,Channel error 0 bit" "0,1" line.long 0x04 "HCER1,HBI Channel Error 1 Register" bitfld.long 0x04 31. " CERR63 ,Channel error 63 bit" "0,1" bitfld.long 0x04 30. " CERR62 ,Channel error 62 bit" "0,1" bitfld.long 0x04 29. " CERR61 ,Channel error 61 bit" "0,1" bitfld.long 0x04 28. " CERR60 ,Channel error 60 bit" "0,1" textline " " bitfld.long 0x04 27. " CERR59 ,Channel error 59 bit" "0,1" bitfld.long 0x04 26. " CERR58 ,Channel error 58 bit" "0,1" bitfld.long 0x04 25. " CERR57 ,Channel error 57 bit" "0,1" bitfld.long 0x04 24. " CERR56 ,Channel error 56 bit" "0,1" textline " " bitfld.long 0x04 23. " CERR55 ,Channel error 55 bit" "0,1" bitfld.long 0x04 22. " CERR54 ,Channel error 54 bit" "0,1" bitfld.long 0x04 21. " CERR53 ,Channel error 53 bit" "0,1" bitfld.long 0x04 20. " CERR52 ,Channel error 52 bit" "0,1" textline " " bitfld.long 0x04 19. " CERR51 ,Channel error 51 bit" "0,1" bitfld.long 0x04 18. " CERR50 ,Channel error 50 bit" "0,1" bitfld.long 0x04 17. " CERR49 ,Channel error 49 bit" "0,1" bitfld.long 0x04 16. " CERR48 ,Channel error 48 bit" "0,1" textline " " bitfld.long 0x04 15. " CERR47 ,Channel error 47 bit" "0,1" bitfld.long 0x04 14. " CERR46 ,Channel error 46 bit" "0,1" bitfld.long 0x04 13. " CERR45 ,Channel error 45 bit" "0,1" bitfld.long 0x04 12. " CERR44 ,Channel error 44 bit" "0,1" textline " " bitfld.long 0x04 11. " CERR43 ,Channel error 43 bit" "0,1" bitfld.long 0x04 10. " CERR42 ,Channel error 42 bit" "0,1" bitfld.long 0x04 9. " CERR41 ,Channel error 41 bit" "0,1" bitfld.long 0x04 8. " CERR40 ,Channel error 40 bit" "0,1" textline " " bitfld.long 0x04 7. " CERR39 ,Channel error 39 bit" "0,1" bitfld.long 0x04 6. " CERR38 ,Channel error 38 bit" "0,1" bitfld.long 0x04 5. " CERR37 ,Channel error 37 bit" "0,1" bitfld.long 0x04 4. " CERR36 ,Channel error 36 bit" "0,1" textline " " bitfld.long 0x04 3. " CERR35 ,Channel error 35 bit" "0,1" bitfld.long 0x04 2. " CERR34 ,Channel error 34 bit" "0,1" bitfld.long 0x04 1. " CERR33 ,Channel error 33 bit" "0,1" bitfld.long 0x04 0. " CERR32 ,Channel error 32 bit" "0,1" line.long 0x08 "HCBR0,HBI Channel Error 0 Register" bitfld.long 0x08 31. " CHB31 ,Channel busy 31 bit" "Idle,Busy" bitfld.long 0x08 30. " CHB30 ,Channel busy 30 bit" "Idle,Busy" bitfld.long 0x08 29. " CHB29 ,Channel busy 29 bit" "Idle,Busy" bitfld.long 0x08 28. " CHB28 ,Channel busy 28 bit" "Idle,Busy" textline " " bitfld.long 0x08 27. " CHB27 ,Channel busy 27 bit" "Idle,Busy" bitfld.long 0x08 26. " CHB26 ,Channel busy 26 bit" "Idle,Busy" bitfld.long 0x08 25. " CHB25 ,Channel busy 25 bit" "Idle,Busy" bitfld.long 0x08 24. " CHB24 ,Channel busy 24 bit" "Idle,Busy" textline " " bitfld.long 0x08 23. " CHB23 ,Channel busy 23 bit" "Idle,Busy" bitfld.long 0x08 22. " CHB22 ,Channel busy 22 bit" "Idle,Busy" bitfld.long 0x08 21. " CHB21 ,Channel busy 21 bit" "Idle,Busy" bitfld.long 0x08 20. " CHB20 ,Channel busy 20 bit" "Idle,Busy" textline " " bitfld.long 0x08 19. " CHB19 ,Channel busy 19 bit" "Idle,Busy" bitfld.long 0x08 18. " CHB18 ,Channel busy 18 bit" "Idle,Busy" bitfld.long 0x08 17. " CHB17 ,Channel busy 17 bit" "Idle,Busy" bitfld.long 0x08 16. " CHB16 ,Channel busy 16 bit" "Idle,Busy" textline " " bitfld.long 0x08 15. " CHB15 ,Channel busy 15 bit" "Idle,Busy" bitfld.long 0x08 14. " CHB14 ,Channel busy 14 bit" "Idle,Busy" bitfld.long 0x08 13. " CHB13 ,Channel busy 13 bit" "Idle,Busy" bitfld.long 0x08 12. " CHB12 ,Channel busy 12 bit" "Idle,Busy" textline " " bitfld.long 0x08 11. " CHB11 ,Channel busy 11 bit" "Idle,Busy" bitfld.long 0x08 10. " CHB10 ,Channel busy 10 bit" "Idle,Busy" bitfld.long 0x08 9. " CHB9 ,Channel busy 9 bit" "Idle,Busy" bitfld.long 0x08 8. " CHB8 ,Channel busy 8 bit" "Idle,Busy" textline " " bitfld.long 0x08 7. " CHB7 ,Channel busy 7 bit" "Idle,Busy" bitfld.long 0x08 6. " CHB6 ,Channel busy 6 bit" "Idle,Busy" bitfld.long 0x08 5. " CHB5 ,Channel busy 5 bit" "Idle,Busy" bitfld.long 0x08 4. " CHB4 ,Channel busy 4 bit" "Idle,Busy" textline " " bitfld.long 0x08 3. " CHB3 ,Channel busy 3 bit" "Idle,Busy" bitfld.long 0x08 2. " CHB2 ,Channel busy 2 bit" "Idle,Busy" bitfld.long 0x08 1. " CHB1 ,Channel busy 1 bit" "Idle,Busy" bitfld.long 0x08 0. " CHB0 ,Channel busy 0 bit" "Idle,Busy" line.long 0x0C "HCBR1,HBI Channel Error 1 Register" bitfld.long 0x0C 31. " CHB63 ,Channel busy 63 bit" "Idle,Busy" bitfld.long 0x0C 30. " CHB62 ,Channel busy 62 bit" "Idle,Busy" bitfld.long 0x0C 29. " CHB61 ,Channel busy 61 bit" "Idle,Busy" bitfld.long 0x0C 28. " CHB60 ,Channel busy 60 bit" "Idle,Busy" textline " " bitfld.long 0x0C 27. " CHB59 ,Channel busy 59 bit" "Idle,Busy" bitfld.long 0x0C 26. " CHB58 ,Channel busy 58 bit" "Idle,Busy" bitfld.long 0x0C 25. " CHB57 ,Channel busy 57 bit" "Idle,Busy" bitfld.long 0x0C 24. " CHB56 ,Channel busy 56 bit" "Idle,Busy" textline " " bitfld.long 0x0C 23. " CHB55 ,Channel busy 55 bit" "Idle,Busy" bitfld.long 0x0C 22. " CHB54 ,Channel busy 54 bit" "Idle,Busy" bitfld.long 0x0C 21. " CHB53 ,Channel busy 53 bit" "Idle,Busy" bitfld.long 0x0C 20. " CHB52 ,Channel busy 52 bit" "Idle,Busy" textline " " bitfld.long 0x0C 19. " CHB51 ,Channel busy 51 bit" "Idle,Busy" bitfld.long 0x0C 18. " CHB50 ,Channel busy 50 bit" "Idle,Busy" bitfld.long 0x0C 17. " CHB49 ,Channel busy 49 bit" "Idle,Busy" bitfld.long 0x0C 16. " CHB48 ,Channel busy 48 bit" "Idle,Busy" textline " " bitfld.long 0x0C 15. " CHB47 ,Channel busy 47 bit" "Idle,Busy" bitfld.long 0x0C 14. " CHB46 ,Channel busy 46 bit" "Idle,Busy" bitfld.long 0x0C 13. " CHB45 ,Channel busy 45 bit" "Idle,Busy" bitfld.long 0x0C 12. " CHB44 ,Channel busy 44 bit" "Idle,Busy" textline " " bitfld.long 0x0C 11. " CHB43 ,Channel busy 43 bit" "Idle,Busy" bitfld.long 0x0C 10. " CHB42 ,Channel busy 42 bit" "Idle,Busy" bitfld.long 0x0C 9. " CHB41 ,Channel busy 41 bit" "Idle,Busy" bitfld.long 0x0C 8. " CHB40 ,Channel busy 40 bit" "Idle,Busy" textline " " bitfld.long 0x0C 7. " CHB39 ,Channel busy 39 bit" "Idle,Busy" bitfld.long 0x0C 6. " CHB38 ,Channel busy 38 bit" "Idle,Busy" bitfld.long 0x0C 5. " CHB37 ,Channel busy 37 bit" "Idle,Busy" bitfld.long 0x0C 4. " CHB36 ,Channel busy 36 bit" "Idle,Busy" textline " " bitfld.long 0x0C 3. " CHB35 ,Channel busy 35 bit" "Idle,Busy" bitfld.long 0x0C 2. " CHB34 ,Channel busy 34 bit" "Idle,Busy" bitfld.long 0x0C 1. " CHB33 ,Channel busy 33 bit" "Idle,Busy" bitfld.long 0x0C 0. " CHB32 ,Channel busy 32 bit" "Idle,Busy" width 0x0b tree.end tree "CTR Transfers Registers" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0218C000 width 10. group.long 0xC0++0x1F line.long 0x00 "MDAT0,MIF Data 0 Register" bitfld.long 0x00 31. " DATA_31 ,Data bit 31" "0,1" bitfld.long 0x00 30. " DATA_30 ,Data bit 30" "0,1" bitfld.long 0x00 29. " DATA_29 ,Data bit 29" "0,1" bitfld.long 0x00 28. " DATA_28 ,Data bit 28" "0,1" textline " " bitfld.long 0x00 27. " DATA_27 ,Data bit 27" "0,1" bitfld.long 0x00 26. " DATA_26 ,Data bit 26" "0,1" bitfld.long 0x00 25. " DATA_25 ,Data bit 25" "0,1" bitfld.long 0x00 24. " DATA_24 ,Data bit 24" "0,1" textline " " bitfld.long 0x00 23. " DATA_23 ,Data bit 23" "0,1" bitfld.long 0x00 22. " DATA_22 ,Data bit 22" "0,1" bitfld.long 0x00 21. " DATA_21 ,Data bit 21" "0,1" bitfld.long 0x00 20. " DATA_20 ,Data bit 20" "0,1" textline " " bitfld.long 0x00 19. " DATA_19 ,Data bit 19" "0,1" bitfld.long 0x00 18. " DATA_18 ,Data bit 18" "0,1" bitfld.long 0x00 17. " DATA_17 ,Data bit 17" "0,1" bitfld.long 0x00 16. " DATA_16 ,Data bit 16" "0,1" textline " " bitfld.long 0x00 15. " DATA_15 ,Data bit 15" "0,1" bitfld.long 0x00 14. " DATA_14 ,Data bit 14" "0,1" bitfld.long 0x00 13. " DATA_13 ,Data bit 13" "0,1" bitfld.long 0x00 12. " DATA_12 ,Data bit 12" "0,1" textline " " bitfld.long 0x00 11. " DATA_11 ,Data bit 11" "0,1" bitfld.long 0x00 10. " DATA_10 ,Data bit 10" "0,1" bitfld.long 0x00 9. " DATA_9 ,Data bit 9" "0,1" bitfld.long 0x00 8. " DATA_8 ,Data bit 8" "0,1" textline " " bitfld.long 0x00 7. " DATA_7 ,Data bit 7" "0,1" bitfld.long 0x00 6. " DATA_6 ,Data bit 6" "0,1" bitfld.long 0x00 5. " DATA_5 ,Data bit 5" "0,1" bitfld.long 0x00 4. " DATA_4 ,Data bit 4" "0,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Data bit 3" "0,1" bitfld.long 0x00 2. " DATA_2 ,Data bit 2" "0,1" bitfld.long 0x00 1. " DATA_1 ,Data bit 1" "0,1" bitfld.long 0x00 0. " DATA_0 ,Data bit 0" "0,1" line.long 0x04 "MDAT1,MIF Data 1 Register" bitfld.long 0x04 31. " DATA_63 ,Data bit 63" "0,1" bitfld.long 0x04 30. " DATA_62 ,Data bit 62" "0,1" bitfld.long 0x04 29. " DATA_61 ,Data bit 61" "0,1" bitfld.long 0x04 28. " DATA_60 ,Data bit 60" "0,1" textline " " bitfld.long 0x04 27. " DATA_59 ,Data bit 59" "0,1" bitfld.long 0x04 26. " DATA_58 ,Data bit 58" "0,1" bitfld.long 0x04 25. " DATA_57 ,Data bit 57" "0,1" bitfld.long 0x04 24. " DATA_56 ,Data bit 56" "0,1" textline " " bitfld.long 0x04 23. " DATA_55 ,Data bit 55" "0,1" bitfld.long 0x04 22. " DATA_54 ,Data bit 54" "0,1" bitfld.long 0x04 21. " DATA_53 ,Data bit 53" "0,1" bitfld.long 0x04 20. " DATA_52 ,Data bit 52" "0,1" textline " " bitfld.long 0x04 19. " DATA_51 ,Data bit 51" "0,1" bitfld.long 0x04 18. " DATA_50 ,Data bit 50" "0,1" bitfld.long 0x04 17. " DATA_49 ,Data bit 49" "0,1" bitfld.long 0x04 16. " DATA_48 ,Data bit 48" "0,1" textline " " bitfld.long 0x04 15. " DATA_47 ,Data bit 47" "0,1" bitfld.long 0x04 14. " DATA_46 ,Data bit 46" "0,1" bitfld.long 0x04 13. " DATA_45 ,Data bit 45" "0,1" bitfld.long 0x04 12. " DATA_44 ,Data bit 44" "0,1" textline " " bitfld.long 0x04 11. " DATA_43 ,Data bit 43" "0,1" bitfld.long 0x04 10. " DATA_42 ,Data bit 42" "0,1" bitfld.long 0x04 9. " DATA_41 ,Data bit 41" "0,1" bitfld.long 0x04 8. " DATA_40 ,Data bit 40" "0,1" textline " " bitfld.long 0x04 7. " DATA_39 ,Data bit 39" "0,1" bitfld.long 0x04 6. " DATA_38 ,Data bit 38" "0,1" bitfld.long 0x04 5. " DATA_37 ,Data bit 37" "0,1" bitfld.long 0x04 4. " DATA_36 ,Data bit 36" "0,1" textline " " bitfld.long 0x04 3. " DATA_35 ,Data bit 35" "0,1" bitfld.long 0x04 2. " DATA_34 ,Data bit 34" "0,1" bitfld.long 0x04 1. " DATA_33 ,Data bit 33" "0,1" bitfld.long 0x04 0. " DATA_32 ,Data bit 32" "0,1" line.long 0x08 "MDAT2,MIF Data 2 Register" bitfld.long 0x08 31. " DATA_95 ,Data bit 95" "0,1" bitfld.long 0x08 30. " DATA_94 ,Data bit 94" "0,1" bitfld.long 0x08 29. " DATA_93 ,Data bit 93" "0,1" bitfld.long 0x08 28. " DATA_92 ,Data bit 92" "0,1" textline " " bitfld.long 0x08 27. " DATA_91 ,Data bit 91" "0,1" bitfld.long 0x08 26. " DATA_90 ,Data bit 90" "0,1" bitfld.long 0x08 25. " DATA_89 ,Data bit 89" "0,1" bitfld.long 0x08 24. " DATA_88 ,Data bit 88" "0,1" textline " " bitfld.long 0x08 23. " DATA_87 ,Data bit 87" "0,1" bitfld.long 0x08 22. " DATA_86 ,Data bit 86" "0,1" bitfld.long 0x08 21. " DATA_85 ,Data bit 85" "0,1" bitfld.long 0x08 20. " DATA_84 ,Data bit 84" "0,1" textline " " bitfld.long 0x08 19. " DATA_83 ,Data bit 83" "0,1" bitfld.long 0x08 18. " DATA_82 ,Data bit 82" "0,1" bitfld.long 0x08 17. " DATA_81 ,Data bit 81" "0,1" bitfld.long 0x08 16. " DATA_80 ,Data bit 80" "0,1" textline " " bitfld.long 0x08 15. " DATA_79 ,Data bit 79" "0,1" bitfld.long 0x08 14. " DATA_78 ,Data bit 78" "0,1" bitfld.long 0x08 13. " DATA_77 ,Data bit 77" "0,1" bitfld.long 0x08 12. " DATA_76 ,Data bit 76" "0,1" textline " " bitfld.long 0x08 11. " DATA_75 ,Data bit 75" "0,1" bitfld.long 0x08 10. " DATA_74 ,Data bit 74" "0,1" bitfld.long 0x08 9. " DATA_73 ,Data bit 73" "0,1" bitfld.long 0x08 8. " DATA_72 ,Data bit 72" "0,1" textline " " bitfld.long 0x08 7. " DATA_71 ,Data bit 71" "0,1" bitfld.long 0x08 6. " DATA_70 ,Data bit 70" "0,1" bitfld.long 0x08 5. " DATA_69 ,Data bit 69" "0,1" bitfld.long 0x08 4. " DATA_68 ,Data bit 68" "0,1" textline " " bitfld.long 0x08 3. " DATA_67 ,Data bit 67" "0,1" bitfld.long 0x08 2. " DATA_66 ,Data bit 66" "0,1" bitfld.long 0x08 1. " DATA_65 ,Data bit 65" "0,1" bitfld.long 0x08 0. " DATA_64 ,Data bit 64" "0,1" line.long 0x0C "MDAT3,MIF Data 3 Register" bitfld.long 0x0C 31. " DATA_127 ,Data bit 127" "0,1" bitfld.long 0x0C 30. " DATA_126 ,Data bit 126" "0,1" bitfld.long 0x0C 29. " DATA_125 ,Data bit 125" "0,1" bitfld.long 0x0C 28. " DATA_124 ,Data bit 124" "0,1" textline " " bitfld.long 0x0C 27. " DATA_123 ,Data bit 123" "0,1" bitfld.long 0x0C 26. " DATA_122 ,Data bit 122" "0,1" bitfld.long 0x0C 25. " DATA_121 ,Data bit 121" "0,1" bitfld.long 0x0C 24. " DATA_120 ,Data bit 120" "0,1" textline " " bitfld.long 0x0C 23. " DATA_119 ,Data bit 119" "0,1" bitfld.long 0x0C 22. " DATA_118 ,Data bit 118" "0,1" bitfld.long 0x0C 21. " DATA_117 ,Data bit 117" "0,1" bitfld.long 0x0C 20. " DATA_116 ,Data bit 116" "0,1" textline " " bitfld.long 0x0C 19. " DATA_115 ,Data bit 115" "0,1" bitfld.long 0x0C 18. " DATA_114 ,Data bit 114" "0,1" bitfld.long 0x0C 17. " DATA_113 ,Data bit 113" "0,1" bitfld.long 0x0C 16. " DATA_112 ,Data bit 112" "0,1" textline " " bitfld.long 0x0C 15. " DATA_111 ,Data bit 111" "0,1" bitfld.long 0x0C 14. " DATA_110 ,Data bit 110" "0,1" bitfld.long 0x0C 13. " DATA_109 ,Data bit 109" "0,1" bitfld.long 0x0C 12. " DATA_108 ,Data bit 108" "0,1" textline " " bitfld.long 0x0C 11. " DATA_107 ,Data bit 107" "0,1" bitfld.long 0x0C 10. " DATA_106 ,Data bit 106" "0,1" bitfld.long 0x0C 9. " DATA_105 ,Data bit 105" "0,1" bitfld.long 0x0C 8. " DATA_104 ,Data bit 104" "0,1" textline " " bitfld.long 0x0C 7. " DATA_103 ,Data bit 103" "0,1" bitfld.long 0x0C 6. " DATA_102 ,Data bit 102" "0,1" bitfld.long 0x0C 5. " DATA_101 ,Data bit 101" "0,1" bitfld.long 0x0C 4. " DATA_100 ,Data bit 100" "0,1" textline " " bitfld.long 0x0C 3. " DATA_99 ,Data bit 99" "0,1" bitfld.long 0x0C 2. " DATA_98 ,Data bit 98" "0,1" bitfld.long 0x0C 1. " DATA_97 ,Data bit 97" "0,1" bitfld.long 0x0C 0. " DATA_96 ,Data bit 96" "0,1" line.long 0x10 "MDWE0,MIF Data Write Enable 0 Register" bitfld.long 0x10 31. " MASK_31 ,Write for CTR data bit 31" "Disabled,Enabled" bitfld.long 0x10 30. " MASK_30 ,Write for CTR data bit 30" "Disabled,Enabled" bitfld.long 0x10 29. " MASK_29 ,Write for CTR data bit 29" "Disabled,Enabled" bitfld.long 0x10 28. " MASK_28 ,Write for CTR data bit 28" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " MASK_27 ,Write for CTR data bit 27" "Disabled,Enabled" bitfld.long 0x10 26. " MASK_26 ,Write for CTR data bit 26" "Disabled,Enabled" bitfld.long 0x10 25. " MASK_25 ,Write for CTR data bit 25" "Disabled,Enabled" bitfld.long 0x10 24. " MASK_24 ,Write for CTR data bit 24" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " MASK_23 ,Write for CTR data bit 23" "Disabled,Enabled" bitfld.long 0x10 22. " MASK_22 ,Write for CTR data bit 22" "Disabled,Enabled" bitfld.long 0x10 21. " MASK_21 ,Write for CTR data bit 21" "Disabled,Enabled" bitfld.long 0x10 20. " MASK_20 ,Write for CTR data bit 20" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " MASK_19 ,Write for CTR data bit 19" "Disabled,Enabled" bitfld.long 0x10 18. " MASK_18 ,Write for CTR data bit 18" "Disabled,Enabled" bitfld.long 0x10 17. " MASK_17 ,Write for CTR data bit 17" "Disabled,Enabled" bitfld.long 0x10 16. " MASK_16 ,Write for CTR data bit 16" "Disabled,Enabled" textline " " bitfld.long 0x10 15. " MASK_15 ,Write for CTR data bit 15" "Disabled,Enabled" bitfld.long 0x10 14. " MASK_14 ,Write for CTR data bit 14" "Disabled,Enabled" bitfld.long 0x10 13. " MASK_13 ,Write for CTR data bit 13" "Disabled,Enabled" bitfld.long 0x10 12. " MASK_12 ,Write for CTR data bit 12" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " MASK_11 ,Write for CTR data bit 11" "Disabled,Enabled" bitfld.long 0x10 10. " MASK_10 ,Write for CTR data bit 10" "Disabled,Enabled" bitfld.long 0x10 9. " MASK_9 ,Write for CTR data bit 9" "Disabled,Enabled" bitfld.long 0x10 8. " MASK_8 ,Write for CTR data bit 8" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " MASK_7 ,Write for CTR data bit 7" "Disabled,Enabled" bitfld.long 0x10 6. " MASK_6 ,Write for CTR data bit 6" "Disabled,Enabled" bitfld.long 0x10 5. " MASK_5 ,Write for CTR data bit 5" "Disabled,Enabled" bitfld.long 0x10 4. " MASK_4 ,Write for CTR data bit 4" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " MASK_3 ,Write for CTR data bit 3" "Disabled,Enabled" bitfld.long 0x10 2. " MASK_2 ,Write for CTR data bit 2" "Disabled,Enabled" bitfld.long 0x10 1. " MASK_1 ,Write for CTR data bit 1" "Disabled,Enabled" bitfld.long 0x10 0. " MASK_0 ,Write for CTR data bit 0" "Disabled,Enabled" line.long 0x14 "MDWE1,MIF Data Write Enable 1 Register" bitfld.long 0x14 31. " MASK_63 ,Write for CTR data bit 63" "Disabled,Enabled" bitfld.long 0x14 30. " MASK_62 ,Write for CTR data bit 62" "Disabled,Enabled" bitfld.long 0x14 29. " MASK_61 ,Write for CTR data bit 61" "Disabled,Enabled" bitfld.long 0x14 28. " MASK_60 ,Write for CTR data bit 60" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " MASK_59 ,Write for CTR data bit 59" "Disabled,Enabled" bitfld.long 0x14 26. " MASK_58 ,Write for CTR data bit 58" "Disabled,Enabled" bitfld.long 0x14 25. " MASK_57 ,Write for CTR data bit 57" "Disabled,Enabled" bitfld.long 0x14 24. " MASK_56 ,Write for CTR data bit 56" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " MASK_55 ,Write for CTR data bit 55" "Disabled,Enabled" bitfld.long 0x14 22. " MASK_54 ,Write for CTR data bit 54" "Disabled,Enabled" bitfld.long 0x14 21. " MASK_53 ,Write for CTR data bit 53" "Disabled,Enabled" bitfld.long 0x14 20. " MASK_52 ,Write for CTR data bit 52" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " MASK_51 ,Write for CTR data bit 51" "Disabled,Enabled" bitfld.long 0x14 18. " MASK_50 ,Write for CTR data bit 50" "Disabled,Enabled" bitfld.long 0x14 17. " MASK_49 ,Write for CTR data bit 49" "Disabled,Enabled" bitfld.long 0x14 16. " MASK_48 ,Write for CTR data bit 48" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " MASK_47 ,Write for CTR data bit 47" "Disabled,Enabled" bitfld.long 0x14 14. " MASK_46 ,Write for CTR data bit 46" "Disabled,Enabled" bitfld.long 0x14 13. " MASK_45 ,Write for CTR data bit 45" "Disabled,Enabled" bitfld.long 0x14 12. " MASK_44 ,Write for CTR data bit 44" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " MASK_43 ,Write for CTR data bit 43" "Disabled,Enabled" bitfld.long 0x14 10. " MASK_42 ,Write for CTR data bit 42" "Disabled,Enabled" bitfld.long 0x14 9. " MASK_41 ,Write for CTR data bit 41" "Disabled,Enabled" bitfld.long 0x14 8. " MASK_40 ,Write for CTR data bit 40" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " MASK_39 ,Write for CTR data bit 39" "Disabled,Enabled" bitfld.long 0x14 6. " MASK_38 ,Write for CTR data bit 38" "Disabled,Enabled" bitfld.long 0x14 5. " MASK_37 ,Write for CTR data bit 37" "Disabled,Enabled" bitfld.long 0x14 4. " MASK_36 ,Write for CTR data bit 36" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " MASK_35 ,Write for CTR data bit 35" "Disabled,Enabled" bitfld.long 0x14 2. " MASK_34 ,Write for CTR data bit 34" "Disabled,Enabled" bitfld.long 0x14 1. " MASK_33 ,Write for CTR data bit 33" "Disabled,Enabled" bitfld.long 0x14 0. " MASK_32 ,Write for CTR data bit 32" "Disabled,Enabled" line.long 0x18 "MDWE2,MIF Data Write Enable 2 Register" bitfld.long 0x18 31. " MASK_95 ,Write for CTR data bit 95" "Disabled,Enabled" bitfld.long 0x18 30. " MASK_94 ,Write for CTR data bit 94" "Disabled,Enabled" bitfld.long 0x18 29. " MASK_93 ,Write for CTR data bit 93" "Disabled,Enabled" bitfld.long 0x18 28. " MASK_92 ,Write for CTR data bit 92" "Disabled,Enabled" textline " " bitfld.long 0x18 27. " MASK_91 ,Write for CTR data bit 91" "Disabled,Enabled" bitfld.long 0x18 26. " MASK_90 ,Write for CTR data bit 90" "Disabled,Enabled" bitfld.long 0x18 25. " MASK_89 ,Write for CTR data bit 89" "Disabled,Enabled" bitfld.long 0x18 24. " MASK_88 ,Write for CTR data bit 88" "Disabled,Enabled" textline " " bitfld.long 0x18 23. " MASK_87 ,Write for CTR data bit 87" "Disabled,Enabled" bitfld.long 0x18 22. " MASK_86 ,Write for CTR data bit 86" "Disabled,Enabled" bitfld.long 0x18 21. " MASK_85 ,Write for CTR data bit 85" "Disabled,Enabled" bitfld.long 0x18 20. " MASK_84 ,Write for CTR data bit 84" "Disabled,Enabled" textline " " bitfld.long 0x18 19. " MASK_83 ,Write for CTR data bit 83" "Disabled,Enabled" bitfld.long 0x18 18. " MASK_82 ,Write for CTR data bit 82" "Disabled,Enabled" bitfld.long 0x18 17. " MASK_81 ,Write for CTR data bit 81" "Disabled,Enabled" bitfld.long 0x18 16. " MASK_80 ,Write for CTR data bit 80" "Disabled,Enabled" textline " " bitfld.long 0x18 15. " MASK_79 ,Write for CTR data bit 79" "Disabled,Enabled" bitfld.long 0x18 14. " MASK_78 ,Write for CTR data bit 78" "Disabled,Enabled" bitfld.long 0x18 13. " MASK_77 ,Write for CTR data bit 77" "Disabled,Enabled" bitfld.long 0x18 12. " MASK_76 ,Write for CTR data bit 76" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " MASK_75 ,Write for CTR data bit 75" "Disabled,Enabled" bitfld.long 0x18 10. " MASK_74 ,Write for CTR data bit 74" "Disabled,Enabled" bitfld.long 0x18 9. " MASK_73 ,Write for CTR data bit 73" "Disabled,Enabled" bitfld.long 0x18 8. " MASK_72 ,Write for CTR data bit 72" "Disabled,Enabled" textline " " bitfld.long 0x18 7. " MASK_71 ,Write for CTR data bit 71" "Disabled,Enabled" bitfld.long 0x18 6. " MASK_70 ,Write for CTR data bit 70" "Disabled,Enabled" bitfld.long 0x18 5. " MASK_69 ,Write for CTR data bit 69" "Disabled,Enabled" bitfld.long 0x18 4. " MASK_68 ,Write for CTR data bit 68" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " MASK_67 ,Write for CTR data bit 67" "Disabled,Enabled" bitfld.long 0x18 2. " MASK_66 ,Write for CTR data bit 66" "Disabled,Enabled" bitfld.long 0x18 1. " MASK_65 ,Write for CTR data bit 65" "Disabled,Enabled" bitfld.long 0x18 0. " MASK_64 ,Write for CTR data bit 64" "Disabled,Enabled" line.long 0x1C "MDWE3,MIF Data Write Enable 3 Register" bitfld.long 0x1C 31. " MASK_127 ,Write for CTR data bit 127" "Disabled,Enabled" bitfld.long 0x1C 30. " MASK_126 ,Write for CTR data bit 126" "Disabled,Enabled" bitfld.long 0x1C 29. " MASK_125 ,Write for CTR data bit 125" "Disabled,Enabled" bitfld.long 0x1C 28. " MASK_124 ,Write for CTR data bit 124" "Disabled,Enabled" textline " " bitfld.long 0x1C 27. " MASK_123 ,Write for CTR data bit 123" "Disabled,Enabled" bitfld.long 0x1C 26. " MASK_122 ,Write for CTR data bit 122" "Disabled,Enabled" bitfld.long 0x1C 25. " MASK_121 ,Write for CTR data bit 121" "Disabled,Enabled" bitfld.long 0x1C 24. " MASK_120 ,Write for CTR data bit 120" "Disabled,Enabled" textline " " bitfld.long 0x1C 23. " MASK_119 ,Write for CTR data bit 119" "Disabled,Enabled" bitfld.long 0x1C 22. " MASK_118 ,Write for CTR data bit 118" "Disabled,Enabled" bitfld.long 0x1C 21. " MASK_117 ,Write for CTR data bit 117" "Disabled,Enabled" bitfld.long 0x1C 20. " MASK_116 ,Write for CTR data bit 116" "Disabled,Enabled" textline " " bitfld.long 0x1C 19. " MASK_115 ,Write for CTR data bit 115" "Disabled,Enabled" bitfld.long 0x1C 18. " MASK_114 ,Write for CTR data bit 114" "Disabled,Enabled" bitfld.long 0x1C 17. " MASK_113 ,Write for CTR data bit 113" "Disabled,Enabled" bitfld.long 0x1C 16. " MASK_112 ,Write for CTR data bit 112" "Disabled,Enabled" textline " " bitfld.long 0x1C 15. " MASK_111 ,Write for CTR data bit 111" "Disabled,Enabled" bitfld.long 0x1C 14. " MASK_110 ,Write for CTR data bit 110" "Disabled,Enabled" bitfld.long 0x1C 13. " MASK_109 ,Write for CTR data bit 109" "Disabled,Enabled" bitfld.long 0x1C 12. " MASK_108 ,Write for CTR data bit 108" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " MASK_107 ,Write for CTR data bit 107" "Disabled,Enabled" bitfld.long 0x1C 10. " MASK_106 ,Write for CTR data bit 106" "Disabled,Enabled" bitfld.long 0x1C 9. " MASK_105 ,Write for CTR data bit 105" "Disabled,Enabled" bitfld.long 0x1C 8. " MASK_104 ,Write for CTR data bit 104" "Disabled,Enabled" textline " " bitfld.long 0x1C 7. " MASK_103 ,Write for CTR data bit 103" "Disabled,Enabled" bitfld.long 0x1C 6. " MASK_102 ,Write for CTR data bit 102" "Disabled,Enabled" bitfld.long 0x1C 5. " MASK_101 ,Write for CTR data bit 101" "Disabled,Enabled" bitfld.long 0x1C 4. " MASK_100 ,Write for CTR data bit 100" "Disabled,Enabled" textline " " bitfld.long 0x1C 3. " MASK_99 ,Write for CTR data bit 99" "Disabled,Enabled" bitfld.long 0x1C 2. " MASK_98 ,Write for CTR data bit 98" "Disabled,Enabled" bitfld.long 0x1C 1. " MASK_97 ,Write for CTR data bit 97" "Disabled,Enabled" bitfld.long 0x1C 0. " MASK_96 ,Write for CTR data bit 96" "Disabled,Enabled" rgroup.long 0xE0++0x03 line.long 0x00 "MCTL,MIF Control Register" bitfld.long 0x00 0. " XCMP ,Transfer complete" "0,1" if (((per.l(ad:0x0218C000+0xE4))&0x40000000)==0x40000000) group.long 0xE4++0x03 line.long 0x00 "MADR,MIF Address Register" bitfld.long 0x00 31. " WNR ,Write-Not-Read selection" "Read,Write" bitfld.long 0x00 30. " TB ,Target location bit" "CTR,DBR" hexmask.long.word 0x00 0.--13. 1. " ADDR ,DBR address of 8-bit entry" else group.long 0xE4++0x03 line.long 0x00 "MADR,MIF Address Register" bitfld.long 0x00 31. " WNR ,Write-Not-Read selection" "Read,Write" bitfld.long 0x00 30. " TB ,Target location bit" "CTR,DBR" hexmask.long.byte 0x00 0.--7. 1. " ADDR ,CTR address of 128-bit entry" endif width 12. else base ad:0x4218C000 width 10. group.long 0xC0++0x1F line.long 0x00 "MDAT0,MIF Data 0 Register" bitfld.long 0x00 31. " DATA_31 ,Data bit 31" "0,1" bitfld.long 0x00 30. " DATA_30 ,Data bit 30" "0,1" bitfld.long 0x00 29. " DATA_29 ,Data bit 29" "0,1" bitfld.long 0x00 28. " DATA_28 ,Data bit 28" "0,1" textline " " bitfld.long 0x00 27. " DATA_27 ,Data bit 27" "0,1" bitfld.long 0x00 26. " DATA_26 ,Data bit 26" "0,1" bitfld.long 0x00 25. " DATA_25 ,Data bit 25" "0,1" bitfld.long 0x00 24. " DATA_24 ,Data bit 24" "0,1" textline " " bitfld.long 0x00 23. " DATA_23 ,Data bit 23" "0,1" bitfld.long 0x00 22. " DATA_22 ,Data bit 22" "0,1" bitfld.long 0x00 21. " DATA_21 ,Data bit 21" "0,1" bitfld.long 0x00 20. " DATA_20 ,Data bit 20" "0,1" textline " " bitfld.long 0x00 19. " DATA_19 ,Data bit 19" "0,1" bitfld.long 0x00 18. " DATA_18 ,Data bit 18" "0,1" bitfld.long 0x00 17. " DATA_17 ,Data bit 17" "0,1" bitfld.long 0x00 16. " DATA_16 ,Data bit 16" "0,1" textline " " bitfld.long 0x00 15. " DATA_15 ,Data bit 15" "0,1" bitfld.long 0x00 14. " DATA_14 ,Data bit 14" "0,1" bitfld.long 0x00 13. " DATA_13 ,Data bit 13" "0,1" bitfld.long 0x00 12. " DATA_12 ,Data bit 12" "0,1" textline " " bitfld.long 0x00 11. " DATA_11 ,Data bit 11" "0,1" bitfld.long 0x00 10. " DATA_10 ,Data bit 10" "0,1" bitfld.long 0x00 9. " DATA_9 ,Data bit 9" "0,1" bitfld.long 0x00 8. " DATA_8 ,Data bit 8" "0,1" textline " " bitfld.long 0x00 7. " DATA_7 ,Data bit 7" "0,1" bitfld.long 0x00 6. " DATA_6 ,Data bit 6" "0,1" bitfld.long 0x00 5. " DATA_5 ,Data bit 5" "0,1" bitfld.long 0x00 4. " DATA_4 ,Data bit 4" "0,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Data bit 3" "0,1" bitfld.long 0x00 2. " DATA_2 ,Data bit 2" "0,1" bitfld.long 0x00 1. " DATA_1 ,Data bit 1" "0,1" bitfld.long 0x00 0. " DATA_0 ,Data bit 0" "0,1" line.long 0x04 "MDAT1,MIF Data 1 Register" bitfld.long 0x04 31. " DATA_63 ,Data bit 63" "0,1" bitfld.long 0x04 30. " DATA_62 ,Data bit 62" "0,1" bitfld.long 0x04 29. " DATA_61 ,Data bit 61" "0,1" bitfld.long 0x04 28. " DATA_60 ,Data bit 60" "0,1" textline " " bitfld.long 0x04 27. " DATA_59 ,Data bit 59" "0,1" bitfld.long 0x04 26. " DATA_58 ,Data bit 58" "0,1" bitfld.long 0x04 25. " DATA_57 ,Data bit 57" "0,1" bitfld.long 0x04 24. " DATA_56 ,Data bit 56" "0,1" textline " " bitfld.long 0x04 23. " DATA_55 ,Data bit 55" "0,1" bitfld.long 0x04 22. " DATA_54 ,Data bit 54" "0,1" bitfld.long 0x04 21. " DATA_53 ,Data bit 53" "0,1" bitfld.long 0x04 20. " DATA_52 ,Data bit 52" "0,1" textline " " bitfld.long 0x04 19. " DATA_51 ,Data bit 51" "0,1" bitfld.long 0x04 18. " DATA_50 ,Data bit 50" "0,1" bitfld.long 0x04 17. " DATA_49 ,Data bit 49" "0,1" bitfld.long 0x04 16. " DATA_48 ,Data bit 48" "0,1" textline " " bitfld.long 0x04 15. " DATA_47 ,Data bit 47" "0,1" bitfld.long 0x04 14. " DATA_46 ,Data bit 46" "0,1" bitfld.long 0x04 13. " DATA_45 ,Data bit 45" "0,1" bitfld.long 0x04 12. " DATA_44 ,Data bit 44" "0,1" textline " " bitfld.long 0x04 11. " DATA_43 ,Data bit 43" "0,1" bitfld.long 0x04 10. " DATA_42 ,Data bit 42" "0,1" bitfld.long 0x04 9. " DATA_41 ,Data bit 41" "0,1" bitfld.long 0x04 8. " DATA_40 ,Data bit 40" "0,1" textline " " bitfld.long 0x04 7. " DATA_39 ,Data bit 39" "0,1" bitfld.long 0x04 6. " DATA_38 ,Data bit 38" "0,1" bitfld.long 0x04 5. " DATA_37 ,Data bit 37" "0,1" bitfld.long 0x04 4. " DATA_36 ,Data bit 36" "0,1" textline " " bitfld.long 0x04 3. " DATA_35 ,Data bit 35" "0,1" bitfld.long 0x04 2. " DATA_34 ,Data bit 34" "0,1" bitfld.long 0x04 1. " DATA_33 ,Data bit 33" "0,1" bitfld.long 0x04 0. " DATA_32 ,Data bit 32" "0,1" line.long 0x08 "MDAT2,MIF Data 2 Register" bitfld.long 0x08 31. " DATA_95 ,Data bit 95" "0,1" bitfld.long 0x08 30. " DATA_94 ,Data bit 94" "0,1" bitfld.long 0x08 29. " DATA_93 ,Data bit 93" "0,1" bitfld.long 0x08 28. " DATA_92 ,Data bit 92" "0,1" textline " " bitfld.long 0x08 27. " DATA_91 ,Data bit 91" "0,1" bitfld.long 0x08 26. " DATA_90 ,Data bit 90" "0,1" bitfld.long 0x08 25. " DATA_89 ,Data bit 89" "0,1" bitfld.long 0x08 24. " DATA_88 ,Data bit 88" "0,1" textline " " bitfld.long 0x08 23. " DATA_87 ,Data bit 87" "0,1" bitfld.long 0x08 22. " DATA_86 ,Data bit 86" "0,1" bitfld.long 0x08 21. " DATA_85 ,Data bit 85" "0,1" bitfld.long 0x08 20. " DATA_84 ,Data bit 84" "0,1" textline " " bitfld.long 0x08 19. " DATA_83 ,Data bit 83" "0,1" bitfld.long 0x08 18. " DATA_82 ,Data bit 82" "0,1" bitfld.long 0x08 17. " DATA_81 ,Data bit 81" "0,1" bitfld.long 0x08 16. " DATA_80 ,Data bit 80" "0,1" textline " " bitfld.long 0x08 15. " DATA_79 ,Data bit 79" "0,1" bitfld.long 0x08 14. " DATA_78 ,Data bit 78" "0,1" bitfld.long 0x08 13. " DATA_77 ,Data bit 77" "0,1" bitfld.long 0x08 12. " DATA_76 ,Data bit 76" "0,1" textline " " bitfld.long 0x08 11. " DATA_75 ,Data bit 75" "0,1" bitfld.long 0x08 10. " DATA_74 ,Data bit 74" "0,1" bitfld.long 0x08 9. " DATA_73 ,Data bit 73" "0,1" bitfld.long 0x08 8. " DATA_72 ,Data bit 72" "0,1" textline " " bitfld.long 0x08 7. " DATA_71 ,Data bit 71" "0,1" bitfld.long 0x08 6. " DATA_70 ,Data bit 70" "0,1" bitfld.long 0x08 5. " DATA_69 ,Data bit 69" "0,1" bitfld.long 0x08 4. " DATA_68 ,Data bit 68" "0,1" textline " " bitfld.long 0x08 3. " DATA_67 ,Data bit 67" "0,1" bitfld.long 0x08 2. " DATA_66 ,Data bit 66" "0,1" bitfld.long 0x08 1. " DATA_65 ,Data bit 65" "0,1" bitfld.long 0x08 0. " DATA_64 ,Data bit 64" "0,1" line.long 0x0C "MDAT3,MIF Data 3 Register" bitfld.long 0x0C 31. " DATA_127 ,Data bit 127" "0,1" bitfld.long 0x0C 30. " DATA_126 ,Data bit 126" "0,1" bitfld.long 0x0C 29. " DATA_125 ,Data bit 125" "0,1" bitfld.long 0x0C 28. " DATA_124 ,Data bit 124" "0,1" textline " " bitfld.long 0x0C 27. " DATA_123 ,Data bit 123" "0,1" bitfld.long 0x0C 26. " DATA_122 ,Data bit 122" "0,1" bitfld.long 0x0C 25. " DATA_121 ,Data bit 121" "0,1" bitfld.long 0x0C 24. " DATA_120 ,Data bit 120" "0,1" textline " " bitfld.long 0x0C 23. " DATA_119 ,Data bit 119" "0,1" bitfld.long 0x0C 22. " DATA_118 ,Data bit 118" "0,1" bitfld.long 0x0C 21. " DATA_117 ,Data bit 117" "0,1" bitfld.long 0x0C 20. " DATA_116 ,Data bit 116" "0,1" textline " " bitfld.long 0x0C 19. " DATA_115 ,Data bit 115" "0,1" bitfld.long 0x0C 18. " DATA_114 ,Data bit 114" "0,1" bitfld.long 0x0C 17. " DATA_113 ,Data bit 113" "0,1" bitfld.long 0x0C 16. " DATA_112 ,Data bit 112" "0,1" textline " " bitfld.long 0x0C 15. " DATA_111 ,Data bit 111" "0,1" bitfld.long 0x0C 14. " DATA_110 ,Data bit 110" "0,1" bitfld.long 0x0C 13. " DATA_109 ,Data bit 109" "0,1" bitfld.long 0x0C 12. " DATA_108 ,Data bit 108" "0,1" textline " " bitfld.long 0x0C 11. " DATA_107 ,Data bit 107" "0,1" bitfld.long 0x0C 10. " DATA_106 ,Data bit 106" "0,1" bitfld.long 0x0C 9. " DATA_105 ,Data bit 105" "0,1" bitfld.long 0x0C 8. " DATA_104 ,Data bit 104" "0,1" textline " " bitfld.long 0x0C 7. " DATA_103 ,Data bit 103" "0,1" bitfld.long 0x0C 6. " DATA_102 ,Data bit 102" "0,1" bitfld.long 0x0C 5. " DATA_101 ,Data bit 101" "0,1" bitfld.long 0x0C 4. " DATA_100 ,Data bit 100" "0,1" textline " " bitfld.long 0x0C 3. " DATA_99 ,Data bit 99" "0,1" bitfld.long 0x0C 2. " DATA_98 ,Data bit 98" "0,1" bitfld.long 0x0C 1. " DATA_97 ,Data bit 97" "0,1" bitfld.long 0x0C 0. " DATA_96 ,Data bit 96" "0,1" line.long 0x10 "MDWE0,MIF Data Write Enable 0 Register" bitfld.long 0x10 31. " MASK_31 ,Write for CTR data bit 31" "Disabled,Enabled" bitfld.long 0x10 30. " MASK_30 ,Write for CTR data bit 30" "Disabled,Enabled" bitfld.long 0x10 29. " MASK_29 ,Write for CTR data bit 29" "Disabled,Enabled" bitfld.long 0x10 28. " MASK_28 ,Write for CTR data bit 28" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " MASK_27 ,Write for CTR data bit 27" "Disabled,Enabled" bitfld.long 0x10 26. " MASK_26 ,Write for CTR data bit 26" "Disabled,Enabled" bitfld.long 0x10 25. " MASK_25 ,Write for CTR data bit 25" "Disabled,Enabled" bitfld.long 0x10 24. " MASK_24 ,Write for CTR data bit 24" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " MASK_23 ,Write for CTR data bit 23" "Disabled,Enabled" bitfld.long 0x10 22. " MASK_22 ,Write for CTR data bit 22" "Disabled,Enabled" bitfld.long 0x10 21. " MASK_21 ,Write for CTR data bit 21" "Disabled,Enabled" bitfld.long 0x10 20. " MASK_20 ,Write for CTR data bit 20" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " MASK_19 ,Write for CTR data bit 19" "Disabled,Enabled" bitfld.long 0x10 18. " MASK_18 ,Write for CTR data bit 18" "Disabled,Enabled" bitfld.long 0x10 17. " MASK_17 ,Write for CTR data bit 17" "Disabled,Enabled" bitfld.long 0x10 16. " MASK_16 ,Write for CTR data bit 16" "Disabled,Enabled" textline " " bitfld.long 0x10 15. " MASK_15 ,Write for CTR data bit 15" "Disabled,Enabled" bitfld.long 0x10 14. " MASK_14 ,Write for CTR data bit 14" "Disabled,Enabled" bitfld.long 0x10 13. " MASK_13 ,Write for CTR data bit 13" "Disabled,Enabled" bitfld.long 0x10 12. " MASK_12 ,Write for CTR data bit 12" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " MASK_11 ,Write for CTR data bit 11" "Disabled,Enabled" bitfld.long 0x10 10. " MASK_10 ,Write for CTR data bit 10" "Disabled,Enabled" bitfld.long 0x10 9. " MASK_9 ,Write for CTR data bit 9" "Disabled,Enabled" bitfld.long 0x10 8. " MASK_8 ,Write for CTR data bit 8" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " MASK_7 ,Write for CTR data bit 7" "Disabled,Enabled" bitfld.long 0x10 6. " MASK_6 ,Write for CTR data bit 6" "Disabled,Enabled" bitfld.long 0x10 5. " MASK_5 ,Write for CTR data bit 5" "Disabled,Enabled" bitfld.long 0x10 4. " MASK_4 ,Write for CTR data bit 4" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " MASK_3 ,Write for CTR data bit 3" "Disabled,Enabled" bitfld.long 0x10 2. " MASK_2 ,Write for CTR data bit 2" "Disabled,Enabled" bitfld.long 0x10 1. " MASK_1 ,Write for CTR data bit 1" "Disabled,Enabled" bitfld.long 0x10 0. " MASK_0 ,Write for CTR data bit 0" "Disabled,Enabled" line.long 0x14 "MDWE1,MIF Data Write Enable 1 Register" bitfld.long 0x14 31. " MASK_63 ,Write for CTR data bit 63" "Disabled,Enabled" bitfld.long 0x14 30. " MASK_62 ,Write for CTR data bit 62" "Disabled,Enabled" bitfld.long 0x14 29. " MASK_61 ,Write for CTR data bit 61" "Disabled,Enabled" bitfld.long 0x14 28. " MASK_60 ,Write for CTR data bit 60" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " MASK_59 ,Write for CTR data bit 59" "Disabled,Enabled" bitfld.long 0x14 26. " MASK_58 ,Write for CTR data bit 58" "Disabled,Enabled" bitfld.long 0x14 25. " MASK_57 ,Write for CTR data bit 57" "Disabled,Enabled" bitfld.long 0x14 24. " MASK_56 ,Write for CTR data bit 56" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " MASK_55 ,Write for CTR data bit 55" "Disabled,Enabled" bitfld.long 0x14 22. " MASK_54 ,Write for CTR data bit 54" "Disabled,Enabled" bitfld.long 0x14 21. " MASK_53 ,Write for CTR data bit 53" "Disabled,Enabled" bitfld.long 0x14 20. " MASK_52 ,Write for CTR data bit 52" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " MASK_51 ,Write for CTR data bit 51" "Disabled,Enabled" bitfld.long 0x14 18. " MASK_50 ,Write for CTR data bit 50" "Disabled,Enabled" bitfld.long 0x14 17. " MASK_49 ,Write for CTR data bit 49" "Disabled,Enabled" bitfld.long 0x14 16. " MASK_48 ,Write for CTR data bit 48" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " MASK_47 ,Write for CTR data bit 47" "Disabled,Enabled" bitfld.long 0x14 14. " MASK_46 ,Write for CTR data bit 46" "Disabled,Enabled" bitfld.long 0x14 13. " MASK_45 ,Write for CTR data bit 45" "Disabled,Enabled" bitfld.long 0x14 12. " MASK_44 ,Write for CTR data bit 44" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " MASK_43 ,Write for CTR data bit 43" "Disabled,Enabled" bitfld.long 0x14 10. " MASK_42 ,Write for CTR data bit 42" "Disabled,Enabled" bitfld.long 0x14 9. " MASK_41 ,Write for CTR data bit 41" "Disabled,Enabled" bitfld.long 0x14 8. " MASK_40 ,Write for CTR data bit 40" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " MASK_39 ,Write for CTR data bit 39" "Disabled,Enabled" bitfld.long 0x14 6. " MASK_38 ,Write for CTR data bit 38" "Disabled,Enabled" bitfld.long 0x14 5. " MASK_37 ,Write for CTR data bit 37" "Disabled,Enabled" bitfld.long 0x14 4. " MASK_36 ,Write for CTR data bit 36" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " MASK_35 ,Write for CTR data bit 35" "Disabled,Enabled" bitfld.long 0x14 2. " MASK_34 ,Write for CTR data bit 34" "Disabled,Enabled" bitfld.long 0x14 1. " MASK_33 ,Write for CTR data bit 33" "Disabled,Enabled" bitfld.long 0x14 0. " MASK_32 ,Write for CTR data bit 32" "Disabled,Enabled" line.long 0x18 "MDWE2,MIF Data Write Enable 2 Register" bitfld.long 0x18 31. " MASK_95 ,Write for CTR data bit 95" "Disabled,Enabled" bitfld.long 0x18 30. " MASK_94 ,Write for CTR data bit 94" "Disabled,Enabled" bitfld.long 0x18 29. " MASK_93 ,Write for CTR data bit 93" "Disabled,Enabled" bitfld.long 0x18 28. " MASK_92 ,Write for CTR data bit 92" "Disabled,Enabled" textline " " bitfld.long 0x18 27. " MASK_91 ,Write for CTR data bit 91" "Disabled,Enabled" bitfld.long 0x18 26. " MASK_90 ,Write for CTR data bit 90" "Disabled,Enabled" bitfld.long 0x18 25. " MASK_89 ,Write for CTR data bit 89" "Disabled,Enabled" bitfld.long 0x18 24. " MASK_88 ,Write for CTR data bit 88" "Disabled,Enabled" textline " " bitfld.long 0x18 23. " MASK_87 ,Write for CTR data bit 87" "Disabled,Enabled" bitfld.long 0x18 22. " MASK_86 ,Write for CTR data bit 86" "Disabled,Enabled" bitfld.long 0x18 21. " MASK_85 ,Write for CTR data bit 85" "Disabled,Enabled" bitfld.long 0x18 20. " MASK_84 ,Write for CTR data bit 84" "Disabled,Enabled" textline " " bitfld.long 0x18 19. " MASK_83 ,Write for CTR data bit 83" "Disabled,Enabled" bitfld.long 0x18 18. " MASK_82 ,Write for CTR data bit 82" "Disabled,Enabled" bitfld.long 0x18 17. " MASK_81 ,Write for CTR data bit 81" "Disabled,Enabled" bitfld.long 0x18 16. " MASK_80 ,Write for CTR data bit 80" "Disabled,Enabled" textline " " bitfld.long 0x18 15. " MASK_79 ,Write for CTR data bit 79" "Disabled,Enabled" bitfld.long 0x18 14. " MASK_78 ,Write for CTR data bit 78" "Disabled,Enabled" bitfld.long 0x18 13. " MASK_77 ,Write for CTR data bit 77" "Disabled,Enabled" bitfld.long 0x18 12. " MASK_76 ,Write for CTR data bit 76" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " MASK_75 ,Write for CTR data bit 75" "Disabled,Enabled" bitfld.long 0x18 10. " MASK_74 ,Write for CTR data bit 74" "Disabled,Enabled" bitfld.long 0x18 9. " MASK_73 ,Write for CTR data bit 73" "Disabled,Enabled" bitfld.long 0x18 8. " MASK_72 ,Write for CTR data bit 72" "Disabled,Enabled" textline " " bitfld.long 0x18 7. " MASK_71 ,Write for CTR data bit 71" "Disabled,Enabled" bitfld.long 0x18 6. " MASK_70 ,Write for CTR data bit 70" "Disabled,Enabled" bitfld.long 0x18 5. " MASK_69 ,Write for CTR data bit 69" "Disabled,Enabled" bitfld.long 0x18 4. " MASK_68 ,Write for CTR data bit 68" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " MASK_67 ,Write for CTR data bit 67" "Disabled,Enabled" bitfld.long 0x18 2. " MASK_66 ,Write for CTR data bit 66" "Disabled,Enabled" bitfld.long 0x18 1. " MASK_65 ,Write for CTR data bit 65" "Disabled,Enabled" bitfld.long 0x18 0. " MASK_64 ,Write for CTR data bit 64" "Disabled,Enabled" line.long 0x1C "MDWE3,MIF Data Write Enable 3 Register" bitfld.long 0x1C 31. " MASK_127 ,Write for CTR data bit 127" "Disabled,Enabled" bitfld.long 0x1C 30. " MASK_126 ,Write for CTR data bit 126" "Disabled,Enabled" bitfld.long 0x1C 29. " MASK_125 ,Write for CTR data bit 125" "Disabled,Enabled" bitfld.long 0x1C 28. " MASK_124 ,Write for CTR data bit 124" "Disabled,Enabled" textline " " bitfld.long 0x1C 27. " MASK_123 ,Write for CTR data bit 123" "Disabled,Enabled" bitfld.long 0x1C 26. " MASK_122 ,Write for CTR data bit 122" "Disabled,Enabled" bitfld.long 0x1C 25. " MASK_121 ,Write for CTR data bit 121" "Disabled,Enabled" bitfld.long 0x1C 24. " MASK_120 ,Write for CTR data bit 120" "Disabled,Enabled" textline " " bitfld.long 0x1C 23. " MASK_119 ,Write for CTR data bit 119" "Disabled,Enabled" bitfld.long 0x1C 22. " MASK_118 ,Write for CTR data bit 118" "Disabled,Enabled" bitfld.long 0x1C 21. " MASK_117 ,Write for CTR data bit 117" "Disabled,Enabled" bitfld.long 0x1C 20. " MASK_116 ,Write for CTR data bit 116" "Disabled,Enabled" textline " " bitfld.long 0x1C 19. " MASK_115 ,Write for CTR data bit 115" "Disabled,Enabled" bitfld.long 0x1C 18. " MASK_114 ,Write for CTR data bit 114" "Disabled,Enabled" bitfld.long 0x1C 17. " MASK_113 ,Write for CTR data bit 113" "Disabled,Enabled" bitfld.long 0x1C 16. " MASK_112 ,Write for CTR data bit 112" "Disabled,Enabled" textline " " bitfld.long 0x1C 15. " MASK_111 ,Write for CTR data bit 111" "Disabled,Enabled" bitfld.long 0x1C 14. " MASK_110 ,Write for CTR data bit 110" "Disabled,Enabled" bitfld.long 0x1C 13. " MASK_109 ,Write for CTR data bit 109" "Disabled,Enabled" bitfld.long 0x1C 12. " MASK_108 ,Write for CTR data bit 108" "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " MASK_107 ,Write for CTR data bit 107" "Disabled,Enabled" bitfld.long 0x1C 10. " MASK_106 ,Write for CTR data bit 106" "Disabled,Enabled" bitfld.long 0x1C 9. " MASK_105 ,Write for CTR data bit 105" "Disabled,Enabled" bitfld.long 0x1C 8. " MASK_104 ,Write for CTR data bit 104" "Disabled,Enabled" textline " " bitfld.long 0x1C 7. " MASK_103 ,Write for CTR data bit 103" "Disabled,Enabled" bitfld.long 0x1C 6. " MASK_102 ,Write for CTR data bit 102" "Disabled,Enabled" bitfld.long 0x1C 5. " MASK_101 ,Write for CTR data bit 101" "Disabled,Enabled" bitfld.long 0x1C 4. " MASK_100 ,Write for CTR data bit 100" "Disabled,Enabled" textline " " bitfld.long 0x1C 3. " MASK_99 ,Write for CTR data bit 99" "Disabled,Enabled" bitfld.long 0x1C 2. " MASK_98 ,Write for CTR data bit 98" "Disabled,Enabled" bitfld.long 0x1C 1. " MASK_97 ,Write for CTR data bit 97" "Disabled,Enabled" bitfld.long 0x1C 0. " MASK_96 ,Write for CTR data bit 96" "Disabled,Enabled" rgroup.long 0xE0++0x03 line.long 0x00 "MCTL,MIF Control Register" bitfld.long 0x00 0. " XCMP ,Transfer complete" "0,1" if (((per.l(ad:0x4218C000+0xE4))&0x40000000)==0x40000000) group.long 0xE4++0x03 line.long 0x00 "MADR,MIF Address Register" bitfld.long 0x00 31. " WNR ,Write-Not-Read selection" "Read,Write" bitfld.long 0x00 30. " TB ,Target location bit" "CTR,DBR" hexmask.long.word 0x00 0.--13. 1. " ADDR ,DBR address of 8-bit entry" else group.long 0xE4++0x03 line.long 0x00 "MADR,MIF Address Register" bitfld.long 0x00 31. " WNR ,Write-Not-Read selection" "Read,Write" bitfld.long 0x00 30. " TB ,Target location bit" "CTR,DBR" hexmask.long.byte 0x00 0.--7. 1. " ADDR ,CTR address of 128-bit entry" endif width 12. endif tree.end tree "AMBA AHB Registers" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0218C000 else base ad:0x4218C000 endif width 10. group.long 0x3C0++0x003 line.long 0x00 "ACTL,AHB Control Register" bitfld.long 0x00 4. " MPB ,DMA Packet buffering mode" "Single,Multiple" bitfld.long 0x00 2. " DMAMODE ,DMA Mode" "Mode 0,Mode 11" textline " " bitfld.long 0x00 1. " SMX ,ACSR0 and ACSR1 generate an interrupts" "Ahb_int[0:1],Ahb_int[0]" bitfld.long 0x00 0. " SCE ,Software clear enable" "Hardware,Software" textline " " rgroup.long 0x3D0++0x007 line.long 0x00 "ACSR0,AHB Channel Status 0 Register" bitfld.long 0x00 31. " CHS31 ,Interrupt status for logical channel 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " CHS30 ,Interrupt status for logical channel 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " CHS29 ,Interrupt status for logical channel 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " CHS28 ,Interrupt status for logical channel 28" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " CHS27 ,Interrupt status for logical channel 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " CHS26 ,Interrupt status for logical channel 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " CHS25 ,Interrupt status for logical channel 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " CHS24 ,Interrupt status for logical channel 24" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " CHS23 ,Interrupt status for logical channel 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " CHS22 ,Interrupt status for logical channel 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " CHS21 ,Interrupt status for logical channel 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " CHS20 ,Interrupt status for logical channel 20" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " CHS19 ,Interrupt status for logical channel 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " CHS18 ,Interrupt status for logical channel 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " CHS17 ,Interrupt status for logical channel 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " CHS16 ,Interrupt status for logical channel 16" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " CHS15 ,Interrupt status for logical channel 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " CHS14 ,Interrupt status for logical channel 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " CHS13 ,Interrupt status for logical channel 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " CHS12 ,Interrupt status for logical channel 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " CHS11 ,Interrupt status for logical channel 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " CHS10 ,Interrupt status for logical channel 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " CHS9 ,Interrupt status for logical channel 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " CHS8 ,Interrupt status for logical channel 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " CHS7 ,Interrupt status for logical channel 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " CHS6 ,Interrupt status for logical channel 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " CHS5 ,Interrupt status for logical channel 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " CHS4 ,Interrupt status for logical channel 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " CHS3 ,Interrupt status for logical channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " CHS2 ,Interrupt status for logical channel 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " CHS1 ,Interrupt status for logical channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " CHS0 ,Interrupt status for logical channel 0" "No interrupt,Interrupt" line.long 0x04 "ACSR1,AHB Channel Status 1 Register" bitfld.long 0x04 31. " CHS63 ,Interrupt status for logical channel 63" "No interrupt,Interrupt" bitfld.long 0x04 30. " CHS62 ,Interrupt status for logical channel 62" "No interrupt,Interrupt" bitfld.long 0x04 29. " CHS61 ,Interrupt status for logical channel 61" "No interrupt,Interrupt" bitfld.long 0x04 28. " CHS60 ,Interrupt status for logical channel 60" "No interrupt,Interrupt" textline " " bitfld.long 0x04 27. " CHS59 ,Interrupt status for logical channel 59" "No interrupt,Interrupt" bitfld.long 0x04 26. " CHS58 ,Interrupt status for logical channel 58" "No interrupt,Interrupt" bitfld.long 0x04 25. " CHS57 ,Interrupt status for logical channel 57" "No interrupt,Interrupt" bitfld.long 0x04 24. " CHS56 ,Interrupt status for logical channel 56" "No interrupt,Interrupt" textline " " bitfld.long 0x04 23. " CHS55 ,Interrupt status for logical channel 55" "No interrupt,Interrupt" bitfld.long 0x04 22. " CHS54 ,Interrupt status for logical channel 54" "No interrupt,Interrupt" bitfld.long 0x04 21. " CHS53 ,Interrupt status for logical channel 53" "No interrupt,Interrupt" bitfld.long 0x04 20. " CHS52 ,Interrupt status for logical channel 52" "No interrupt,Interrupt" textline " " bitfld.long 0x04 19. " CHS51 ,Interrupt status for logical channel 51" "No interrupt,Interrupt" bitfld.long 0x04 18. " CHS50 ,Interrupt status for logical channel 50" "No interrupt,Interrupt" bitfld.long 0x04 17. " CHS49 ,Interrupt status for logical channel 49" "No interrupt,Interrupt" bitfld.long 0x04 16. " CHS48 ,Interrupt status for logical channel 48" "No interrupt,Interrupt" textline " " bitfld.long 0x04 15. " CHS47 ,Interrupt status for logical channel 47" "No interrupt,Interrupt" bitfld.long 0x04 14. " CHS46 ,Interrupt status for logical channel 46" "No interrupt,Interrupt" bitfld.long 0x04 13. " CHS45 ,Interrupt status for logical channel 45" "No interrupt,Interrupt" bitfld.long 0x04 12. " CHS44 ,Interrupt status for logical channel 44" "No interrupt,Interrupt" textline " " bitfld.long 0x04 11. " CHS43 ,Interrupt status for logical channel 43" "No interrupt,Interrupt" bitfld.long 0x04 10. " CHS42 ,Interrupt status for logical channel 42" "No interrupt,Interrupt" bitfld.long 0x04 9. " CHS41 ,Interrupt status for logical channel 41" "No interrupt,Interrupt" bitfld.long 0x04 8. " CHS40 ,Interrupt status for logical channel 40" "No interrupt,Interrupt" textline " " bitfld.long 0x04 7. " CHS39 ,Interrupt status for logical channel 39" "No interrupt,Interrupt" bitfld.long 0x04 6. " CHS38 ,Interrupt status for logical channel 38" "No interrupt,Interrupt" bitfld.long 0x04 5. " CHS37 ,Interrupt status for logical channel 37" "No interrupt,Interrupt" bitfld.long 0x04 4. " CHS36 ,Interrupt status for logical channel 36" "No interrupt,Interrupt" textline " " bitfld.long 0x04 3. " CHS35 ,Interrupt status for logical channel 35" "No interrupt,Interrupt" bitfld.long 0x04 2. " CHS34 ,Interrupt status for logical channel 34" "No interrupt,Interrupt" bitfld.long 0x04 1. " CHS33 ,Interrupt status for logical channel 33" "No interrupt,Interrupt" bitfld.long 0x04 0. " CHS32 ,Interrupt status for logical channel 32" "No interrupt,Interrupt" group.long 0x3D8++0x007 line.long 0x00 "ACMR0,AHB Channel Mask 0 Register" bitfld.long 0x00 31. " CHM31 ,Bitwise channel mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " CHM30 ,Bitwise channel mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " CHM29 ,Bitwise channel mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " CHM28 ,Bitwise channel mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " CHM27 ,Bitwise channel mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " CHM26 ,Bitwise channel mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " CHM25 ,Bitwise channel mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " CHM24 ,Bitwise channel mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " CHM23 ,Bitwise channel mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " CHM22 ,Bitwise channel mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " CHM21 ,Bitwise channel mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " CHM20 ,Bitwise channel mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " CHM19 ,Bitwise channel mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " CHM18 ,Bitwise channel mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " CHM17 ,Bitwise channel mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " CHM16 ,Bitwise channel mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " CHM15 ,Bitwise channel mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " CHM14 ,Bitwise channel mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " CHM13 ,Bitwise channel mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " CHM12 ,Bitwise channel mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " CHM11 ,Bitwise channel mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " CHM10 ,Bitwise channel mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " CHM9 ,Bitwise channel mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " CHM8 ,Bitwise channel mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " CHM7 ,Bitwise channel mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " CHM6 ,Bitwise channel mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " CHM5 ,Bitwise channel mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " CHM4 ,Bitwise channel mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " CHM3 ,Bitwise channel mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " CHM2 ,Bitwise channel mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " CHM1 ,Bitwise channel mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " CHM0 ,Bitwise channel mask bit 0" "Masked,Not masked" line.long 0x04 "ACMR1,AHB Channel Mask 1 Register" bitfld.long 0x04 31. " CHM63 ,Bitwise channel mask bit 63" "Masked,Not masked" bitfld.long 0x04 30. " CHM62 ,Bitwise channel mask bit 62" "Masked,Not masked" bitfld.long 0x04 29. " CHM61 ,Bitwise channel mask bit 61" "Masked,Not masked" bitfld.long 0x04 28. " CHM60 ,Bitwise channel mask bit 60" "Masked,Not masked" textline " " bitfld.long 0x04 27. " CHM59 ,Bitwise channel mask bit 59" "Masked,Not masked" bitfld.long 0x04 26. " CHM58 ,Bitwise channel mask bit 58" "Masked,Not masked" bitfld.long 0x04 25. " CHM57 ,Bitwise channel mask bit 57" "Masked,Not masked" bitfld.long 0x04 24. " CHM56 ,Bitwise channel mask bit 56" "Masked,Not masked" textline " " bitfld.long 0x04 23. " CHM55 ,Bitwise channel mask bit 55" "Masked,Not masked" bitfld.long 0x04 22. " CHM54 ,Bitwise channel mask bit 54" "Masked,Not masked" bitfld.long 0x04 21. " CHM53 ,Bitwise channel mask bit 53" "Masked,Not masked" bitfld.long 0x04 20. " CHM52 ,Bitwise channel mask bit 52" "Masked,Not masked" textline " " bitfld.long 0x04 19. " CHM51 ,Bitwise channel mask bit 51" "Masked,Not masked" bitfld.long 0x04 18. " CHM50 ,Bitwise channel mask bit 50" "Masked,Not masked" bitfld.long 0x04 17. " CHM49 ,Bitwise channel mask bit 49" "Masked,Not masked" bitfld.long 0x04 16. " CHM48 ,Bitwise channel mask bit 48" "Masked,Not masked" textline " " bitfld.long 0x04 15. " CHM47 ,Bitwise channel mask bit 47" "Masked,Not masked" bitfld.long 0x04 14. " CHM46 ,Bitwise channel mask bit 46" "Masked,Not masked" bitfld.long 0x04 13. " CHM45 ,Bitwise channel mask bit 45" "Masked,Not masked" bitfld.long 0x04 12. " CHM44 ,Bitwise channel mask bit 44" "Masked,Not masked" textline " " bitfld.long 0x04 11. " CHM43 ,Bitwise channel mask bit 43" "Masked,Not masked" bitfld.long 0x04 10. " CHM42 ,Bitwise channel mask bit 42" "Masked,Not masked" bitfld.long 0x04 9. " CHM41 ,Bitwise channel mask bit 41" "Masked,Not masked" bitfld.long 0x04 8. " CHM40 ,Bitwise channel mask bit 40" "Masked,Not masked" textline " " bitfld.long 0x04 7. " CHM39 ,Bitwise channel mask bit 39" "Masked,Not masked" bitfld.long 0x04 6. " CHM38 ,Bitwise channel mask bit 38" "Masked,Not masked" bitfld.long 0x04 5. " CHM37 ,Bitwise channel mask bit 37" "Masked,Not masked" bitfld.long 0x04 4. " CHM36 ,Bitwise channel mask bit 36" "Masked,Not masked" textline " " bitfld.long 0x04 3. " CHM35 ,Bitwise channel mask bit 35" "Masked,Not masked" bitfld.long 0x04 2. " CHM34 ,Bitwise channel mask bit 34" "Masked,Not masked" bitfld.long 0x04 1. " CHM33 ,Bitwise channel mask bit 33" "Masked,Not masked" bitfld.long 0x04 0. " CHM32 ,Bitwise channel mask bit 32" "Masked,Not masked" width 12. tree.end tree.end tree "MMDC (Multi Mode DDR Controller Register)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021B0000 width 10. if (((per.l(ad:0x021B0000+0x18))&0x18)==0x08) group.long (0x00)++0x07 line.long 0x00 "MDCTL,MMDC Core Control Register" bitfld.long 0x00 31. " SDE_0 ,MMDC Enable CS0" "Disabled,Enabled" bitfld.long 0x00 30. " SDE_1 ,MMDC Enable CS1" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--26. " ROW ,Row Address Width" "11-bits,12-bits,13-bits,14-bits,15-bits,16-bits,," bitfld.long 0x00 20.--22. " COL ,Column Address Width" "9-bits,10-bits,11-bits,8-bits,12-bits,,," textline " " bitfld.long 0x00 19. " BL ,Burst Length" "4,8" bitfld.long 0x00 16.--17. " DSIZ ,DDR data bus size" "16-bit,32-bit,," line.long 0x04 "MDPDC,MMDC Core Power Down Control Register" bitfld.long 0x04 28.--30. " PRCT_1 ,Precharge Timer - Chip Select 1" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x04 24.--26. " PRCT_0 ,Precharge Timer - Chip Select 0" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" textline " " bitfld.long 0x04 16.--18. " TCKE ,CKE minimum pulse width" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 12.--15. " PWDT_1 ,Power Down Timer - Chip Select 1" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,,," textline " " bitfld.long 0x04 8.--11. " PWDT_0 ,Power Down Timer - Chip Select 0" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,,," bitfld.long 0x04 7. " SLOW_PD ,Slow/fast power down" "Fast,Slow" textline " " bitfld.long 0x04 6. " BOTH_CS_PD ,Both chip selects power-down" "Independently,Both" bitfld.long 0x04 3.--5. " TCKSRX ,Valid clock requirement before self-refresh exit" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x04 0.--2. " TCKSRE ,Valid clock requirement after self-refresh entry" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" hgroup.long (0x08)++0x03 hide.long 0x00 "MDOTC,MMDC Core ODT Timing Control Register" group.long (0x0C)++0x17 line.long 0x00 "MDCFG0,MMDC Core Timing Configuration Register 0" hexmask.long.byte 0x00 24.--31. 1. " TRFC ,Refresh command to Active or Refresh command time" hexmask.long.byte 0x00 16.--23. 1. " TXS ,Exit self refresh to non READ command." textline " " bitfld.long 0x00 13.--15. " TXP ,Exit power-down to next valid command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 4.--8. " TFAW ,Four Active Window" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" textline " " bitfld.long 0x00 0.--3. " TRL ,CAS Read Latency" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,,,,,,," line.long 0x04 "MDCFG1,MMDC Core Timing Configuration Register 1" bitfld.long 0x04 29.--31. " TRCD_LP ,Active command to internal read or write delay time" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x04 26.--28. " TRPPB_LP ,Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" textline " " bitfld.long 0x04 21.--25. " TRC_LP ,Active to Active or Refresh command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 cloks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x04 16.--20. " TRAS ,Active to Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks," textline " " bitfld.long 0x04 15. " TRPAB_LP ,Precharge-all command period" "TRP,TRP+1" bitfld.long 0x04 9.--11. " TWR ,WRITE recovery time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x04 5.--8. " TMRD ,Mode Register Set command cycle" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x04 0.--2. " WL ,CAS Write Latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles," line.long 0x08 "MDCFG2,MMDC Core Timing Configuration Register 2" bitfld.long 0x08 6.--8. " TRTP ,Internal READ command to PRECHARGE command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x08 3.--5. " TWTR ,Internal WRITE to READ command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x08 0.--2. " TRRD ,ACTIVE to ACTIVE command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles," line.long 0x0C "MDMISC,MMDC Core Miscellaneous Register" rbitfld.long 0x0C 31. " CS0_RDY ,External status device on CS0" "Wake-up,Ready" rbitfld.long 0x0C 30. " CS1_RDY ,External status device on CS1" "Wake-up,Ready" textline " " bitfld.long 0x0C 21. " CK1_GATING ,Gating the secondary DDR clock" "Not gated,Gated" bitfld.long 0x0C 20. " CALIB_PER_CS ,Defines the CS number that the associated calibration is targeted at" "CS0,CS1" textline " " bitfld.long 0x0C 18. " LHD ,Latency hiding disable" "No,Yes" bitfld.long 0x0C 16.--17. " WALAT ,Write Additional latency" "Not required,1 cycles,2 cycles,3 cycles" textline " " bitfld.long 0x0C 12. " BI_ON ,Bank Interleaving On" "Not interleaved,Interleaved" bitfld.long 0x0C 11. " LPDDR2_S2 ,LPDDR2 S2 device type indication" "LPDDR2-S4,LPDDR2-S2" textline " " bitfld.long 0x0C 9.--10. " MIF3_MODE ,Command prediction working mode" "Disabled,First pipe line stage,First pipe line stage/axi bus,First pipe line stage/axi bus/access queue" textline " " bitfld.long 0x0C 6.--8. " RALAT ,Read Additional Latency" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x0C 5. " DDR_4_BANK ,DDR device with 4 Banks" "8 banks,4 banks" textline " " bitfld.long 0x0C 3.--4. " DDR_TYPE ,DDR TYPE" "DDR3,LPDDR2,," bitfld.long 0x0C 2. " LPDDR2_2CH ,LPDDR2_2CH" "0,1" textline " " bitfld.long 0x0C 1. " RST ,Software Reset" "No operation,Asserted" line.long 0x10 "MDSCR,MMDC Core Special Command Register" hexmask.long.byte 0x10 24.--31. 1. " MR_OP ,MRW 8 bit operand" hexmask.long.byte 0x10 16.--23. 1. " MR_ADDR , MRR/MRW ADDRESS" textline " " bitfld.long 0x10 15. " CON_REQ ,Configuration request" "Not requested,Requested" rbitfld.long 0x10 14. " CON_ACK ,Configuration acknowledge" "Forbidden,Permitted" textline " " rbitfld.long 0x10 10. " MRR_READ_DATA_VALID ,MRR READ DATA VALID" "Cleared,Set" bitfld.long 0x10 9. " WL_EN ,Write Level Enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4.--6. " CMD ,Command" "Normal operation,Precharge all,Auto-Refresh,MRW Command,ZQ calibration,Precharge all,MRR," bitfld.long 0x10 3. " CMD_CS ,Chip Select" "0,1" textline " " bitfld.long 0x10 0.--2. " CMD_BA ,Bank Address" "0,1,2,3,4,5,6,7" line.long 0x14 "MDREF,MMDC Core Refresh Control Register" hexmask.long.word 0x14 16.--31. 1. " REF_CNT ,Refresh Counter" bitfld.long 0x14 14.--15. " REF_SEL ,Refresh Selector" "64KHz,32KHz,REF_CNT,Disabled" textline " " bitfld.long 0x14 11.--13. " REFR ,Number of refresh commands every refresh cycle" "1 refresh,2 refreshes,3 refreshes,4 refreshes,5 refreshes,6 refreshes,7 refreshes,8 refreshes" bitfld.long 0x14 0. " START_REF ,Start Refresh cycle" "No operation,Started" group.long (0x2C)++0x7 line.long 0x00 "MDRWD,MMDC Core Read/Write Command Delay Register" hexmask.long.word 0x00 16.--28. 1. " TDAI ,Device auto initialization period" bitfld.long 0x00 12.--14. " RTW_SAME ,Controls the cycles delay between Read to Write commands in same chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 9.--11. " WTR_DIFF ,Controls the cycles delay between Write to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 6.--8. " WTW_DIFF ,Controls the cycles delay between Write to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 3.--5. " RTW_DIFF ,Controls the cycles delay between Read to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " RTR_DIFF ,Controls the cycles delay between Read to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" line.long 0x04 "MDOR,MMDC Core Out of Reset Delays Register" bitfld.long 0x04 0.--5. " RST_TO_CKE ,Idle time after first CKE assertion" ",,,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles" textline " " width 13. rgroup.long 0x34++0x03 line.long 0x00 "MDMRR,MMDC Core MRR Data Register" hexmask.long.byte 0x00 24.--31. 1. " MRR_READ_DATA3 ,MRR DATA that arrived on DQ[31:24]" hexmask.long.byte 0x00 16.--23. 1. " MRR_READ_DATA2 ,MRR DATA that arrived on DQ[23:16]" hexmask.long.byte 0x00 8.--15. 1. " MRR_READ_DATA1 ,MRR DATA that arrived on DQ[15:8]" textline " " hexmask.long.byte 0x00 0.--7. 1. " MRR_READ_DATA0 ,MRR DATA that arrived on DQ[7:0]" group.long 0x38++0x0B line.long 0x00 "MDCFG3LP,MMDC Core Timing Configuration Register 3" bitfld.long 0x00 16.--21. " RC_LP ,ACT to ACT or REF command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks,33 clocks,34 clocks,35 clocks,36 clocks,37 clocks,38 clocks,39 clocks,40 clocks,41 clocks,42 clocks,43 clocks,44 clocks,45 clocks,46 clocks,47 clocks,48 clocks,49 clocks,50 clocks,51 clocks,52 clocks,53 clocks,54 clocks,55 clocks,56 clocks,57 clocks,58 clocks,59 clocks,60 clocks,61 clocks,62 clocks,63 clocks," bitfld.long 0x00 8.--11. " TRCD_LP ,ACT command to internal read or write delay time" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks," bitfld.long 0x00 4.--7. " TRPPB_LP ,PRECHARGE (per bank) command period (same bank)" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks," textline " " bitfld.long 0x00 0.--3. " TRPAB_LP ,PRECHARGE (all banks) command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks," line.long 0x04 "MDMR4,MMDC Core MR4 Derating Register" bitfld.long 0x04 8. " TRRD_DE ,TRRD derating value" "None,1 cycle" bitfld.long 0x04 7. " TRP_DE ,TRP derating value" "None,1 cycle" bitfld.long 0x04 6. " TRAS_DE ,TRAS derating value" "None,1 cycle" textline " " bitfld.long 0x04 5. " TRC_DE ,TRC derating value" "None,1 cycle" bitfld.long 0x04 4. " TRCD_DE ,TRCD derating value" "None,1 cycle" rbitfld.long 0x04 1. " UPDATE_DE_ACK ,Update Derated Values Acknowledge" "No update,Updated" textline " " bitfld.long 0x04 0. " UPDATE_DE_REQ ,Update Derated Values Request" "No operation,Requested" line.long 0x08 "MDASP,MMDC Core Address Space Partition Register" hexmask.long.byte 0x08 0.--6. 1. " CS0_END ,Define the absolute last address associated with CS0" group.long (0x400)++0x0F line.long 0x00 "MAARCR,MMDC Core AXI Re-ordering Control Register" bitfld.long 0x00 31. " ARCR_SEC_ERR_LOCK ,ARCR_SEC_ERR_EN lock" "Unlocked,Locked" bitfld.long 0x00 30. " ARCR_SEC_ERR_EN ,Security read/write access violation in OKAY/SLV Error response " "OKAY,SLAVE error" bitfld.long 0x00 28. " ARCR_EXC_ERR_EN ,Exclusive read/write access violation of AXI 6.2.4 rule in OKAY/SLV Error response " "OKAY,SLAVE error" textline " " bitfld.long 0x00 24. " ARCR_RCH_EN ,Real time channel enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ARCR_PAG_HIT ,ARCR Page Hit Rate" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " ARCR_ACC_HIT ,ARCR Access Hit Rate" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--11. " ARCR_DYN_JMP ,ARCR Dynamic Jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ARCR_DYN_MAX ,ARCR Dynamic Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARCR_GUARD ,ARCR Guard" "15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30" line.long 0x04 "MAPSR,MMDC Core Power Saving Control and Status Register" rbitfld.long 0x04 25. " DVACK ,General DVFS acknowledge" "Not asserted,Asserted" rbitfld.long 0x04 24. " LPACK ,General low-power acknowledge" "Not asserted,Asserted" bitfld.long 0x04 21. " DVFS ,General DVFS request" "Not requested,Requested" textline " " bitfld.long 0x04 20. " LPMD ,General LPMD request" "Not requested,Requested" hexmask.long.byte 0x04 8.--15. 1. " PST ,Automatic Power saving timer" rbitfld.long 0x04 6. " WIS ,Write Idle Status" "Idle,Not Idle" textline " " rbitfld.long 0x04 5. " RIS ,Read Idle Status" "Idle,Not Idle" rbitfld.long 0x04 4. " PSS ,Power Saving Status" "Disabled,Enabled" bitfld.long 0x04 0. " PSD ,Automatic Power Saving Disable" "No,Yes" line.long 0x08 "MAEXIDR0,MMDC Core Exclusive ID Monitor Register 0" hexmask.long.word 0x08 16.--31. 1. " EXC_ID_MONITOR1 ,Defines ID for Exclusive monitor #1" hexmask.long.word 0x08 0.--15. 1. " EXC_ID_MONITOR0 ,Defines ID for Exclusive monitor #0" line.long 0x0C "MAEXIDR1,MMDC Core Exclusive ID Monitor Register 1" hexmask.long.word 0x0C 16.--31. 1. " EXC_ID_MONITOR3 ,Defines ID for Exclusive monitor #3" hexmask.long.word 0x0C 0.--15. 1. " EXC_ID_MONITOR2 ,Defines ID for Exclusive monitor #2" group.long (0x410)++0x07 line.long 0x00 "MADPCR0,MMDC Core Debug and Profiling Control Register 0" bitfld.long 0x00 9. " SBS ,Step By Step trigger" "Not launched,Launched" bitfld.long 0x00 8. " SBS_EN ,Step By Step debug enable" "Disabled,Enabled" eventfld.long 0x00 3. " CYC_OVF ,Total Cycles Count Overflow" "No overflow,Overflow" textline " " bitfld.long 0x00 2. " PRF_FRZ ,Profiling freeze" "Not frozen,Frozen" bitfld.long 0x00 1. " DBG_RST ,Debug and Profiling Reset" "No reset,Reset" bitfld.long 0x00 0. " DBG_EN ,Debug and Profiling Enable" "Disabled,Enabled" textline " " line.long 0x04 "MADPCR1,MMDC Core Debug and Profiling Control Register 1" bitfld.long 0x04 31. " PRF_AXI_ID_MASK_31 ,Profiling AXI ID Mask 31" "Masked,Not masked" bitfld.long 0x04 30. " PRF_AXI_ID_MASK_30 ,Profiling AXI ID Mask 30" "Masked,Not masked" bitfld.long 0x04 29. " PRF_AXI_ID_MASK_29 ,Profiling AXI ID Mask 29" "Masked,Not masked" textline " " bitfld.long 0x04 28. " PRF_AXI_ID_MASK_28 ,Profiling AXI ID Mask 28" "Masked,Not masked" bitfld.long 0x04 27. " PRF_AXI_ID_MASK_27 ,Profiling AXI ID Mask 27" "Masked,Not masked" bitfld.long 0x04 26. " PRF_AXI_ID_MASK_26 ,Profiling AXI ID Mask 26" "Masked,Not masked" textline " " bitfld.long 0x04 25. " PRF_AXI_ID_MASK_25 ,Profiling AXI ID Mask 25" "Masked,Not masked" bitfld.long 0x04 24. " PRF_AXI_ID_MASK_24 ,Profiling AXI ID Mask 24" "Masked,Not masked" bitfld.long 0x04 23. " PRF_AXI_ID_MASK_23 ,Profiling AXI ID Mask 23" "Masked,Not masked" textline " " bitfld.long 0x04 22. " PRF_AXI_ID_MASK_22 ,Profiling AXI ID Mask 22" "Masked,Not masked" bitfld.long 0x04 21. " PRF_AXI_ID_MASK_21 ,Profiling AXI ID Mask 21" "Masked,Not masked" bitfld.long 0x04 20. " PRF_AXI_ID_MASK_20 ,Profiling AXI ID Mask 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " PRF_AXI_ID_MASK_19 ,Profiling AXI ID Mask 19" "Masked,Not masked" bitfld.long 0x04 18. " PRF_AXI_ID_MASK_18 ,Profiling AXI ID Mask 18" "Masked,Not masked" bitfld.long 0x04 17. " PRF_AXI_ID_MASK_17 ,Profiling AXI ID Mask 17" "Masked,Not masked" textline " " bitfld.long 0x04 16. " PRF_AXI_ID_MASK_16 ,Profiling AXI ID Mask 16" "Masked,Not masked" bitfld.long 0x04 15. " PRF_AXI_ID[15] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 14. " PRF_AXI_ID[14] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 13. " PRF_AXI_ID[13] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 12. " PRF_AXI_ID[12] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 11. " PRF_AXI_ID[11] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 10. " PRF_AXI_ID[10] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 9. " PRF_AXI_ID[9] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 8. " PRF_AXI_ID[8] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 7. " PRF_AXI_ID[7] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 6. " PRF_AXI_ID[6] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 5. " PRF_AXI_ID[5] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 4. " PRF_AXI_ID[4] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 3. " PRF_AXI_ID[3] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 2. " PRF_AXI_ID[2] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 1. " PRF_AXI_ID[1] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 0. " PRF_AXI_ID[0] ,Profiling AXI ID" "Low,High" textline " " rgroup.long (0x418)++0x1F line.long 0x00 "MADPSR0,MMDC Core Debug and Profiling Status Register 0" line.long 0x04 "MADPSR1,MMDC Core Debug and Profiling Status Register 1" line.long 0x08 "MADPSR2,MMDC Core Debug and Profiling Status Register 2" line.long 0x0C "MADPSR3,MMDC Core Debug and Profiling Status Register 3" line.long 0x10 "MADPSR4,MMDC Core Debug and Profiling Status Register 4" line.long 0x14 "MADPSR5,MMDC Core Debug and Profiling Status Register 5" line.long 0x18 "MASBS0,MMDC Core Step By Step Address" line.long 0x1C "MASBS1,MMDC Core Step By Step Address Attributes" hexmask.long.word 0x1C 16.--31. 1. " SBS_AXI_ID ,Step By Step AXI ID" bitfld.long 0x1C 13.--15. " SBS_LEN ,Step By Step Length" "1,2,3,4,5,6,7,8" bitfld.long 0x1C 12. " SBS_BUFF ,Step By Step Buffered" "0,1" textline " " bitfld.long 0x1C 10.--11. " SBS_BURST ,Step By Step Burst" "Fixed,INCR,WRAP," bitfld.long 0x1C 7.--9. " SBS_SIZE ,Step By Step Size" "8 bits,16 bits,32 bits,64 bits,128 bits,,," bitfld.long 0x1C 4.--6. " SBS_PROT ,Step By Step Protection" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1C 2.--3. " SBS_LOCK ,Step By Step Lock" "0,1,2,3" bitfld.long 0x1C 1. " SBS_TYPE ,Step By Step Request Type" "Write,Read" bitfld.long 0x1C 0. " SBS_VLD ,Step By Step Valid" "Not valid,Valid" textline " " group.long (0x440)++0x03 line.long 0x00 "MAGENP,MMDC Core General Purpose Register" bitfld.long 0x00 31. " GP31 ,General purpose read/write bit 31" "0,1" bitfld.long 0x00 30. " GP30 ,General purpose read/write bit 30" "0,1" bitfld.long 0x00 29. " GP29 ,General purpose read/write bit 29" "0,1" textline " " bitfld.long 0x00 28. " GP28 ,General purpose read/write bit 28" "0,1" bitfld.long 0x00 27. " GP27 ,General purpose read/write bit 27" "0,1" bitfld.long 0x00 26. " GP26 ,General purpose read/write bit 26" "0,1" textline " " bitfld.long 0x00 25. " GP25 ,General purpose read/write bit 25" "0,1" bitfld.long 0x00 24. " GP24 ,General purpose read/write bit 24" "0,1" bitfld.long 0x00 23. " GP23 ,General purpose read/write bit 23" "0,1" textline " " bitfld.long 0x00 22. " GP22 ,General purpose read/write bit 22" "0,1" bitfld.long 0x00 21. " GP21 ,General purpose read/write bit 21" "0,1" bitfld.long 0x00 20. " GP20 ,General purpose read/write bit 20" "0,1" textline " " bitfld.long 0x00 19. " GP19 ,General purpose read/write bit 19" "0,1" bitfld.long 0x00 18. " GP18 ,General purpose read/write bit 18" "0,1" bitfld.long 0x00 17. " GP17 ,General purpose read/write bit 17" "0,1" textline " " bitfld.long 0x00 16. " GP16 ,General purpose read/write bit 16" "0,1" bitfld.long 0x00 15. " GP15 ,General purpose read/write bit 15" "0,1" bitfld.long 0x00 14. " GP14 ,General purpose read/write bit 14" "0,1" textline " " bitfld.long 0x00 13. " GP13 ,General purpose read/write bit 13" "0,1" bitfld.long 0x00 12. " GP12 ,General purpose read/write bit 12" "0,1" bitfld.long 0x00 11. " GP11 ,General purpose read/write bit 11" "0,1" textline " " bitfld.long 0x00 10. " GP10 ,General purpose read/write bit 10" "0,1" bitfld.long 0x00 9. " GP9 ,General purpose read/write bit 9" "0,1" bitfld.long 0x00 8. " GP8 ,General purpose read/write bit 8" "0,1" textline " " bitfld.long 0x00 7. " GP7 ,General purpose read/write bit 7" "0,1" bitfld.long 0x00 6. " GP6 ,General purpose read/write bit 6" "0,1" bitfld.long 0x00 5. " GP5 ,General purpose read/write bit 5" "0,1" textline " " bitfld.long 0x00 4. " GP4 ,General purpose read/write bit 4" "0,1" bitfld.long 0x00 3. " GP3 ,General purpose read/write bit 3" "0,1" bitfld.long 0x00 2. " GP2 ,General purpose read/write bit 2" "0,1" textline " " bitfld.long 0x00 1. " GP1 ,General purpose read/write bit 1" "0,1" bitfld.long 0x00 0. " GP0 ,General purpose read/write bit 0" "0,1" textline " " group.long 0x800++0x07 line.long 0x00 "MPZQHWCTRL,MMDC PHY ZQ HW Control Register" bitfld.long 0x00 27.--31. " ZQ_EARLY_COMPARATOR_EN_TIMER ,ZQ early comparator enable timer" ",,,,,,,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" bitfld.long 0x00 23.--25. " TZQ_CS ,Device ZQ short time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," bitfld.long 0x00 20.--22. " TZQ_OPER ,Device ZQ long/oper time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," textline " " bitfld.long 0x00 17.--19. " TZQ_INIT ,Device ZQ long/init time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," bitfld.long 0x00 16. " ZQ_HW_FOR ,Force ZQ automatic calibration process with the i.MX ZQ calibration pad" "Not forced,Forced" rbitfld.long 0x00 11.--15. " ZQ_HW_PD_RES ,ZQ HW calibration pull-down result" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" textline " " rbitfld.long 0x00 6.--10. " ZQ_HW_PU_RES ,ZQ automatic calibration pull-up result" "0 (minimum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (maximum)" bitfld.long 0x00 2.--5. " ZQ_HW_PER ,ZQ periodic calibration time" "1 ms,2 ms,4 ms,8 ms,16 ms,32 ms,64 ms,128 ms,256 ms,512 ms,1 sec,2 sec,4 sec,8 sec,16 sec,32 sec" bitfld.long 0x00 0.--1. " ZQ_MODE ,ZQ calibration mode" "Not issued,i.MX ZQ calibration pad/External DDR (when exiting),External DDR,i.MX ZQ calibration pad/External DDR (periodic/when exiting)" line.long 0x04 "MPZQSWCTRL,MMDC PHY ZQ SW control register" bitfld.long 0x04 16.--17. " ZQ_CMP_OUT_SMP ,Amount of cycles between driving the ZQ signals to the ZQ pad" "7 cycles,15 cycles,23 cycles,31 cycles" bitfld.long 0x04 13. " USE_ZQ_SW_VAL ,Use SW ZQ configured value for I/O pads resistor controls" "ZQ_HW_PD_VAL & ZQ_HW_PU_VAL,ZQ_SW_PD_VAL & ZQ_SW_PU_VAL" bitfld.long 0x04 12. " ZQ_SW_PD ,ZQ software PU/PD calibration" "PU,PD" textline " " bitfld.long 0x04 7.--11. " ZQ_SW_PD_VAL ,ZQ software pull-down resistence" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" bitfld.long 0x04 2.--6. " ZQ_SW_PU_VAL ,ZQ software pull-up resistence" "0 (minimum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (maximum)" rbitfld.long 0x04 1. " ZQ_SW_RES ,ZQ software calibration result" "VDD/2" textline " " bitfld.long 0x04 0. " ZQ_SW_FOR ,Force ZQ SW calibration" "Not forced,Forced" textline " " group.long (0x808)++0x0B line.long 0x00 "MPWLGCR0,MMDC PHY Write Leveling Error Status Register 0" rbitfld.long 0x00 11. " WL_HW_ERR3 ,Byte3 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x00 10. " WL_HW_ERR2 ,Byte2 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x00 9. " WL_HW_ERR1 ,Byte1 write-leveling HW calibration error" "No error,Error" textline " " rbitfld.long 0x00 8. " WL_HW_ERR0 ,Byte0 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x00 7. " WL_SW_RES3 ,Byte3 write-leveling software result" "Low,High" rbitfld.long 0x00 6. " WL_SW_RES2 ,Byte2 write-leveling software result" "Low,High" textline " " rbitfld.long 0x00 5. " WL_SW_RES1 ,Byte1 write-leveling software result" "Low,High" rbitfld.long 0x00 4. " WL_SW_RES0 ,Byte0 write-leveling software result" "Low,High" bitfld.long 0x00 2. " SW_WL_CNT_EN ,SW WL count down enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SW_WL_EN ,Enable WL SW update" "Disabled,Enabled" bitfld.long 0x00 0. " HW_WL_EN ,Enable WL HW enable" "Disabled,Enabled" line.long 0x04 "MPWLDECTRL0,MMDC PHY Write Leveling Delay Control Register 0" bitfld.long 0x04 25.--26. " WL_CYC_DEL1 ,Write level cycle delay for Byte 1" "No delay,1 cycle,2 cycles," bitfld.long 0x04 24. " WL_HC_DEL1 ,Write level half cycle delay for Byte 1" "No delay,Half cycle" hexmask.long.byte 0x04 16.--22. 1. " WR_DL_ABS_OFFSET1 ,Absolute write-leveling delay offset for Byte 1" textline " " bitfld.long 0x04 9.--10. " WL_CYC_DEL0 ,Write level cycle delay for Byte 0" "No delay,1 cycle,2 cycles," bitfld.long 0x04 8. " WL_HC_DEL0 ,Write level half cycle delay for Byte 0" "No delay,Half cycle" hexmask.long.byte 0x04 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute write-leveling delay offset for Byte 0" line.long 0x08 "MPWLDECTRL1,MMDC PHY Write Leveling Delay Control Register 1" bitfld.long 0x08 25.--26. " WL_CYC_DEL3 ,Write level cycle delay for Byte 3" "No delay,1 cycle,2 cycles," bitfld.long 0x08 24. " WL_HC_DEL3 ,Write level half cycle delay for Byte 3" "No delay,Half cycle" hexmask.long.byte 0x08 16.--22. 1. " WR_DL_ABS_OFFSET3 ,Absolute delay offset for Byte 3" textline " " bitfld.long 0x08 9.--10. " WL_CYC_DEL2 ,Write level cycle delay for Byte 2" "No delay,1 cycle,2 cycles," bitfld.long 0x08 8. " WL_HC_DEL2 ,Write level half cycle delay for Byte 2" "No delay,Half cycle" hexmask.long.byte 0x08 0.--6. 1. " WR_DL_ABS_OFFSET2 ,Absolute delay offset for Byte 2" rgroup.long 0x814++0x03 line.long 0x00 "MPWLDLST,MMDC PHY Write Leveling Delay Line Status Register" hexmask.long.byte 0x00 24.--30. 1. " WL_DL_UNIT_NUM3 ,Number of delay units that is actually used by write leveling delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WL_DL_UNIT_NUM2 ,Number of delay units that is actually used by write leveling delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WL_DL_UNIT_NUM1 ,Number of delay units that is actually used by write leveling delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WL_DL_UNIT_NUM0 ,Number of delay units that is actually used by write leveling delay line 0" hgroup.long 0x818++0x03 hide.long 0x00 "MPODTCTRL,MMDC PHY ODT Control Register" group.long 0x81C++0x1F line.long 0x00 "MPRDDQBY0DL,MMDC PHY Read DQ Byte0 Delay Register" bitfld.long 0x00 28.--30. " RD_DQ7_DEL ,Read dqs0 to dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 24.--26. " RD_DQ6_DEL ,Read dqs0 to dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 20.--22. " RD_DQ5_DEL ,Read dqs0 to dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x00 16.--18. " RD_DQ4_DEL ,Read dqs0 to dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 12.--14. " RD_DQ3_DEL ,Read dqs0 to dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 8.--10. " RD_DQ2_DEL ,Read dqs0 to dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x00 4.--6. " RD_DQ1_DEL ,Read dqs0 to dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 0.--2. " RD_DQ0_DEL ,Read dqs0 to dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x04 "MPRDDQBY1DL,MMDC PHY Read DQ Byte1 Delay Register" bitfld.long 0x04 28.--30. " RD_DQ15_DEL ,Read dqs1 to dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 24.--26. " RD_DQ14_DEL ,Read dqs1 to dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 20.--22. " RD_DQ13_DEL ,Read dqs1 to dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x04 16.--18. " RD_DQ12_DEL ,Read dqs1 to dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 12.--14. " RD_DQ11_DEL ,Read dqs1 to dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 8.--10. " RD_DQ10_DEL ,Read dqs1 to dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x04 4.--6. " RD_DQ9_DEL ,Read dqs1 to dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 0.--2. " RD_DQ8_DEL ,Read dqs1 to dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x08 "MPRDDQBY2DL,MMDC PHY Read DQ Byte2 Delay Register" bitfld.long 0x08 28.--30. " RD_DQ23_DEL ,Read dqs2 to dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 24.--26. " RD_DQ22_DEL ,Read dqs2 to dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 20.--22. " RD_DQ21_DEL ,Read dqs2 to dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x08 16.--18. " RD_DQ20_DEL ,Read dqs2 to dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 12.--14. " RD_DQ19_DEL ,Read dqs2 to dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 8.--10. " RD_DQ18_DEL ,Read dqs2 to dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x08 4.--6. " RD_DQ17_DEL ,Read dqs2 to dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 0.--2. " RD_DQ16_DEL ,Read dqs2 to dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x0C "MPRDDQBY3DL,MMDC PHY Read DQ Byte3 Delay Register" bitfld.long 0x0C 28.--30. " RD_DQ31_DEL ,Read dqs3 to dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 24.--26. " RD_DQ30_DEL ,Read dqs3 to dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 20.--22. " RD_DQ29_DEL ,Read dqs3 to dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x0C 16.--18. " RD_DQ28_DEL ,Read dqs3 to dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 12.--14. " RD_DQ27_DEL ,Read dqs3 to dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 8.--10. " RD_DQ26_DEL ,Read dqs3 to dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x0C 4.--6. " RD_DQ25_DEL ,Read dqs3 to dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 0.--2. " RD_DQ24_DEL ,Read dqs3 to dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x10 "MPWRDQBY0DL,MMDC PHY Write DQ Byte0 Delay Register" bitfld.long 0x10 30.--31. " WR_DM0_DEL ,Write dm0 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 28.--29. " WR_DQ7_DEL ,Write dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 24.--25. " WR_DQ6_DEL ,Write dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x10 20.--21. " WR_DQ5_DEL ,Write dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 16.--17. " WR_DQ4_DEL ,Write dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 12.--13. " WR_DQ3_DEL ,Write dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x10 8.--9. " WR_DQ2_DEL ,Write dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 4.--5. " WR_DQ1_DEL ,Write dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 0.--1. " WR_DQ0_DEL ,Write dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x14 "MPWRDQBY1DL,MMDC PHY Write DQ Byte1 Delay Register" bitfld.long 0x14 30.--31. " WR_DM1_DEL ,Write dm1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 28.--29. " WR_DQ15_DEL ,Write dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 24.--25. " WR_DQ14_DEL ,Write dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x14 20.--21. " WR_DQ13_DEL ,Write dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 16.--17. " WR_DQ12_DEL ,Write dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 12.--13. " WR_D11_DEL ,Write dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x14 8.--9. " WR_DQ10_DEL ,Write dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 4.--5. " WR_DQ9_DEL ,Write dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 0.--1. " WR_DQ8_DEL ,Write dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x18 "MPWRDQBY2DL, MMDC PHY Write DQ Byte2 Delay Register" bitfld.long 0x18 30.--31. " WR_DM2_DEL ,Write dm2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 28.--29. " WR_DQ23_DEL ,Write dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 24.--25. " WR_DQ22_DEL ,Write dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x18 20.--21. " WR_DQ21_DEL ,Write dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 16.--17. " WR_DQ20_DEL ,Write dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 12.--13. " WR_D19_DEL ,Write dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x18 8.--9. " WR_DQ18_DEL ,Write dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 4.--5. " WR_DQ17_DEL ,Write dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 0.--1. " WR_DQ16_DEL ,Write dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x1C "MPWRDQBY3DL, MMDC PHY Write DQ Byte3 Delay Register" bitfld.long 0x1C 30.--31. " WR_DM3_DEL ,Write dm3 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 28.--29. " WR_DQ31_DEL ,Write dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 24.--25. " WR_DQ30_DEL ,Write dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x1C 20.--21. " WR_DQ29_DEL ,Write dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 16.--17. " WR_DQ28_DEL ,Write dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 12.--13. " WR_D27_DEL ,Write dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x1C 8.--9. " WR_DQ26_DEL ,Write dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 4.--5. " WR_DQ25_DEL ,Write dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 0.--1. " WR_DQ24_DEL ,Write dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays" group.long 0x83C++0x07 line.long 0x00 "MPDGCTRL0,MMDC PHY Read DQS gating control register 0" bitfld.long 0x00 31. " RST_RD_FIFO ,Reset Read Data FIFO & pointers" "No reset,Reset" bitfld.long 0x00 30. " DG_CMP_CYC ,Read DQS gating sample cycle" "16 cycles,32 cycles" bitfld.long 0x00 29. " DG_DIS ,Read DQS gating disable" "No,Yes" textline " " bitfld.long 0x00 28. " HW_DG_EN ,Enable automatic read DQS gating calibration" "Disabled,Enabled" bitfld.long 0x00 24.--27. " DG_HC_DEL1 ,Read Dqs1 gating half cycles delay for Byte 1" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," bitfld.long 0x00 23. " DG_EXT_UP ,DG extend upper boundary" "Not extended,Extended" textline " " hexmask.long.byte 0x00 16.--22. 1. " DG_DL_ABS_OFFSET1 ,Absolute delay offset" rbitfld.long 0x00 12. " HW_DG_ERR ,HW DQS gating error" "No error,Error" bitfld.long 0x00 8.--11. " DG_HC_DEL0 ,Read DQS0 gating half cycles delay for Byte 0" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," textline " " hexmask.long.byte 0x00 0.--6. 1. " DG_DL_ABS_OFFSET0 ,Absolute read DQS gating delay offset" line.long 0x04 "MPDGCTRL1,MMDC PHY Read DQS gating control register 1" bitfld.long 0x04 24.--27. " DG_HC_DEL3 ,Read DQS3 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," hexmask.long.byte 0x04 16.--22. 1. " DG_DL_ABS_OFFSET3 ,Absolute read DQS gating delay offset for Byte 3" bitfld.long 0x04 8.--11. " DG_HC_DEL2 ,Read DQS2 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," textline " " hexmask.long.byte 0x04 0.--6. 1. " DG_DL_ABS_OFFSET2 ,Absolute read DQS gating delay offset" rgroup.long 0x844++0x03 line.long 0x00 "MPDGDLST0,MMDC PHY Read DQS gating Delay Line Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " DG_DL_UNIT_NUM3 ,Number of delay units that is actually used by DQS gating delay line 3" hexmask.long.byte 0x00 16.--22. 1. " DG_DL_UNIT_NUM2 ,Number of delay units that is actually used by DQS gating delay line 2" hexmask.long.byte 0x00 8.--14. 1. " DG_DL_UNIT_NUM1 ,Number of delay units that is actually used by DQS gating delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " DG_DL_UNIT_NUM0 ,Number of delay units that is actually used by DQS gating delay line 0" group.long 0x848++0x03 line.long 0x00 "MPRDDLCTL,MMDC PHY Read Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_ABS_OFFSET3 ,Absolute read delay offset byte 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_ABS_OFFSET2 ,Absolute read delay offset byte 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_ABS_OFFSET1 ,Absolute read delay offset byte 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " RD_DL_ABS_OFFSET0 ,Absolute read delay offset byte 0" rgroup.long 0x84C++0x03 line.long 0x00 "MPRDDLST0,MMDC PHY Read Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_UNIT_NUM3 ,Number of delay units that is actually used by read delay line 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_UNIT_NUM2 ,Number of delay units that is actually used by read delay line 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_UNIT_NUM1 ,Number of delay units that is actually used by read delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " RD_DL_UNIT_NUM0 ,Number of delay units that is actually used by read delay line 0" group.long 0x850++0x03 line.long 0x00 "MPWRDLCTL0,MMDC PHY Write Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_ABS_OFFSET3 ,Absolute write delay offset for Byte 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_ABS_OFFSET2 ,Absolute write delay offset for Byte 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_ABS_OFFSET1 ,Absolute write delay offset for Byte 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute write delay offset for Byte 30" rgroup.long 0x854++0x03 line.long 0x00 "MPWRDLST0,MMDC PHY Write Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_UNIT_NUM3 ,Number of delay units that is actually used by write delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_UNIT_NUM2 ,Number of delay units that is actually used by write delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_UNIT_NUM1 ,Number of delay units that is actually used by write delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WR_DL_UNIT_NUM0 ,Number of delay units that is actually used by write delay line 0" group.long 0x858++0x0F line.long 0x00 "MPSDCTRL,MMDC PHY CK control Register" bitfld.long 0x00 8.--9. " SDCLK1_DEL ,SDCLK0 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x00 10.--11. " SDCLK0_DEL ,SDCLK0 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x04 "MPZQLP2CTL,MMDC PHY ZQ LPDDR2 HW Control Register" hexmask.long.byte 0x04 24.--30. 1. " ZQ_LP2_HW_ZQCS ,Period in cycles that it takes the memory device to perform a Short ZQ calibration" hexmask.long.byte 0x04 16.--23. 1. " ZQ_LP2_HW_ZQCL ,Period in cycles that it takes the memory device to perform a Long ZQ calibration" hexmask.long.word 0x04 0.--8. 1. " ZQ_LP2_HW_ZQINIT ,Period in cycles that it takes the memory device to perform a Init ZQ calibration" line.long 0x08 "MPRDDLHWCTL,MMDC PHY Read Delay HW Calibration Control Register" bitfld.long 0x08 5. " HW_RD_DL_CMP_CYC ,HW RD DL sample cycle" "Not compared,Compared" bitfld.long 0x08 4. " HW_RD_DL_EN ,Enable HW RD DL calibration" "Disabled,Enabled" rbitfld.long 0x08 3. " HW_RD_DL_ERR3 ,HW RD DL3 error" "No error,Error" textline " " rbitfld.long 0x08 2. " HW_RD_DL_ERR2 ,HW RD DL2 error" "No error,Error" rbitfld.long 0x08 1. " HW_RD_DL_ERR1 ,HW RD DL1 error" "No error,Error" rbitfld.long 0x08 0. " HW_RD_DL_ERR0 ,HW RD DL0 error" "No error,Error" line.long 0x0C "MPWRDLHWCTL,MMDC PHY Write Delay HW Calibration Control Register" bitfld.long 0x0C 5. " HW_WR_DL_CMP_CYC ,HW WR DL sample cycle" "Not compared,Compared" bitfld.long 0x0C 4. " HW_WR_DL_EN ,Enable HW WR DL calibration" "Disabled,Enabled" rbitfld.long 0x0C 3. " HW_WR_DL_ERR3 ,HW WR DL3 error" "No error,Error" textline " " rbitfld.long 0x0C 2. " HW_WR_DL_ERR2 ,HW WR DL2 error" "No error,Error" rbitfld.long 0x0C 1. " HW_WR_DL_ERR1 ,HW WR DL1 error" "No error,Error" rbitfld.long 0x0C 0. " HW_WR_DL_ERR0 ,HW WR DL0 error" "No error,Error" rgroup.long 0x868++0x13 line.long 0x00 "MPRDDLHWST0,MMDC PHY Read Delay HW Calibration Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " HW_RD_DL_UP1 ,HW RD DL1 upper boundary" hexmask.long.byte 0x00 16.--22. 1. " HW_RD_DL_LOW1 ,HW RD DL1 lower boundary" hexmask.long.byte 0x00 8.--14. 1. " HW_RD_DL_UP0 ,HW RD DL0 upper boundary" textline " " hexmask.long.byte 0x00 0.--6. 1. " HW_RD_DL_LOW0 ,HW RD DL0 lower boundary" line.long 0x04 "MPRDDLHWST1,MMDC PHY Read Delay HW Calibration Status Register 1" hexmask.long.byte 0x04 24.--30. 1. " HW_RD_DL_UP3 ,HW RD DL3 upper boundary" hexmask.long.byte 0x04 16.--22. 1. " HW_RD_DL_LOW3 ,HW RD DL3 lower boundary" hexmask.long.byte 0x04 8.--14. 1. " HW_RD_DL_UP2 ,HW RD DL2 upper boundary" textline " " hexmask.long.byte 0x04 0.--6. 1. " HW_RD_DL_LOW2 ,HW RD DL2 lower boundary" line.long 0x08 "MPWRDLHWST0,MMDC PHY Write Delay HW Calibration Status Register 0" hexmask.long.byte 0x08 24.--30. 1. " HW_WR_DL_UP1 ,HW WR DL1 upper boundary" hexmask.long.byte 0x08 16.--22. 1. " HW_WR_DL_LOW1 ,HW WR DL1 lower boundary" hexmask.long.byte 0x08 8.--14. 1. " HW_WR_DL_UP0 ,HW WR DL0 upper boundary" textline " " hexmask.long.byte 0x08 0.--6. 1. " HW_WR_DL_LOW0 ,HW WR DL0 lower boundary" line.long 0x0C "MPWRDLHWST1,MMDC PHY Write Delay HW Calibration Status Register 1" hexmask.long.byte 0x0C 24.--30. 1. " HW_WR_DL_UP3 ,HW WR DL3 upper boundary" hexmask.long.byte 0x0C 16.--22. 1. " HW_WR_DL_LOW3 ,HW WR DL3 lower boundary" hexmask.long.byte 0x0C 8.--14. 1. " HW_WR_DL_UP2 ,HW WR DL2 upper boundary" textline " " hexmask.long.byte 0x0C 0.--6. 1. " HW_WR_DL_LOW2 ,HW WR DL2 lower boundary" line.long 0x10 "MPWLHWERR0,MMDC PHY Write Leveling HW Error Register 0 " hexmask.long.byte 0x10 24.--31. 1. " HW_WL3_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 16.--23. 1. " HW_WL2_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 8.--15. 1. " HW_WL1_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" textline " " hexmask.long.byte 0x10 0.--7. 1. " HW_WL0_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" textline " " rgroup.long 0x87C++0x0F line.long 0x00 "MPDGHWST0,MMDC PHY Read DQS Gating HW Status Register 0" hexmask.long.word 0x00 16.--26. 1. " HW_DG_UP0 ,HW DG0 upper boundary" hexmask.long.word 0x00 0.--10. 1. " HW_DG_LOW0 ,HW DG0 lower boundary" line.long 0x04 "MPDGHWST1,MMDC PHY Read DQS Gating HW Status Register 1" hexmask.long.word 0x04 16.--26. 1. " HW_DG_UP1 ,HW DG1 upper boundary" hexmask.long.word 0x04 0.--10. 1. " HW_DG_LOW1 ,HW DG1 lower boundary" line.long 0x08 "MPDGHWST2,MMDC PHY Read DQS Gating HW Status Register 2" hexmask.long.word 0x08 16.--26. 1. " HW_DG_UP2 ,HW DG2 upper boundary" hexmask.long.word 0x08 0.--10. 1. " HW_DG_LOW2 ,HW DG2 lower boundary" line.long 0x0C "MPDGHWST3,MMDC PHY Read DQS Gating HW Status Register 3" hexmask.long.word 0x0C 16.--26. 1. " HW_DG_UP3 ,HW DG3 upper boundary" hexmask.long.word 0x0C 0.--10. 1. " HW_DG_LOW3 ,HW DG3 lower boundary" group.long 0x88C++0x0B line.long 0x00 "MPPDCMPR1,MMDC PHY Pre-defined Compare Register 1" hexmask.long.word 0x00 16.--31. 1. " PDV2 ,Pre defined compare value2" hexmask.long.word 0x00 0.--15. 1. " PDV1 ,Pre defined compare value2" line.long 0x04 "MPPDCMPR2,MMDC PHY Pre-defined Compare and CA Delay Line Configuration Register" hexmask.long.byte 0x04 24.--30. 1. " PHY_CA_DL_UNIT ,Number of delay units that is actually used by phy CA delay unit" hexmask.long.byte 0x04 16.--22. 1. " CA_DL_ABS_OFFSET ,Absolute delay offset" bitfld.long 0x04 2. " READ_LEVEL_PATTERN ,DQ calibration Read level pattern" "1010,0011" textline " " bitfld.long 0x04 1. " MPR_FULL_CMP ,DQ calibration full compare enable" "Disabled,Enabled" bitfld.long 0x04 0. " MPR_CMP ,DQ calibration compare enable" "Disabled,Enabled" line.long 0x08 "MPSWDAR0,MMDC PHY SW Dummy Access Register 0" rbitfld.long 0x08 5. " SW_DUM_CMP3 ,SW dummy read byte3 compare results" "Failed,Passed" rbitfld.long 0x08 4. " SW_DUM_CMP2 ,SW dummy read byte2 compare results" "Failed,Passed" rbitfld.long 0x08 3. " SW_DUM_CMP1 ,SW dummy read byte1 compare results" "Failed,Passed" textline " " rbitfld.long 0x08 2. " SW_DUM_CMP0 ,SW dummy read byte0 compare results" "Failed,Passed" bitfld.long 0x08 1. " SW_DUMMY_RD ,SW dummy read" "Not generated,Generated" bitfld.long 0x08 0. " SW_DUMMY_WR ,SW dummy write" "Not generated,Generated" textline " " rgroup.long 0x898++0x1F line.long 0x00 "MPSWDRDR0,MMDC PHY SW Dummy Read Data Register 0" line.long 0x04 "MPSWDRDR1,MMDC PHY SW Dummy Read Data Register 1" line.long 0x08 "MPSWDRDR2,MMDC PHY SW Dummy Read Data Register 2" line.long 0x0C "MPSWDRDR3,MMDC PHY SW Dummy Read Data Register 3" line.long 0x10 "MPSWDRDR4,MMDC PHY SW Dummy Read Data Register 4" line.long 0x14 "MPSWDRDR5,MMDC PHY SW Dummy Read Data Register 5" line.long 0x18 "MPSWDRDR6,MMDC PHY SW Dummy Read Data Register 6" line.long 0x1C "MPSWDRDR7,MMDC PHY SW Dummy Read Data Register 7" textline " " group.long 0x8B8++0x07 line.long 0x00 "MPMUR0,MMDC PHY Measure Unit Register for DQ0-3" hexmask.long.word 0x00 16.--25. 1. " MU_UNIT_DEL_NUM ,Measure unit measured number of unit delay per cycle" bitfld.long 0x00 11. " FRC_MSR ,Force measuement on delay-lines" "Not forced,Forced" bitfld.long 0x00 10. " MU_BYP_EN ,Measure unit bypass enable" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--9. 1. " MU_BYP_VAL ,Measure unit bypass value" line.long 0x04 "MPWRCADL,MMDC PHY Write CA Delay Control Register" bitfld.long 0x04 18.--19. " WR_CA9_DEL ,CA9 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 16.--17. " WR_CA8_DEL ,CA8 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 14.--15. " WR_CA7_DEL ,CA7 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x04 12.--13. " WR_CA6_DEL ,CA6 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 10.--11. " WR_CA5_DEL ,CA5 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 8.--9. " WR_CA4_DEL ,CA4 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x04 6.--7. " WR_CA3_DEL ,CA3 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 4.--5. " WR_CA2_DEL ,CA2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 2.--3. " WR_CA1_DEL ,CA1 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x04 0.--1. " WR_CA0_DEL ,CA0 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline "" rgroup.long 0x8C0++0x03 line.long 0x00 "MPDCCR,MMDC PHY Duty Cycle Control Register" bitfld.long 0x00 28.--30. " RD_DQS3_FT_DCC ,Read dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 25.--27. " RD_DQS2_FT_DCC ,Read dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 22.--24. " RD_DQS1_FT_DCC ,Read dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 19.--21. " RD_DQS0_FT_DCC ,Read dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 16.--18. " CK_FT1_DCC ,Secondary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 12.--14. " CK_FT0_DCC ,Primary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 9.--11. " WR_DQS3_FT_DCC ,Write dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 6.--8. " WR_DQS2_FT_DCC ,Write dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 3.--5. " WR_DQS1_FT_DCC ,Write dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 0.--2. " WR_DQS0_FT_DCC ,Write dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," elif (((per.l(ad:0x021B0000+0x18))&0x18)==0x00) width 10. group.long (0x00)++0x07 line.long 0x00 "MDCTL,MMDC Core Control Register" bitfld.long 0x00 31. " SDE_0 ,MMDC Enable CS0" "Disabled,Enabled" bitfld.long 0x00 30. " SDE_1 ,MMDC Enable CS1" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--26. " ROW ,Row Address Width" "11-bits,12-bits,13-bits,14-bits,15-bits,16-bits,," bitfld.long 0x00 20.--22. " COL ,Column Address Width" "9-bits,10-bits,11-bits,8-bits,12-bits,,," textline " " bitfld.long 0x00 19. " BL ,Burst Length" ",8" bitfld.long 0x00 16.--17. " DSIZ ,SDRAM Memory Data Width" "16-bit,32-bit,64-bit," line.long 0x04 "MDPDC,MMDC Core Power Down Control Register" bitfld.long 0x04 28.--30. " PRCT_1 ,Precharge Timer - Chip Select 1" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x04 24.--26. " PRCT_0 ,Precharge Timer - Chip Select 0" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" textline " " bitfld.long 0x04 16.--18. " TCKE ,CKE minimum pulse width" "1 cycle,2 cycles,,,,,7 cycles,8 cycles" bitfld.long 0x04 12.--15. " PWDT_1 ,Power Down Timer - Chip Select 1" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,,," textline " " bitfld.long 0x04 8.--11. " PWDT_0 ,Power Down Timer - Chip Select 0" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,,," bitfld.long 0x04 7. " SLOW_PD ,Slow precharge power-down" "Fast,Slow" textline " " bitfld.long 0x04 6. " BOTH_CS_PD ,Both chip selects power-down" "Independently,Both" bitfld.long 0x04 3.--5. " TCKSRX ,Valid clock requirement before self-refresh exit" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x04 0.--2. " TCKSRE ,Valid clock requirement after self-refresh entry" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" group.long (0x08)++0x03 line.long 0x00 "MDOTC,MMDC Core ODT Timing Control Register" bitfld.long 0x00 27.--29. " TAOFPD ,Asynchronous RTT turn-off delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 24.--26. " TAONPD ,Asynchronous RTT turn-on delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x00 20.--23. " TANPD ,ODT to power down entry latency" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x00 16.--19. " TAXPD ,ODT power down exit latency" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" textline " " bitfld.long 0x00 12.--14. " TODTLON ,ODT turn on latency" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles," bitfld.long 0x00 4.--8. " TODT_IDLE_OFF ,Idle period before turning memory ODT off" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles" group.long (0x0C)++0x17 line.long 0x00 "MDCFG0,MMDC Core Timing Configuration Register 0" hexmask.long.byte 0x00 24.--31. 1. " TRFC ,Refresh command to Active or Refresh command time" hexmask.long.byte 0x00 16.--23. 1. " TXS ,Self-refresh exit to next valid command delay" textline " " bitfld.long 0x00 13.--15. " TXP ,Exit power down with DLL-on to any valid command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 9.--12. " TXPDLL ,Exit precharge power down with DLL frozen to commands requiring DLL" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" textline " " bitfld.long 0x00 4.--8. " TFAW ,Four Active Window" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x00 0.--3. " TCL ,CAS Read Latency" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,,,,,,," line.long 0x04 "MDCFG1,MMDC Core Timing Configuration Register 1" bitfld.long 0x04 29.--31. " TRCD ,Active command to internal read or write delay time" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x04 26.--28. " TRP ,Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" textline " " bitfld.long 0x04 21.--25. " TRC ,Active to Active or Refresh command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 cloks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x04 16.--20. " TRAS ,Active to Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks," textline " " bitfld.long 0x04 15. " TRPA ,Precharge-all command period" "tRP,tRP+1" bitfld.long 0x04 9.--11. " TWR ,WRITE recovery time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x04 5.--8. " TMRD ,Mode Register Set command cycle" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x04 0.--2. " TCWL ,CAS Write Latency" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles," line.long 0x08 "MDCFG2,MMDC Core Timing Configuration Register 2" hexmask.long.word 0x08 16.--24. 1. " TDLLK ,DLL locking time" bitfld.long 0x08 6.--8. " TRTP ,Internal READ command to PRECHARGE command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x08 3.--5. " TWTR ,Internal WRITE to READ command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x08 0.--2. " TRRD ,ACTIVE to ACTIVE command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles," line.long 0x0C "MDMISC,MMDC Core Miscellaneous Register" rbitfld.long 0x0C 31. " CS0_RDY ,External status device on CS0" "Wake-up,Ready" rbitfld.long 0x0C 30. " CS1_RDY ,External status device on CS1" "Wake-up,Ready" textline " " bitfld.long 0x0C 20. " CALIB_PER_CS ,Defines the CS number that the associated calibration is targetted at" "CS0,CS1" bitfld.long 0x0C 19. " ADDR_MIRROR ,Address mirroring" "Disabled,Enabled" textline " " bitfld.long 0x0C 18. " LHD ,Latency hiding disable" "No,Yes" bitfld.long 0x0C 16.--17. " WALAT ,Write Additional latency" "Not required,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x0C 12. " BI_ON ,Bank Interleaving On" "Not interleaved,Interleaved" bitfld.long 0x0C 9.--10. " MIF3_MODE ,Command prediction working mode" "Disabled,First pipe line stage,First pipe line stage/axi bus,First pipe line stage/axi bus/access queue" textline " " bitfld.long 0x0C 6.--8. " RALAT ,Read Additional Latency" "ASAP,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x0C 5. " DDR_4_BANK ,DDR device with 4 Banks" "8 banks,4 banks" textline " " bitfld.long 0x0C 3.--4. " DDR_TYPE ,DDR TYPE" "DDR3,LPDDR2,," bitfld.long 0x0C 1. " RST ,Software Reset" "No operation,Asserted" line.long 0x10 "MDSCR,MMDC Core Special Command Register" hexmask.long.byte 0x10 24.--31. 1. " CMD_ADDR_MSB ,Command/Address MSB" hexmask.long.byte 0x10 16.--23. 1. " CMD_ADDR_LSB , Command/Address LSB" textline " " bitfld.long 0x10 15. " CON_REQ ,Configuration request" "Not requested,Requested" rbitfld.long 0x10 14. " CON_ACK ,Configuration acknowledge" "Forbidden,Permitted" textline " " bitfld.long 0x10 9. " WL_EN ,Write Level Enable" "Disabled,Enabled" bitfld.long 0x10 4.--6. " CMD ,Command" "Normal operation,Precharge all,Auto-Refresh,Load Mode Register,ZQ calibration,Precharge all,," textline " " bitfld.long 0x10 3. " CMD_CS ,Chip Select" "0,1" bitfld.long 0x10 0.--2. " CMD_BA ,Bank Address" "0,1,2,3,4,5,6,7" line.long 0x14 "MDREF,MMDC Core Refresh Control Register" hexmask.long.word 0x14 16.--31. 1. " REF_CNT ,Refresh Counter" bitfld.long 0x14 14.--15. " REF_SEL ,Refresh Selector" "64KHz,32KHz,REF_CNT,Disabled" textline " " bitfld.long 0x14 11.--13. " REFR ,Refresh Rate" "1 refresh,2 refreshes,3 refreshes,4 refreshes,5 refreshes,6 refreshes,7 refreshes,8 refreshes" bitfld.long 0x14 0. " START_REF ,Start Refresh cycle" "No operation,Started" group.long (0x2C)++0x07 line.long 0x00 "MDRWD,MMDC Core Read/Write Command Delay Register" bitfld.long 0x00 12.--14. " RTW_SAME ,Controls the cycles delay between Read to Write commands in same chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WTR_DIFF ,Controls the cycles delay between Write to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 6.--8. " WTW_DIFF ,Controls the cycles delay between Write to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " RTW_DIFF ,Controls the cycles delay between Read to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 0.--2. " RTR_DIFF ,Controls the cycles delay between Read to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" line.long 0x04 "MDOR,MMDC Core Out of Reset Delays Register" hexmask.long.byte 0x04 16.--23. 1. " TXPR ,CKE HIGH to a valid command" bitfld.long 0x04 8.--13. " SDE_TO_RST , Time from SDE enable until DDR reset is high" ",,1 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles" textline " " bitfld.long 0x04 0.--5. " RST_TO_CKE ,Time from SDE enable to CKE rise" ",,,1 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles" textline " " ;ssection width 13. hgroup.long (0x34)++0x0B hide.long 0x00 "MDMRR,MMDC Core MRR Data Register" hide.long 0x04 "MDCFG3LP,MMDC Core Timing Configuration Register 3" hide.long 0x08 "MDMR4,MMDC Core MR4 Derating Register" group.long (0x40)++0x03 line.long 0x00 "MDASP,MMDC Core Address Space Partition Register" hexmask.long.byte 0x00 0.--6. 1. " CS0_END ,Define the absolute last address associated with CS0" group.long (0x400)++0x0F line.long 0x00 "MAARCR,MMDC Core AXI Re-ordering Control Register" bitfld.long 0x00 31. " ARCR_SEC_ERR_LOCK ,ARCR_SEC_ERR_EN lock" "Not locked,Locked" bitfld.long 0x00 30. " ARCR_SEC_ERR_EN ,Security read/write access violation in OKAY/SLV Error response " "OKAY,SLAVE error" bitfld.long 0x00 28. " ARCR_EXC_ERR_EN ,Exclusive read/write access violation of AXI 6.2.4 rule in OKAY/SLV Error response " "OKAY,SLAVE error" textline " " bitfld.long 0x00 24. " ARCR_RCH_EN ,Real time channel enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ARCR_PAG_HIT ,ARCR Page Hit Rate" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " ARCR_ACC_HIT ,ARCR Access Hit Rate" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--11. " ARCR_DYN_JMP ,ARCR Dynamic Jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ARCR_DYN_MAX ,ARCR Dynamic Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARCR_GUARD ,ARCR Guard" "15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30" line.long 0x04 "MAPSR,MMDC Core Power Saving Control and Status Register" rbitfld.long 0x04 25. " DVACK ,General DVFS acknowledge" "Not asserted,Asserted" rbitfld.long 0x04 24. " LPACK ,General low-power acknowledge" "Not asserted,Asserted" bitfld.long 0x04 21. " DVFS ,General DVFS request" "Not requested,Requested" textline " " bitfld.long 0x04 20. " LPMD ,General LPMD request" "Not requested,Requested" hexmask.long.byte 0x04 8.--15. 1. " PST ,Automatic Power saving timer" rbitfld.long 0x04 6. " WIS ,Write Idle Status" "Idle,Busy" textline " " rbitfld.long 0x04 5. " RIS ,Read Idle Status" "Idle,Busy" rbitfld.long 0x04 4. " PSS ,Power Saving Status" "Disabled,Enabled" bitfld.long 0x04 0. " PSD ,Automatic Power Saving Disable" "No,Yes" line.long 0x08 "MAEXIDR0,MMDC Core Exclusive ID Monitor Register 0" hexmask.long.word 0x08 16.--31. 1. " EXC_ID_MONITOR1 ,Defines ID for Exclusive monitor#1" hexmask.long.word 0x08 0.--15. 1. " EXC_ID_MONITOR0 ,Defines ID for Exclusive monitor#0" line.long 0x0C "MAEXIDR1,MMDC Core Exclusive ID Monitor Register 1" hexmask.long.word 0x0C 16.--31. 1. " EXC_ID_MONITOR3 ,Defines ID for Exclusive monitor#3" hexmask.long.word 0x0C 0.--15. 1. " EXC_ID_MONITOR2 ,Defines ID for Exclusive monitor#2" group.long (0x410)++0x07 line.long 0x00 "MADPCR0,MMDC Core Debug and Profiling Control Register 0" bitfld.long 0x00 9. " SBS ,Step By Step trigger" "Not launched,Launched" bitfld.long 0x00 8. " SBS_EN ,Step By Step debug Enable" "Disabled,Enabled" eventfld.long 0x00 3. " CYC_OVF ,Total Cycles count Overflow" "No overflow,Overflow" textline " " bitfld.long 0x00 2. " PRF_FRZ ,Profiling freeze" "Not frozen,Frozen" bitfld.long 0x00 1. " DBG_RST ,Debug and Profiling Reset" "No reset,Reset" bitfld.long 0x00 0. " DBG_EN ,Debug and Profiling Enable" "Disabled,Enabled" Textline "" line.long 0x04 "MADPCR1,MMDC Core Debug and Profiling Control Register 1" bitfld.long 0x04 31. " PRF_AXI_ID_MASK_31 ,Profiling AXI ID Mask 31" "Masked,Not masked" bitfld.long 0x04 30. " PRF_AXI_ID_MASK_30 ,Profiling AXI ID Mask 30" "Masked,Not masked" bitfld.long 0x04 29. " PRF_AXI_ID_MASK_29 ,Profiling AXI ID Mask 29" "Masked,Not masked" textline " " bitfld.long 0x04 28. " PRF_AXI_ID_MASK_28 ,Profiling AXI ID Mask 28" "Masked,Not masked" bitfld.long 0x04 27. " PRF_AXI_ID_MASK_27 ,Profiling AXI ID Mask 27" "Masked,Not masked" bitfld.long 0x04 26. " PRF_AXI_ID_MASK_26 ,Profiling AXI ID Mask 26" "Masked,Not masked" textline " " bitfld.long 0x04 25. " PRF_AXI_ID_MASK_25 ,Profiling AXI ID Mask 25" "Masked,Not masked" bitfld.long 0x04 24. " PRF_AXI_ID_MASK_24 ,Profiling AXI ID Mask 24" "Masked,Not masked" bitfld.long 0x04 23. " PRF_AXI_ID_MASK_23 ,Profiling AXI ID Mask 23" "Masked,Not masked" textline " " bitfld.long 0x04 22. " PRF_AXI_ID_MASK_22 ,Profiling AXI ID Mask 22" "Masked,Not masked" bitfld.long 0x04 21. " PRF_AXI_ID_MASK_21 ,Profiling AXI ID Mask 21" "Masked,Not masked" bitfld.long 0x04 20. " PRF_AXI_ID_MASK_20 ,Profiling AXI ID Mask 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " PRF_AXI_ID_MASK_19 ,Profiling AXI ID Mask 19" "Masked,Not masked" bitfld.long 0x04 18. " PRF_AXI_ID_MASK_18 ,Profiling AXI ID Mask 18" "Masked,Not masked" bitfld.long 0x04 17. " PRF_AXI_ID_MASK_17 ,Profiling AXI ID Mask 17" "Masked,Not masked" textline " " bitfld.long 0x04 16. " PRF_AXI_ID_MASK_16 ,Profiling AXI ID Mask 16" "Masked,Not masked" bitfld.long 0x04 15. " PRF_AXI_ID[15] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 14. " PRF_AXI_ID[14] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 13. " PRF_AXI_ID[13] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 12. " PRF_AXI_ID[12] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 11. " PRF_AXI_ID[11] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 10. " PRF_AXI_ID[10] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 9. " PRF_AXI_ID[9] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 8. " PRF_AXI_ID[8] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 7. " PRF_AXI_ID[7] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 6. " PRF_AXI_ID[6] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 5. " PRF_AXI_ID[5] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 4. " PRF_AXI_ID[4] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 3. " PRF_AXI_ID[3] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 2. " PRF_AXI_ID[2] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 1. " PRF_AXI_ID[1] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 0. " PRF_AXI_ID[0] ,Profiling AXI ID" "Low,High" textline " " rgroup.long (0x418)++0x1F line.long 0x00 "MADPSR0,MMDC Core Debug and Profiling Status Register 0" line.long 0x04 "MADPSR1,MMDC Core Debug and Profiling Status Register 1" line.long 0x08 "MADPSR2,MMDC Core Debug and Profiling Status Register 2" line.long 0x0C "MADPSR3,MMDC Core Debug and Profiling Status Register 3" line.long 0x10 "MADPSR4,MMDC Core Debug and Profiling Status Register 4" line.long 0x14 "MADPSR5,MMDC Core Debug and Profiling Status Register 5" line.long 0x18 "MASBS0,MMDC Core Step By Step Address" line.long 0x1C "MASBS1,MMDC Core Step By Step Address Attributes" hexmask.long.word 0x1C 16.--31. 1. " SBS_AXI_ID ,Step By Step AXI ID" bitfld.long 0x1C 13.--15. " SBS_LEN ,Step By Step Length" "1,2,3,4,5,6,7,8" bitfld.long 0x1C 12. " SBS_BUFF ,Step By Step Buffered" "0,1" textline " " bitfld.long 0x1C 10.--11. " SBS_BURST ,Step By Step Burst" "Fixed,INCR,WRAP," bitfld.long 0x1C 7.--9. " SBS_SIZE ,Step By Step Size" "8 bits,16 bits,32 bits,64 bits,128 bits,,," bitfld.long 0x1C 4.--6. " SBS_PROT ,Step By Step Protection" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1C 2.--3. " SBS_LOCK ,Step By Step Lock" "0,1,2,3" bitfld.long 0x1C 1. " SBS_TYPE ,Step By Step Request Type" "Write,Read" bitfld.long 0x1C 0. " SBS_VLD ,Step By Step Valid" "Not valid,Valid" textline " " group.long (0x440)++0x03 line.long 0x00 "MAGENP,MMDC Core General Purpose Register" bitfld.long 0x00 31. " GP31 ,General purpose read/write bit 31" "0,1" bitfld.long 0x00 30. " GP30 ,General purpose read/write bit 30" "0,1" bitfld.long 0x00 29. " GP29 ,General purpose read/write bit 29" "0,1" textline " " bitfld.long 0x00 28. " GP28 ,General purpose read/write bit 28" "0,1" bitfld.long 0x00 27. " GP27 ,General purpose read/write bit 27" "0,1" bitfld.long 0x00 26. " GP26 ,General purpose read/write bit 26" "0,1" textline " " bitfld.long 0x00 25. " GP25 ,General purpose read/write bit 25" "0,1" bitfld.long 0x00 24. " GP24 ,General purpose read/write bit 24" "0,1" bitfld.long 0x00 23. " GP23 ,General purpose read/write bit 23" "0,1" textline " " bitfld.long 0x00 22. " GP22 ,General purpose read/write bit 22" "0,1" bitfld.long 0x00 21. " GP21 ,General purpose read/write bit 21" "0,1" bitfld.long 0x00 20. " GP20 ,General purpose read/write bit 20" "0,1" textline " " bitfld.long 0x00 19. " GP19 ,General purpose read/write bit 19" "0,1" bitfld.long 0x00 18. " GP18 ,General purpose read/write bit 18" "0,1" bitfld.long 0x00 17. " GP17 ,General purpose read/write bit 17" "0,1" textline " " bitfld.long 0x00 16. " GP16 ,General purpose read/write bit 16" "0,1" bitfld.long 0x00 15. " GP15 ,General purpose read/write bit 15" "0,1" bitfld.long 0x00 14. " GP14 ,General purpose read/write bit 14" "0,1" textline " " bitfld.long 0x00 13. " GP13 ,General purpose read/write bit 13" "0,1" bitfld.long 0x00 12. " GP12 ,General purpose read/write bit 12" "0,1" bitfld.long 0x00 11. " GP11 ,General purpose read/write bit 11" "0,1" textline " " bitfld.long 0x00 10. " GP10 ,General purpose read/write bit 10" "0,1" bitfld.long 0x00 9. " GP9 ,General purpose read/write bit 9" "0,1" bitfld.long 0x00 8. " GP8 ,General purpose read/write bit 8" "0,1" textline " " bitfld.long 0x00 7. " GP7 ,General purpose read/write bit 7" "0,1" bitfld.long 0x00 6. " GP6 ,General purpose read/write bit 6" "0,1" bitfld.long 0x00 5. " GP5 ,General purpose read/write bit 5" "0,1" textline " " bitfld.long 0x00 4. " GP4 ,General purpose read/write bit 4" "0,1" bitfld.long 0x00 3. " GP3 ,General purpose read/write bit 3" "0,1" bitfld.long 0x00 2. " GP2 ,General purpose read/write bit 2" "0,1" textline " " bitfld.long 0x00 1. " GP1 ,General purpose read/write bit 1" "0,1" bitfld.long 0x00 0. " GP0 ,General purpose read/write bit 0" "0,1" textline " " width 13. group.long 0x800++0x07 line.long 0x00 "MPZQHWCTRL,MMDC PHY ZQ HW Control Register" bitfld.long 0x00 27.--31. " ZQ_EARLY_COMPARATOR_EN_TIMER ,ZQ early comparator enable timer" ",,,,,,,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" bitfld.long 0x00 23.--25. " TZQ_CS ,Device ZQ short time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," bitfld.long 0x00 20.--22. " TZQ_OPER ,Device ZQ long/oper time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," textline " " bitfld.long 0x00 17.--19. " TZQ_INIT ,Device ZQ long/init time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," bitfld.long 0x00 16. " ZQ_HW_FOR ,Force ZQ automatic calibration process with the i.MX ZQ calibration pad" "Not forced,Forced" rbitfld.long 0x00 11.--15. " ZQ_HW_PD_RES ,ZQ HW calibration pull-down result" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" textline " " rbitfld.long 0x00 6.--10. " ZQ_HW_PU_RES ,ZQ automatic calibration pull-up result" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" bitfld.long 0x00 2.--5. " ZQ_HW_PER ,ZQ periodic calibration time" "1 ms,2 ms,4 ms,8 ms,16 ms,32 ms,64 ms,128 ms,256 ms,512 ms,1 sec,2 sec,4 sec,8 sec,16 sec,32 sec" bitfld.long 0x00 0.--1. " ZQ_MODE ,ZQ calibration mode" "Not issued,i.MX ZQ calibration pad/External DDR(when exiting),External DDR,i.MX ZQ calibration pad/External DDR(periodic/when exiting)" line.long 0x04 "MPZQSWCTRL,MMDC PHY ZQ SW control register" bitfld.long 0x04 16.--17. " ZQ_CMP_OUT_SMP ,Amount of cycles between driving the ZQ signals to the ZQ pad" "7 cycles,15 cycles,23 cycles,31 cycles" bitfld.long 0x04 13. " USE_ZQ_SW_VAL ,Use SW ZQ configured value for I/O pads resistor controls" "ZQ_HW_PD_VAL & ZQ_HW_PU_VAL,ZQ_SW_PD_VAL & ZQ_SW_PU_VAL" bitfld.long 0x04 12. " ZQ_SW_PD ,ZQ software PU/PD calibration" "PU,PD" textline " " bitfld.long 0x04 7.--11. " ZQ_SW_PD_VAL ,ZQ software pull-down resistence" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" bitfld.long 0x04 2.--6. " ZQ_SW_PU_VAL ,ZQ software pull-up resistence" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" rbitfld.long 0x04 1. " ZQ_SW_RES ,ZQ software calibration result" "VDD/2" textline " " bitfld.long 0x04 0. " ZQ_SW_FOR ,Force ZQ SW calibration" "Not forced,Forced" group.long (0x808)++0x0B line.long 0x00 "MPWLGCR0,MMDC PHY Write Leveling Error Status Register 0" rbitfld.long 0x00 11. " WL_HW_ERR3 ,Byte3 WL HW calibration error" "No error,Error" rbitfld.long 0x00 10. " WL_HW_ERR2 ,Byte2 WL HW calibration error" "No error,Error" rbitfld.long 0x00 9. " WL_HW_ERR1 ,Byte1 WL HW calibration error" "No error,Error" textline " " rbitfld.long 0x00 8. " WL_HW_ERR0 ,Byte0 WL HW calibration error" "No error,Error" rbitfld.long 0x00 7. " WL_SW_RES3 ,Byte3 WL software result" "Low,High" rbitfld.long 0x00 6. " WL_SW_RES2 ,Byte2 WL software result" "Low,High" textline " " rbitfld.long 0x00 5. " WL_SW_RES1 ,Byte1 WL software result" "Low,High" rbitfld.long 0x00 4. " WL_SW_RES0 ,Byte0 WL software result" "Low,High" bitfld.long 0x00 2. " SW_WL_CNT_EN ,SW WL count down enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SW_WL_EN ,Enable WL SW update" "Disabled,Enabled" bitfld.long 0x00 0. " HW_WL_EN ,Enable WL HW enable" "Disabled,Enabled" line.long 0x04 "MPWLDECTRL0,MMDC PHY Write Leveling Delay Control Register 0" bitfld.long 0x04 25.--26. " WL_CYC_DEL1 ,Write level cycle delay for Byte 1" "No delay,1 cycle,2 cycles," bitfld.long 0x04 24. " WL_HC_DEL1 ,Write level half cycle delay for Byte 1" "No delay,Half cycle" hexmask.long.byte 0x04 16.--22. 1. " WR_DL_ABS_OFFSET1 ,Absolute delay offset for Byte 1" textline " " bitfld.long 0x04 9.--10. " WL_CYC_DEL0 ,Write level cycle delay for Byte 0" "No delay,1 cycle,2 cycles," bitfld.long 0x04 8. " WL_HC_DEL0 ,Write level half cycle delay for Byte 0" "No delay,Half cycle" hexmask.long.byte 0x04 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute delay offset for Byte 0" line.long 0x08 "MPWLDECTRL1,MMDC PHY Write Leveling Delay Control Register 1" bitfld.long 0x08 25.--26. " WL_CYC_DEL3 ,Write level cycle delay for Byte 3" "No delay,1 cycle,2 cycles," bitfld.long 0x08 24. " WL_HC_DEL3 ,Write level half cycle delay for Byte 3" "No delay,Half cycle" hexmask.long.byte 0x08 16.--22. 1. " WR_DL_ABS_OFFSET3 ,Absolute delay offset for Byte 3" textline " " bitfld.long 0x08 9.--10. " WL_CYC_DEL2 ,Write level cycle delay for Byte 2" "No delay,1 cycle,2 cycles," bitfld.long 0x08 8. " WL_HC_DEL2 ,Write level half cycle delay for Byte 2" "No delay,Half cycle" hexmask.long.byte 0x08 0.--6. 1. " WR_DL_ABS_OFFSET2 ,Absolute delay offset for Byte 2" rgroup.long 0x814++0x03 line.long 0x00 "MPWLDLST0,MMDC PHY Write Leveling Delay Line Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " WL_DL_UNIT_NUM3 ,Number of delay units that is actually used by write leveling delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WL_DL_UNIT_NUM2 ,Number of delay units that is actually used by write leveling delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WL_DL_UNIT_NUM1 ,Number of delay units that is actually used by write leveling delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WL_DL_UNIT_NUM0 ,Number of delay units that is actually used by write leveling delay line 0" textline " " group.long 0x818++0x2B line.long 0x00 "MPODTCTRL,MMDC PHY ODT Control Register" bitfld.long 0x00 16.--18. " ODT3_INT_RES ,On chip ODT byte3 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 12.--14. " ODT2_INT_RES ,On chip ODT byte2 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 8.--10. " ODT1_INT_RES ,On chip ODT byte1 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" textline " " bitfld.long 0x00 4.--6. " ODT0_INT_RES ,On chip ODT byte0 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 3. " ODT_RD_ACT_EN ,Active read CS ODT enable" "Disabled,Enabled" bitfld.long 0x00 2. " ODT_RD_PAS_EN ,Inactive read CS ODT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ODT_WR_ACT_EN ,Active write CS ODT enable" "Disabled,Enabled" bitfld.long 0x00 0. " ODT_WR_PAS_EN ,Inactive write CS ODT enable" "Disabled,Enabled" line.long 0x04 "MPRDDQBY0DL,MMDC PHY Read DQ Byte0 Delay Register" bitfld.long 0x04 28.--30. " RD_DQ7_DEL ,Read dqs0 to dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 24.--26. " RD_DQ6_DEL ,Read dqs0 to dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 20.--22. " RD_DQ5_DEL ,Read dqs0 to dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x04 16.--18. " RD_DQ4_DEL ,Read dqs0 to dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 12.--14. " RD_DQ3_DEL ,Read dqs0 to dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 8.--10. " RD_DQ2_DEL ,Read dqs0 to dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x04 4.--6. " RD_DQ1_DEL ,Read dqs0 to dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 0.--2. " RD_DQ0_DEL ,Read dqs0 to dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x08 "MPRDDQBY1DL,MMDC PHY Read DQ Byte1 Delay Register" bitfld.long 0x08 28.--30. " RD_DQ15_DEL ,Read dqs1 to dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 24.--26. " RD_DQ14_DEL ,Read dqs1 to dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 20.--22. " RD_DQ13_DEL ,Read dqs1 to dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x08 16.--18. " RD_DQ12_DEL ,Read dqs1 to dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 12.--14. " RD_DQ11_DEL ,Read dqs1 to dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 8.--10. " RD_DQ10_DEL ,Read dqs1 to dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x08 4.--6. " RD_DQ9_DEL ,Read dqs1 to dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 0.--2. " RD_DQ8_DEL ,Read dqs1 to dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x0C "MPRDDQBY2DL,MMDC PHY Read DQ Byte2 Delay Register" bitfld.long 0x0C 28.--30. " RD_DQ23_DEL ,Read dqs2 to dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 24.--26. " RD_DQ22_DEL ,Read dqs2 to dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 20.--22. " RD_DQ21_DEL ,Read dqs2 to dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x0C 16.--18. " RD_DQ20_DEL ,Read dqs2 to dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 12.--14. " RD_DQ19_DEL ,Read dqs2 to dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 8.--10. " RD_DQ18_DEL ,Read dqs2 to dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x0C 4.--6. " RD_DQ17_DEL ,Read dqs2 to dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 0.--2. " RD_DQ16_DEL ,Read dqs2 to dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x10 "MPRDDQBY3DL,MMDC PHY Read DQ Byte3 Delay Register" bitfld.long 0x10 28.--30. " RD_DQ31_DEL ,Read dqs3 to dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 24.--26. " RD_DQ30_DEL ,Read dqs3 to dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 20.--22. " RD_DQ29_DEL ,Read dqs3 to dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x10 16.--18. " RD_DQ28_DEL ,Read dqs3 to dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 12.--14. " RD_DQ27_DEL ,Read dqs3 to dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 8.--10. " RD_DQ26_DEL ,Read dqs3 to dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x10 4.--6. " RD_DQ25_DEL ,Read dqs3 to dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 0.--2. " RD_DQ24_DEL ,Read dqs3 to dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x14 "MPWRDQBY0DL,MMDC PHY Write DQ Byte0 Delay Register" bitfld.long 0x14 30.--31. " WR_DM0_DEL ,Write dm0 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 28.--29. " WR_DQ7_DEL ,Write dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 24.--25. " WR_DQ6_DEL ,Write dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x14 20.--21. " WR_DQ5_DEL ,Write dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 16.--17. " WR_DQ4_DEL ,Write dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 12.--13. " WR_DQ3_DEL ,Write dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x14 8.--9. " WR_DQ2_DEL ,Write dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 4.--5. " WR_DQ1_DEL ,Write dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 0.--1. " WR_DQ0_DEL ,Write dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x18 "MPWRDQBY1DL,MMDC PHY Write DQ Byte1 Delay Register" bitfld.long 0x18 30.--31. " WR_DM1_DEL ,Write dm1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 28.--29. " WR_DQ15_DEL ,Write dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 24.--25. " WR_DQ14_DEL ,Write dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x18 20.--21. " WR_DQ13_DEL ,Write dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 16.--17. " WR_DQ12_DEL ,Write dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 12.--13. " WR_D11_DEL ,Write dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x18 8.--9. " WR_DQ10_DEL ,Write dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 4.--5. " WR_DQ9_DEL ,Write dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 0.--1. " WR_DQ8_DEL ,Write dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x1C "MPWRDQBY2DL, MMDC PHY Write DQ Byte2 Delay Register" bitfld.long 0x1C 30.--31. " WR_DM2_DEL ,Write dm2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 28.--29. " WR_DQ23_DEL ,Write dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 24.--25. " WR_DQ22_DEL ,Write dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x1C 20.--21. " WR_DQ21_DEL ,Write dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 16.--17. " WR_DQ20_DEL ,Write dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 12.--13. " WR_D19_DEL ,Write dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x1C 8.--9. " WR_DQ18_DEL ,Write dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 4.--5. " WR_DQ17_DEL ,Write dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 0.--1. " WR_DQ16_DEL ,Write dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x20 "MPWRDQBY3DL, MMDC PHY Write DQ Byte3 Delay Register" bitfld.long 0x20 30.--31. " WR_DM3_DEL ,Write dm3 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 28.--29. " WR_DQ31_DEL ,Write dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 24.--25. " WR_DQ30_DEL ,Write dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x20 20.--21. " WR_DQ29_DEL ,Write dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 16.--17. " WR_DQ28_DEL ,Write dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 12.--13. " WR_D27_DEL ,Write dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x20 8.--9. " WR_DQ26_DEL ,Write dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 4.--5. " WR_DQ25_DEL ,Write dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 0.--1. " WR_DQ24_DEL ,Write dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " line.long 0x24 "MPDGCTRL0,MMDC PHY Read DQS gating control register 0" bitfld.long 0x24 31. " RST_RD_FIFO ,Reset Read Data FIFO & pointers" "No reset,Reset" bitfld.long 0x24 30. " DG_CMP_CYC ,Read DQS gating sample cycle" "16 cycles,32 cycles" bitfld.long 0x24 29. " DG_DIS ,Read DQS gating disable" "No,Yes" textline " " bitfld.long 0x24 28. " HW_DG_EN ,Enable automatic read DQS gating calibration" "Disabled,Enabled" bitfld.long 0x24 24.--27. " DG_HC_DEL1 ,Read Dqs1 gating half cycles delay for Byte 1" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," bitfld.long 0x24 23. " DG_EXT_UP ,DG extend upper boundary" "Not extended,Extended" textline " " hexmask.long.byte 0x24 16.--22. 1. " DG_DL_ABS_OFFSET1 ,Absolute delay offset" rbitfld.long 0x24 12. " HW_DG_ERR ,HW DQS gating error " "No error,Error" bitfld.long 0x24 8.--11. " DG_HC_DEL0 ,Read DQS0 gating half cycles delay for Byte 0" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," textline " " hexmask.long.byte 0x24 0.--6. 1. " DG_DL_ABS_OFFSET0 ,Absolute read DQS gating delay offset" line.long 0x28 "MPDGCTRL1,MMDC PHY Read DQS gating control register 1" bitfld.long 0x28 24.--27. " DG_HC_DEL3 ,Read DQS3 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," hexmask.long.byte 0x28 16.--22. 1. " DG_DL_ABS_OFFSET3 ,Absolute read DQS gating delay offset for Byte 3" bitfld.long 0x28 8.--11. " DG_HC_DEL2 ,Read DQS2 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," textline " " hexmask.long.byte 0x28 0.--6. 1. " DG_DL_ABS_OFFSET2 ,Absolute read DQS gating delay offset" rgroup.long 0x844++0x03 line.long 0x00 "MPDGDLST0,MMDC PHY Read DQS gating Delay Line Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " DG_DL_UNIT_NUM3 ,Number of delay units that is actually used by DQS gating delay line 3" hexmask.long.byte 0x00 16.--22. 1. " DG_DL_UNIT_NUM2 ,Number of delay units that is actually used by DQS gating delay line 2" hexmask.long.byte 0x00 8.--14. 1. " DG_DL_UNIT_NUM1 ,Number of delay units that is actually used by DQS gating delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " DG_DL_UNIT_NUM0 ,Number of delay units that is actually used by DQS gating delay line 0" group.long 0x848++0x03 line.long 0x00 "MPRDDLCTL,MMDC PHY Read Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_ABS_OFFSET3 ,Absolute read delay offset byte 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_ABS_OFFSET2 ,Absolute read delay offset byte 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_ABS_OFFSET1 ,Absolute read delay offset byte 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " RD_DL_ABS_OFFSET0 ,Absolute read delay offset byte 0" rgroup.long 0x84C++0x03 line.long 0x00 "MPRDDLST0,MMDC PHY Read Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_UNIT_NUM3 ,Number of delay units that is actually used by read delay line 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_UNIT_NUM2 ,Number of delay units that is actually used by read delay line 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_UNIT_NUM1 ,Number of delay units that is actually used by read delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " RD_DL_UNIT_NUM0 ,Number of delay units that is actually used by read delay line 0" group.long 0x850++0x03 line.long 0x00 "MPWRDLCTL0,MMDC PHY Write Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_ABS_OFFSET3 ,Absolute write delay offset for Byte 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_ABS_OFFSET2 ,Absolute write delay offset for Byte 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_ABS_OFFSET1 ,Absolute write delay offset for Byte 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute write delay offset for Byte 0" rgroup.long 0x854++0x03 line.long 0x00 "MPWRDLST0,MMDC PHY Write Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_UNIT_NUM3 ,Number of delay units that is actually used by write delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_UNIT_NUM2 ,Number of delay units that is actually used by write delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_UNIT_NUM1 ,Number of delay units that is actually used by write delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WR_DL_UNIT_NUM0 ,Number of delay units that is actually used by write delay line 0" textline " " group.long 0x858++0x03 line.long 0x00 "MPSDCTRL,MMDC PHY CK control Register" bitfld.long 0x00 8.--9. " SDCLK_DEL ,SDCLK0 delay fine tuning" "No change,1 delay,2 delays,3 delays" hgroup.long 0x85C++0x03 hide.long 0x00 "MPZQLP2CTL,MMDC PHY ZQ LPDDR2 HW Control Register" group.long 0x860++0x07 line.long 0x00 "MPRDDLHWCTL,MMDC PHY Read Delay HW Calibration Control Register" bitfld.long 0x00 5. " HW_RDL_CMP_CYC ,HW RD DL sample cycle" "Not compared,Compared" bitfld.long 0x00 4. " HW_RDL_EN ,Enable HW RD DL calibration" "Disabled,Enabled" rbitfld.long 0x00 3. " HW_RDL_ERR3 ,HW RD DL3 error" "No error,Error" textline " " rbitfld.long 0x00 2. " HW_RDL_ERR2 ,HW RD DL2 error" "No error,Error" rbitfld.long 0x00 1. " HW_RDL_ERR1 ,HW RD DL1 error" "No error,Error" rbitfld.long 0x00 0. " HW_RDL_ERR0 ,HW RD DL0 error" "No error,Error" line.long 0x04 "MPWRDLHWCTL,MMDC PHY Write Delay HW Calibration Control Register" bitfld.long 0x04 5. " HW_WDL_CMP_CYC ,HW RD DL sample cycle" "Not compared,Compared" bitfld.long 0x04 4. " HW_WDL_EN ,Enable HW RD DL calibration" "Disabled,Enabled" rbitfld.long 0x04 3. " HW_WDL_ERR3 ,HW RD DL3 error" "No error,Error" textline " " rbitfld.long 0x04 2. " HW_WDL_ERR2 ,HW RD DL2 error" "No error,Error" rbitfld.long 0x04 1. " HW_WDL_ERR1 ,HW RD DL1 error" "No error,Error" rbitfld.long 0x04 0. " HW_WDL_ERR0 ,HW RD DL0 error" "No error,Error" rgroup.long 0x868++0x23 line.long 0x00 "MPRDDLHWST0,MMDC PHY Read Delay HW Calibration Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " HW_RD_DL_UP1 ,HW RD DL1 upper boundary" hexmask.long.byte 0x00 16.--22. 1. " HW_RD_DL_LOW1 ,HW RD DL1 lower boundary" hexmask.long.byte 0x00 8.--14. 1. " HW_RD_DL_UP0 ,HW RD DL0 upper boundary" textline " " hexmask.long.byte 0x00 0.--6. 1. " HW_RD_DL_LOW0 ,HW RD DL0 lower boundary" line.long 0x04 "MPRDDLHWST1,MMDC PHY Read Delay HW Calibration Status Register 1" hexmask.long.byte 0x04 24.--30. 1. " HW_RD_DL_UP3 ,HW RD DL3 upper boundary" hexmask.long.byte 0x04 16.--22. 1. " HW_RD_DL_LOW3 ,HW RD DL3 lower boundary" hexmask.long.byte 0x04 8.--14. 1. " HW_RD_DL_UP2 ,HW RD DL2 upper boundary" textline " " hexmask.long.byte 0x04 0.--6. 1. " HW_RD_DL_LOW2 ,HW RD DL2 lower boundary" line.long 0x08 "MPWRDLHWST0,MMDC PHY Write Delay HW Calibration Status Register 0" hexmask.long.byte 0x08 24.--30. 1. " HW_WR_DL_UP1 ,HW WR DL1 upper boundary" hexmask.long.byte 0x08 16.--22. 1. " HW_WR_DL_LOW1 ,HW WR DL1 lower boundary" hexmask.long.byte 0x08 8.--14. 1. " HW_WR_DL_UP0 ,HW WR DL0 upper boundary" textline " " hexmask.long.byte 0x08 0.--6. 1. " HW_WR_DL_LOW0 ,HW WR DL0 lower boundary" line.long 0x0C "MPWRDLHWST1,MMDC PHY Write Delay HW Calibration Status Register 1" hexmask.long.byte 0x0C 24.--30. 1. " HW_WR_DL_UP3 ,HW WR DL3 upper boundary" hexmask.long.byte 0x0C 16.--22. 1. " HW_WR_DL_LOW3 ,HW WR DL3 lower boundary" hexmask.long.byte 0x0C 8.--14. 1. " HW_WR_DL_UP2 ,HW WR DL2 upper boundary" textline " " hexmask.long.byte 0x0C 0.--6. 1. " HW_WR_DL_LOW2 ,HW WR DL2 lower boundary" line.long 0x10 "MPWLHWERR0,MMDC PHY Write Leveling HW Error Register 0" hexmask.long.byte 0x10 24.--31. 1. " HW_WL3_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 16.--23. 1. " HW_WL2_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 8.--15. 1. " HW_WL1_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" textline " " hexmask.long.byte 0x10 0.--7. 1. " HW_WL0_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" textline " " line.long 0x14 "MPDGHWST0,MMDC PHY Read DQS Gating HW Status Register 0" hexmask.long.word 0x14 16.--26. 1. " HW_DG_UP0 ,HW DG0 upper boundary" hexmask.long.word 0x14 0.--10. 1. " HW_DG_LOW0 ,HW DG0 lower boundary" line.long 0x18 "MPDGHWST1,MMDC PHY Read DQS Gating HW Status Register 1" hexmask.long.word 0x18 16.--26. 1. " HW_DG_UP1 ,HW DG1 upper boundary" hexmask.long.word 0x18 0.--10. 1. " HW_DG_LOW1 ,HW DG1 lower boundary" line.long 0x1C "MPDGHWST2,MMDC PHY Read DQS Gating HW Status Register 2" hexmask.long.word 0x1C 16.--26. 1. " HW_DG_UP2 ,HW DG2 upper boundary" hexmask.long.word 0x1C 0.--10. 1. " HW_DG_LOW2 ,HW DG2 lower boundary" line.long 0x20 "MPDGHWST3,MMDC PHY Read DQS Gating HW Status Register 3" hexmask.long.word 0x20 16.--26. 1. " HW_DG_UP3 ,HW DG3 upper boundary" hexmask.long.word 0x20 0.--10. 1. " HW_DG_LOW3 ,HW DG3 lower boundary" group.long 0x88C++0x0B line.long 0x00 "MPPDCMPR1,MMDC PHY Pre-defined Compare Register 1" hexmask.long.word 0x00 16.--31. 1. " PDV2 ,Pre defined compare value2" hexmask.long.word 0x00 0.--15. 1. " PDV1 ,Pre defined compare value2" line.long 0x04 "MPPDCMPR2,MMDC PHY Pre-defined Compare and CA Delay Line Configuration Register" bitfld.long 0x04 2. " READ_LEVEL_PATTERN ,MPR calibration Read level pattern" "1010," bitfld.long 0x04 1. " MPR_FULL_CMP ,MPR full compare enable" "Disabled,Enabled" bitfld.long 0x04 0. " MPR_CMP ,MPR compare enable" "Disabled,Enabled" line.long 0x08 "MPSWDAR0,MMDC PHY SW Dummy Access Register 0" rbitfld.long 0x08 5. " SW_DUM_CMP3 ,SW dummy read byte3 compare results" "Failed,Passed" rbitfld.long 0x08 4. " SW_DUM_CMP2 ,SW dummy read byte2 compare results" "Failed,Passed" rbitfld.long 0x08 3. " SW_DUM_CMP1 ,SW dummy read byte1 compare results" "Failed,Passed" textline " " rbitfld.long 0x08 2. " SW_DUM_CMP0 ,SW dummy read byte0 compare results" "Failed,Passed" bitfld.long 0x08 1. " SW_DUMMY_RD ,SW dummy read" "Not generated,Generated" bitfld.long 0x08 0. " SW_DUMMY_WR ,SW dummy write" "Not generated,Generated" rgroup.long 0x898++0x1F line.long 0x00 "MPSWDRDR0,MMDC PHY SW Dummy Read Data Register 0" line.long 0x04 "MPSWDRDR1,MMDC PHY SW Dummy Read Data Register 1" line.long 0x08 "MPSWDRDR2,MMDC PHY SW Dummy Read Data Register 2" line.long 0x0C "MPSWDRDR3,MMDC PHY SW Dummy Read Data Register 3" line.long 0x10 "MPSWDRDR4,MMDC PHY SW Dummy Read Data Register 4" line.long 0x14 "MPSWDRDR5,MMDC PHY SW Dummy Read Data Register 5" line.long 0x18 "MPSWDRDR6,MMDC PHY SW Dummy Read Data Register 6" line.long 0x1C "MPSWDRDR7,MMDC PHY SW Dummy Read Data Register 7" textline " " group.long 0x8B8++0x03 line.long 0x00 "MPMUR0,MMDC PHY Measure Unit Register for DQ0-3" hexmask.long.word 0x00 16.--25. 1. " MU_UNIT_DEL_NUM ,Measure unit measured number of unit delay per cycle" bitfld.long 0x00 11. " FRC_MSR ,Force measuement on delay line" "Not forced,Forced" bitfld.long 0x00 10. " MU_BYP_EN ,Measure unit bypass enable" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--9. 1. " MU_BYP_VAL ,Measure unit bypass value" hgroup.long 0x8BC++0x03 hide.long 0x00 "MPWRCADL,MMDC PHY Write CA Delay Control Register" rgroup.long 0x8C0++0x03 line.long 0x00 "MPDCCR,MMDC PHY Duty Cycle Control Register" bitfld.long 0x00 28.--30. " RD_DQS3_FT_DCC ,Read dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 25.--27. " RD_DQS2_FT_DCC ,Read dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 22.--24. " RD_DQS1_FT_DCC ,Read dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 19.--21. " RD_DQS0_FT_DCC ,Read dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 16.--18. " CK_FT1_DCC ,Secondary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 12.--14. " CK_FT0_DCC ,Primary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 9.--11. " WR_DQS3_FT_DCC ,Write dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 6.--8. " WR_DQS2_FT_DCC ,Write dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 3.--5. " WR_DQS1_FT_DCC ,Write dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 0.--2. " WR_DQS0_FT_DCC ,Write dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," else group.long 0x18++0x03 line.long 0x00 "MDMISC,MMDC Core Miscellaneous Register" bitfld.long 0x00 3.--4. " DDR_TYPE ,DDR TYPE" "DDR3,LPDDR2,..." endif width 11. else base ad:0x421B0000 width 10. if (((per.l(ad:0x421B0000+0x18))&0x18)==0x08) group.long (0x00)++0x07 line.long 0x00 "MDCTL,MMDC Core Control Register" bitfld.long 0x00 31. " SDE_0 ,MMDC Enable CS0" "Disabled,Enabled" bitfld.long 0x00 30. " SDE_1 ,MMDC Enable CS1" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--26. " ROW ,Row Address Width" "11-bits,12-bits,13-bits,14-bits,15-bits,16-bits,," bitfld.long 0x00 20.--22. " COL ,Column Address Width" "9-bits,10-bits,11-bits,8-bits,12-bits,,," textline " " bitfld.long 0x00 19. " BL ,Burst Length" "4,8" bitfld.long 0x00 16.--17. " DSIZ ,DDR data bus size" "16-bit,32-bit,," line.long 0x04 "MDPDC,MMDC Core Power Down Control Register" bitfld.long 0x04 28.--30. " PRCT_1 ,Precharge Timer - Chip Select 1" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x04 24.--26. " PRCT_0 ,Precharge Timer - Chip Select 0" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" textline " " bitfld.long 0x04 16.--18. " TCKE ,CKE minimum pulse width" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 12.--15. " PWDT_1 ,Power Down Timer - Chip Select 1" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,,," textline " " bitfld.long 0x04 8.--11. " PWDT_0 ,Power Down Timer - Chip Select 0" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,,," bitfld.long 0x04 7. " SLOW_PD ,Slow/fast power down" "Fast,Slow" textline " " bitfld.long 0x04 6. " BOTH_CS_PD ,Both chip selects power-down" "Independently,Both" bitfld.long 0x04 3.--5. " TCKSRX ,Valid clock requirement before self-refresh exit" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x04 0.--2. " TCKSRE ,Valid clock requirement after self-refresh entry" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" hgroup.long (0x08)++0x03 hide.long 0x00 "MDOTC,MMDC Core ODT Timing Control Register" group.long (0x0C)++0x17 line.long 0x00 "MDCFG0,MMDC Core Timing Configuration Register 0" hexmask.long.byte 0x00 24.--31. 1. " TRFC ,Refresh command to Active or Refresh command time" hexmask.long.byte 0x00 16.--23. 1. " TXS ,Exit self refresh to non READ command." textline " " bitfld.long 0x00 13.--15. " TXP ,Exit power-down to next valid command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 4.--8. " TFAW ,Four Active Window" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" textline " " bitfld.long 0x00 0.--3. " TRL ,CAS Read Latency" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,,,,,,," line.long 0x04 "MDCFG1,MMDC Core Timing Configuration Register 1" bitfld.long 0x04 29.--31. " TRCD_LP ,Active command to internal read or write delay time" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x04 26.--28. " TRPPB_LP ,Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" textline " " bitfld.long 0x04 21.--25. " TRC_LP ,Active to Active or Refresh command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 cloks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x04 16.--20. " TRAS ,Active to Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks," textline " " bitfld.long 0x04 15. " TRPAB_LP ,Precharge-all command period" "TRP,TRP+1" bitfld.long 0x04 9.--11. " TWR ,WRITE recovery time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x04 5.--8. " TMRD ,Mode Register Set command cycle" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x04 0.--2. " WL ,CAS Write Latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles," line.long 0x08 "MDCFG2,MMDC Core Timing Configuration Register 2" bitfld.long 0x08 6.--8. " TRTP ,Internal READ command to PRECHARGE command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x08 3.--5. " TWTR ,Internal WRITE to READ command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x08 0.--2. " TRRD ,ACTIVE to ACTIVE command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles," line.long 0x0C "MDMISC,MMDC Core Miscellaneous Register" rbitfld.long 0x0C 31. " CS0_RDY ,External status device on CS0" "Wake-up,Ready" rbitfld.long 0x0C 30. " CS1_RDY ,External status device on CS1" "Wake-up,Ready" textline " " bitfld.long 0x0C 21. " CK1_GATING ,Gating the secondary DDR clock" "Not gated,Gated" bitfld.long 0x0C 20. " CALIB_PER_CS ,Defines the CS number that the associated calibration is targeted at" "CS0,CS1" textline " " bitfld.long 0x0C 18. " LHD ,Latency hiding disable" "No,Yes" bitfld.long 0x0C 16.--17. " WALAT ,Write Additional latency" "Not required,1 cycles,2 cycles,3 cycles" textline " " bitfld.long 0x0C 12. " BI_ON ,Bank Interleaving On" "Not interleaved,Interleaved" bitfld.long 0x0C 11. " LPDDR2_S2 ,LPDDR2 S2 device type indication" "LPDDR2-S4,LPDDR2-S2" textline " " bitfld.long 0x0C 9.--10. " MIF3_MODE ,Command prediction working mode" "Disabled,First pipe line stage,First pipe line stage/axi bus,First pipe line stage/axi bus/access queue" textline " " bitfld.long 0x0C 6.--8. " RALAT ,Read Additional Latency" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x0C 5. " DDR_4_BANK ,DDR device with 4 Banks" "8 banks,4 banks" textline " " bitfld.long 0x0C 3.--4. " DDR_TYPE ,DDR TYPE" "DDR3,LPDDR2,," bitfld.long 0x0C 2. " LPDDR2_2CH ,LPDDR2_2CH" "0,1" textline " " bitfld.long 0x0C 1. " RST ,Software Reset" "No operation,Asserted" line.long 0x10 "MDSCR,MMDC Core Special Command Register" hexmask.long.byte 0x10 24.--31. 1. " MR_OP ,MRW 8 bit operand" hexmask.long.byte 0x10 16.--23. 1. " MR_ADDR , MRR/MRW ADDRESS" textline " " bitfld.long 0x10 15. " CON_REQ ,Configuration request" "Not requested,Requested" rbitfld.long 0x10 14. " CON_ACK ,Configuration acknowledge" "Forbidden,Permitted" textline " " rbitfld.long 0x10 10. " MRR_READ_DATA_VALID ,MRR READ DATA VALID" "Cleared,Set" bitfld.long 0x10 9. " WL_EN ,Write Level Enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4.--6. " CMD ,Command" "Normal operation,Precharge all,Auto-Refresh,MRW Command,ZQ calibration,Precharge all,MRR," bitfld.long 0x10 3. " CMD_CS ,Chip Select" "0,1" textline " " bitfld.long 0x10 0.--2. " CMD_BA ,Bank Address" "0,1,2,3,4,5,6,7" line.long 0x14 "MDREF,MMDC Core Refresh Control Register" hexmask.long.word 0x14 16.--31. 1. " REF_CNT ,Refresh Counter" bitfld.long 0x14 14.--15. " REF_SEL ,Refresh Selector" "64KHz,32KHz,REF_CNT,Disabled" textline " " bitfld.long 0x14 11.--13. " REFR ,Number of refresh commands every refresh cycle" "1 refresh,2 refreshes,3 refreshes,4 refreshes,5 refreshes,6 refreshes,7 refreshes,8 refreshes" bitfld.long 0x14 0. " START_REF ,Start Refresh cycle" "No operation,Started" group.long (0x2C)++0x7 line.long 0x00 "MDRWD,MMDC Core Read/Write Command Delay Register" hexmask.long.word 0x00 16.--28. 1. " TDAI ,Device auto initialization period" bitfld.long 0x00 12.--14. " RTW_SAME ,Controls the cycles delay between Read to Write commands in same chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 9.--11. " WTR_DIFF ,Controls the cycles delay between Write to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 6.--8. " WTW_DIFF ,Controls the cycles delay between Write to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 3.--5. " RTW_DIFF ,Controls the cycles delay between Read to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " RTR_DIFF ,Controls the cycles delay between Read to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" line.long 0x04 "MDOR,MMDC Core Out of Reset Delays Register" bitfld.long 0x04 0.--5. " RST_TO_CKE ,Idle time after first CKE assertion" ",,,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles" textline " " width 13. rgroup.long 0x34++0x03 line.long 0x00 "MDMRR,MMDC Core MRR Data Register" hexmask.long.byte 0x00 24.--31. 1. " MRR_READ_DATA3 ,MRR DATA that arrived on DQ[31:24]" hexmask.long.byte 0x00 16.--23. 1. " MRR_READ_DATA2 ,MRR DATA that arrived on DQ[23:16]" hexmask.long.byte 0x00 8.--15. 1. " MRR_READ_DATA1 ,MRR DATA that arrived on DQ[15:8]" textline " " hexmask.long.byte 0x00 0.--7. 1. " MRR_READ_DATA0 ,MRR DATA that arrived on DQ[7:0]" group.long 0x38++0x0B line.long 0x00 "MDCFG3LP,MMDC Core Timing Configuration Register 3" bitfld.long 0x00 16.--21. " RC_LP ,ACT to ACT or REF command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks,33 clocks,34 clocks,35 clocks,36 clocks,37 clocks,38 clocks,39 clocks,40 clocks,41 clocks,42 clocks,43 clocks,44 clocks,45 clocks,46 clocks,47 clocks,48 clocks,49 clocks,50 clocks,51 clocks,52 clocks,53 clocks,54 clocks,55 clocks,56 clocks,57 clocks,58 clocks,59 clocks,60 clocks,61 clocks,62 clocks,63 clocks," bitfld.long 0x00 8.--11. " TRCD_LP ,ACT command to internal read or write delay time" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks," bitfld.long 0x00 4.--7. " TRPPB_LP ,PRECHARGE (per bank) command period (same bank)" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks," textline " " bitfld.long 0x00 0.--3. " TRPAB_LP ,PRECHARGE (all banks) command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks," line.long 0x04 "MDMR4,MMDC Core MR4 Derating Register" bitfld.long 0x04 8. " TRRD_DE ,TRRD derating value" "None,1 cycle" bitfld.long 0x04 7. " TRP_DE ,TRP derating value" "None,1 cycle" bitfld.long 0x04 6. " TRAS_DE ,TRAS derating value" "None,1 cycle" textline " " bitfld.long 0x04 5. " TRC_DE ,TRC derating value" "None,1 cycle" bitfld.long 0x04 4. " TRCD_DE ,TRCD derating value" "None,1 cycle" rbitfld.long 0x04 1. " UPDATE_DE_ACK ,Update Derated Values Acknowledge" "No update,Updated" textline " " bitfld.long 0x04 0. " UPDATE_DE_REQ ,Update Derated Values Request" "No operation,Requested" line.long 0x08 "MDASP,MMDC Core Address Space Partition Register" hexmask.long.byte 0x08 0.--6. 1. " CS0_END ,Define the absolute last address associated with CS0" group.long (0x400)++0x0F line.long 0x00 "MAARCR,MMDC Core AXI Re-ordering Control Register" bitfld.long 0x00 31. " ARCR_SEC_ERR_LOCK ,ARCR_SEC_ERR_EN lock" "Unlocked,Locked" bitfld.long 0x00 30. " ARCR_SEC_ERR_EN ,Security read/write access violation in OKAY/SLV Error response " "OKAY,SLAVE error" bitfld.long 0x00 28. " ARCR_EXC_ERR_EN ,Exclusive read/write access violation of AXI 6.2.4 rule in OKAY/SLV Error response " "OKAY,SLAVE error" textline " " bitfld.long 0x00 24. " ARCR_RCH_EN ,Real time channel enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ARCR_PAG_HIT ,ARCR Page Hit Rate" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " ARCR_ACC_HIT ,ARCR Access Hit Rate" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--11. " ARCR_DYN_JMP ,ARCR Dynamic Jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ARCR_DYN_MAX ,ARCR Dynamic Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARCR_GUARD ,ARCR Guard" "15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30" line.long 0x04 "MAPSR,MMDC Core Power Saving Control and Status Register" rbitfld.long 0x04 25. " DVACK ,General DVFS acknowledge" "Not asserted,Asserted" rbitfld.long 0x04 24. " LPACK ,General low-power acknowledge" "Not asserted,Asserted" bitfld.long 0x04 21. " DVFS ,General DVFS request" "Not requested,Requested" textline " " bitfld.long 0x04 20. " LPMD ,General LPMD request" "Not requested,Requested" hexmask.long.byte 0x04 8.--15. 1. " PST ,Automatic Power saving timer" rbitfld.long 0x04 6. " WIS ,Write Idle Status" "Idle,Not Idle" textline " " rbitfld.long 0x04 5. " RIS ,Read Idle Status" "Idle,Not Idle" rbitfld.long 0x04 4. " PSS ,Power Saving Status" "Disabled,Enabled" bitfld.long 0x04 0. " PSD ,Automatic Power Saving Disable" "No,Yes" line.long 0x08 "MAEXIDR0,MMDC Core Exclusive ID Monitor Register 0" hexmask.long.word 0x08 16.--31. 1. " EXC_ID_MONITOR1 ,Defines ID for Exclusive monitor #1" hexmask.long.word 0x08 0.--15. 1. " EXC_ID_MONITOR0 ,Defines ID for Exclusive monitor #0" line.long 0x0C "MAEXIDR1,MMDC Core Exclusive ID Monitor Register 1" hexmask.long.word 0x0C 16.--31. 1. " EXC_ID_MONITOR3 ,Defines ID for Exclusive monitor #3" hexmask.long.word 0x0C 0.--15. 1. " EXC_ID_MONITOR2 ,Defines ID for Exclusive monitor #2" group.long (0x410)++0x07 line.long 0x00 "MADPCR0,MMDC Core Debug and Profiling Control Register 0" bitfld.long 0x00 9. " SBS ,Step By Step trigger" "Not launched,Launched" bitfld.long 0x00 8. " SBS_EN ,Step By Step debug enable" "Disabled,Enabled" eventfld.long 0x00 3. " CYC_OVF ,Total Cycles Count Overflow" "No overflow,Overflow" textline " " bitfld.long 0x00 2. " PRF_FRZ ,Profiling freeze" "Not frozen,Frozen" bitfld.long 0x00 1. " DBG_RST ,Debug and Profiling Reset" "No reset,Reset" bitfld.long 0x00 0. " DBG_EN ,Debug and Profiling Enable" "Disabled,Enabled" textline " " line.long 0x04 "MADPCR1,MMDC Core Debug and Profiling Control Register 1" bitfld.long 0x04 31. " PRF_AXI_ID_MASK_31 ,Profiling AXI ID Mask 31" "Masked,Not masked" bitfld.long 0x04 30. " PRF_AXI_ID_MASK_30 ,Profiling AXI ID Mask 30" "Masked,Not masked" bitfld.long 0x04 29. " PRF_AXI_ID_MASK_29 ,Profiling AXI ID Mask 29" "Masked,Not masked" textline " " bitfld.long 0x04 28. " PRF_AXI_ID_MASK_28 ,Profiling AXI ID Mask 28" "Masked,Not masked" bitfld.long 0x04 27. " PRF_AXI_ID_MASK_27 ,Profiling AXI ID Mask 27" "Masked,Not masked" bitfld.long 0x04 26. " PRF_AXI_ID_MASK_26 ,Profiling AXI ID Mask 26" "Masked,Not masked" textline " " bitfld.long 0x04 25. " PRF_AXI_ID_MASK_25 ,Profiling AXI ID Mask 25" "Masked,Not masked" bitfld.long 0x04 24. " PRF_AXI_ID_MASK_24 ,Profiling AXI ID Mask 24" "Masked,Not masked" bitfld.long 0x04 23. " PRF_AXI_ID_MASK_23 ,Profiling AXI ID Mask 23" "Masked,Not masked" textline " " bitfld.long 0x04 22. " PRF_AXI_ID_MASK_22 ,Profiling AXI ID Mask 22" "Masked,Not masked" bitfld.long 0x04 21. " PRF_AXI_ID_MASK_21 ,Profiling AXI ID Mask 21" "Masked,Not masked" bitfld.long 0x04 20. " PRF_AXI_ID_MASK_20 ,Profiling AXI ID Mask 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " PRF_AXI_ID_MASK_19 ,Profiling AXI ID Mask 19" "Masked,Not masked" bitfld.long 0x04 18. " PRF_AXI_ID_MASK_18 ,Profiling AXI ID Mask 18" "Masked,Not masked" bitfld.long 0x04 17. " PRF_AXI_ID_MASK_17 ,Profiling AXI ID Mask 17" "Masked,Not masked" textline " " bitfld.long 0x04 16. " PRF_AXI_ID_MASK_16 ,Profiling AXI ID Mask 16" "Masked,Not masked" bitfld.long 0x04 15. " PRF_AXI_ID[15] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 14. " PRF_AXI_ID[14] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 13. " PRF_AXI_ID[13] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 12. " PRF_AXI_ID[12] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 11. " PRF_AXI_ID[11] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 10. " PRF_AXI_ID[10] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 9. " PRF_AXI_ID[9] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 8. " PRF_AXI_ID[8] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 7. " PRF_AXI_ID[7] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 6. " PRF_AXI_ID[6] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 5. " PRF_AXI_ID[5] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 4. " PRF_AXI_ID[4] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 3. " PRF_AXI_ID[3] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 2. " PRF_AXI_ID[2] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 1. " PRF_AXI_ID[1] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 0. " PRF_AXI_ID[0] ,Profiling AXI ID" "Low,High" textline " " rgroup.long (0x418)++0x1F line.long 0x00 "MADPSR0,MMDC Core Debug and Profiling Status Register 0" line.long 0x04 "MADPSR1,MMDC Core Debug and Profiling Status Register 1" line.long 0x08 "MADPSR2,MMDC Core Debug and Profiling Status Register 2" line.long 0x0C "MADPSR3,MMDC Core Debug and Profiling Status Register 3" line.long 0x10 "MADPSR4,MMDC Core Debug and Profiling Status Register 4" line.long 0x14 "MADPSR5,MMDC Core Debug and Profiling Status Register 5" line.long 0x18 "MASBS0,MMDC Core Step By Step Address" line.long 0x1C "MASBS1,MMDC Core Step By Step Address Attributes" hexmask.long.word 0x1C 16.--31. 1. " SBS_AXI_ID ,Step By Step AXI ID" bitfld.long 0x1C 13.--15. " SBS_LEN ,Step By Step Length" "1,2,3,4,5,6,7,8" bitfld.long 0x1C 12. " SBS_BUFF ,Step By Step Buffered" "0,1" textline " " bitfld.long 0x1C 10.--11. " SBS_BURST ,Step By Step Burst" "Fixed,INCR,WRAP," bitfld.long 0x1C 7.--9. " SBS_SIZE ,Step By Step Size" "8 bits,16 bits,32 bits,64 bits,128 bits,,," bitfld.long 0x1C 4.--6. " SBS_PROT ,Step By Step Protection" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1C 2.--3. " SBS_LOCK ,Step By Step Lock" "0,1,2,3" bitfld.long 0x1C 1. " SBS_TYPE ,Step By Step Request Type" "Write,Read" bitfld.long 0x1C 0. " SBS_VLD ,Step By Step Valid" "Not valid,Valid" textline " " group.long (0x440)++0x03 line.long 0x00 "MAGENP,MMDC Core General Purpose Register" bitfld.long 0x00 31. " GP31 ,General purpose read/write bit 31" "0,1" bitfld.long 0x00 30. " GP30 ,General purpose read/write bit 30" "0,1" bitfld.long 0x00 29. " GP29 ,General purpose read/write bit 29" "0,1" textline " " bitfld.long 0x00 28. " GP28 ,General purpose read/write bit 28" "0,1" bitfld.long 0x00 27. " GP27 ,General purpose read/write bit 27" "0,1" bitfld.long 0x00 26. " GP26 ,General purpose read/write bit 26" "0,1" textline " " bitfld.long 0x00 25. " GP25 ,General purpose read/write bit 25" "0,1" bitfld.long 0x00 24. " GP24 ,General purpose read/write bit 24" "0,1" bitfld.long 0x00 23. " GP23 ,General purpose read/write bit 23" "0,1" textline " " bitfld.long 0x00 22. " GP22 ,General purpose read/write bit 22" "0,1" bitfld.long 0x00 21. " GP21 ,General purpose read/write bit 21" "0,1" bitfld.long 0x00 20. " GP20 ,General purpose read/write bit 20" "0,1" textline " " bitfld.long 0x00 19. " GP19 ,General purpose read/write bit 19" "0,1" bitfld.long 0x00 18. " GP18 ,General purpose read/write bit 18" "0,1" bitfld.long 0x00 17. " GP17 ,General purpose read/write bit 17" "0,1" textline " " bitfld.long 0x00 16. " GP16 ,General purpose read/write bit 16" "0,1" bitfld.long 0x00 15. " GP15 ,General purpose read/write bit 15" "0,1" bitfld.long 0x00 14. " GP14 ,General purpose read/write bit 14" "0,1" textline " " bitfld.long 0x00 13. " GP13 ,General purpose read/write bit 13" "0,1" bitfld.long 0x00 12. " GP12 ,General purpose read/write bit 12" "0,1" bitfld.long 0x00 11. " GP11 ,General purpose read/write bit 11" "0,1" textline " " bitfld.long 0x00 10. " GP10 ,General purpose read/write bit 10" "0,1" bitfld.long 0x00 9. " GP9 ,General purpose read/write bit 9" "0,1" bitfld.long 0x00 8. " GP8 ,General purpose read/write bit 8" "0,1" textline " " bitfld.long 0x00 7. " GP7 ,General purpose read/write bit 7" "0,1" bitfld.long 0x00 6. " GP6 ,General purpose read/write bit 6" "0,1" bitfld.long 0x00 5. " GP5 ,General purpose read/write bit 5" "0,1" textline " " bitfld.long 0x00 4. " GP4 ,General purpose read/write bit 4" "0,1" bitfld.long 0x00 3. " GP3 ,General purpose read/write bit 3" "0,1" bitfld.long 0x00 2. " GP2 ,General purpose read/write bit 2" "0,1" textline " " bitfld.long 0x00 1. " GP1 ,General purpose read/write bit 1" "0,1" bitfld.long 0x00 0. " GP0 ,General purpose read/write bit 0" "0,1" textline " " group.long 0x800++0x07 line.long 0x00 "MPZQHWCTRL,MMDC PHY ZQ HW Control Register" bitfld.long 0x00 27.--31. " ZQ_EARLY_COMPARATOR_EN_TIMER ,ZQ early comparator enable timer" ",,,,,,,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" bitfld.long 0x00 23.--25. " TZQ_CS ,Device ZQ short time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," bitfld.long 0x00 20.--22. " TZQ_OPER ,Device ZQ long/oper time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," textline " " bitfld.long 0x00 17.--19. " TZQ_INIT ,Device ZQ long/init time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," bitfld.long 0x00 16. " ZQ_HW_FOR ,Force ZQ automatic calibration process with the i.MX ZQ calibration pad" "Not forced,Forced" rbitfld.long 0x00 11.--15. " ZQ_HW_PD_RES ,ZQ HW calibration pull-down result" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" textline " " rbitfld.long 0x00 6.--10. " ZQ_HW_PU_RES ,ZQ automatic calibration pull-up result" "0 (minimum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (maximum)" bitfld.long 0x00 2.--5. " ZQ_HW_PER ,ZQ periodic calibration time" "1 ms,2 ms,4 ms,8 ms,16 ms,32 ms,64 ms,128 ms,256 ms,512 ms,1 sec,2 sec,4 sec,8 sec,16 sec,32 sec" bitfld.long 0x00 0.--1. " ZQ_MODE ,ZQ calibration mode" "Not issued,i.MX ZQ calibration pad/External DDR (when exiting),External DDR,i.MX ZQ calibration pad/External DDR (periodic/when exiting)" line.long 0x04 "MPZQSWCTRL,MMDC PHY ZQ SW control register" bitfld.long 0x04 16.--17. " ZQ_CMP_OUT_SMP ,Amount of cycles between driving the ZQ signals to the ZQ pad" "7 cycles,15 cycles,23 cycles,31 cycles" bitfld.long 0x04 13. " USE_ZQ_SW_VAL ,Use SW ZQ configured value for I/O pads resistor controls" "ZQ_HW_PD_VAL & ZQ_HW_PU_VAL,ZQ_SW_PD_VAL & ZQ_SW_PU_VAL" bitfld.long 0x04 12. " ZQ_SW_PD ,ZQ software PU/PD calibration" "PU,PD" textline " " bitfld.long 0x04 7.--11. " ZQ_SW_PD_VAL ,ZQ software pull-down resistence" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" bitfld.long 0x04 2.--6. " ZQ_SW_PU_VAL ,ZQ software pull-up resistence" "0 (minimum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (maximum)" rbitfld.long 0x04 1. " ZQ_SW_RES ,ZQ software calibration result" "VDD/2" textline " " bitfld.long 0x04 0. " ZQ_SW_FOR ,Force ZQ SW calibration" "Not forced,Forced" textline " " group.long (0x808)++0x0B line.long 0x00 "MPWLGCR0,MMDC PHY Write Leveling Error Status Register 0" rbitfld.long 0x00 11. " WL_HW_ERR3 ,Byte3 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x00 10. " WL_HW_ERR2 ,Byte2 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x00 9. " WL_HW_ERR1 ,Byte1 write-leveling HW calibration error" "No error,Error" textline " " rbitfld.long 0x00 8. " WL_HW_ERR0 ,Byte0 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x00 7. " WL_SW_RES3 ,Byte3 write-leveling software result" "Low,High" rbitfld.long 0x00 6. " WL_SW_RES2 ,Byte2 write-leveling software result" "Low,High" textline " " rbitfld.long 0x00 5. " WL_SW_RES1 ,Byte1 write-leveling software result" "Low,High" rbitfld.long 0x00 4. " WL_SW_RES0 ,Byte0 write-leveling software result" "Low,High" bitfld.long 0x00 2. " SW_WL_CNT_EN ,SW WL count down enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SW_WL_EN ,Enable WL SW update" "Disabled,Enabled" bitfld.long 0x00 0. " HW_WL_EN ,Enable WL HW enable" "Disabled,Enabled" line.long 0x04 "MPWLDECTRL0,MMDC PHY Write Leveling Delay Control Register 0" bitfld.long 0x04 25.--26. " WL_CYC_DEL1 ,Write level cycle delay for Byte 1" "No delay,1 cycle,2 cycles," bitfld.long 0x04 24. " WL_HC_DEL1 ,Write level half cycle delay for Byte 1" "No delay,Half cycle" hexmask.long.byte 0x04 16.--22. 1. " WR_DL_ABS_OFFSET1 ,Absolute write-leveling delay offset for Byte 1" textline " " bitfld.long 0x04 9.--10. " WL_CYC_DEL0 ,Write level cycle delay for Byte 0" "No delay,1 cycle,2 cycles," bitfld.long 0x04 8. " WL_HC_DEL0 ,Write level half cycle delay for Byte 0" "No delay,Half cycle" hexmask.long.byte 0x04 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute write-leveling delay offset for Byte 0" line.long 0x08 "MPWLDECTRL1,MMDC PHY Write Leveling Delay Control Register 1" bitfld.long 0x08 25.--26. " WL_CYC_DEL3 ,Write level cycle delay for Byte 3" "No delay,1 cycle,2 cycles," bitfld.long 0x08 24. " WL_HC_DEL3 ,Write level half cycle delay for Byte 3" "No delay,Half cycle" hexmask.long.byte 0x08 16.--22. 1. " WR_DL_ABS_OFFSET3 ,Absolute delay offset for Byte 3" textline " " bitfld.long 0x08 9.--10. " WL_CYC_DEL2 ,Write level cycle delay for Byte 2" "No delay,1 cycle,2 cycles," bitfld.long 0x08 8. " WL_HC_DEL2 ,Write level half cycle delay for Byte 2" "No delay,Half cycle" hexmask.long.byte 0x08 0.--6. 1. " WR_DL_ABS_OFFSET2 ,Absolute delay offset for Byte 2" rgroup.long 0x814++0x03 line.long 0x00 "MPWLDLST,MMDC PHY Write Leveling Delay Line Status Register" hexmask.long.byte 0x00 24.--30. 1. " WL_DL_UNIT_NUM3 ,Number of delay units that is actually used by write leveling delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WL_DL_UNIT_NUM2 ,Number of delay units that is actually used by write leveling delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WL_DL_UNIT_NUM1 ,Number of delay units that is actually used by write leveling delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WL_DL_UNIT_NUM0 ,Number of delay units that is actually used by write leveling delay line 0" hgroup.long 0x818++0x03 hide.long 0x00 "MPODTCTRL,MMDC PHY ODT Control Register" group.long 0x81C++0x1F line.long 0x00 "MPRDDQBY0DL,MMDC PHY Read DQ Byte0 Delay Register" bitfld.long 0x00 28.--30. " RD_DQ7_DEL ,Read dqs0 to dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 24.--26. " RD_DQ6_DEL ,Read dqs0 to dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 20.--22. " RD_DQ5_DEL ,Read dqs0 to dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x00 16.--18. " RD_DQ4_DEL ,Read dqs0 to dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 12.--14. " RD_DQ3_DEL ,Read dqs0 to dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 8.--10. " RD_DQ2_DEL ,Read dqs0 to dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x00 4.--6. " RD_DQ1_DEL ,Read dqs0 to dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 0.--2. " RD_DQ0_DEL ,Read dqs0 to dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x04 "MPRDDQBY1DL,MMDC PHY Read DQ Byte1 Delay Register" bitfld.long 0x04 28.--30. " RD_DQ15_DEL ,Read dqs1 to dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 24.--26. " RD_DQ14_DEL ,Read dqs1 to dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 20.--22. " RD_DQ13_DEL ,Read dqs1 to dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x04 16.--18. " RD_DQ12_DEL ,Read dqs1 to dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 12.--14. " RD_DQ11_DEL ,Read dqs1 to dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 8.--10. " RD_DQ10_DEL ,Read dqs1 to dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x04 4.--6. " RD_DQ9_DEL ,Read dqs1 to dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 0.--2. " RD_DQ8_DEL ,Read dqs1 to dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x08 "MPRDDQBY2DL,MMDC PHY Read DQ Byte2 Delay Register" bitfld.long 0x08 28.--30. " RD_DQ23_DEL ,Read dqs2 to dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 24.--26. " RD_DQ22_DEL ,Read dqs2 to dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 20.--22. " RD_DQ21_DEL ,Read dqs2 to dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x08 16.--18. " RD_DQ20_DEL ,Read dqs2 to dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 12.--14. " RD_DQ19_DEL ,Read dqs2 to dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 8.--10. " RD_DQ18_DEL ,Read dqs2 to dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x08 4.--6. " RD_DQ17_DEL ,Read dqs2 to dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 0.--2. " RD_DQ16_DEL ,Read dqs2 to dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x0C "MPRDDQBY3DL,MMDC PHY Read DQ Byte3 Delay Register" bitfld.long 0x0C 28.--30. " RD_DQ31_DEL ,Read dqs3 to dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 24.--26. " RD_DQ30_DEL ,Read dqs3 to dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 20.--22. " RD_DQ29_DEL ,Read dqs3 to dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x0C 16.--18. " RD_DQ28_DEL ,Read dqs3 to dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 12.--14. " RD_DQ27_DEL ,Read dqs3 to dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 8.--10. " RD_DQ26_DEL ,Read dqs3 to dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x0C 4.--6. " RD_DQ25_DEL ,Read dqs3 to dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 0.--2. " RD_DQ24_DEL ,Read dqs3 to dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x10 "MPWRDQBY0DL,MMDC PHY Write DQ Byte0 Delay Register" bitfld.long 0x10 30.--31. " WR_DM0_DEL ,Write dm0 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 28.--29. " WR_DQ7_DEL ,Write dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 24.--25. " WR_DQ6_DEL ,Write dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x10 20.--21. " WR_DQ5_DEL ,Write dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 16.--17. " WR_DQ4_DEL ,Write dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 12.--13. " WR_DQ3_DEL ,Write dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x10 8.--9. " WR_DQ2_DEL ,Write dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 4.--5. " WR_DQ1_DEL ,Write dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 0.--1. " WR_DQ0_DEL ,Write dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x14 "MPWRDQBY1DL,MMDC PHY Write DQ Byte1 Delay Register" bitfld.long 0x14 30.--31. " WR_DM1_DEL ,Write dm1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 28.--29. " WR_DQ15_DEL ,Write dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 24.--25. " WR_DQ14_DEL ,Write dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x14 20.--21. " WR_DQ13_DEL ,Write dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 16.--17. " WR_DQ12_DEL ,Write dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 12.--13. " WR_D11_DEL ,Write dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x14 8.--9. " WR_DQ10_DEL ,Write dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 4.--5. " WR_DQ9_DEL ,Write dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 0.--1. " WR_DQ8_DEL ,Write dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x18 "MPWRDQBY2DL, MMDC PHY Write DQ Byte2 Delay Register" bitfld.long 0x18 30.--31. " WR_DM2_DEL ,Write dm2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 28.--29. " WR_DQ23_DEL ,Write dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 24.--25. " WR_DQ22_DEL ,Write dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x18 20.--21. " WR_DQ21_DEL ,Write dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 16.--17. " WR_DQ20_DEL ,Write dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 12.--13. " WR_D19_DEL ,Write dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x18 8.--9. " WR_DQ18_DEL ,Write dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 4.--5. " WR_DQ17_DEL ,Write dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 0.--1. " WR_DQ16_DEL ,Write dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x1C "MPWRDQBY3DL, MMDC PHY Write DQ Byte3 Delay Register" bitfld.long 0x1C 30.--31. " WR_DM3_DEL ,Write dm3 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 28.--29. " WR_DQ31_DEL ,Write dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 24.--25. " WR_DQ30_DEL ,Write dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x1C 20.--21. " WR_DQ29_DEL ,Write dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 16.--17. " WR_DQ28_DEL ,Write dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 12.--13. " WR_D27_DEL ,Write dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x1C 8.--9. " WR_DQ26_DEL ,Write dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 4.--5. " WR_DQ25_DEL ,Write dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 0.--1. " WR_DQ24_DEL ,Write dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays" group.long 0x83C++0x07 line.long 0x00 "MPDGCTRL0,MMDC PHY Read DQS gating control register 0" bitfld.long 0x00 31. " RST_RD_FIFO ,Reset Read Data FIFO & pointers" "No reset,Reset" bitfld.long 0x00 30. " DG_CMP_CYC ,Read DQS gating sample cycle" "16 cycles,32 cycles" bitfld.long 0x00 29. " DG_DIS ,Read DQS gating disable" "No,Yes" textline " " bitfld.long 0x00 28. " HW_DG_EN ,Enable automatic read DQS gating calibration" "Disabled,Enabled" bitfld.long 0x00 24.--27. " DG_HC_DEL1 ,Read Dqs1 gating half cycles delay for Byte 1" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," bitfld.long 0x00 23. " DG_EXT_UP ,DG extend upper boundary" "Not extended,Extended" textline " " hexmask.long.byte 0x00 16.--22. 1. " DG_DL_ABS_OFFSET1 ,Absolute delay offset" rbitfld.long 0x00 12. " HW_DG_ERR ,HW DQS gating error" "No error,Error" bitfld.long 0x00 8.--11. " DG_HC_DEL0 ,Read DQS0 gating half cycles delay for Byte 0" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," textline " " hexmask.long.byte 0x00 0.--6. 1. " DG_DL_ABS_OFFSET0 ,Absolute read DQS gating delay offset" line.long 0x04 "MPDGCTRL1,MMDC PHY Read DQS gating control register 1" bitfld.long 0x04 24.--27. " DG_HC_DEL3 ,Read DQS3 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," hexmask.long.byte 0x04 16.--22. 1. " DG_DL_ABS_OFFSET3 ,Absolute read DQS gating delay offset for Byte 3" bitfld.long 0x04 8.--11. " DG_HC_DEL2 ,Read DQS2 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," textline " " hexmask.long.byte 0x04 0.--6. 1. " DG_DL_ABS_OFFSET2 ,Absolute read DQS gating delay offset" rgroup.long 0x844++0x03 line.long 0x00 "MPDGDLST0,MMDC PHY Read DQS gating Delay Line Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " DG_DL_UNIT_NUM3 ,Number of delay units that is actually used by DQS gating delay line 3" hexmask.long.byte 0x00 16.--22. 1. " DG_DL_UNIT_NUM2 ,Number of delay units that is actually used by DQS gating delay line 2" hexmask.long.byte 0x00 8.--14. 1. " DG_DL_UNIT_NUM1 ,Number of delay units that is actually used by DQS gating delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " DG_DL_UNIT_NUM0 ,Number of delay units that is actually used by DQS gating delay line 0" group.long 0x848++0x03 line.long 0x00 "MPRDDLCTL,MMDC PHY Read Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_ABS_OFFSET3 ,Absolute read delay offset byte 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_ABS_OFFSET2 ,Absolute read delay offset byte 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_ABS_OFFSET1 ,Absolute read delay offset byte 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " RD_DL_ABS_OFFSET0 ,Absolute read delay offset byte 0" rgroup.long 0x84C++0x03 line.long 0x00 "MPRDDLST0,MMDC PHY Read Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_UNIT_NUM3 ,Number of delay units that is actually used by read delay line 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_UNIT_NUM2 ,Number of delay units that is actually used by read delay line 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_UNIT_NUM1 ,Number of delay units that is actually used by read delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " RD_DL_UNIT_NUM0 ,Number of delay units that is actually used by read delay line 0" group.long 0x850++0x03 line.long 0x00 "MPWRDLCTL0,MMDC PHY Write Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_ABS_OFFSET3 ,Absolute write delay offset for Byte 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_ABS_OFFSET2 ,Absolute write delay offset for Byte 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_ABS_OFFSET1 ,Absolute write delay offset for Byte 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute write delay offset for Byte 30" rgroup.long 0x854++0x03 line.long 0x00 "MPWRDLST0,MMDC PHY Write Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_UNIT_NUM3 ,Number of delay units that is actually used by write delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_UNIT_NUM2 ,Number of delay units that is actually used by write delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_UNIT_NUM1 ,Number of delay units that is actually used by write delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WR_DL_UNIT_NUM0 ,Number of delay units that is actually used by write delay line 0" group.long 0x858++0x0F line.long 0x00 "MPSDCTRL,MMDC PHY CK control Register" bitfld.long 0x00 8.--9. " SDCLK1_DEL ,SDCLK0 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x00 10.--11. " SDCLK0_DEL ,SDCLK0 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x04 "MPZQLP2CTL,MMDC PHY ZQ LPDDR2 HW Control Register" hexmask.long.byte 0x04 24.--30. 1. " ZQ_LP2_HW_ZQCS ,Period in cycles that it takes the memory device to perform a Short ZQ calibration" hexmask.long.byte 0x04 16.--23. 1. " ZQ_LP2_HW_ZQCL ,Period in cycles that it takes the memory device to perform a Long ZQ calibration" hexmask.long.word 0x04 0.--8. 1. " ZQ_LP2_HW_ZQINIT ,Period in cycles that it takes the memory device to perform a Init ZQ calibration" line.long 0x08 "MPRDDLHWCTL,MMDC PHY Read Delay HW Calibration Control Register" bitfld.long 0x08 5. " HW_RD_DL_CMP_CYC ,HW RD DL sample cycle" "Not compared,Compared" bitfld.long 0x08 4. " HW_RD_DL_EN ,Enable HW RD DL calibration" "Disabled,Enabled" rbitfld.long 0x08 3. " HW_RD_DL_ERR3 ,HW RD DL3 error" "No error,Error" textline " " rbitfld.long 0x08 2. " HW_RD_DL_ERR2 ,HW RD DL2 error" "No error,Error" rbitfld.long 0x08 1. " HW_RD_DL_ERR1 ,HW RD DL1 error" "No error,Error" rbitfld.long 0x08 0. " HW_RD_DL_ERR0 ,HW RD DL0 error" "No error,Error" line.long 0x0C "MPWRDLHWCTL,MMDC PHY Write Delay HW Calibration Control Register" bitfld.long 0x0C 5. " HW_WR_DL_CMP_CYC ,HW WR DL sample cycle" "Not compared,Compared" bitfld.long 0x0C 4. " HW_WR_DL_EN ,Enable HW WR DL calibration" "Disabled,Enabled" rbitfld.long 0x0C 3. " HW_WR_DL_ERR3 ,HW WR DL3 error" "No error,Error" textline " " rbitfld.long 0x0C 2. " HW_WR_DL_ERR2 ,HW WR DL2 error" "No error,Error" rbitfld.long 0x0C 1. " HW_WR_DL_ERR1 ,HW WR DL1 error" "No error,Error" rbitfld.long 0x0C 0. " HW_WR_DL_ERR0 ,HW WR DL0 error" "No error,Error" rgroup.long 0x868++0x13 line.long 0x00 "MPRDDLHWST0,MMDC PHY Read Delay HW Calibration Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " HW_RD_DL_UP1 ,HW RD DL1 upper boundary" hexmask.long.byte 0x00 16.--22. 1. " HW_RD_DL_LOW1 ,HW RD DL1 lower boundary" hexmask.long.byte 0x00 8.--14. 1. " HW_RD_DL_UP0 ,HW RD DL0 upper boundary" textline " " hexmask.long.byte 0x00 0.--6. 1. " HW_RD_DL_LOW0 ,HW RD DL0 lower boundary" line.long 0x04 "MPRDDLHWST1,MMDC PHY Read Delay HW Calibration Status Register 1" hexmask.long.byte 0x04 24.--30. 1. " HW_RD_DL_UP3 ,HW RD DL3 upper boundary" hexmask.long.byte 0x04 16.--22. 1. " HW_RD_DL_LOW3 ,HW RD DL3 lower boundary" hexmask.long.byte 0x04 8.--14. 1. " HW_RD_DL_UP2 ,HW RD DL2 upper boundary" textline " " hexmask.long.byte 0x04 0.--6. 1. " HW_RD_DL_LOW2 ,HW RD DL2 lower boundary" line.long 0x08 "MPWRDLHWST0,MMDC PHY Write Delay HW Calibration Status Register 0" hexmask.long.byte 0x08 24.--30. 1. " HW_WR_DL_UP1 ,HW WR DL1 upper boundary" hexmask.long.byte 0x08 16.--22. 1. " HW_WR_DL_LOW1 ,HW WR DL1 lower boundary" hexmask.long.byte 0x08 8.--14. 1. " HW_WR_DL_UP0 ,HW WR DL0 upper boundary" textline " " hexmask.long.byte 0x08 0.--6. 1. " HW_WR_DL_LOW0 ,HW WR DL0 lower boundary" line.long 0x0C "MPWRDLHWST1,MMDC PHY Write Delay HW Calibration Status Register 1" hexmask.long.byte 0x0C 24.--30. 1. " HW_WR_DL_UP3 ,HW WR DL3 upper boundary" hexmask.long.byte 0x0C 16.--22. 1. " HW_WR_DL_LOW3 ,HW WR DL3 lower boundary" hexmask.long.byte 0x0C 8.--14. 1. " HW_WR_DL_UP2 ,HW WR DL2 upper boundary" textline " " hexmask.long.byte 0x0C 0.--6. 1. " HW_WR_DL_LOW2 ,HW WR DL2 lower boundary" line.long 0x10 "MPWLHWERR0,MMDC PHY Write Leveling HW Error Register 0 " hexmask.long.byte 0x10 24.--31. 1. " HW_WL3_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 16.--23. 1. " HW_WL2_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 8.--15. 1. " HW_WL1_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" textline " " hexmask.long.byte 0x10 0.--7. 1. " HW_WL0_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" textline " " rgroup.long 0x87C++0x0F line.long 0x00 "MPDGHWST0,MMDC PHY Read DQS Gating HW Status Register 0" hexmask.long.word 0x00 16.--26. 1. " HW_DG_UP0 ,HW DG0 upper boundary" hexmask.long.word 0x00 0.--10. 1. " HW_DG_LOW0 ,HW DG0 lower boundary" line.long 0x04 "MPDGHWST1,MMDC PHY Read DQS Gating HW Status Register 1" hexmask.long.word 0x04 16.--26. 1. " HW_DG_UP1 ,HW DG1 upper boundary" hexmask.long.word 0x04 0.--10. 1. " HW_DG_LOW1 ,HW DG1 lower boundary" line.long 0x08 "MPDGHWST2,MMDC PHY Read DQS Gating HW Status Register 2" hexmask.long.word 0x08 16.--26. 1. " HW_DG_UP2 ,HW DG2 upper boundary" hexmask.long.word 0x08 0.--10. 1. " HW_DG_LOW2 ,HW DG2 lower boundary" line.long 0x0C "MPDGHWST3,MMDC PHY Read DQS Gating HW Status Register 3" hexmask.long.word 0x0C 16.--26. 1. " HW_DG_UP3 ,HW DG3 upper boundary" hexmask.long.word 0x0C 0.--10. 1. " HW_DG_LOW3 ,HW DG3 lower boundary" group.long 0x88C++0x0B line.long 0x00 "MPPDCMPR1,MMDC PHY Pre-defined Compare Register 1" hexmask.long.word 0x00 16.--31. 1. " PDV2 ,Pre defined compare value2" hexmask.long.word 0x00 0.--15. 1. " PDV1 ,Pre defined compare value2" line.long 0x04 "MPPDCMPR2,MMDC PHY Pre-defined Compare and CA Delay Line Configuration Register" hexmask.long.byte 0x04 24.--30. 1. " PHY_CA_DL_UNIT ,Number of delay units that is actually used by phy CA delay unit" hexmask.long.byte 0x04 16.--22. 1. " CA_DL_ABS_OFFSET ,Absolute delay offset" bitfld.long 0x04 2. " READ_LEVEL_PATTERN ,DQ calibration Read level pattern" "1010,0011" textline " " bitfld.long 0x04 1. " MPR_FULL_CMP ,DQ calibration full compare enable" "Disabled,Enabled" bitfld.long 0x04 0. " MPR_CMP ,DQ calibration compare enable" "Disabled,Enabled" line.long 0x08 "MPSWDAR0,MMDC PHY SW Dummy Access Register 0" rbitfld.long 0x08 5. " SW_DUM_CMP3 ,SW dummy read byte3 compare results" "Failed,Passed" rbitfld.long 0x08 4. " SW_DUM_CMP2 ,SW dummy read byte2 compare results" "Failed,Passed" rbitfld.long 0x08 3. " SW_DUM_CMP1 ,SW dummy read byte1 compare results" "Failed,Passed" textline " " rbitfld.long 0x08 2. " SW_DUM_CMP0 ,SW dummy read byte0 compare results" "Failed,Passed" bitfld.long 0x08 1. " SW_DUMMY_RD ,SW dummy read" "Not generated,Generated" bitfld.long 0x08 0. " SW_DUMMY_WR ,SW dummy write" "Not generated,Generated" textline " " rgroup.long 0x898++0x1F line.long 0x00 "MPSWDRDR0,MMDC PHY SW Dummy Read Data Register 0" line.long 0x04 "MPSWDRDR1,MMDC PHY SW Dummy Read Data Register 1" line.long 0x08 "MPSWDRDR2,MMDC PHY SW Dummy Read Data Register 2" line.long 0x0C "MPSWDRDR3,MMDC PHY SW Dummy Read Data Register 3" line.long 0x10 "MPSWDRDR4,MMDC PHY SW Dummy Read Data Register 4" line.long 0x14 "MPSWDRDR5,MMDC PHY SW Dummy Read Data Register 5" line.long 0x18 "MPSWDRDR6,MMDC PHY SW Dummy Read Data Register 6" line.long 0x1C "MPSWDRDR7,MMDC PHY SW Dummy Read Data Register 7" textline " " group.long 0x8B8++0x07 line.long 0x00 "MPMUR0,MMDC PHY Measure Unit Register for DQ0-3" hexmask.long.word 0x00 16.--25. 1. " MU_UNIT_DEL_NUM ,Measure unit measured number of unit delay per cycle" bitfld.long 0x00 11. " FRC_MSR ,Force measuement on delay-lines" "Not forced,Forced" bitfld.long 0x00 10. " MU_BYP_EN ,Measure unit bypass enable" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--9. 1. " MU_BYP_VAL ,Measure unit bypass value" line.long 0x04 "MPWRCADL,MMDC PHY Write CA Delay Control Register" bitfld.long 0x04 18.--19. " WR_CA9_DEL ,CA9 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 16.--17. " WR_CA8_DEL ,CA8 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 14.--15. " WR_CA7_DEL ,CA7 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x04 12.--13. " WR_CA6_DEL ,CA6 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 10.--11. " WR_CA5_DEL ,CA5 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 8.--9. " WR_CA4_DEL ,CA4 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x04 6.--7. " WR_CA3_DEL ,CA3 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 4.--5. " WR_CA2_DEL ,CA2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 2.--3. " WR_CA1_DEL ,CA1 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x04 0.--1. " WR_CA0_DEL ,CA0 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline "" rgroup.long 0x8C0++0x03 line.long 0x00 "MPDCCR,MMDC PHY Duty Cycle Control Register" bitfld.long 0x00 28.--30. " RD_DQS3_FT_DCC ,Read dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 25.--27. " RD_DQS2_FT_DCC ,Read dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 22.--24. " RD_DQS1_FT_DCC ,Read dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 19.--21. " RD_DQS0_FT_DCC ,Read dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 16.--18. " CK_FT1_DCC ,Secondary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 12.--14. " CK_FT0_DCC ,Primary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 9.--11. " WR_DQS3_FT_DCC ,Write dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 6.--8. " WR_DQS2_FT_DCC ,Write dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 3.--5. " WR_DQS1_FT_DCC ,Write dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 0.--2. " WR_DQS0_FT_DCC ,Write dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," elif (((per.l(ad:0x421B0000+0x18))&0x18)==0x00) width 10. group.long (0x00)++0x07 line.long 0x00 "MDCTL,MMDC Core Control Register" bitfld.long 0x00 31. " SDE_0 ,MMDC Enable CS0" "Disabled,Enabled" bitfld.long 0x00 30. " SDE_1 ,MMDC Enable CS1" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--26. " ROW ,Row Address Width" "11-bits,12-bits,13-bits,14-bits,15-bits,16-bits,," bitfld.long 0x00 20.--22. " COL ,Column Address Width" "9-bits,10-bits,11-bits,8-bits,12-bits,,," textline " " bitfld.long 0x00 19. " BL ,Burst Length" ",8" bitfld.long 0x00 16.--17. " DSIZ ,SDRAM Memory Data Width" "16-bit,32-bit,64-bit," line.long 0x04 "MDPDC,MMDC Core Power Down Control Register" bitfld.long 0x04 28.--30. " PRCT_1 ,Precharge Timer - Chip Select 1" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x04 24.--26. " PRCT_0 ,Precharge Timer - Chip Select 0" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" textline " " bitfld.long 0x04 16.--18. " TCKE ,CKE minimum pulse width" "1 cycle,2 cycles,,,,,7 cycles,8 cycles" bitfld.long 0x04 12.--15. " PWDT_1 ,Power Down Timer - Chip Select 1" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,,," textline " " bitfld.long 0x04 8.--11. " PWDT_0 ,Power Down Timer - Chip Select 0" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,,," bitfld.long 0x04 7. " SLOW_PD ,Slow precharge power-down" "Fast,Slow" textline " " bitfld.long 0x04 6. " BOTH_CS_PD ,Both chip selects power-down" "Independently,Both" bitfld.long 0x04 3.--5. " TCKSRX ,Valid clock requirement before self-refresh exit" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x04 0.--2. " TCKSRE ,Valid clock requirement after self-refresh entry" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" group.long (0x08)++0x03 line.long 0x00 "MDOTC,MMDC Core ODT Timing Control Register" bitfld.long 0x00 27.--29. " TAOFPD ,Asynchronous RTT turn-off delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 24.--26. " TAONPD ,Asynchronous RTT turn-on delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x00 20.--23. " TANPD ,ODT to power down entry latency" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x00 16.--19. " TAXPD ,ODT power down exit latency" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" textline " " bitfld.long 0x00 12.--14. " TODTLON ,ODT turn on latency" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles," bitfld.long 0x00 4.--8. " TODT_IDLE_OFF ,Idle period before turning memory ODT off" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles" group.long (0x0C)++0x17 line.long 0x00 "MDCFG0,MMDC Core Timing Configuration Register 0" hexmask.long.byte 0x00 24.--31. 1. " TRFC ,Refresh command to Active or Refresh command time" hexmask.long.byte 0x00 16.--23. 1. " TXS ,Self-refresh exit to next valid command delay" textline " " bitfld.long 0x00 13.--15. " TXP ,Exit power down with DLL-on to any valid command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 9.--12. " TXPDLL ,Exit precharge power down with DLL frozen to commands requiring DLL" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" textline " " bitfld.long 0x00 4.--8. " TFAW ,Four Active Window" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x00 0.--3. " TCL ,CAS Read Latency" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,,,,,,," line.long 0x04 "MDCFG1,MMDC Core Timing Configuration Register 1" bitfld.long 0x04 29.--31. " TRCD ,Active command to internal read or write delay time" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x04 26.--28. " TRP ,Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" textline " " bitfld.long 0x04 21.--25. " TRC ,Active to Active or Refresh command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 cloks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x04 16.--20. " TRAS ,Active to Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks," textline " " bitfld.long 0x04 15. " TRPA ,Precharge-all command period" "tRP,tRP+1" bitfld.long 0x04 9.--11. " TWR ,WRITE recovery time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x04 5.--8. " TMRD ,Mode Register Set command cycle" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x04 0.--2. " TCWL ,CAS Write Latency" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles," line.long 0x08 "MDCFG2,MMDC Core Timing Configuration Register 2" hexmask.long.word 0x08 16.--24. 1. " TDLLK ,DLL locking time" bitfld.long 0x08 6.--8. " TRTP ,Internal READ command to PRECHARGE command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x08 3.--5. " TWTR ,Internal WRITE to READ command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x08 0.--2. " TRRD ,ACTIVE to ACTIVE command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles," line.long 0x0C "MDMISC,MMDC Core Miscellaneous Register" rbitfld.long 0x0C 31. " CS0_RDY ,External status device on CS0" "Wake-up,Ready" rbitfld.long 0x0C 30. " CS1_RDY ,External status device on CS1" "Wake-up,Ready" textline " " bitfld.long 0x0C 20. " CALIB_PER_CS ,Defines the CS number that the associated calibration is targetted at" "CS0,CS1" bitfld.long 0x0C 19. " ADDR_MIRROR ,Address mirroring" "Disabled,Enabled" textline " " bitfld.long 0x0C 18. " LHD ,Latency hiding disable" "No,Yes" bitfld.long 0x0C 16.--17. " WALAT ,Write Additional latency" "Not required,1 cycle,2 cycles,3 cycles" textline " " bitfld.long 0x0C 12. " BI_ON ,Bank Interleaving On" "Not interleaved,Interleaved" bitfld.long 0x0C 9.--10. " MIF3_MODE ,Command prediction working mode" "Disabled,First pipe line stage,First pipe line stage/axi bus,First pipe line stage/axi bus/access queue" textline " " bitfld.long 0x0C 6.--8. " RALAT ,Read Additional Latency" "ASAP,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x0C 5. " DDR_4_BANK ,DDR device with 4 Banks" "8 banks,4 banks" textline " " bitfld.long 0x0C 3.--4. " DDR_TYPE ,DDR TYPE" "DDR3,LPDDR2,," bitfld.long 0x0C 1. " RST ,Software Reset" "No operation,Asserted" line.long 0x10 "MDSCR,MMDC Core Special Command Register" hexmask.long.byte 0x10 24.--31. 1. " CMD_ADDR_MSB ,Command/Address MSB" hexmask.long.byte 0x10 16.--23. 1. " CMD_ADDR_LSB , Command/Address LSB" textline " " bitfld.long 0x10 15. " CON_REQ ,Configuration request" "Not requested,Requested" rbitfld.long 0x10 14. " CON_ACK ,Configuration acknowledge" "Forbidden,Permitted" textline " " bitfld.long 0x10 9. " WL_EN ,Write Level Enable" "Disabled,Enabled" bitfld.long 0x10 4.--6. " CMD ,Command" "Normal operation,Precharge all,Auto-Refresh,Load Mode Register,ZQ calibration,Precharge all,," textline " " bitfld.long 0x10 3. " CMD_CS ,Chip Select" "0,1" bitfld.long 0x10 0.--2. " CMD_BA ,Bank Address" "0,1,2,3,4,5,6,7" line.long 0x14 "MDREF,MMDC Core Refresh Control Register" hexmask.long.word 0x14 16.--31. 1. " REF_CNT ,Refresh Counter" bitfld.long 0x14 14.--15. " REF_SEL ,Refresh Selector" "64KHz,32KHz,REF_CNT,Disabled" textline " " bitfld.long 0x14 11.--13. " REFR ,Refresh Rate" "1 refresh,2 refreshes,3 refreshes,4 refreshes,5 refreshes,6 refreshes,7 refreshes,8 refreshes" bitfld.long 0x14 0. " START_REF ,Start Refresh cycle" "No operation,Started" group.long (0x2C)++0x07 line.long 0x00 "MDRWD,MMDC Core Read/Write Command Delay Register" bitfld.long 0x00 12.--14. " RTW_SAME ,Controls the cycles delay between Read to Write commands in same chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WTR_DIFF ,Controls the cycles delay between Write to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 6.--8. " WTW_DIFF ,Controls the cycles delay between Write to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " RTW_DIFF ,Controls the cycles delay between Read to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" textline " " bitfld.long 0x00 0.--2. " RTR_DIFF ,Controls the cycles delay between Read to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" line.long 0x04 "MDOR,MMDC Core Out of Reset Delays Register" hexmask.long.byte 0x04 16.--23. 1. " TXPR ,CKE HIGH to a valid command" bitfld.long 0x04 8.--13. " SDE_TO_RST , Time from SDE enable until DDR reset is high" ",,1 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles" textline " " bitfld.long 0x04 0.--5. " RST_TO_CKE ,Time from SDE enable to CKE rise" ",,,1 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles" textline " " ;ssection width 13. hgroup.long (0x34)++0x0B hide.long 0x00 "MDMRR,MMDC Core MRR Data Register" hide.long 0x04 "MDCFG3LP,MMDC Core Timing Configuration Register 3" hide.long 0x08 "MDMR4,MMDC Core MR4 Derating Register" group.long (0x40)++0x03 line.long 0x00 "MDASP,MMDC Core Address Space Partition Register" hexmask.long.byte 0x00 0.--6. 1. " CS0_END ,Define the absolute last address associated with CS0" group.long (0x400)++0x0F line.long 0x00 "MAARCR,MMDC Core AXI Re-ordering Control Register" bitfld.long 0x00 31. " ARCR_SEC_ERR_LOCK ,ARCR_SEC_ERR_EN lock" "Not locked,Locked" bitfld.long 0x00 30. " ARCR_SEC_ERR_EN ,Security read/write access violation in OKAY/SLV Error response " "OKAY,SLAVE error" bitfld.long 0x00 28. " ARCR_EXC_ERR_EN ,Exclusive read/write access violation of AXI 6.2.4 rule in OKAY/SLV Error response " "OKAY,SLAVE error" textline " " bitfld.long 0x00 24. " ARCR_RCH_EN ,Real time channel enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ARCR_PAG_HIT ,ARCR Page Hit Rate" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " ARCR_ACC_HIT ,ARCR Access Hit Rate" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--11. " ARCR_DYN_JMP ,ARCR Dynamic Jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ARCR_DYN_MAX ,ARCR Dynamic Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARCR_GUARD ,ARCR Guard" "15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30" line.long 0x04 "MAPSR,MMDC Core Power Saving Control and Status Register" rbitfld.long 0x04 25. " DVACK ,General DVFS acknowledge" "Not asserted,Asserted" rbitfld.long 0x04 24. " LPACK ,General low-power acknowledge" "Not asserted,Asserted" bitfld.long 0x04 21. " DVFS ,General DVFS request" "Not requested,Requested" textline " " bitfld.long 0x04 20. " LPMD ,General LPMD request" "Not requested,Requested" hexmask.long.byte 0x04 8.--15. 1. " PST ,Automatic Power saving timer" rbitfld.long 0x04 6. " WIS ,Write Idle Status" "Idle,Busy" textline " " rbitfld.long 0x04 5. " RIS ,Read Idle Status" "Idle,Busy" rbitfld.long 0x04 4. " PSS ,Power Saving Status" "Disabled,Enabled" bitfld.long 0x04 0. " PSD ,Automatic Power Saving Disable" "No,Yes" line.long 0x08 "MAEXIDR0,MMDC Core Exclusive ID Monitor Register 0" hexmask.long.word 0x08 16.--31. 1. " EXC_ID_MONITOR1 ,Defines ID for Exclusive monitor#1" hexmask.long.word 0x08 0.--15. 1. " EXC_ID_MONITOR0 ,Defines ID for Exclusive monitor#0" line.long 0x0C "MAEXIDR1,MMDC Core Exclusive ID Monitor Register 1" hexmask.long.word 0x0C 16.--31. 1. " EXC_ID_MONITOR3 ,Defines ID for Exclusive monitor#3" hexmask.long.word 0x0C 0.--15. 1. " EXC_ID_MONITOR2 ,Defines ID for Exclusive monitor#2" group.long (0x410)++0x07 line.long 0x00 "MADPCR0,MMDC Core Debug and Profiling Control Register 0" bitfld.long 0x00 9. " SBS ,Step By Step trigger" "Not launched,Launched" bitfld.long 0x00 8. " SBS_EN ,Step By Step debug Enable" "Disabled,Enabled" eventfld.long 0x00 3. " CYC_OVF ,Total Cycles count Overflow" "No overflow,Overflow" textline " " bitfld.long 0x00 2. " PRF_FRZ ,Profiling freeze" "Not frozen,Frozen" bitfld.long 0x00 1. " DBG_RST ,Debug and Profiling Reset" "No reset,Reset" bitfld.long 0x00 0. " DBG_EN ,Debug and Profiling Enable" "Disabled,Enabled" Textline "" line.long 0x04 "MADPCR1,MMDC Core Debug and Profiling Control Register 1" bitfld.long 0x04 31. " PRF_AXI_ID_MASK_31 ,Profiling AXI ID Mask 31" "Masked,Not masked" bitfld.long 0x04 30. " PRF_AXI_ID_MASK_30 ,Profiling AXI ID Mask 30" "Masked,Not masked" bitfld.long 0x04 29. " PRF_AXI_ID_MASK_29 ,Profiling AXI ID Mask 29" "Masked,Not masked" textline " " bitfld.long 0x04 28. " PRF_AXI_ID_MASK_28 ,Profiling AXI ID Mask 28" "Masked,Not masked" bitfld.long 0x04 27. " PRF_AXI_ID_MASK_27 ,Profiling AXI ID Mask 27" "Masked,Not masked" bitfld.long 0x04 26. " PRF_AXI_ID_MASK_26 ,Profiling AXI ID Mask 26" "Masked,Not masked" textline " " bitfld.long 0x04 25. " PRF_AXI_ID_MASK_25 ,Profiling AXI ID Mask 25" "Masked,Not masked" bitfld.long 0x04 24. " PRF_AXI_ID_MASK_24 ,Profiling AXI ID Mask 24" "Masked,Not masked" bitfld.long 0x04 23. " PRF_AXI_ID_MASK_23 ,Profiling AXI ID Mask 23" "Masked,Not masked" textline " " bitfld.long 0x04 22. " PRF_AXI_ID_MASK_22 ,Profiling AXI ID Mask 22" "Masked,Not masked" bitfld.long 0x04 21. " PRF_AXI_ID_MASK_21 ,Profiling AXI ID Mask 21" "Masked,Not masked" bitfld.long 0x04 20. " PRF_AXI_ID_MASK_20 ,Profiling AXI ID Mask 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " PRF_AXI_ID_MASK_19 ,Profiling AXI ID Mask 19" "Masked,Not masked" bitfld.long 0x04 18. " PRF_AXI_ID_MASK_18 ,Profiling AXI ID Mask 18" "Masked,Not masked" bitfld.long 0x04 17. " PRF_AXI_ID_MASK_17 ,Profiling AXI ID Mask 17" "Masked,Not masked" textline " " bitfld.long 0x04 16. " PRF_AXI_ID_MASK_16 ,Profiling AXI ID Mask 16" "Masked,Not masked" bitfld.long 0x04 15. " PRF_AXI_ID[15] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 14. " PRF_AXI_ID[14] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 13. " PRF_AXI_ID[13] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 12. " PRF_AXI_ID[12] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 11. " PRF_AXI_ID[11] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 10. " PRF_AXI_ID[10] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 9. " PRF_AXI_ID[9] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 8. " PRF_AXI_ID[8] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 7. " PRF_AXI_ID[7] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 6. " PRF_AXI_ID[6] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 5. " PRF_AXI_ID[5] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 4. " PRF_AXI_ID[4] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 3. " PRF_AXI_ID[3] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 2. " PRF_AXI_ID[2] ,Profiling AXI ID" "Low,High" textline " " bitfld.long 0x04 1. " PRF_AXI_ID[1] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 0. " PRF_AXI_ID[0] ,Profiling AXI ID" "Low,High" textline " " rgroup.long (0x418)++0x1F line.long 0x00 "MADPSR0,MMDC Core Debug and Profiling Status Register 0" line.long 0x04 "MADPSR1,MMDC Core Debug and Profiling Status Register 1" line.long 0x08 "MADPSR2,MMDC Core Debug and Profiling Status Register 2" line.long 0x0C "MADPSR3,MMDC Core Debug and Profiling Status Register 3" line.long 0x10 "MADPSR4,MMDC Core Debug and Profiling Status Register 4" line.long 0x14 "MADPSR5,MMDC Core Debug and Profiling Status Register 5" line.long 0x18 "MASBS0,MMDC Core Step By Step Address" line.long 0x1C "MASBS1,MMDC Core Step By Step Address Attributes" hexmask.long.word 0x1C 16.--31. 1. " SBS_AXI_ID ,Step By Step AXI ID" bitfld.long 0x1C 13.--15. " SBS_LEN ,Step By Step Length" "1,2,3,4,5,6,7,8" bitfld.long 0x1C 12. " SBS_BUFF ,Step By Step Buffered" "0,1" textline " " bitfld.long 0x1C 10.--11. " SBS_BURST ,Step By Step Burst" "Fixed,INCR,WRAP," bitfld.long 0x1C 7.--9. " SBS_SIZE ,Step By Step Size" "8 bits,16 bits,32 bits,64 bits,128 bits,,," bitfld.long 0x1C 4.--6. " SBS_PROT ,Step By Step Protection" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1C 2.--3. " SBS_LOCK ,Step By Step Lock" "0,1,2,3" bitfld.long 0x1C 1. " SBS_TYPE ,Step By Step Request Type" "Write,Read" bitfld.long 0x1C 0. " SBS_VLD ,Step By Step Valid" "Not valid,Valid" textline " " group.long (0x440)++0x03 line.long 0x00 "MAGENP,MMDC Core General Purpose Register" bitfld.long 0x00 31. " GP31 ,General purpose read/write bit 31" "0,1" bitfld.long 0x00 30. " GP30 ,General purpose read/write bit 30" "0,1" bitfld.long 0x00 29. " GP29 ,General purpose read/write bit 29" "0,1" textline " " bitfld.long 0x00 28. " GP28 ,General purpose read/write bit 28" "0,1" bitfld.long 0x00 27. " GP27 ,General purpose read/write bit 27" "0,1" bitfld.long 0x00 26. " GP26 ,General purpose read/write bit 26" "0,1" textline " " bitfld.long 0x00 25. " GP25 ,General purpose read/write bit 25" "0,1" bitfld.long 0x00 24. " GP24 ,General purpose read/write bit 24" "0,1" bitfld.long 0x00 23. " GP23 ,General purpose read/write bit 23" "0,1" textline " " bitfld.long 0x00 22. " GP22 ,General purpose read/write bit 22" "0,1" bitfld.long 0x00 21. " GP21 ,General purpose read/write bit 21" "0,1" bitfld.long 0x00 20. " GP20 ,General purpose read/write bit 20" "0,1" textline " " bitfld.long 0x00 19. " GP19 ,General purpose read/write bit 19" "0,1" bitfld.long 0x00 18. " GP18 ,General purpose read/write bit 18" "0,1" bitfld.long 0x00 17. " GP17 ,General purpose read/write bit 17" "0,1" textline " " bitfld.long 0x00 16. " GP16 ,General purpose read/write bit 16" "0,1" bitfld.long 0x00 15. " GP15 ,General purpose read/write bit 15" "0,1" bitfld.long 0x00 14. " GP14 ,General purpose read/write bit 14" "0,1" textline " " bitfld.long 0x00 13. " GP13 ,General purpose read/write bit 13" "0,1" bitfld.long 0x00 12. " GP12 ,General purpose read/write bit 12" "0,1" bitfld.long 0x00 11. " GP11 ,General purpose read/write bit 11" "0,1" textline " " bitfld.long 0x00 10. " GP10 ,General purpose read/write bit 10" "0,1" bitfld.long 0x00 9. " GP9 ,General purpose read/write bit 9" "0,1" bitfld.long 0x00 8. " GP8 ,General purpose read/write bit 8" "0,1" textline " " bitfld.long 0x00 7. " GP7 ,General purpose read/write bit 7" "0,1" bitfld.long 0x00 6. " GP6 ,General purpose read/write bit 6" "0,1" bitfld.long 0x00 5. " GP5 ,General purpose read/write bit 5" "0,1" textline " " bitfld.long 0x00 4. " GP4 ,General purpose read/write bit 4" "0,1" bitfld.long 0x00 3. " GP3 ,General purpose read/write bit 3" "0,1" bitfld.long 0x00 2. " GP2 ,General purpose read/write bit 2" "0,1" textline " " bitfld.long 0x00 1. " GP1 ,General purpose read/write bit 1" "0,1" bitfld.long 0x00 0. " GP0 ,General purpose read/write bit 0" "0,1" textline " " width 13. group.long 0x800++0x07 line.long 0x00 "MPZQHWCTRL,MMDC PHY ZQ HW Control Register" bitfld.long 0x00 27.--31. " ZQ_EARLY_COMPARATOR_EN_TIMER ,ZQ early comparator enable timer" ",,,,,,,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" bitfld.long 0x00 23.--25. " TZQ_CS ,Device ZQ short time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," bitfld.long 0x00 20.--22. " TZQ_OPER ,Device ZQ long/oper time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," textline " " bitfld.long 0x00 17.--19. " TZQ_INIT ,Device ZQ long/init time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,," bitfld.long 0x00 16. " ZQ_HW_FOR ,Force ZQ automatic calibration process with the i.MX ZQ calibration pad" "Not forced,Forced" rbitfld.long 0x00 11.--15. " ZQ_HW_PD_RES ,ZQ HW calibration pull-down result" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" textline " " rbitfld.long 0x00 6.--10. " ZQ_HW_PU_RES ,ZQ automatic calibration pull-up result" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" bitfld.long 0x00 2.--5. " ZQ_HW_PER ,ZQ periodic calibration time" "1 ms,2 ms,4 ms,8 ms,16 ms,32 ms,64 ms,128 ms,256 ms,512 ms,1 sec,2 sec,4 sec,8 sec,16 sec,32 sec" bitfld.long 0x00 0.--1. " ZQ_MODE ,ZQ calibration mode" "Not issued,i.MX ZQ calibration pad/External DDR(when exiting),External DDR,i.MX ZQ calibration pad/External DDR(periodic/when exiting)" line.long 0x04 "MPZQSWCTRL,MMDC PHY ZQ SW control register" bitfld.long 0x04 16.--17. " ZQ_CMP_OUT_SMP ,Amount of cycles between driving the ZQ signals to the ZQ pad" "7 cycles,15 cycles,23 cycles,31 cycles" bitfld.long 0x04 13. " USE_ZQ_SW_VAL ,Use SW ZQ configured value for I/O pads resistor controls" "ZQ_HW_PD_VAL & ZQ_HW_PU_VAL,ZQ_SW_PD_VAL & ZQ_SW_PU_VAL" bitfld.long 0x04 12. " ZQ_SW_PD ,ZQ software PU/PD calibration" "PU,PD" textline " " bitfld.long 0x04 7.--11. " ZQ_SW_PD_VAL ,ZQ software pull-down resistence" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" bitfld.long 0x04 2.--6. " ZQ_SW_PU_VAL ,ZQ software pull-up resistence" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 (minimum)" rbitfld.long 0x04 1. " ZQ_SW_RES ,ZQ software calibration result" "VDD/2" textline " " bitfld.long 0x04 0. " ZQ_SW_FOR ,Force ZQ SW calibration" "Not forced,Forced" group.long (0x808)++0x0B line.long 0x00 "MPWLGCR0,MMDC PHY Write Leveling Error Status Register 0" rbitfld.long 0x00 11. " WL_HW_ERR3 ,Byte3 WL HW calibration error" "No error,Error" rbitfld.long 0x00 10. " WL_HW_ERR2 ,Byte2 WL HW calibration error" "No error,Error" rbitfld.long 0x00 9. " WL_HW_ERR1 ,Byte1 WL HW calibration error" "No error,Error" textline " " rbitfld.long 0x00 8. " WL_HW_ERR0 ,Byte0 WL HW calibration error" "No error,Error" rbitfld.long 0x00 7. " WL_SW_RES3 ,Byte3 WL software result" "Low,High" rbitfld.long 0x00 6. " WL_SW_RES2 ,Byte2 WL software result" "Low,High" textline " " rbitfld.long 0x00 5. " WL_SW_RES1 ,Byte1 WL software result" "Low,High" rbitfld.long 0x00 4. " WL_SW_RES0 ,Byte0 WL software result" "Low,High" bitfld.long 0x00 2. " SW_WL_CNT_EN ,SW WL count down enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SW_WL_EN ,Enable WL SW update" "Disabled,Enabled" bitfld.long 0x00 0. " HW_WL_EN ,Enable WL HW enable" "Disabled,Enabled" line.long 0x04 "MPWLDECTRL0,MMDC PHY Write Leveling Delay Control Register 0" bitfld.long 0x04 25.--26. " WL_CYC_DEL1 ,Write level cycle delay for Byte 1" "No delay,1 cycle,2 cycles," bitfld.long 0x04 24. " WL_HC_DEL1 ,Write level half cycle delay for Byte 1" "No delay,Half cycle" hexmask.long.byte 0x04 16.--22. 1. " WR_DL_ABS_OFFSET1 ,Absolute delay offset for Byte 1" textline " " bitfld.long 0x04 9.--10. " WL_CYC_DEL0 ,Write level cycle delay for Byte 0" "No delay,1 cycle,2 cycles," bitfld.long 0x04 8. " WL_HC_DEL0 ,Write level half cycle delay for Byte 0" "No delay,Half cycle" hexmask.long.byte 0x04 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute delay offset for Byte 0" line.long 0x08 "MPWLDECTRL1,MMDC PHY Write Leveling Delay Control Register 1" bitfld.long 0x08 25.--26. " WL_CYC_DEL3 ,Write level cycle delay for Byte 3" "No delay,1 cycle,2 cycles," bitfld.long 0x08 24. " WL_HC_DEL3 ,Write level half cycle delay for Byte 3" "No delay,Half cycle" hexmask.long.byte 0x08 16.--22. 1. " WR_DL_ABS_OFFSET3 ,Absolute delay offset for Byte 3" textline " " bitfld.long 0x08 9.--10. " WL_CYC_DEL2 ,Write level cycle delay for Byte 2" "No delay,1 cycle,2 cycles," bitfld.long 0x08 8. " WL_HC_DEL2 ,Write level half cycle delay for Byte 2" "No delay,Half cycle" hexmask.long.byte 0x08 0.--6. 1. " WR_DL_ABS_OFFSET2 ,Absolute delay offset for Byte 2" rgroup.long 0x814++0x03 line.long 0x00 "MPWLDLST0,MMDC PHY Write Leveling Delay Line Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " WL_DL_UNIT_NUM3 ,Number of delay units that is actually used by write leveling delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WL_DL_UNIT_NUM2 ,Number of delay units that is actually used by write leveling delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WL_DL_UNIT_NUM1 ,Number of delay units that is actually used by write leveling delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WL_DL_UNIT_NUM0 ,Number of delay units that is actually used by write leveling delay line 0" textline " " group.long 0x818++0x2B line.long 0x00 "MPODTCTRL,MMDC PHY ODT Control Register" bitfld.long 0x00 16.--18. " ODT3_INT_RES ,On chip ODT byte3 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 12.--14. " ODT2_INT_RES ,On chip ODT byte2 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 8.--10. " ODT1_INT_RES ,On chip ODT byte1 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" textline " " bitfld.long 0x00 4.--6. " ODT0_INT_RES ,On chip ODT byte0 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 3. " ODT_RD_ACT_EN ,Active read CS ODT enable" "Disabled,Enabled" bitfld.long 0x00 2. " ODT_RD_PAS_EN ,Inactive read CS ODT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ODT_WR_ACT_EN ,Active write CS ODT enable" "Disabled,Enabled" bitfld.long 0x00 0. " ODT_WR_PAS_EN ,Inactive write CS ODT enable" "Disabled,Enabled" line.long 0x04 "MPRDDQBY0DL,MMDC PHY Read DQ Byte0 Delay Register" bitfld.long 0x04 28.--30. " RD_DQ7_DEL ,Read dqs0 to dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 24.--26. " RD_DQ6_DEL ,Read dqs0 to dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 20.--22. " RD_DQ5_DEL ,Read dqs0 to dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x04 16.--18. " RD_DQ4_DEL ,Read dqs0 to dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 12.--14. " RD_DQ3_DEL ,Read dqs0 to dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 8.--10. " RD_DQ2_DEL ,Read dqs0 to dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x04 4.--6. " RD_DQ1_DEL ,Read dqs0 to dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 0.--2. " RD_DQ0_DEL ,Read dqs0 to dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x08 "MPRDDQBY1DL,MMDC PHY Read DQ Byte1 Delay Register" bitfld.long 0x08 28.--30. " RD_DQ15_DEL ,Read dqs1 to dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 24.--26. " RD_DQ14_DEL ,Read dqs1 to dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 20.--22. " RD_DQ13_DEL ,Read dqs1 to dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x08 16.--18. " RD_DQ12_DEL ,Read dqs1 to dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 12.--14. " RD_DQ11_DEL ,Read dqs1 to dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 8.--10. " RD_DQ10_DEL ,Read dqs1 to dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x08 4.--6. " RD_DQ9_DEL ,Read dqs1 to dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 0.--2. " RD_DQ8_DEL ,Read dqs1 to dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x0C "MPRDDQBY2DL,MMDC PHY Read DQ Byte2 Delay Register" bitfld.long 0x0C 28.--30. " RD_DQ23_DEL ,Read dqs2 to dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 24.--26. " RD_DQ22_DEL ,Read dqs2 to dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 20.--22. " RD_DQ21_DEL ,Read dqs2 to dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x0C 16.--18. " RD_DQ20_DEL ,Read dqs2 to dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 12.--14. " RD_DQ19_DEL ,Read dqs2 to dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 8.--10. " RD_DQ18_DEL ,Read dqs2 to dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x0C 4.--6. " RD_DQ17_DEL ,Read dqs2 to dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 0.--2. " RD_DQ16_DEL ,Read dqs2 to dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x10 "MPRDDQBY3DL,MMDC PHY Read DQ Byte3 Delay Register" bitfld.long 0x10 28.--30. " RD_DQ31_DEL ,Read dqs3 to dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 24.--26. " RD_DQ30_DEL ,Read dqs3 to dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 20.--22. " RD_DQ29_DEL ,Read dqs3 to dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x10 16.--18. " RD_DQ28_DEL ,Read dqs3 to dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 12.--14. " RD_DQ27_DEL ,Read dqs3 to dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 8.--10. " RD_DQ26_DEL ,Read dqs3 to dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" textline " " bitfld.long 0x10 4.--6. " RD_DQ25_DEL ,Read dqs3 to dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 0.--2. " RD_DQ24_DEL ,Read dqs3 to dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x14 "MPWRDQBY0DL,MMDC PHY Write DQ Byte0 Delay Register" bitfld.long 0x14 30.--31. " WR_DM0_DEL ,Write dm0 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 28.--29. " WR_DQ7_DEL ,Write dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 24.--25. " WR_DQ6_DEL ,Write dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x14 20.--21. " WR_DQ5_DEL ,Write dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 16.--17. " WR_DQ4_DEL ,Write dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 12.--13. " WR_DQ3_DEL ,Write dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x14 8.--9. " WR_DQ2_DEL ,Write dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 4.--5. " WR_DQ1_DEL ,Write dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 0.--1. " WR_DQ0_DEL ,Write dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x18 "MPWRDQBY1DL,MMDC PHY Write DQ Byte1 Delay Register" bitfld.long 0x18 30.--31. " WR_DM1_DEL ,Write dm1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 28.--29. " WR_DQ15_DEL ,Write dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 24.--25. " WR_DQ14_DEL ,Write dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x18 20.--21. " WR_DQ13_DEL ,Write dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 16.--17. " WR_DQ12_DEL ,Write dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 12.--13. " WR_D11_DEL ,Write dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x18 8.--9. " WR_DQ10_DEL ,Write dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 4.--5. " WR_DQ9_DEL ,Write dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 0.--1. " WR_DQ8_DEL ,Write dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x1C "MPWRDQBY2DL, MMDC PHY Write DQ Byte2 Delay Register" bitfld.long 0x1C 30.--31. " WR_DM2_DEL ,Write dm2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 28.--29. " WR_DQ23_DEL ,Write dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 24.--25. " WR_DQ22_DEL ,Write dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x1C 20.--21. " WR_DQ21_DEL ,Write dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 16.--17. " WR_DQ20_DEL ,Write dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 12.--13. " WR_D19_DEL ,Write dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x1C 8.--9. " WR_DQ18_DEL ,Write dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 4.--5. " WR_DQ17_DEL ,Write dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 0.--1. " WR_DQ16_DEL ,Write dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x20 "MPWRDQBY3DL, MMDC PHY Write DQ Byte3 Delay Register" bitfld.long 0x20 30.--31. " WR_DM3_DEL ,Write dm3 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 28.--29. " WR_DQ31_DEL ,Write dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 24.--25. " WR_DQ30_DEL ,Write dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x20 20.--21. " WR_DQ29_DEL ,Write dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 16.--17. " WR_DQ28_DEL ,Write dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 12.--13. " WR_D27_DEL ,Write dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " bitfld.long 0x20 8.--9. " WR_DQ26_DEL ,Write dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 4.--5. " WR_DQ25_DEL ,Write dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 0.--1. " WR_DQ24_DEL ,Write dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays" textline " " line.long 0x24 "MPDGCTRL0,MMDC PHY Read DQS gating control register 0" bitfld.long 0x24 31. " RST_RD_FIFO ,Reset Read Data FIFO & pointers" "No reset,Reset" bitfld.long 0x24 30. " DG_CMP_CYC ,Read DQS gating sample cycle" "16 cycles,32 cycles" bitfld.long 0x24 29. " DG_DIS ,Read DQS gating disable" "No,Yes" textline " " bitfld.long 0x24 28. " HW_DG_EN ,Enable automatic read DQS gating calibration" "Disabled,Enabled" bitfld.long 0x24 24.--27. " DG_HC_DEL1 ,Read Dqs1 gating half cycles delay for Byte 1" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," bitfld.long 0x24 23. " DG_EXT_UP ,DG extend upper boundary" "Not extended,Extended" textline " " hexmask.long.byte 0x24 16.--22. 1. " DG_DL_ABS_OFFSET1 ,Absolute delay offset" rbitfld.long 0x24 12. " HW_DG_ERR ,HW DQS gating error " "No error,Error" bitfld.long 0x24 8.--11. " DG_HC_DEL0 ,Read DQS0 gating half cycles delay for Byte 0" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," textline " " hexmask.long.byte 0x24 0.--6. 1. " DG_DL_ABS_OFFSET0 ,Absolute read DQS gating delay offset" line.long 0x28 "MPDGCTRL1,MMDC PHY Read DQS gating control register 1" bitfld.long 0x28 24.--27. " DG_HC_DEL3 ,Read DQS3 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," hexmask.long.byte 0x28 16.--22. 1. " DG_DL_ABS_OFFSET3 ,Absolute read DQS gating delay offset for Byte 3" bitfld.long 0x28 8.--11. " DG_HC_DEL2 ,Read DQS2 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,," textline " " hexmask.long.byte 0x28 0.--6. 1. " DG_DL_ABS_OFFSET2 ,Absolute read DQS gating delay offset" rgroup.long 0x844++0x03 line.long 0x00 "MPDGDLST0,MMDC PHY Read DQS gating Delay Line Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " DG_DL_UNIT_NUM3 ,Number of delay units that is actually used by DQS gating delay line 3" hexmask.long.byte 0x00 16.--22. 1. " DG_DL_UNIT_NUM2 ,Number of delay units that is actually used by DQS gating delay line 2" hexmask.long.byte 0x00 8.--14. 1. " DG_DL_UNIT_NUM1 ,Number of delay units that is actually used by DQS gating delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " DG_DL_UNIT_NUM0 ,Number of delay units that is actually used by DQS gating delay line 0" group.long 0x848++0x03 line.long 0x00 "MPRDDLCTL,MMDC PHY Read Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_ABS_OFFSET3 ,Absolute read delay offset byte 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_ABS_OFFSET2 ,Absolute read delay offset byte 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_ABS_OFFSET1 ,Absolute read delay offset byte 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " RD_DL_ABS_OFFSET0 ,Absolute read delay offset byte 0" rgroup.long 0x84C++0x03 line.long 0x00 "MPRDDLST0,MMDC PHY Read Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_UNIT_NUM3 ,Number of delay units that is actually used by read delay line 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_UNIT_NUM2 ,Number of delay units that is actually used by read delay line 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_UNIT_NUM1 ,Number of delay units that is actually used by read delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " RD_DL_UNIT_NUM0 ,Number of delay units that is actually used by read delay line 0" group.long 0x850++0x03 line.long 0x00 "MPWRDLCTL0,MMDC PHY Write Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_ABS_OFFSET3 ,Absolute write delay offset for Byte 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_ABS_OFFSET2 ,Absolute write delay offset for Byte 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_ABS_OFFSET1 ,Absolute write delay offset for Byte 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute write delay offset for Byte 0" rgroup.long 0x854++0x03 line.long 0x00 "MPWRDLST0,MMDC PHY Write Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_UNIT_NUM3 ,Number of delay units that is actually used by write delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_UNIT_NUM2 ,Number of delay units that is actually used by write delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_UNIT_NUM1 ,Number of delay units that is actually used by write delay line 1" textline " " hexmask.long.byte 0x00 0.--6. 1. " WR_DL_UNIT_NUM0 ,Number of delay units that is actually used by write delay line 0" textline " " group.long 0x858++0x03 line.long 0x00 "MPSDCTRL,MMDC PHY CK control Register" bitfld.long 0x00 8.--9. " SDCLK_DEL ,SDCLK0 delay fine tuning" "No change,1 delay,2 delays,3 delays" hgroup.long 0x85C++0x03 hide.long 0x00 "MPZQLP2CTL,MMDC PHY ZQ LPDDR2 HW Control Register" group.long 0x860++0x07 line.long 0x00 "MPRDDLHWCTL,MMDC PHY Read Delay HW Calibration Control Register" bitfld.long 0x00 5. " HW_RDL_CMP_CYC ,HW RD DL sample cycle" "Not compared,Compared" bitfld.long 0x00 4. " HW_RDL_EN ,Enable HW RD DL calibration" "Disabled,Enabled" rbitfld.long 0x00 3. " HW_RDL_ERR3 ,HW RD DL3 error" "No error,Error" textline " " rbitfld.long 0x00 2. " HW_RDL_ERR2 ,HW RD DL2 error" "No error,Error" rbitfld.long 0x00 1. " HW_RDL_ERR1 ,HW RD DL1 error" "No error,Error" rbitfld.long 0x00 0. " HW_RDL_ERR0 ,HW RD DL0 error" "No error,Error" line.long 0x04 "MPWRDLHWCTL,MMDC PHY Write Delay HW Calibration Control Register" bitfld.long 0x04 5. " HW_WDL_CMP_CYC ,HW RD DL sample cycle" "Not compared,Compared" bitfld.long 0x04 4. " HW_WDL_EN ,Enable HW RD DL calibration" "Disabled,Enabled" rbitfld.long 0x04 3. " HW_WDL_ERR3 ,HW RD DL3 error" "No error,Error" textline " " rbitfld.long 0x04 2. " HW_WDL_ERR2 ,HW RD DL2 error" "No error,Error" rbitfld.long 0x04 1. " HW_WDL_ERR1 ,HW RD DL1 error" "No error,Error" rbitfld.long 0x04 0. " HW_WDL_ERR0 ,HW RD DL0 error" "No error,Error" rgroup.long 0x868++0x23 line.long 0x00 "MPRDDLHWST0,MMDC PHY Read Delay HW Calibration Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " HW_RD_DL_UP1 ,HW RD DL1 upper boundary" hexmask.long.byte 0x00 16.--22. 1. " HW_RD_DL_LOW1 ,HW RD DL1 lower boundary" hexmask.long.byte 0x00 8.--14. 1. " HW_RD_DL_UP0 ,HW RD DL0 upper boundary" textline " " hexmask.long.byte 0x00 0.--6. 1. " HW_RD_DL_LOW0 ,HW RD DL0 lower boundary" line.long 0x04 "MPRDDLHWST1,MMDC PHY Read Delay HW Calibration Status Register 1" hexmask.long.byte 0x04 24.--30. 1. " HW_RD_DL_UP3 ,HW RD DL3 upper boundary" hexmask.long.byte 0x04 16.--22. 1. " HW_RD_DL_LOW3 ,HW RD DL3 lower boundary" hexmask.long.byte 0x04 8.--14. 1. " HW_RD_DL_UP2 ,HW RD DL2 upper boundary" textline " " hexmask.long.byte 0x04 0.--6. 1. " HW_RD_DL_LOW2 ,HW RD DL2 lower boundary" line.long 0x08 "MPWRDLHWST0,MMDC PHY Write Delay HW Calibration Status Register 0" hexmask.long.byte 0x08 24.--30. 1. " HW_WR_DL_UP1 ,HW WR DL1 upper boundary" hexmask.long.byte 0x08 16.--22. 1. " HW_WR_DL_LOW1 ,HW WR DL1 lower boundary" hexmask.long.byte 0x08 8.--14. 1. " HW_WR_DL_UP0 ,HW WR DL0 upper boundary" textline " " hexmask.long.byte 0x08 0.--6. 1. " HW_WR_DL_LOW0 ,HW WR DL0 lower boundary" line.long 0x0C "MPWRDLHWST1,MMDC PHY Write Delay HW Calibration Status Register 1" hexmask.long.byte 0x0C 24.--30. 1. " HW_WR_DL_UP3 ,HW WR DL3 upper boundary" hexmask.long.byte 0x0C 16.--22. 1. " HW_WR_DL_LOW3 ,HW WR DL3 lower boundary" hexmask.long.byte 0x0C 8.--14. 1. " HW_WR_DL_UP2 ,HW WR DL2 upper boundary" textline " " hexmask.long.byte 0x0C 0.--6. 1. " HW_WR_DL_LOW2 ,HW WR DL2 lower boundary" line.long 0x10 "MPWLHWERR0,MMDC PHY Write Leveling HW Error Register 0" hexmask.long.byte 0x10 24.--31. 1. " HW_WL3_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 16.--23. 1. " HW_WL2_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 8.--15. 1. " HW_WL1_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" textline " " hexmask.long.byte 0x10 0.--7. 1. " HW_WL0_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" textline " " line.long 0x14 "MPDGHWST0,MMDC PHY Read DQS Gating HW Status Register 0" hexmask.long.word 0x14 16.--26. 1. " HW_DG_UP0 ,HW DG0 upper boundary" hexmask.long.word 0x14 0.--10. 1. " HW_DG_LOW0 ,HW DG0 lower boundary" line.long 0x18 "MPDGHWST1,MMDC PHY Read DQS Gating HW Status Register 1" hexmask.long.word 0x18 16.--26. 1. " HW_DG_UP1 ,HW DG1 upper boundary" hexmask.long.word 0x18 0.--10. 1. " HW_DG_LOW1 ,HW DG1 lower boundary" line.long 0x1C "MPDGHWST2,MMDC PHY Read DQS Gating HW Status Register 2" hexmask.long.word 0x1C 16.--26. 1. " HW_DG_UP2 ,HW DG2 upper boundary" hexmask.long.word 0x1C 0.--10. 1. " HW_DG_LOW2 ,HW DG2 lower boundary" line.long 0x20 "MPDGHWST3,MMDC PHY Read DQS Gating HW Status Register 3" hexmask.long.word 0x20 16.--26. 1. " HW_DG_UP3 ,HW DG3 upper boundary" hexmask.long.word 0x20 0.--10. 1. " HW_DG_LOW3 ,HW DG3 lower boundary" group.long 0x88C++0x0B line.long 0x00 "MPPDCMPR1,MMDC PHY Pre-defined Compare Register 1" hexmask.long.word 0x00 16.--31. 1. " PDV2 ,Pre defined compare value2" hexmask.long.word 0x00 0.--15. 1. " PDV1 ,Pre defined compare value2" line.long 0x04 "MPPDCMPR2,MMDC PHY Pre-defined Compare and CA Delay Line Configuration Register" bitfld.long 0x04 2. " READ_LEVEL_PATTERN ,MPR calibration Read level pattern" "1010," bitfld.long 0x04 1. " MPR_FULL_CMP ,MPR full compare enable" "Disabled,Enabled" bitfld.long 0x04 0. " MPR_CMP ,MPR compare enable" "Disabled,Enabled" line.long 0x08 "MPSWDAR0,MMDC PHY SW Dummy Access Register 0" rbitfld.long 0x08 5. " SW_DUM_CMP3 ,SW dummy read byte3 compare results" "Failed,Passed" rbitfld.long 0x08 4. " SW_DUM_CMP2 ,SW dummy read byte2 compare results" "Failed,Passed" rbitfld.long 0x08 3. " SW_DUM_CMP1 ,SW dummy read byte1 compare results" "Failed,Passed" textline " " rbitfld.long 0x08 2. " SW_DUM_CMP0 ,SW dummy read byte0 compare results" "Failed,Passed" bitfld.long 0x08 1. " SW_DUMMY_RD ,SW dummy read" "Not generated,Generated" bitfld.long 0x08 0. " SW_DUMMY_WR ,SW dummy write" "Not generated,Generated" rgroup.long 0x898++0x1F line.long 0x00 "MPSWDRDR0,MMDC PHY SW Dummy Read Data Register 0" line.long 0x04 "MPSWDRDR1,MMDC PHY SW Dummy Read Data Register 1" line.long 0x08 "MPSWDRDR2,MMDC PHY SW Dummy Read Data Register 2" line.long 0x0C "MPSWDRDR3,MMDC PHY SW Dummy Read Data Register 3" line.long 0x10 "MPSWDRDR4,MMDC PHY SW Dummy Read Data Register 4" line.long 0x14 "MPSWDRDR5,MMDC PHY SW Dummy Read Data Register 5" line.long 0x18 "MPSWDRDR6,MMDC PHY SW Dummy Read Data Register 6" line.long 0x1C "MPSWDRDR7,MMDC PHY SW Dummy Read Data Register 7" textline " " group.long 0x8B8++0x03 line.long 0x00 "MPMUR0,MMDC PHY Measure Unit Register for DQ0-3" hexmask.long.word 0x00 16.--25. 1. " MU_UNIT_DEL_NUM ,Measure unit measured number of unit delay per cycle" bitfld.long 0x00 11. " FRC_MSR ,Force measuement on delay line" "Not forced,Forced" bitfld.long 0x00 10. " MU_BYP_EN ,Measure unit bypass enable" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--9. 1. " MU_BYP_VAL ,Measure unit bypass value" hgroup.long 0x8BC++0x03 hide.long 0x00 "MPWRCADL,MMDC PHY Write CA Delay Control Register" rgroup.long 0x8C0++0x03 line.long 0x00 "MPDCCR,MMDC PHY Duty Cycle Control Register" bitfld.long 0x00 28.--30. " RD_DQS3_FT_DCC ,Read dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 25.--27. " RD_DQS2_FT_DCC ,Read dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 22.--24. " RD_DQS1_FT_DCC ,Read dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 19.--21. " RD_DQS0_FT_DCC ,Read dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 16.--18. " CK_FT1_DCC ,Secondary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 12.--14. " CK_FT0_DCC ,Primary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 9.--11. " WR_DQS3_FT_DCC ,Write dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 6.--8. " WR_DQS2_FT_DCC ,Write dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," bitfld.long 0x00 3.--5. " WR_DQS1_FT_DCC ,Write dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," textline " " bitfld.long 0x00 0.--2. " WR_DQS0_FT_DCC ,Write dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,,," else group.long 0x18++0x03 line.long 0x00 "MDMISC,MMDC Core Miscellaneous Register" bitfld.long 0x00 3.--4. " DDR_TYPE ,DDR TYPE" "DDR3,LPDDR2,..." endif width 11. endif tree.end tree "MU (Messaging Unit)" sif (cpu()=="IMX6SOLOX-CA9") tree "A-side" base ad:0x02294000 width 8. wgroup.long 0x00++0x0F line.long 0x00 "ATR0,Processor A Transmit Register 0" line.long 0x04 "ATR1,Processor A Transmit Register 1" line.long 0x08 "ATR2,Processor A Transmit Register 2" line.long 0x0C "ATR3,Processor A Transmit Register 3" hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP3 ,Processor A General Interrupt Request 3 Pending" "Not pending,Pending" bitfld.long 0x00 30. " GIP2 ,Processor A General Interrupt Request 2 Pending" "Not pending,Pending" bitfld.long 0x00 29. " GIP1 ,Processor A General Interrupt Request 1 Pending" "Not pending,Pending" bitfld.long 0x00 28. " GIP0 ,Processor A General Interrupt Request 0 Pending" "Not pending,Pending" textline " " rbitfld.long 0x00 27. " RFI3 ,Processor A Receive register 3 full" "Not full,Full" rbitfld.long 0x00 26. " RFI2 ,Processor A Receive register 2 full" "Not full,Full" rbitfld.long 0x00 25. " RFI1 ,Processor A Receive register 1 full" "Not full,Full" rbitfld.long 0x00 24. " RFI0 ,Processor A Receive register 0 full" "Not full,Full" textline " " rbitfld.long 0x00 23. " TE3 ,Processor A Transmit register 3 empty" "Not empty,Empty" rbitfld.long 0x00 22. " TE2 ,Processor A Transmit register 2 empty" "Not empty,Empty" rbitfld.long 0x00 21. " TE1 ,Processor A Transmit register 1 empty" "Not empty,Empty" rbitfld.long 0x00 20. " TE0 ,Processor A Transmit register 0 empty" "Not empty,Empty" textline " " bitfld.long 0x00 9. " BRDIP ,Processor B Reset Deasserted Interrupt Pending" "Not pending,Pending" rbitfld.long 0x00 8. " FUP ,Processor A Flags Update Pending" "Not pending,Pending" rbitfld.long 0x00 7. " BRS ,Processor B-side Reset State" "Not reset,Reset" rbitfld.long 0x00 4. " EP ,Processor A-Side Event Pending" "Not pending,Pending" textline " " rbitfld.long 0x00 2. " F2 ,BAF2 bit value" "0,1" rbitfld.long 0x00 1. " F1 ,BAF1 bit value" "0,1" rbitfld.long 0x00 0. " F0 ,BAF0 bit value" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE3 ,Processor A General Purpose Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " GIE2 ,Processor A General Purpose Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " GIE1 ,Processor A General Purpose Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " GIE0 ,Processor A General Purpose Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " RIE3 ,Processor A Receive Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " RIE2 ,Processor A Receive Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " RIE1 ,Processor A Receive Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " RIE0 ,Processor A Receive Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " TIE3 ,Processor A Transmit Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " TIE2 ,Processor A Transmit Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " TIE1 ,Processor A Transmit Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " TIE0 ,Processor A Transmit Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " GIR3 ,Processor A General Purpose Interrupt Request 3" "Not requested,Requested" bitfld.long 0x04 18. " GIR2 ,Processor A General Purpose Interrupt Request 2" "Not requested,Requested" bitfld.long 0x04 17. " GIR1 ,Processor A General Purpose Interrupt Request 1" "Not requested,Requested" bitfld.long 0x04 16. " GIR0 ,Processor A General Purpose Interrupt Request 0" "Not requested,Requested" textline " " bitfld.long 0x04 6. " BRDIE ,Processor B Reset De-assertion Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" textline " " bitfld.long 0x04 2. " ABF2 ,Processor A to Processor B Flag 2" "Not reset,Reset" bitfld.long 0x04 1. " ABF1 ,Processor A to Processor B Flag 1" "Not reset,Reset" bitfld.long 0x04 0. " ABF0 ,Processor A to Processor B Flag 0" "Not reset,Reset" width 12. tree.end else tree "B-side" base ad:0x4229C000 width 8. wgroup.long 0x00++0x0F line.long 0x00 "BTR0,Processor B Transmit Register 0" line.long 0x04 "BTR1,Processor B Transmit Register 1" line.long 0x08 "BTR2,Processor B Transmit Register 2" line.long 0x0C "BTR3,Processor B Transmit Register 3" hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP3 ,Processor B General Purpose Interrupt Request 3 Pending" "Not pending,Pending" bitfld.long 0x00 30. " GIP2 ,Processor B General Purpose Interrupt Request 2 Pending" "Not pending,Pending" bitfld.long 0x00 29. " GIP1 ,Processor B General Purpose Interrupt Request 1 Pending" "Not pending,Pending" bitfld.long 0x00 28. " GIP0 ,Processor B General Purpose Interrupt Request 0 Pending" "Not pending,Pending" textline " " rbitfld.long 0x00 27. " RF3 ,Processor B Receive register 3 full" "Not full,Full" rbitfld.long 0x00 26. " RF2 ,Processor B Receive register 2 full" "Not full,Full" rbitfld.long 0x00 25. " RF1 ,Processor B Receive register 1 full" "Not full,Full" rbitfld.long 0x00 24. " RF0 ,Processor B Receive register 0 full" "Not full,Full" textline " " rbitfld.long 0x00 23. " TE3 ,Processor B Transmit register 3 empty" "Not empty,Empty" rbitfld.long 0x00 22. " TE2 ,Processor B Transmit register 2 empty" "Not empty,Empty" rbitfld.long 0x00 21. " TE1 ,Processor B Transmit register 1 empty" "Not empty,Empty" rbitfld.long 0x00 20. " TE0 ,Processor B Transmit register 0 empty" "Not empty,Empty" textline " " rbitfld.long 0x00 8. " FUP ,Processor A Flags Update Pending" "Not pending,Pending" rbitfld.long 0x00 7. " ARS ,Processor B-side Reset State" "Not reset,Reset" rbitfld.long 0x00 5.--6. " APM ,System Power Mode" "RUN,WAIT,,STOP" rbitfld.long 0x00 4. " EP ,Processor B-Side Event Pending" "Not pending,Pending" textline " " rbitfld.long 0x00 2. " F2 ,ABF2 bit value" "0,1" rbitfld.long 0x00 1. " F1 ,ABF1 bit value" "0,1" rbitfld.long 0x00 0. " F0 ,ABF0 bit value" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE3 ,Processor B General Purpose Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " GIE2 ,Processor B General Purpose Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " GIE1 ,Processor B General Purpose Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " GIE0 ,Processor B General Purpose Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " RIE3 ,Processor B Receive Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " RIE2 ,Processor B Receive Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " RIE1 ,Processor B Receive Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " RIE0 ,Processor B Receive Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " TIE3 ,Processor B Transmit Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " TIE2 ,Processor B Transmit Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " TIE1 ,Processor B Transmit Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " TIE0 ,Processor B Transmit Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " GIR3 ,Processor B General Purpose Interrupt Request 3" "Not requested,Requested" bitfld.long 0x04 18. " GIR2 ,Processor B General Purpose Interrupt Request 2" "Not requested,Requested" bitfld.long 0x04 17. " GIR1 ,Processor B General Purpose Interrupt Request 1" "Not requested,Requested" bitfld.long 0x04 16. " GIR0 ,Processor B General Purpose Interrupt Request 0" "Not requested,Requested" textline " " bitfld.long 0x04 2. " BAF2 ,Processor B to Processor A Flag 2" "Not reset,Reset" bitfld.long 0x04 1. " BAF1 ,Processor B to Processor A Flag 1" "Not reset,Reset" bitfld.long 0x04 0. " BAF0 ,Processor B to Processor A Flag 0" "Not reset,Reset" width 12. tree.end endif tree.end tree "OCOTP_CTRL (On-Chip OTP Controller)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021BC000 else base ad:0x421BC000 endif width 22. group.long 0x00++0x13 line.long 0x00 "OCOTP_CTRL,OTP Controller Control Register" hexmask.long.word 0x00 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable [key: 0x3E77]" bitfld.long 0x00 10. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not forced,Forced" bitfld.long 0x00 9. " ERROR ,Accessing to locked region error" "No error,Error" rbitfld.long 0x00 8. " BUSY ,OTP controller status bit" "Not busy,Busy" textline " " hexmask.long.byte 0x00 0.--6. 1. " ADDR ,OTP write and read access address register" line.long 0x04 "OCOTP_CTRL_SET,OTP Controller Control Set Register" hexmask.long.word 0x04 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable" bitfld.long 0x04 10. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not effect,Set" bitfld.long 0x04 9. " ERROR ,Accessing to locked region error" "Not effect,Set" rbitfld.long 0x04 8. " BUSY ,OTP controller status bit" "Not effect,Set" textline " " hexmask.long.byte 0x04 0.--6. 1. " ADDR ,OTP write and read access address register" line.long 0x08 "OCOTP_CTRL_CLR,OTP Controller Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable" bitfld.long 0x08 10. " RELOAD_SHADOWS ,Re-loading the shadow registers" "No effect,Cleared" bitfld.long 0x08 9. " ERROR ,Accessing to locked region error" "No effect,Cleared" rbitfld.long 0x08 8. " BUSY ,OTP controller status bit" "No effect,Cleared" textline " " hexmask.long.byte 0x08 0.--6. 1. " ADDR ,OTP write and read access address register" line.long 0x0c "OCOTP_CTRL_TOG,OTP Controller Control Toggle Register" hexmask.long.word 0x0C 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable" bitfld.long 0x0C 10. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not toggled,Toggled" bitfld.long 0x0C 9. " ERROR ,Accessing to locked region error" "Not toggled,Toggled" rbitfld.long 0x0C 8. " BUSY ,OTP controller status bit" "Not toggled,Toggled" textline " " hexmask.long.byte 0x0C 0.--6. 1. " ADDR ,OTP write and read access address register" line.long 0x10 "OCOTP_TIMING,OTP Controller Timing Register" bitfld.long 0x10 22.--27. " WAIT ,Time interval between auto read and write access in one time program" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 16.--21. " STROBE_READ ,Strobe period in one time read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 12.--15. " RELAX ,Time to add to all default timing parameters other than the Tpgm and Trd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 0.--11. 1. " STROBE_PROG ,Strobe period in one time write OTP" group.long 0x20++0x03 line.long 0x00 "OCOTP_DATA,OTP Controller Write Data Register" group.long 0x30++0x03 line.long 0x00 "OCOTP_READ_CTRL,OTP Controller Write Data Register" bitfld.long 0x00 0. " READ_FUSE ,Initiate a read to OTP" "Not initiated,Initiated" group.long 0x40++0x03 line.long 0x00 "OCOTP_READ_FUSE_DATA,OTP Controller Read Data Register" group.long 0x50++0x03 line.long 0x00 "OCOTP_SW_STICKY,Sticky bit Register" bitfld.long 0x00 4. " JTAG_BLOCK_RELEASE ,JTAG blocking" "Blocked,Released" bitfld.long 0x00 3. " BLOCK_ROM_PART ,Secret part of Boot ROM" "Not hidden,Hidden" bitfld.long 0x00 2. " FIELD_RETURN_LOCK ,Shadow register write and OTP write lock for FIELD_RETURN region" "Not locked,Locked" bitfld.long 0x00 1. " SRK_REVOKE_LOCK ,Shadow register write and OTP write lock for SRK_REVOKE/MC_ERA/AP_BI_VER region" "Not locked,Locked" group.long 0x60++0x0F line.long 0x00 "OCOTP_SCS,Software Controllable Signals Register" bitfld.long 0x00 31. " LOCK ,HW_OCOTP_SCS register lock" "Not locked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use" bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG Debug Enable" "Disabled,Enabled" line.long 0x04 "OCOTP_SCS_SET,Software Controllable Signals Set Register" bitfld.long 0x04 31. " LOCK ,Lock set" "No effect,Set" hexmask.long 0x04 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use" bitfld.long 0x04 0. " HAB_JDE ,HAB JTAG Debug Enable Set" "No effect,Set" line.long 0x08 "OCOTP_SCS_CLR,Software Controllable Signals Clear Register" bitfld.long 0x08 31. " LOCK ,Lock clear" "No effect,Cleared" hexmask.long 0x08 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use" bitfld.long 0x08 0. " HAB_JDE ,HAB JTAG Debug Enable Clear" "No effect,Cleared" line.long 0x0C "OCOTP_SCS_TOG,Software Controllable Signals Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock toggle" "Not toggled,Toggled" hexmask.long 0x0C 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use" bitfld.long 0x0C 0. " HAB_JDE ,HAB JTAG Debug Enable Clear" "Not toggled,Toggled" rgroup.long 0x90++0x03 line.long 0x00 "OCOTP_VERSION,OTP Controller Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" rgroup.long 0x400++0x03 line.long 0x00 "OCOTP_LOCK,Value of OTP Bank0 Word0" bitfld.long 0x00 31. " GP3[1] ,Writing of GP3 region's shadow register" "Not blocked,Blocked" bitfld.long 0x00 30. " GP3[0] ,Writing of GP3 region's OTP fuse word" "Not blocked,Blocked" bitfld.long 0x00 22. " MISC_CONF ,Status of shadow register/OTP write lock for sata_conf region" "Not locked,Locked" bitfld.long 0x00 19. " ANALOG[1] ,Status of lock for analog region's shadow register" "Not locked,Locked" textline " " bitfld.long 0x00 18. " ANALOG[0] ,Status of lock for analog region's OTP fuse word" "Not locked,Locked" bitfld.long 0x00 14. " SRK ,Status of shadow register/OTP write lock for srk region" "Not locked,Locked" bitfld.long 0x00 13. " GP2[1] ,Status of lock for gp2 region's shadow register" "Not locked,Locked" bitfld.long 0x00 12. " GP2[0] ,Status of lock for gp2 region's OTP fuse word" "Not locked,Locked" textline " " bitfld.long 0x00 11. " GP1[1] ,Status of lock for gp1 region's shadow register" "Not locked,Locked" bitfld.long 0x00 10. " GP1[0] ,Status of lock for gp1 region's OTP fuse word" "Not locked,Locked" bitfld.long 0x00 9. " MAC_ADDR[1] ,Status of lock for mac_addr region's shadow register" "Not locked,Locked" bitfld.long 0x00 8. " MAC_ADDR[0] ,Status of lock for mac_addr region's OTP fuse word" "Not locked,Locked" textline " " bitfld.long 0x00 6. " SJC_RESP ,Status of shadow register/OTP read and write lock for sjc_resp region" "Not locked,Locked" bitfld.long 0x00 5. " MEM_TRIM[1] ,Status of lock for mem_trim region's shadow register" "Not locked,Locked" bitfld.long 0x00 4. " MEM_TRIM[0] ,Status of lock for mem_trim region's OTP fuse word" "Not locked,Locked" bitfld.long 0x00 3. " BOOT_CFG[1] ,Status of lock for boot_cfg region's shadow register" "Not locked,Locked" textline " " bitfld.long 0x00 2. " BOOT_CFG[0] ,Status of lock for boot_cfg region's OTP fuse word" "Not locked,Locked" bitfld.long 0x00 1. " TESTER[1] ,Status of lock for tester region's shadow register" "Not locked,Locked" bitfld.long 0x00 0. " TESTER[0] ,Status of lock for tester region's OTP fuse word" "Not locked,Locked" group.long 0x410++0x03 line.long 0x00 "OCOTP_CFG0,Value of OTP Bank0 Word1" group.long 0x420++0x03 line.long 0x00 "OCOTP_CFG1,Value of OTP Bank0 Word2" group.long 0x430++0x03 line.long 0x00 "OCOTP_CFG2,Value of OTP Bank0 Word3" group.long 0x440++0x03 line.long 0x00 "OCOTP_CFG3,Value of OTP Bank0 Word4" group.long 0x450++0x03 line.long 0x00 "OCOTP_CFG4,Value of OTP Bank0 Word5" group.long 0x460++0x03 line.long 0x00 "OCOTP_CFG5,Value of OTP Bank0 Word6" group.long 0x470++0x03 line.long 0x00 "OCOTP_CFG6,Value of OTP Bank0 Word7" group.long 0x480++0x03 line.long 0x00 "OCOTP_MEM0,Value of OTP Bank1 Word0" group.long 0x490++0x03 line.long 0x00 "OCOTP_MEM1,Value of OTP Bank1 Word1" group.long 0x4A0++0x03 line.long 0x00 "OCOTP_MEM2,Value of OTP Bank1 Word2" group.long 0x4B0++0x03 line.long 0x00 "OCOTP_MEM3,Value of OTP Bank1 Word3" group.long 0x4C0++0x03 line.long 0x00 "OCOTP_MEM4,Value of OTP Bank1 Word4" group.long 0x4D0++0x03 line.long 0x00 "OCOTP_ANA0,Value of OTP Bank1 Word5" group.long 0x4E0++0x03 line.long 0x00 "OCOTP_ANA1,Value of OTP Bank1 Word6" group.long 0x4F0++0x03 line.long 0x00 "OCOTP_ANA2,Value of OTP Bank1 Word7" group.long 0x580++0x03 line.long 0x00 "OCOTP_SRK0,Shadow Register for OTP Bank3 Word0" group.long 0x590++0x03 line.long 0x00 "OCOTP_SRK1,Shadow Register for OTP Bank3 Word1" group.long 0x5A0++0x03 line.long 0x00 "OCOTP_SRK2,Shadow Register for OTP Bank3 Word2" group.long 0x5B0++0x03 line.long 0x00 "OCOTP_SRK3,Shadow Register for OTP Bank3 Word3" group.long 0x5C0++0x03 line.long 0x00 "OCOTP_SRK4,Shadow Register for OTP Bank3 Word4" group.long 0x5D0++0x03 line.long 0x00 "OCOTP_SRK5,Shadow Register for OTP Bank3 Word5" group.long 0x5E0++0x03 line.long 0x00 "OCOTP_SRK6,Shadow Register for OTP Bank3 Word6" group.long 0x5F0++0x03 line.long 0x00 "OCOTP_SRK7,Shadow Register for OTP Bank3 Word7" group.long 0x600++0x03 line.long 0x00 "OCOTP_RESP0,Value of OTP Bank4 Word0" group.long 0x610++0x03 line.long 0x00 "OCOTP_HSJC_RESP1,Value of OTP Bank4 Word1" group.long 0x620++0x03 line.long 0x00 "OCOTP_MAC0,Value of OTP Bank4 Word2" group.long 0x630++0x03 line.long 0x00 "OCOTP_MAC1,Value of OTP Bank4 Word3" group.long 0x640++0x03 line.long 0x00 "OCOTP_MAC2,Value of OTP Bank4 Word4" group.long 0x660++0x03 line.long 0x00 "OCOTP_GP1,Value of OTP Bank4 Word6" group.long 0x670++0x03 line.long 0x00 "OCOTP_GP2,Value of OTP Bank4 Word7" group.long 0x6D0++0x03 line.long 0x00 "OCOTP_MISC_CONF,Value of OTP Bank5 Word5" group.long 0x6E0++0x03 line.long 0x00 "OCOTP_FIELD_RETURN,Value of OTP Bank5 Word6" group.long 0x6F0++0x03 line.long 0x00 "OCOTP_SRK_REVOKE,Value of OTP Bank5 Word7" group.long 0xA10++0x03 line.long 0x00 "OCOTP_GP30,Value of OTP Bank10 Word1" group.long 0xA20++0x03 line.long 0x00 "OCOTP_GP31,Value of OTP Bank10 Word2" group.long 0xA30++0x03 line.long 0x00 "OCOTP_GP32,Value of OTP Bank10 Word3" group.long 0xA40++0x03 line.long 0x00 "OCOTP_GP33,Value of OTP Bank10 Word4" group.long 0xA50++0x03 line.long 0x00 "OCOTP_GP34,Value of OTP Bank10 Word5" group.long 0xA60++0x03 line.long 0x00 "OCOTP_GP35,Value of OTP Bank10 Word6" group.long 0xA70++0x03 line.long 0x00 "OCOTP_GP36,Value of OTP Bank10 Word7" width 0xB tree.end tree "PMU (Power Management Unit)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021BC000 else base ad:0x421BC000 endif width 15. group.long 0x00++0x03 line.long 0x00 "PMU_REG_1P1,Regulator 1P1 Register" bitfld.long 0x00 19. " SELREF_WEAK_LINREG ,Source for the reference voltage of the weak 1p1 regulator" "Low power bandgap,VDD SOC CAP" bitfld.long 0x00 18. " SELREF_WEAK_LINREG ,Source for the reference voltage of the weak 1p1 regulator" "Low power bandgap,VDD SOC CAP" group.long 0x10++0x03 line.long 0x00 "PMU_REG_3P0,Regulator 3P0 Register" group.long 0x20++0x03 line.long 0x00 "PMU_REG_2P5,Regulator 2P5 Register" group.long 0x30++0x03 line.long 0x00 "PMU_REG_CORE,Digital Regulator Core Register" bitfld.long 0x00 29. " FET_ODRIVE ,Increases the gate drive on power gating fets to reduce leakage in the off state" "Not set,Set" bitfld.long 0x00 23.--26. " REG2_ADJ ,Defines the adjustment bits to calibrate the target value of REG2 (REG_SOC)" "No adjustment,+0.25%,+0.50%,+0.75%,+1.00%,+1.25%,+1.50%,+1.75%,-0.25%,-0.50%,-0.75%,-1.00%,-1.25%,-1.50%,-1.75%,-2.00%" textline " " bitfld.long 0x00 18.--22. " REG2_TARG ,Defines the target voltage for the SOC power domain" "Power gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" bitfld.long 0x00 14.--17. " REG1_ADJ ,Defines the adjustment bits to calibrate the target value of REG1 (REG_PU)" "No adjustment,+0.25%,+0.50%,+0.75%,+1.00%,+1.25%,+1.50%,+1.75%,-0.25%,-0.50%,-0.75%,-1.00%,-1.25%,-1.50%,-1.75%,-2.00%" bitfld.long 0x00 9.--13. " REG1_TARG ,Defines the target voltage for the VPU/GPU power domain" "Power gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" textline " " bitfld.long 0x00 5.--8. " REG0_ADJ ,Defines the adjustment bits to calibrate the target value of REG1 (ARM_CORE)" "No adjustment,+0.25%,+0.50%,+0.75%,+1.00%,+1.25%,+1.50%,+1.75%,-0.25%,-0.50%,-0.75%,-1.00%,-1.25%,-1.50%,-1.75%,-2.00%" bitfld.long 0x00 0.--4. " REG0_TRIG ,Defines the target voltage for the arm core power domain" "Power gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" group.long 0x40++0x03 line.long 0x00 "PMU_MISC0,Miscellaneous Register 0" bitfld.long 0x00 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock" "0.5ms,1ms,2.0ms,3.0ms,4.0ms,5.0ms,6.0ms,7.0ms" bitfld.long 0x00 25. " CLKGATE_CTRL ,Allows disabling the clock gate" "Allowed,Not allowed" bitfld.long 0x00 18.--19. " WBCP_VPW_THRESH ,Voltage that the pwell is charged pumped to" "Nominal,Increase by 25mV,Decrease by 25mV,Decrease by 50mV" textline " " bitfld.long 0x00 17. " OSC_XTALOK_EN ,24MHz oscillator close to operating frequency" "Not asserted,Asserted" bitfld.long 0x00 16. " OSC_XTALOK ,Signals that the output of the 24MHz crystal oscillator is stable" "Not stable,Stable" bitfld.long 0x00 14.--15. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,Decrease by 12.5%,Decrease by 25%,Decrease by 37.5%" textline " " sif (cpu()=="iMX6Solo")||(cpu()=="iMX6DualLite") bitfld.long 0x00 13. " DISCON_HIGH_SNVS ,Forces the short between VDDHIGH_IN and VSNVS_IN to open" "Not forced,Forced" textline " " endif bitfld.long 0x00 12. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode" "Powered down,Left up" bitfld.long 0x00 7. " REFTOP_VBGUP ,Signals that the analog bandgap voltage is up and stable" "Not stable,Stable" bitfld.long 0x00 4.--6. " REFTOP_VBGADJ ,REFTOP_ VBGADJ" "Nominal VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG+0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" textline " " bitfld.long 0x00 3. " REFTOP_SELFBIASOFF ,Disable the self-bias circuit in the analog bandgap" "Coarse used,Bandgap used" bitfld.long 0x00 0. " REFTOP_PWD ,Power-down the analog bandgap reference circuitry" "Powered,Powered down" group.long 0x50++0x0F line.long 0x00 "PMU_MISC1,Miscellaneous Register 1" eventfld.long 0x00 31. " IRQ_DIG_BO ,Digital regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " IRQ_ANA_BO ,Analog regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " IRQ_TEMPSENSE ,Temperature sensor interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " LVDSCLK2_IBEN ,Enables the lvds input buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x00 12. " LVDSCLK1_IBEN ,Enables the lvds input buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x00 11. " LVDSCLK2_OBEN ,Enables the lvds output buffer for anaclk2/2b" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " LVDSCLK1_OBEN ,Enables the lvds output buffer for anaclk1/1b" "Disabled,Enabled" textline " " sif (cpu()=="iMX6Solo")||(cpu()=="iMX6DualLite") bitfld.long 0x00 5.--9. " LVDS2_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,Reserved,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x00 0.--4. " LVDS1_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,Reserved,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" else bitfld.long 0x00 5.--9. " LVDS2_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,SATA ref clock,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x00 0.--4. " LVDS1_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,SATA ref clock,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" endif line.long 0x04 "PMU_MISC1_SET,Miscellaneous Register 1" eventfld.long 0x04 31. " IRQ_DIG_BO ,Digital regulator brownout interrupt" "Not set,Set" eventfld.long 0x04 30. " IRQ_ANA_BO ,Analog regulator brownout interrupt" "Not set,Set" eventfld.long 0x04 29. " IRQ_TEMPSENSE ,Temperature sensor interrupt assertst" "Not set,Set" textline " " bitfld.long 0x04 13. " LVDSCLK2_IBEN ,Enables the lvds input buffer for anaclk2/2b" "Not set,Set" bitfld.long 0x04 12. " LVDSCLK1_IBEN ,Enables the lvds input buffer for anaclk1/1b" "Not set,Set" bitfld.long 0x04 11. " LVDSCLK2_OBEN ,Enables the lvds output buffer for anaclk2/2b" "Not set,Set" textline " " bitfld.long 0x04 10. " LVDSCLK1_OBEN ,Enables the lvds output buffer for anaclk1/1b" "Not set,Set" textline " " sif (cpu()=="iMX6Solo")||(cpu()=="iMX6DualLite") bitfld.long 0x04 5.--9. " LVDS2_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,Reserved,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x04 0.--4. " LVDS1_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,Reserved,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" else bitfld.long 0x04 5.--9. " LVDS2_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,SATA ref clock,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x04 0.--4. " LVDS1_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,SATA ref clock,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" endif line.long 0x08 "PMU_MISC1_CLR,Miscellaneous Register 1" eventfld.long 0x08 31. " IRQ_DIG_BO ,Digital regulator brownout interrupt" "Not cleared,Cleared" eventfld.long 0x08 30. " IRQ_ANA_BO ,Analog regulator brownout interrupt" "Not cleared,Cleared" eventfld.long 0x08 29. " IRQ_TEMPSENSE ,Temperature sensor interrupt assertst" "Not cleared,Cleared" textline " " bitfld.long 0x08 13. " LVDSCLK2_IBEN ,Enables the lvds input buffer for anaclk2/2b" "Not cleared,Cleared" bitfld.long 0x08 12. " LVDSCLK1_IBEN ,Enables the lvds input buffer for anaclk1/1b" "Not cleared,Cleared" bitfld.long 0x08 11. " LVDSCLK2_OBEN ,Enables the lvds output buffer for anaclk2/2b" "Not cleared,Cleared" textline " " bitfld.long 0x08 10. " LVDSCLK1_OBEN ,Enables the lvds output buffer for anaclk1/1b" "Not cleared,Cleared" textline " " sif (cpu()=="iMX6Solo")||(cpu()=="iMX6DualLite") bitfld.long 0x08 5.--9. " LVDS2_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,Reserved,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x08 0.--4. " LVDS1_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,Reserved,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" else bitfld.long 0x08 5.--9. " LVDS2_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,SATA ref clock,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x08 0.--4. " LVDS1_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,SATA ref clock,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" endif line.long 0x0C "PMU_MISC1_TOG,Miscellaneous Register 1" eventfld.long 0x0C 31. " IRQ_DIG_BO ,Digital regulator brownout interrupt" "Not toggled,Toggled" eventfld.long 0x0C 30. " IRQ_ANA_BO ,Analog regulator brownout interrupt" "Not toggled,Toggled" eventfld.long 0x0C 29. " IRQ_TEMPSENSE ,Temperature sensor interrupt assertst" "Not toggled,Toggled" textline " " bitfld.long 0x0C 13. " LVDSCLK2_IBEN ,Enables the lvds input buffer for anaclk2/2b" "Not toggled,Toggled" bitfld.long 0x0C 12. " LVDSCLK1_IBEN ,Enables the lvds input buffer for anaclk1/1b" "Not toggled,Toggled" bitfld.long 0x0C 11. " LVDSCLK2_OBEN ,Enables the lvds output buffer for anaclk2/2b" "Not toggled,Toggled" textline " " bitfld.long 0x0C 10. " LVDSCLK1_OBEN ,Enables the lvds output buffer for anaclk1/1b" "Not toggled,Toggled" textline " " sif (cpu()=="iMX6Solo")||(cpu()=="iMX6DualLite") bitfld.long 0x0C 5.--9. " LVDS2_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,Reserved,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x0C 0.--4. " LVDS1_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,Reserved,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" else bitfld.long 0x0C 5.--9. " LVDS2_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,SATA ref clock,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x0C 0.--4. " LVDS1_CLK_SEL ,Selects the clk to be routed to anaclk2/2b" "ARM PLL,SYS PLL,PFD4,PFD5,PFD6,PFD7,Audio PLL,Video PLL,MLB PLL,Eth ref clock,PCIe ref clock,SATA ref clock,USB1 PLL clock,USB2 PLL clock,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" endif group.long 0x60++0x0F line.long 0x00 "PMU_MISC2,Miscellaneous Register 2" bitfld.long 0x00 30.--31. " VIDEO_DIV ,Post-divider for video PLL" "/1,/2,/1,/4" bitfld.long 0x00 28.--29. " REG2_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x00 26.--27. " REG1_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" textline " " bitfld.long 0x00 24.--25. " REG0_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" textline " " sif (cpu()=="iMX6Solo")||(cpu()=="iMX6DualLite") bitfld.long 0x00 23. 15. " AUDIO_DIV_MSB ,2 bit post-divider field for the Audio PLL" "/1,/2,/1,/4" textline " " endif bitfld.long 0x00 22. " REG2_OK ,Signals that the voltage is above the brownout level for the SOC supply" "Below/equal,Above" bitfld.long 0x00 21. " REG2_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "Disabled,Enabled" bitfld.long 0x00 16.--18. " REG2_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" bitfld.long 0x00 13. " REG1_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "Reserved,Below target" bitfld.long 0x00 8.--10. " REG1_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" bitfld.long 0x00 7. " PLL3_DISABLE ,Turn off the USB-PLL(PLL3) in run mode" "No,Yes" textline " " bitfld.long 0x00 5. " REG0_ENABLE_BO ,Enables the brownout detection" "Enabled,Disabled" bitfld.long 0x00 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "Reserved,Below target" bitfld.long 0x00 0.--2. " REG0_BO_OFFSET ,Defines the brown out voltage offset for the CORE power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" line.long 0x04 "PMU_MISC2_SET,Miscellaneous Register 2" bitfld.long 0x04 30.--31. " VIDEO_DIV ,Post-divider for video PLL" "/1,/2,/1,/4" bitfld.long 0x04 28.--29. " REG2_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x04 26.--27. " REG1_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" textline " " bitfld.long 0x04 24.--25. " REG0_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" textline " " sif (cpu()=="iMX6Solo")||(cpu()=="iMX6DualLite") bitfld.long 0x04 23. 15. " AUDIO_DIV_MSB ,2 bit post-divider field for the Audio PLL" "/1,/2,/1,/4" textline " " endif bitfld.long 0x04 22. " REG2_OK ,Signals that the voltage is above the brownout level for the SOC supply" "Below/equal,Above" bitfld.long 0x04 21. " REG2_ENABLE_BO ,Enables the brownout detection" "Not set,Set" textline " " bitfld.long 0x04 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "Not set,Set" bitfld.long 0x04 16.--18. " REG2_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" bitfld.long 0x04 13. " REG1_ENABLE_BO ,Enables the brownout detection" "Not set,Set" textline " " bitfld.long 0x04 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "Not set,Set" bitfld.long 0x04 8.--10. " REG1_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" bitfld.long 0x04 7. " PLL3_DISABLE ,Turn off the USB-PLL(PLL3) in run mode" "Not set,Set" textline " " bitfld.long 0x04 5. " REG0_ENABLE_BO ,Enables the brownout detection" "Not set,Set" bitfld.long 0x04 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "Not set,Set" bitfld.long 0x04 0.--2. " REG0_BO_OFFSET ,Defines the brown out voltage offset for the CORE power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" line.long 0x08 "PMU_MISC2_CLR,Miscellaneous Register 2" bitfld.long 0x08 30.--31. " VIDEO_DIV ,Post-divider for video PLL" "/1,/2,/1,/4" bitfld.long 0x08 28.--29. " REG2_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x08 26.--27. " REG1_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" textline " " bitfld.long 0x08 24.--25. " REG0_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" textline " " sif (cpu()=="iMX6Solo")||(cpu()=="iMX6DualLite") bitfld.long 0x08 23. 15. " AUDIO_DIV_MSB ,2 bit post-divider field for the Audio PLL" "/1,/2,/1,/4" textline " " endif bitfld.long 0x08 22. " REG2_OK ,Signals that the voltage is above the brownout level for the SOC supply" "Below/equal,Above" bitfld.long 0x08 21. " REG2_ENABLE_BO ,Enables the brownout detection" "Not cleared,Cleared" textline " " bitfld.long 0x08 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "Not cleared,Cleared" bitfld.long 0x08 16.--18. " REG2_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" bitfld.long 0x08 13. " REG1_ENABLE_BO ,Enables the brownout detection" "Not cleared,Cleared" textline " " bitfld.long 0x08 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "Not cleared,Cleared" bitfld.long 0x08 8.--10. " REG1_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" bitfld.long 0x08 7. " PLL3_DISABLE ,Turn off the USB-PLL(PLL3) in run mode" "Not cleared,Cleared" textline " " bitfld.long 0x08 5. " REG0_ENABLE_BO ,Enables the brownout detection" "Not cleared,Cleared" bitfld.long 0x08 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "Not cleared,Cleared" bitfld.long 0x08 0.--2. " REG0_BO_OFFSET ,Defines the brown out voltage offset for the CORE power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" line.long 0x0C "PMU_MISC2_TOG,Miscellaneous Register 2" bitfld.long 0x0C 30.--31. " VIDEO_DIV ,Post-divider for video PLL" "/1,/2,/1,/4" bitfld.long 0x0C 28.--29. " REG2_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x0C 26.--27. " REG1_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" textline " " bitfld.long 0x0C 24.--25. " REG0_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" textline " " sif (cpu()=="iMX6Solo")||(cpu()=="iMX6DualLite") bitfld.long 0x0C 23. 15. " AUDIO_DIV_MSB ,2 bit post-divider field for the Audio PLL" "/1,/2,/1,/4" textline " " endif bitfld.long 0x0C 22. " REG2_OK ,Signals that the voltage is above the brownout level for the SOC supply" "Below/equal,Above" bitfld.long 0x0C 21. " REG2_ENABLE_BO ,Enables the brownout detection" "Not toggled,Toggled" textline " " bitfld.long 0x0C 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "Not toggled,Toggled" bitfld.long 0x0C 16.--18. " REG2_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" bitfld.long 0x0C 13. " REG1_ENABLE_BO ,Enables the brownout detection" "Not toggled,Toggled" textline " " bitfld.long 0x0C 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "Not toggled,Toggled" bitfld.long 0x0C 8.--10. " REG1_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" bitfld.long 0x0C 7. " PLL3_DISABLE ,Turn off the USB-PLL(PLL3) in run mode" "Not toggled,Toggled" textline " " bitfld.long 0x0C 5. " REG0_ENABLE_BO ,Enables the brownout detection" "Not toggled,Toggled" bitfld.long 0x0C 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "Not toggled,Toggled" bitfld.long 0x0C 0.--2. " REG0_BO_OFFSET ,Defines the brown out voltage offset for the CORE power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" width 11. tree.end tree.open "PWM (Pulse Width Modulation)" tree "PWM 1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02080000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x02080000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B else base ad:0x42080000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x42080000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B endif tree.end tree "PWM 2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02084000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x02084000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B else base ad:0x42084000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x42084000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B endif tree.end tree "PWM 3" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02088000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x02088000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B else base ad:0x42088000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x42088000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B endif tree.end tree "PWM 4" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0208C000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x0208C000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B else base ad:0x4208C000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x4208C000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B endif tree.end tree "PWM 5" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x022A4000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x022A4000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B else base ad:0x422A4000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x422A4000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B endif tree.end tree "PWM 6" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x022A8000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x022A8000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B else base ad:0x422A8000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x422A8000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B endif tree.end tree "PWM 7" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x022AC000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x022AC000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B else base ad:0x422AC000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x422AC000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B endif tree.end tree "PWM 8" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x022B0000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x022B0000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B else base ad:0x422B0000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected" textline " " bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value" bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times" textline " " bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark" textline " " sif (cpu()=="IMX6SOLOLITE") rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." else bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..." endif line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled" sif (cpu()=="IMX6SOLOLITE") if (((per.l(ad:0x422B0000+0x00))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" else wgroup.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif else group.long 0x0C++0x03 line.long 0x00 "PWMSAR,PWM Sample Register" hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value" endif group.long 0x10++0x03 line.long 0x00 "PWMPR,PWM Period Register" hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value" rgroup.long 0x14++0x3 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value" width 0x0B endif tree.end tree.end tree "PXP (Pixel Pipeline)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02218000 else base ad:0x42218000 endif width 15. group.long 0x00++0x33 line.long 0x00 "CTRL,Control Register 0" bitfld.long 0x00 31. " SFTRST ,Clocks with the PXP and holds LP state" "Enabled,Disabled" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Not gated,Gated" bitfld.long 0x00 28. " EN_REPEAT ,Enable the PXP to run continuously" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " BLOCK_SIZE ,Select the block size to process" "8x8,16x16" bitfld.long 0x00 22. " ROT_POS ,Place of rotation in the PXP datapath" "Output stage,Before image composition" bitfld.long 0x00 11. " VFLIP ,Output buffer flipped vertically" "No,Yes" textline " " bitfld.long 0x00 10. " HFLIP ,Output buffer flipped horizontally" "No,Yes" bitfld.long 0x00 8.--9. " ROTATE ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x00 3. " LUT_DMA_IRQ_EN ,LUT DMA interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " NEXT_IRQ_EN ,Next command interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " IRQ_EN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE ,Enables PXP operation with specified parameters" "Disabled,Enabled" line.long 0x04 "CTRL_SET,Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Clocks with the PXP and holds LP state set" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" bitfld.long 0x04 28. " EN_REPEAT ,Enable the PXP to run continuously" "No effect,Set" textline " " bitfld.long 0x04 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Set" bitfld.long 0x04 22. " ROT_POS ,Place of rotation in the PXP datapath" "No effect,Set" bitfld.long 0x04 11. " VFLIP ,Output buffer flipped vertically" "No effect,Set" textline " " bitfld.long 0x04 10. " HFLIP ,Output buffer flipped horizontally" "No effect,Set" bitfld.long 0x04 8.--9. " ROTATE ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x04 3. " LUT_DMA_IRQ_EN ,LUT DMA interrupt enable" "No effect,Set" textline " " bitfld.long 0x04 2. " NEXT_IRQ_EN ,Next command interrupt enable" "No effect,Set" bitfld.long 0x04 1. " IRQ_EN ,Interrupt enable" "No effect,Set" bitfld.long 0x04 0. " ENABLE ,Enables PXP operation with specified parameters" "No effect,Set" line.long 0x08 "CTRL_CLR,Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Clocks with the PXP and holds LP state" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" bitfld.long 0x08 28. " EN_REPEAT ,Enable the PXP to run continuously" "No effect,Clear" textline " " bitfld.long 0x08 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Clear" bitfld.long 0x08 22. " ROT_POS ,Place of rotation in the PXP datapath" "No effect,Clear" bitfld.long 0x08 11. " VFLIP ,Output buffer flipped vertically" "No effect,Clear" textline " " bitfld.long 0x08 10. " HFLIP ,Output buffer flipped horizontally" "No effect,Clear" bitfld.long 0x08 8.--9. " ROTATE ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x08 3. " LUT_DMA_IRQ_EN ,LUT DMA interrupt enable" "No effect,Clear" textline " " bitfld.long 0x08 2. " NEXT_IRQ_EN ,Next command interrupt enable" "No effect,Clear" bitfld.long 0x08 1. " IRQ_EN ,Interrupt enable" "No effect,Clear" bitfld.long 0x08 0. " ENABLE ,Enables PXP operation with specified parameters" "No effect,Clear" line.long 0x0C "CTRL_TOG,Control Toggle Register 0" bitfld.long 0x0C 31. " SFTRST ,Clocks with the PXP and holds LP state" "Not toggled,Toggled" bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "Not toggled,Toggled" bitfld.long 0x0C 28. " EN_REPEAT ,Enable the PXP to run continuously" "Not toggled,Toggled" textline " " bitfld.long 0x0C 23. " BLOCK_SIZE ,Select the block size to process" "Not toggled,Toggled" bitfld.long 0x0C 22. " ROT_POS ,Place of rotation in the PXP datapath" "Not toggled,Toggled" bitfld.long 0x0C 11. " VFLIP ,Output buffer flipped vertically" "Not toggled,Toggled" textline " " bitfld.long 0x0C 10. " HFLIP ,Output buffer flipped horizontally" "Not toggled,Toggled" bitfld.long 0x0C 8.--9. " ROTATE ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x0C 3. " LUT_DMA_IRQ_EN ,LUT DMA interrupt enable" "Not toggled,Toggled" textline " " bitfld.long 0x0C 2. " NEXT_IRQ_EN ,Next command interrupt enable" "Not toggled,Toggled" bitfld.long 0x0C 1. " IRQ_EN ,Interrupt enable" "Not toggled,Toggled" bitfld.long 0x0C 0. " ENABLE ,Enables PXP operation with specified parameters" "Not toggled,Toggled" line.long 0x10 "STAT,Status Register" hexmask.long.byte 0x10 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x10 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x10 8. " LUT_DMA_LOAD_DONE_IRQ ,LUT DMA transfer complete" "Not completed,completed" textline " " rbitfld.long 0x10 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 3. " NEXT_IRQ ,Next Command issue" "Not issued,Issued" bitfld.long 0x10 2. " AXI_READ_ERROR ,PXP encountered an AXI read error" "No error,Error" textline " " bitfld.long 0x10 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error" "No error,Error" bitfld.long 0x10 0. " IRQ ,Current PXP interrupt status" "No interrupt,Interrupt" line.long 0x14 "STAT_SET,Status Register" hexmask.long.byte 0x14 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x14 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x14 8. " LUT_DMA_LOAD_DONE_IRQ ,LUT DMA transfer complete" "No effect,Set" textline " " rbitfld.long 0x14 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 3. " NEXT_IRQ ,Next Command issue" "No effect,Set" bitfld.long 0x14 2. " AXI_READ_ERROR ,PXP encountered an AXI read error" "No effect,Set" textline " " bitfld.long 0x14 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error" "No effect,Set" bitfld.long 0x14 0. " IRQ ,Current PXP interrupt status" "No effect,Set" line.long 0x18 "STAT_CLR,Status Register" hexmask.long.byte 0x18 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x18 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x18 8. " LUT_DMA_LOAD_DONE_IRQ ,LUT DMA transfer complete" "No effect,Clear" textline " " rbitfld.long 0x18 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 3. " NEXT_IRQ ,Next Command issue" "No effect,Clear" bitfld.long 0x18 2. " AXI_READ_ERROR ,PXP encountered an AXI read error" "No effect,Clear" textline " " bitfld.long 0x18 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error" "No effect,Clear" bitfld.long 0x18 0. " IRQ ,Current PXP interrupt status" "No effect,Clear" line.long 0x1C "STAT_TOG,Status Register" hexmask.long.byte 0x1C 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x1C 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x1C 8. " LUT_DMA_LOAD_DONE_IRQ ,LUT DMA transfer complete" "Not toggled,Toggled" textline " " rbitfld.long 0x1C 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 3. " NEXT_IRQ ,Next Command issue" "Not toggled,Toggled" bitfld.long 0x1C 2. " AXI_READ_ERROR ,PXP encountered an AXI read error" "Not toggled,Toggled" textline " " bitfld.long 0x1C 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error" "Not toggled,Toggled" bitfld.long 0x1C 0. " IRQ ,Current PXP interrupt status" "Not toggled,Toggled" line.long 0x20 "OUT_CTRL,Output Buffer Control Register" hexmask.long.byte 0x20 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x20 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "Computed,Overwritten" bitfld.long 0x20 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" textline " " bitfld.long 0x20 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x24 "OUT_CTRL_SET,Output Buffer Control Set Register" hexmask.long.byte 0x24 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x24 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "Computed,Overwritten" bitfld.long 0x24 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" textline " " bitfld.long 0x24 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x28 "OUT_CTRL_ClR,Output Buffer Control Clear Register" hexmask.long.byte 0x28 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x28 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "Computed,Overwritten" bitfld.long 0x28 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" textline " " bitfld.long 0x28 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x2C "OUT_CTRL_TOG,Output Buffer Control Toggle Register" hexmask.long.byte 0x2C 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x2C 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "Computed,Overwritten" bitfld.long 0x2C 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" textline " " bitfld.long 0x2C 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x30 "OUT_BUF,Output Frame Buffer Pointer" group.long 0x40++0x03 line.long 0x00 "OUT_BUF2,Output Frame Buffer Pointer 2" group.long 0x50++0x03 line.long 0x00 "OUT_PITCH,Output Buffer Pitch" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Number of bytes in memory between two vertically adjacent pixels" group.long 0x60++0x03 line.long 0x00 "OUT_LRC,Output Surface Lower Right Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Number of horizontal PIXELS in the output surface (non-rotated)" hexmask.long.word 0x00 0.--13. 1. " Y ,Number of vertical PIXELS in the output surface (non-rotated)" group.long 0x70++0x03 line.long 0x00 "OUT_PS_ULC,Processed Surface Upper Left Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Upper left X-coordinate (in pixels) of PS in the output buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Upper left Y-coordinate (in pixels) of PS in the output buffer" group.long 0x80++0x03 line.long 0x00 "OUT_PS_LRC,Processed Surface Lower Right Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Lower right X-coordinate (in pixels) of PS in the output frame buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Lower right Y-coordinate (in pixels) of PS in the output frame buffer" group.long 0x90++0x03 line.long 0x00 "OUT_AS_ULC,Alpha Surface Upper Left Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Upper left X-coordinate (in pixels) of AS in the output frame buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Upper left Y-coordinate (in pixels) of AS in the output frame buffer" group.long 0xA0++0x03 line.long 0x00 "OUT_AS_LRC,Alpha Surface Lower Right Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Lower right X-coordinate (in pixels) of AS in the output frame buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Lower right Y-coordinate (in pixels) of AS in the output frame buffer" group.long 0xB0++0x13 line.long 0x00 "PS_CTRL,Processed Surface (PS) Control Register" bitfld.long 0x00 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,by 2,by 4,by 8" bitfld.long 0x00 8.--9. " DECY ,Verticle pre decimation filter control" "Disabled,by 2,by 4,by 8" bitfld.long 0x00 5. " WB_SWAP ,Swap bytes in words" "Not swapped,Swapped" textline " " bitfld.long 0x00 0.--4. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420" line.long 0x04 "PS_CTRL_SET,Processed Surface (PS) Control Set Register" bitfld.long 0x04 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,by 2,by 4,by 8" bitfld.long 0x04 8.--9. " DECY ,Verticle pre decimation filter control" "Disabled,by 2,by 4,by 8" bitfld.long 0x04 5. " WB_SWAP ,Swap bytes in words" "No effect,Set" textline " " bitfld.long 0x04 0.--4. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420" line.long 0x08 "PS_CTRL_CLR,Processed Surface (PS) Control Clear Register" bitfld.long 0x08 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,by 2,by 4,by 8" bitfld.long 0x08 8.--9. " DECY ,Verticle pre decimation filter control" "Disabled,by 2,by 4,by 8" bitfld.long 0x08 5. " WB_SWAP ,Swap bytes in words" "No effect,Clear" textline " " bitfld.long 0x08 0.--4. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420" line.long 0x0C "PS_CTRL_TOG,Processed Surface (PS) Control Toggle Register" bitfld.long 0x0C 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,by 2,by 4,by 8" bitfld.long 0x0C 8.--9. " DECY ,Verticle pre decimation filter control" "Disabled,by 2,by 4,by 8" bitfld.long 0x0C 5. " WB_SWAP ,Swap bytes in words" "Not toggled,Toggled" textline " " bitfld.long 0x0C 0.--4. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420" line.long 0x10 "PS_BUF,PS Input Buffer Address" group.long 0xD0++0x03 line.long 0x00 "PS_UBUF,PS U/Cb or 2 Plane UV Input Buffer Address" group.long 0xE0++0x03 line.long 0x00 "PS_VBUF,PS V/Cr Input Buffer Address" group.long 0xF0++0x03 line.long 0x00 "PS_PITCH,Processed Surface Pitch" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Number of bytes in memory between two vertically adjacent pixels" group.long 0x100++0x03 line.long 0x00 "PS_BACKGROUND,PS Background Color" hexmask.long.tbyte 0x00 0.--23. 1. " COLOR ,Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC" group.long 0x110++0x03 line.long 0x00 "PS_SCALE,PS Scale Factor Register" hexmask.long.word 0x00 16.--30. 1. " YSCALE ,Two bit integer and 12 bit fractional representation of the Y scaling factor for the PS source buffer" hexmask.long.word 0x00 0.--14. 1. " XSCALE ,Two bit integer and 12 bit fractional representation of the X scaling factor for the PS source buffer" group.long 0x120++0x03 line.long 0x00 "PS_OFFSET,PS Scale Offset Register" hexmask.long.word 0x00 16.--27. 1. " YOFFSET ,12 bit fractional representation of the Y scaling offset" hexmask.long.word 0x00 0.--11. 1. " XOFFSET ,12 bit fractional representation of the X scaling offset" group.long 0x130++0x03 line.long 0x00 "PS_CLRKEYLOW,PS Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of color key applied to PS buffer" group.long 0x140++0x03 line.long 0x00 "PS_CLRKEYHIGH,PS Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of color key applied to PS buffer" group.long 0x150++0x03 line.long 0x00 "AS_CTRL,Alpha Surface Control" bitfld.long 0x00 20. " ALPHA_INVERT ,Invert the alpha value and apply (1- alpha) for image composition" "Not inverted,Inverted" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform" "AS AND PS,nAS AND PS,AS AND nPS,AS OR PS,nAS OR PS,AS OR nPS,nAS,nPS,AS NAND PS,AS NOR PS,AS XOR PS,AS XNOR PS,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for AS" "ARGB8888,,,,RGB888,,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,?..." textline " " bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled" bitfld.long 0x00 1.--2. " ALPHA_CTRL ,Methods of construction of alpha value" "Embedded,Override,Multiply,ROPs" group.long 0x160++0x03 line.long 0x00 "AS_BUF,Alpha Surface Buffer Pointer" group.long 0x170++0x03 line.long 0x00 "AS_PITCH,Alpha Surface Pitch" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Number of bytes in memory between two vertically adjacent pixels" group.long 0x180++0x03 line.long 0x00 "AS_CLRKEYLOW,Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x190++0x03 line.long 0x00 "AS_CLRKEYHIGH,Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x1A0++0x03 line.long 0x00 "CSC1_COEF0,Color Space Conversion Coefficient Register 0" bitfld.long 0x00 31. " YCBCR_MODE ,Conversion data type" "YUV to RGB,YCbCr to RGB" bitfld.long 0x00 30. " BYPASS ,Bypass the CSC unit in the scaling engine" "Not bypassed,Bypassed" textline " " hexmask.long.word 0x00 18.--28. 1. " C0 ,Two's compliment Y multiplier coefficient" hexmask.long.word 0x00 9.--17. 1. " UV_OFFSET ,Two's compliment phase offset implicit for CbCr data" hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two's compliment amplitude offset implicit in the Y data" group.long 0x1B0++0x03 line.long 0x00 "CSC1_COEF1,Color Space Conversion Coefficient Register 1" hexmask.long.word 0x00 16.--26. 1. " C1 ,Two's compliment Red V/Cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C4 ,Two's compliment Blue U/Cb multiplier coefficient" group.long 0x1C0++0x03 line.long 0x00 "CSC1_COEF2,Color Space Conversion Coefficient Register 2" hexmask.long.word 0x00 16.--26. 1. " C2 ,Two's complement Green V/Cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C3 ,Two's complement Green U/Cb multiplier coefficient" group.long 0x1D0++0x03 line.long 0x00 "CSC2_CTRL,Color Space Conversion Control Register" bitfld.long 0x00 1.--2. " CSC_MODE ,Methods of CSC unit operates on pixels when the CSC is not bypassed (converted from)" "YUV to RGB,YCbCr to RGB,RGB to YUV,RGB to YCbCr" bitfld.long 0x00 0. " BYPASS ,Bypass CSC2 unit" "Not bypassed,Bypassed" group.long 0x1E0++0x03 line.long 0x00 "CSC2_COEF0,Color Space Conversion Coefficient Register 0" hexmask.long.word 0x00 16.--26. 1. " A2 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " A1 ,Two's complement coefficient offset" group.long 0x1F0++0x03 line.long 0x00 "CSC2_COEF1,Color Space Conversion Coefficient Register 1" hexmask.long.word 0x00 16.--26. 1. " B1 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " A3 ,Two's complement coefficient offset" group.long 0x200++0x03 line.long 0x00 "CSC2_COEF2,Color Space Conversion Coefficient Register 2" hexmask.long.word 0x00 16.--26. 1. " B3 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " B2 ,Two's complement coefficient offset" group.long 0x210++0x03 line.long 0x00 "CSC2_COEF3,Color Space Conversion Coefficient Register 3" hexmask.long.word 0x00 16.--26. 1. " C2 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " C1 ,Two's complement coefficient offset" group.long 0x220++0x03 line.long 0x00 "CSC2_COEF4,Color Space Conversion Coefficient Register 4" hexmask.long.word 0x00 16.--24. 1. " D1 ,Two's complement coefficient integer offset to be added" hexmask.long.word 0x00 0.--10. 1. " C3 ,Two's complement coefficient offset" group.long 0x230++0x03 line.long 0x00 "CSC2_COEF5,Color Space Conversion Coefficient Register 5" hexmask.long.word 0x00 16.--24. 1. " D3 ,Two's complement coefficient integer offset to be added" hexmask.long.word 0x00 0.--8. 1. " D2 ,Two's complement D1 coefficient integer offset to be added" textline " " group.long 0x240++0x03 line.long 0x00 "LUT_CTRL,Lookup Table Control Register" bitfld.long 0x00 31. " BYPASS ,bypass the LUT memory resource completely" "Not bypassed,Bypassed" bitfld.long 0x00 24.--25. " LOOKUP_MODE ,Configure the input address for the 16KB" "R[7:3]/G[7:2]/B[7:3],16'b0/Y[7:0],R[7:4]/G[7:4]/B[7:4],R[7:4]/G[7:3]/B[7:4]" bitfld.long 0x00 16.--17. " OUT_MODE ,Select the output mode of operation for the LUT resource" ",Y8,RGBW4444CFA,RGB888" textline " " bitfld.long 0x00 10. " SEL_8KB ,Selects which 8KB bank of memory to use for direct 12bpp lookup modes" "First,Second" bitfld.long 0x00 9. " LRU_UPD ,Block LRU update for hit after miss" "Hit,All hits" bitfld.long 0x00 8. " INVALID ,Invalidate the cache LRU and valid bits" "Invalid,Valid" textline " " bitfld.long 0x00 0. " DMA_START ,Load the PXP LUT memory based on PXP_LUT_ADDR_NUM_BYTES, PXP_LUT_ADDR_ADDR, and PXP_LUT_MEM_ADDR" "Not loaded,Loaded" textline " " group.long 0x250++0x03 line.long 0x00 "LUT_ADDR,Lookup Table Control Register" hexmask.long.word 0x00 16.--30. 1. " NUM_BYTES ,Number of bytes to load via a DMA operation" hexmask.long.word 0x00 0.--13. 1. " ADDR ,LUT indexed address pointer" group.long 0x260++0x03 line.long 0x00 "LUT_DATA,Lookup Table Data Register" group.long 0x270++0x03 line.long 0x00 "LUT_EXTMEM,Lookup Table External Memory Address Register" group.long 0x280++0x03 line.long 0x00 "CFA,Color Filter Array Register" group.long 0x290++0x03 line.long 0x00 "HIST_CTRL,Histogram Control Register" bitfld.long 0x00 4.--5. " PANEL_MODE ,Specifies the EPDC panel grayscale depth" "4-bit,8-bit,16-bit,32-bit" bitfld.long 0x00 3. " STATUS[3] ,Bitmap pixels were fully contained within the 4-bit grayscale histogram" "Not contained,Contained" bitfld.long 0x00 2. " STATUS[2] ,Bitmap pixels were fully contained within the 3-bit grayscale histogram" "Not contained,Contained" textline " " bitfld.long 0x00 1. " STATUS[1] ,Bitmap pixels were fully contained within the 2-bit grayscale histogram" "Not contained,Contained" bitfld.long 0x00 0. " STATUS[0] ,Bitmap pixels were fully contained within the black/white histogram" "Not contained,Contained" group.long 0x2A0++0x03 line.long 0x00 "HIST2_PARAM,2-level Histogram Parameter Register" bitfld.long 0x00 8.--12. " VALUE1 ,White value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE0 ,Black value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2B0++0x03 line.long 0x00 "HIST4_PARAM,4-level Histogram Parameter Register" bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 (White) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2C0++0x03 line.long 0x00 "HIST8_PARAM0,8-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2D0++0x03 line.long 0x00 "HIST8_PARAM1,8-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--28. " VALUE7 ,GRAY7 (White) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE6 ,GRAY6 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE5 ,GRAY5 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " VALUE4 ,GRAY4 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2E0++0x03 line.long 0x00 "HIST16_PARAM0,16-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2F0++0x03 line.long 0x00 "HIST16_PARAM1,16-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--28. " VALUE7 ,GRAY7 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE6 ,GRAY6 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE5 ,GRAY5 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " VALUE4 ,GRAY4 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x300++0x03 line.long 0x00 "HIST16_PARAM2,16-level Histogram Parameter 2 Register" bitfld.long 0x00 24.--28. " VALUE11 ,GRAY11 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE10 ,GRAY10 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE9 ,GRAY9 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " VALUE8 ,GRAY8 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x03 line.long 0x00 "HIST16_PARAM3,16-level Histogram Parameter 3 Register" bitfld.long 0x00 24.--28. " VALUE15 ,GRAY15 (White) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE14 ,GRAY14 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " VALUE13 ,GRAY13 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " VALUE12 ,GRAY12 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " group.long 0x320++0x03 line.long 0x00 "POWER,PXP Power Control Register" hexmask.long.tbyte 0x00 12.--31. 1. " CTRL ,Power control for the PXP" bitfld.long 0x00 9.--11. " ROT_MEM_LP_STATE ,Select the low power state of the ROT memory" "None,Light Sleep,Deep Sleep,,Shut Down,?..." bitfld.long 0x00 6.--8. " LUT_LP_STATE_WAY1_BANKN ,Select the low power state of the LUT's WAY0-BANK0,1,2,3 memory" "None,Light Sleep,Deep Sleep,,Shut Down,?..." textline " " bitfld.long 0x00 3.--5. " LUT_LP_STATE_WAY0_BANKN ,Select the low power state of the LUT's WAY0-BANK1,2,3 memory" "None,Light Sleep,Deep Sleep,,Shut Down,?..." bitfld.long 0x00 0.--2. " LUT_LP_STATE_WAY0_BANK0 ,Select the low power state of the LUT's WAY0-BANK0 memory" "None,Light Sleep,Deep Sleep,,Shut Down,?..." group.long 0x400++0x03 line.long 0x00 "NEXT,Next Frame Pointer" hexmask.long 0x00 2.--31. 0x04 " POINTER ,Pointer to a data structure containing register values to be used when processing the next frame" rbitfld.long 0x00 0. " ENABLED ,Next frame functionality enable (reload operation)" "Disabled,Enabled" width 0x0B tree.end tree "QSPI (Quad Serial Peripheral Interface)" sif (cpu()=="IMX6SOLOX-CA9") tree "QSPI1 Rx Buffer" base ad:0x0C000000 width 7. group.long 0x00++0x7F line.long 0x0 "ARDB0,AHB RX Data Buffer register 0" line.long 0x4 "ARDB1,AHB RX Data Buffer register 1" line.long 0x8 "ARDB2,AHB RX Data Buffer register 2" line.long 0xC "ARDB3,AHB RX Data Buffer register 3" line.long 0x10 "ARDB4,AHB RX Data Buffer register 4" line.long 0x14 "ARDB5,AHB RX Data Buffer register 5" line.long 0x18 "ARDB6,AHB RX Data Buffer register 6" line.long 0x1C "ARDB7,AHB RX Data Buffer register 7" line.long 0x20 "ARDB8,AHB RX Data Buffer register 8" line.long 0x24 "ARDB9,AHB RX Data Buffer register 9" line.long 0x28 "ARDB10,AHB RX Data Buffer register 10" line.long 0x2C "ARDB11,AHB RX Data Buffer register 11" line.long 0x30 "ARDB12,AHB RX Data Buffer register 12" line.long 0x34 "ARDB13,AHB RX Data Buffer register 13" line.long 0x38 "ARDB14,AHB RX Data Buffer register 14" line.long 0x3C "ARDB15,AHB RX Data Buffer register 15" line.long 0x40 "ARDB16,AHB RX Data Buffer register 16" line.long 0x44 "ARDB17,AHB RX Data Buffer register 17" line.long 0x48 "ARDB18,AHB RX Data Buffer register 18" line.long 0x4C "ARDB19,AHB RX Data Buffer register 19" line.long 0x50 "ARDB20,AHB RX Data Buffer register 20" line.long 0x54 "ARDB21,AHB RX Data Buffer register 21" line.long 0x58 "ARDB22,AHB RX Data Buffer register 22" line.long 0x5C "ARDB23,AHB RX Data Buffer register 23" line.long 0x60 "ARDB24,AHB RX Data Buffer register 24" line.long 0x64 "ARDB25,AHB RX Data Buffer register 25" line.long 0x68 "ARDB26,AHB RX Data Buffer register 26" line.long 0x6C "ARDB27,AHB RX Data Buffer register 27" line.long 0x70 "ARDB28,AHB RX Data Buffer register 28" line.long 0x74 "ARDB29,AHB RX Data Buffer register 29" line.long 0x78 "ARDB30,AHB RX Data Buffer register 30" line.long 0x7C "ARDB31,AHB RX Data Buffer register 31" width 0xB tree.end tree "QSPI2 Rx Buffer" base ad:0x0E000000 width 7. group.long 0x00++0x7F line.long 0x0 "ARDB0,AHB RX Data Buffer register 0" line.long 0x4 "ARDB1,AHB RX Data Buffer register 1" line.long 0x8 "ARDB2,AHB RX Data Buffer register 2" line.long 0xC "ARDB3,AHB RX Data Buffer register 3" line.long 0x10 "ARDB4,AHB RX Data Buffer register 4" line.long 0x14 "ARDB5,AHB RX Data Buffer register 5" line.long 0x18 "ARDB6,AHB RX Data Buffer register 6" line.long 0x1C "ARDB7,AHB RX Data Buffer register 7" line.long 0x20 "ARDB8,AHB RX Data Buffer register 8" line.long 0x24 "ARDB9,AHB RX Data Buffer register 9" line.long 0x28 "ARDB10,AHB RX Data Buffer register 10" line.long 0x2C "ARDB11,AHB RX Data Buffer register 11" line.long 0x30 "ARDB12,AHB RX Data Buffer register 12" line.long 0x34 "ARDB13,AHB RX Data Buffer register 13" line.long 0x38 "ARDB14,AHB RX Data Buffer register 14" line.long 0x3C "ARDB15,AHB RX Data Buffer register 15" line.long 0x40 "ARDB16,AHB RX Data Buffer register 16" line.long 0x44 "ARDB17,AHB RX Data Buffer register 17" line.long 0x48 "ARDB18,AHB RX Data Buffer register 18" line.long 0x4C "ARDB19,AHB RX Data Buffer register 19" line.long 0x50 "ARDB20,AHB RX Data Buffer register 20" line.long 0x54 "ARDB21,AHB RX Data Buffer register 21" line.long 0x58 "ARDB22,AHB RX Data Buffer register 22" line.long 0x5C "ARDB23,AHB RX Data Buffer register 23" line.long 0x60 "ARDB24,AHB RX Data Buffer register 24" line.long 0x64 "ARDB25,AHB RX Data Buffer register 25" line.long 0x68 "ARDB26,AHB RX Data Buffer register 26" line.long 0x6C "ARDB27,AHB RX Data Buffer register 27" line.long 0x70 "ARDB28,AHB RX Data Buffer register 28" line.long 0x74 "ARDB29,AHB RX Data Buffer register 29" line.long 0x78 "ARDB30,AHB RX Data Buffer register 30" line.long 0x7C "ARDB31,AHB RX Data Buffer register 31" width 0xB tree.end else tree "QSPI1 Rx Buffer" base ad:0x2C000000 width 7. group.long 0x00++0x7F line.long 0x0 "ARDB0,AHB RX Data Buffer register 0" line.long 0x4 "ARDB1,AHB RX Data Buffer register 1" line.long 0x8 "ARDB2,AHB RX Data Buffer register 2" line.long 0xC "ARDB3,AHB RX Data Buffer register 3" line.long 0x10 "ARDB4,AHB RX Data Buffer register 4" line.long 0x14 "ARDB5,AHB RX Data Buffer register 5" line.long 0x18 "ARDB6,AHB RX Data Buffer register 6" line.long 0x1C "ARDB7,AHB RX Data Buffer register 7" line.long 0x20 "ARDB8,AHB RX Data Buffer register 8" line.long 0x24 "ARDB9,AHB RX Data Buffer register 9" line.long 0x28 "ARDB10,AHB RX Data Buffer register 10" line.long 0x2C "ARDB11,AHB RX Data Buffer register 11" line.long 0x30 "ARDB12,AHB RX Data Buffer register 12" line.long 0x34 "ARDB13,AHB RX Data Buffer register 13" line.long 0x38 "ARDB14,AHB RX Data Buffer register 14" line.long 0x3C "ARDB15,AHB RX Data Buffer register 15" line.long 0x40 "ARDB16,AHB RX Data Buffer register 16" line.long 0x44 "ARDB17,AHB RX Data Buffer register 17" line.long 0x48 "ARDB18,AHB RX Data Buffer register 18" line.long 0x4C "ARDB19,AHB RX Data Buffer register 19" line.long 0x50 "ARDB20,AHB RX Data Buffer register 20" line.long 0x54 "ARDB21,AHB RX Data Buffer register 21" line.long 0x58 "ARDB22,AHB RX Data Buffer register 22" line.long 0x5C "ARDB23,AHB RX Data Buffer register 23" line.long 0x60 "ARDB24,AHB RX Data Buffer register 24" line.long 0x64 "ARDB25,AHB RX Data Buffer register 25" line.long 0x68 "ARDB26,AHB RX Data Buffer register 26" line.long 0x6C "ARDB27,AHB RX Data Buffer register 27" line.long 0x70 "ARDB28,AHB RX Data Buffer register 28" line.long 0x74 "ARDB29,AHB RX Data Buffer register 29" line.long 0x78 "ARDB30,AHB RX Data Buffer register 30" line.long 0x7C "ARDB31,AHB RX Data Buffer register 31" width 0xB tree.end tree "QSPI2 Rx Buffer" base ad:0x2E000000 width 7. group.long 0x00++0x7F line.long 0x0 "ARDB0,AHB RX Data Buffer register 0" line.long 0x4 "ARDB1,AHB RX Data Buffer register 1" line.long 0x8 "ARDB2,AHB RX Data Buffer register 2" line.long 0xC "ARDB3,AHB RX Data Buffer register 3" line.long 0x10 "ARDB4,AHB RX Data Buffer register 4" line.long 0x14 "ARDB5,AHB RX Data Buffer register 5" line.long 0x18 "ARDB6,AHB RX Data Buffer register 6" line.long 0x1C "ARDB7,AHB RX Data Buffer register 7" line.long 0x20 "ARDB8,AHB RX Data Buffer register 8" line.long 0x24 "ARDB9,AHB RX Data Buffer register 9" line.long 0x28 "ARDB10,AHB RX Data Buffer register 10" line.long 0x2C "ARDB11,AHB RX Data Buffer register 11" line.long 0x30 "ARDB12,AHB RX Data Buffer register 12" line.long 0x34 "ARDB13,AHB RX Data Buffer register 13" line.long 0x38 "ARDB14,AHB RX Data Buffer register 14" line.long 0x3C "ARDB15,AHB RX Data Buffer register 15" line.long 0x40 "ARDB16,AHB RX Data Buffer register 16" line.long 0x44 "ARDB17,AHB RX Data Buffer register 17" line.long 0x48 "ARDB18,AHB RX Data Buffer register 18" line.long 0x4C "ARDB19,AHB RX Data Buffer register 19" line.long 0x50 "ARDB20,AHB RX Data Buffer register 20" line.long 0x54 "ARDB21,AHB RX Data Buffer register 21" line.long 0x58 "ARDB22,AHB RX Data Buffer register 22" line.long 0x5C "ARDB23,AHB RX Data Buffer register 23" line.long 0x60 "ARDB24,AHB RX Data Buffer register 24" line.long 0x64 "ARDB25,AHB RX Data Buffer register 25" line.long 0x68 "ARDB26,AHB RX Data Buffer register 26" line.long 0x6C "ARDB27,AHB RX Data Buffer register 27" line.long 0x70 "ARDB28,AHB RX Data Buffer register 28" line.long 0x74 "ARDB29,AHB RX Data Buffer register 29" line.long 0x78 "ARDB30,AHB RX Data Buffer register 30" line.long 0x7C "ARDB31,AHB RX Data Buffer register 31" width 0xB tree.end endif tree "Peripheral Bus Register" tree "QSPI 1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021E0000 else base ad:0x421E0000 endif width 9. group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " DQS_PHASE_EN ,Control of internal DQS output phase" "Disabled,Enabled" bitfld.long 0x00 29. " TX_DDR_DELAY_EN ,TX data delay" "Disabled,Enabled" bitfld.long 0x00 24. " DQS_LOOPBACK_EN ,DQS loopback sampling" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" textline " " bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/Buffer" "No effect,Cleared" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/Buffer" "No effect,Cleared" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "0,1,2,3" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for Serial Flash domain" "No reset,Reset" group.long 0x08++0x1B line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" line.long 0x04 "FLSHCR,Flash Configuration Register" bitfld.long 0x04 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x08 31. " HP_EN ,High Priority Enable" "Disabled,Enabled" hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF1CR,Buffer1 Configuration Register" hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BUF2CR,Buffer2 Configuration Register" hexmask.long.byte 0x10 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x10 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "BUF3CR,Buffer0 Configuration Register" bitfld.long 0x14 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x14 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x14 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "BFGENCR,Buffer0 Configuration Register" bitfld.long 0x18 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x18 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" group.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" group.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR Sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--6. " SDRSMP ,SDR sampling point" "0,1,2,3" rgroup.long 0x10C++0x03 line.long 0x00 "RBSR,RX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " RDCTR ,Indicates how many entries of 4 bytes have been removed from the RX Buffer" bitfld.long 0x00 8.--13. " RDBFL ,Indicates how many entries of 4 bytes are still available in the RX Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX Buffer readout" "AHB Bus,IP Bus" bitfld.long 0x00 0.--4. " WMRK ,Field determines when the readout action of the RX Buffer is triggered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x150++0x03 line.long 0x00 "TBSR,TX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " TRCTR ,field indicates how many entries of 4 bytes have been written into the TX Buffer by host accesses" bitfld.long 0x00 8.--12. " TRBFL ,Number of entries of 4 bytes each available in the TX Buffer for the QuadSPI module to transmit to the serial flash device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" rgroup.long 0x15C++0x03 line.long 0x00 "SR,Status register" bitfld.long 0x00 29.--31. " DLPSMP ,Data learning pattern sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " TXFULL ,TX Buffer Full" "Not full,Full" bitfld.long 0x00 24. " TXEDA ,Tx Buffer Enough Data Available" "Not available,Available" bitfld.long 0x00 23. " RXDMA ,RX Buffer read out via DMA" "Not active,Active" textline " " bitfld.long 0x00 19. " RXFULL ,RX Buffer Full" "Not full,Full" bitfld.long 0x00 16. " RXWE ,RX Buffer Watermark Exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 14. " AHB3FUL ,AHB 3 Buffer Full" "Not full,Full" bitfld.long 0x00 13. " AHB2FUL ,AHB 2 Buffer Full" "Not full,Full" textline " " bitfld.long 0x00 12. " AHB1FUL ,AHB 1 Buffer Full" "Not full,Full" bitfld.long 0x00 11. " AHB0FUL ,AHB 0 Buffer Full" "Not full,Full" bitfld.long 0x00 10. " AHB3NE ,AHB 3 Buffer Not Empty" "Empty,Not empty" bitfld.long 0x00 9. " AHB2NE ,AHB 2 Buffer Not Empty" "Empty,Not empty" textline " " bitfld.long 0x00 8. " AHB1NE ,AHB 1 Buffer Not Empty" "Empty,Not empty" bitfld.long 0x00 7. " AHB0NE ,AHB 0 Buffer Not Empty" "Empty,Not empty" bitfld.long 0x00 6. " AHBTRN ,AHB Access Transaction pending" "Not pending,Pending" bitfld.long 0x00 5. " AHBGNT ,AHB Command priority Granted" "Not granted,Granted" textline " " bitfld.long 0x00 2. " AHB_ACC ,AHB Access" "Not AHB initiated,AHB initiated" bitfld.long 0x00 1. " IP_ACC ,IP Access" "Not IP bus initiated,IP bus initiated" bitfld.long 0x00 0. " BUSY ,Indicates whether module is currently busy handling a transaction to an external flash device" "Not busy,Busy" group.long 0x160++0x07 line.long 0x00 "FR,Flag register" eventfld.long 0x00 31. " DLPFF ,Data Learning Pattern Failure" "Not occurred,Occurred" eventfld.long 0x00 27. " TBFF ,TX Buffer fulfilment" "Full,Not full" eventfld.long 0x00 26. " TBUF ,TX Buffer underrun" "Not occurred,Occurred" eventfld.long 0x00 23. " ILLINE ,Illegal Instruction Error" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " RBOF ,RX Buffer Overflow" "Not occurred,Occurred" eventfld.long 0x00 16. " RBDF ,RX Buffer Drain" "Not occurred,Occurred" eventfld.long 0x00 15. " ABSEF ,AHB Sequence Error" "Not occurred,Occurred" eventfld.long 0x00 12. " ABOF ,AHB Buffer Overflow" "Not occurred,Occurred" textline " " eventfld.long 0x00 11. " IUEF ,IP Command Usage Error" "Not occurred,Occurred" eventfld.long 0x00 7. " IPAEF ,IP Command Trigger during AHB Access Error" "Not occurred,Occurred" eventfld.long 0x00 6. " IPIEF ,IP Command Trigger could not be executed" "Not occurred,Occurred" eventfld.long 0x00 4. " IPGEF ,IP Command Trigger during AHB Grant" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " TFF ,IP Command Transaction Finished" "Not occurred,Occurred" line.long 0x04 "RSER,Interrupt and DMA Request Select and Enable Register" bitfld.long 0x04 31. " DLPFIE ,Data Learning Pattern Failure Interrupt enable" "Disabled,Enabled" bitfld.long 0x04 27. " TBFIE ,TX Buffer Fill Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 26. " TBUIE ,TX Buffer Underrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 23. " ILLINIE ,Illegal Instruction Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " RBDDE ,RX Buffer Drain DMA Enable" "Disabled,Enabled" bitfld.long 0x04 17. " RBOIE ,RX Buffer Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 16. " RBDIE ,RX Buffer Drain Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 15. " ABSEIE ,AHB Sequence Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " ABOIE ,AHB Buffer Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 11. " IUEIE ,AIP Command Usage Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 7. " IPAEIE ,IP Command Trigger during AHB Access Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 6. " IPIEIE ,IP Command Trigger during IP Access Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " IPGEIE ,IP Command Trigger during AHB Grant Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " TFIE ,Transaction Finished Interrupt Enable" "Disabled,Enabled" rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" hexmask.long.byte 0x00 9.--15. 1. " DATLFT ,Data left" bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer number" "0,1,2,3" bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Disabled,Enabled" group.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP Pointer Clear" "No effect,Cleared" bitfld.long 0x00 0. " BFPTRC ,Buffer Pointer Clear" "No effect,Cleared" group.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long 0x00 10.--31. 0x400 " TPADA1 ,Top address for Serial Flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long 0x04 10.--31. 0x400 " TPADA2 ,Top address for Serial Flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long 0x08 10.--31. 0x400 " TPADB1 ,Top address for Serial Flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long 0x0C 10.--31. 0x400 " TPADB2 ,Top address for Serial Flash B2" group.long 0x200++0x7F line.long 0x0 "RBDR0,RX Buffer Data Register 0" line.long 0x4 "RBDR1,RX Buffer Data Register 1" line.long 0x8 "RBDR2,RX Buffer Data Register 2" line.long 0xC "RBDR3,RX Buffer Data Register 3" line.long 0x10 "RBDR4,RX Buffer Data Register 4" line.long 0x14 "RBDR5,RX Buffer Data Register 5" line.long 0x18 "RBDR6,RX Buffer Data Register 6" line.long 0x1C "RBDR7,RX Buffer Data Register 7" line.long 0x20 "RBDR8,RX Buffer Data Register 8" line.long 0x24 "RBDR9,RX Buffer Data Register 9" line.long 0x28 "RBDR10,RX Buffer Data Register 10" line.long 0x2C "RBDR11,RX Buffer Data Register 11" line.long 0x30 "RBDR12,RX Buffer Data Register 12" line.long 0x34 "RBDR13,RX Buffer Data Register 13" line.long 0x38 "RBDR14,RX Buffer Data Register 14" line.long 0x3C "RBDR15,RX Buffer Data Register 15" line.long 0x40 "RBDR16,RX Buffer Data Register 16" line.long 0x44 "RBDR17,RX Buffer Data Register 17" line.long 0x48 "RBDR18,RX Buffer Data Register 18" line.long 0x4C "RBDR19,RX Buffer Data Register 19" line.long 0x50 "RBDR20,RX Buffer Data Register 20" line.long 0x54 "RBDR21,RX Buffer Data Register 21" line.long 0x58 "RBDR22,RX Buffer Data Register 22" line.long 0x5C "RBDR23,RX Buffer Data Register 23" line.long 0x60 "RBDR24,RX Buffer Data Register 24" line.long 0x64 "RBDR25,RX Buffer Data Register 25" line.long 0x68 "RBDR26,RX Buffer Data Register 26" line.long 0x6C "RBDR27,RX Buffer Data Register 27" line.long 0x70 "RBDR28,RX Buffer Data Register 28" line.long 0x74 "RBDR29,RX Buffer Data Register 29" line.long 0x78 "RBDR30,RX Buffer Data Register 30" line.long 0x7C "RBDR31,RX Buffer Data Register 31" group.long 0x300++0x07 line.long 0x00 "LUTKEY,LUT Key Register" line.long 0x04 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x04 1. " UNLOCK ,LUT unlock" "Locked,Unlocked" bitfld.long 0x04 0. " LOCK ,LUT lock" "Unlocked,Locked" tree "Look-up Tables" group.long 0x310++0x0FF line.long 0x0 "LUT0,Look-up Table register 0" bitfld.long 0x0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x4 "LUT1,Look-up Table register 1" bitfld.long 0x4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x8 "LUT2,Look-up Table register 2" bitfld.long 0x8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xC "LUT3,Look-up Table register 3" bitfld.long 0xC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x10 "LUT4,Look-up Table register 4" bitfld.long 0x10 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x10 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x10 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x10 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x14 "LUT5,Look-up Table register 5" bitfld.long 0x14 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x14 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x14 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x14 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x18 "LUT6,Look-up Table register 6" bitfld.long 0x18 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x18 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x18 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x18 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x1C "LUT7,Look-up Table register 7" bitfld.long 0x1C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x1C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x1C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x1C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x20 "LUT8,Look-up Table register 8" bitfld.long 0x20 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x20 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x20 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x20 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x24 "LUT9,Look-up Table register 9" bitfld.long 0x24 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x24 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x24 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x24 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x28 "LUT10,Look-up Table register 10" bitfld.long 0x28 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x28 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x28 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x28 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x2C "LUT11,Look-up Table register 11" bitfld.long 0x2C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x2C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x2C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x2C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x30 "LUT12,Look-up Table register 12" bitfld.long 0x30 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x30 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x30 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x30 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x34 "LUT13,Look-up Table register 13" bitfld.long 0x34 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x34 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x34 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x34 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x38 "LUT14,Look-up Table register 14" bitfld.long 0x38 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x38 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x38 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x38 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x3C "LUT15,Look-up Table register 15" bitfld.long 0x3C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x3C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x3C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x3C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x40 "LUT16,Look-up Table register 16" bitfld.long 0x40 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x40 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x40 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x40 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x44 "LUT17,Look-up Table register 17" bitfld.long 0x44 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x44 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x44 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x44 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x44 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x44 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x48 "LUT18,Look-up Table register 18" bitfld.long 0x48 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x48 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x48 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x48 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x48 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x48 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x4C "LUT19,Look-up Table register 19" bitfld.long 0x4C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x4C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x4C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x4C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x50 "LUT20,Look-up Table register 20" bitfld.long 0x50 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x50 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x50 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x50 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x50 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x50 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x54 "LUT21,Look-up Table register 21" bitfld.long 0x54 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x54 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x54 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x54 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x54 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x54 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x58 "LUT22,Look-up Table register 22" bitfld.long 0x58 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x58 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x58 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x58 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x58 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x58 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x5C "LUT23,Look-up Table register 23" bitfld.long 0x5C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x5C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x5C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x5C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x60 "LUT24,Look-up Table register 24" bitfld.long 0x60 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x60 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x60 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x60 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x60 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x60 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x64 "LUT25,Look-up Table register 25" bitfld.long 0x64 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x64 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x64 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x64 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x68 "LUT26,Look-up Table register 26" bitfld.long 0x68 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x68 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x68 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x68 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x68 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x68 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x6C "LUT27,Look-up Table register 27" bitfld.long 0x6C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x6C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x6C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x6C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x70 "LUT28,Look-up Table register 28" bitfld.long 0x70 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x70 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x70 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x70 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x70 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x70 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x74 "LUT29,Look-up Table register 29" bitfld.long 0x74 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x74 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x74 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x74 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x74 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x74 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x78 "LUT30,Look-up Table register 30" bitfld.long 0x78 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x78 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x78 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x78 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x78 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x78 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x7C "LUT31,Look-up Table register 31" bitfld.long 0x7C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x7C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x7C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x7C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x80 "LUT32,Look-up Table register 32" bitfld.long 0x80 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x80 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x80 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x80 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x80 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x80 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x84 "LUT33,Look-up Table register 33" bitfld.long 0x84 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x84 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x84 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x84 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x84 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x84 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x88 "LUT34,Look-up Table register 34" bitfld.long 0x88 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x88 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x88 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x88 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x88 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x88 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x8C "LUT35,Look-up Table register 35" bitfld.long 0x8C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x8C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x8C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x8C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x90 "LUT36,Look-up Table register 36" bitfld.long 0x90 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x90 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x90 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x90 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x90 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x90 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x94 "LUT37,Look-up Table register 37" bitfld.long 0x94 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x94 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x94 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x94 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x94 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x94 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x98 "LUT38,Look-up Table register 38" bitfld.long 0x98 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x98 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x98 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x98 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x98 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x98 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x9C "LUT39,Look-up Table register 39" bitfld.long 0x9C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x9C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x9C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x9C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xA0 "LUT40,Look-up Table register 40" bitfld.long 0xA0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xA0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xA0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xA0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xA4 "LUT41,Look-up Table register 41" bitfld.long 0xA4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xA4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xA4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xA4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xA8 "LUT42,Look-up Table register 42" bitfld.long 0xA8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xA8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xA8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xA8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xAC "LUT43,Look-up Table register 43" bitfld.long 0xAC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xAC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xAC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xAC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xB0 "LUT44,Look-up Table register 44" bitfld.long 0xB0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xB0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xB0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xB0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xB4 "LUT45,Look-up Table register 45" bitfld.long 0xB4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xB4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xB4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xB4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xB8 "LUT46,Look-up Table register 46" bitfld.long 0xB8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xB8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xB8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xB8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xBC "LUT47,Look-up Table register 47" bitfld.long 0xBC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xBC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xBC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xBC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xC0 "LUT48,Look-up Table register 48" bitfld.long 0xC0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xC0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xC0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xC0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xC4 "LUT49,Look-up Table register 49" bitfld.long 0xC4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xC4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xC4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xC4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xC8 "LUT50,Look-up Table register 50" bitfld.long 0xC8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xC8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xC8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xC8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xCC "LUT51,Look-up Table register 51" bitfld.long 0xCC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xCC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xCC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xCC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xD0 "LUT52,Look-up Table register 52" bitfld.long 0xD0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xD0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xD0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xD0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xD4 "LUT53,Look-up Table register 53" bitfld.long 0xD4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xD4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xD4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xD4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xD8 "LUT54,Look-up Table register 54" bitfld.long 0xD8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xD8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xD8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xD8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xDC "LUT55,Look-up Table register 55" bitfld.long 0xDC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xDC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xDC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xDC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xDC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xDC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xE0 "LUT56,Look-up Table register 56" bitfld.long 0xE0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xE0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xE0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xE0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xE4 "LUT57,Look-up Table register 57" bitfld.long 0xE4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xE4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xE4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xE4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xE8 "LUT58,Look-up Table register 58" bitfld.long 0xE8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xE8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xE8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xE8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xEC "LUT59,Look-up Table register 59" bitfld.long 0xEC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xEC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xEC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xEC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xEC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xEC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xF0 "LUT60,Look-up Table register 60" bitfld.long 0xF0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xF0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xF0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xF0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xF4 "LUT61,Look-up Table register 61" bitfld.long 0xF4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xF4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xF4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xF4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xF8 "LUT62,Look-up Table register 62" bitfld.long 0xF8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xF8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xF8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xF8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xFC "LUT63,Look-up Table register 63" bitfld.long 0xFC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xFC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xFC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xFC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xFC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xFC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" tree.end width 12. tree.end tree "QSPI 2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021E4000 else base ad:0x421E4000 endif width 9. group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " DQS_PHASE_EN ,Control of internal DQS output phase" "Disabled,Enabled" bitfld.long 0x00 29. " TX_DDR_DELAY_EN ,TX data delay" "Disabled,Enabled" bitfld.long 0x00 24. " DQS_LOOPBACK_EN ,DQS loopback sampling" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" textline " " bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/Buffer" "No effect,Cleared" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/Buffer" "No effect,Cleared" bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "0,1,2,3" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for Serial Flash domain" "No reset,Reset" group.long 0x08++0x1B line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" line.long 0x04 "FLSHCR,Flash Configuration Register" bitfld.long 0x04 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x08 31. " HP_EN ,High Priority Enable" "Disabled,Enabled" hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF1CR,Buffer1 Configuration Register" hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BUF2CR,Buffer2 Configuration Register" hexmask.long.byte 0x10 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x10 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "BUF3CR,Buffer0 Configuration Register" bitfld.long 0x14 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x14 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x14 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "BFGENCR,Buffer0 Configuration Register" bitfld.long 0x18 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x18 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" group.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" group.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR Sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--6. " SDRSMP ,SDR sampling point" "0,1,2,3" rgroup.long 0x10C++0x03 line.long 0x00 "RBSR,RX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " RDCTR ,Indicates how many entries of 4 bytes have been removed from the RX Buffer" bitfld.long 0x00 8.--13. " RDBFL ,Indicates how many entries of 4 bytes are still available in the RX Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX Buffer readout" "AHB Bus,IP Bus" bitfld.long 0x00 0.--4. " WMRK ,Field determines when the readout action of the RX Buffer is triggered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x150++0x03 line.long 0x00 "TBSR,TX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " TRCTR ,field indicates how many entries of 4 bytes have been written into the TX Buffer by host accesses" bitfld.long 0x00 8.--12. " TRBFL ,Number of entries of 4 bytes each available in the TX Buffer for the QuadSPI module to transmit to the serial flash device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" rgroup.long 0x15C++0x03 line.long 0x00 "SR,Status register" bitfld.long 0x00 29.--31. " DLPSMP ,Data learning pattern sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " TXFULL ,TX Buffer Full" "Not full,Full" bitfld.long 0x00 24. " TXEDA ,Tx Buffer Enough Data Available" "Not available,Available" bitfld.long 0x00 23. " RXDMA ,RX Buffer read out via DMA" "Not active,Active" textline " " bitfld.long 0x00 19. " RXFULL ,RX Buffer Full" "Not full,Full" bitfld.long 0x00 16. " RXWE ,RX Buffer Watermark Exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 14. " AHB3FUL ,AHB 3 Buffer Full" "Not full,Full" bitfld.long 0x00 13. " AHB2FUL ,AHB 2 Buffer Full" "Not full,Full" textline " " bitfld.long 0x00 12. " AHB1FUL ,AHB 1 Buffer Full" "Not full,Full" bitfld.long 0x00 11. " AHB0FUL ,AHB 0 Buffer Full" "Not full,Full" bitfld.long 0x00 10. " AHB3NE ,AHB 3 Buffer Not Empty" "Empty,Not empty" bitfld.long 0x00 9. " AHB2NE ,AHB 2 Buffer Not Empty" "Empty,Not empty" textline " " bitfld.long 0x00 8. " AHB1NE ,AHB 1 Buffer Not Empty" "Empty,Not empty" bitfld.long 0x00 7. " AHB0NE ,AHB 0 Buffer Not Empty" "Empty,Not empty" bitfld.long 0x00 6. " AHBTRN ,AHB Access Transaction pending" "Not pending,Pending" bitfld.long 0x00 5. " AHBGNT ,AHB Command priority Granted" "Not granted,Granted" textline " " bitfld.long 0x00 2. " AHB_ACC ,AHB Access" "Not AHB initiated,AHB initiated" bitfld.long 0x00 1. " IP_ACC ,IP Access" "Not IP bus initiated,IP bus initiated" bitfld.long 0x00 0. " BUSY ,Indicates whether module is currently busy handling a transaction to an external flash device" "Not busy,Busy" group.long 0x160++0x07 line.long 0x00 "FR,Flag register" eventfld.long 0x00 31. " DLPFF ,Data Learning Pattern Failure" "Not occurred,Occurred" eventfld.long 0x00 27. " TBFF ,TX Buffer fulfilment" "Full,Not full" eventfld.long 0x00 26. " TBUF ,TX Buffer underrun" "Not occurred,Occurred" eventfld.long 0x00 23. " ILLINE ,Illegal Instruction Error" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " RBOF ,RX Buffer Overflow" "Not occurred,Occurred" eventfld.long 0x00 16. " RBDF ,RX Buffer Drain" "Not occurred,Occurred" eventfld.long 0x00 15. " ABSEF ,AHB Sequence Error" "Not occurred,Occurred" eventfld.long 0x00 12. " ABOF ,AHB Buffer Overflow" "Not occurred,Occurred" textline " " eventfld.long 0x00 11. " IUEF ,IP Command Usage Error" "Not occurred,Occurred" eventfld.long 0x00 7. " IPAEF ,IP Command Trigger during AHB Access Error" "Not occurred,Occurred" eventfld.long 0x00 6. " IPIEF ,IP Command Trigger could not be executed" "Not occurred,Occurred" eventfld.long 0x00 4. " IPGEF ,IP Command Trigger during AHB Grant" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " TFF ,IP Command Transaction Finished" "Not occurred,Occurred" line.long 0x04 "RSER,Interrupt and DMA Request Select and Enable Register" bitfld.long 0x04 31. " DLPFIE ,Data Learning Pattern Failure Interrupt enable" "Disabled,Enabled" bitfld.long 0x04 27. " TBFIE ,TX Buffer Fill Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 26. " TBUIE ,TX Buffer Underrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 23. " ILLINIE ,Illegal Instruction Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " RBDDE ,RX Buffer Drain DMA Enable" "Disabled,Enabled" bitfld.long 0x04 17. " RBOIE ,RX Buffer Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 16. " RBDIE ,RX Buffer Drain Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 15. " ABSEIE ,AHB Sequence Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " ABOIE ,AHB Buffer Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 11. " IUEIE ,AIP Command Usage Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 7. " IPAEIE ,IP Command Trigger during AHB Access Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 6. " IPIEIE ,IP Command Trigger during IP Access Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " IPGEIE ,IP Command Trigger during AHB Grant Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " TFIE ,Transaction Finished Interrupt Enable" "Disabled,Enabled" rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" hexmask.long.byte 0x00 9.--15. 1. " DATLFT ,Data left" bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer number" "0,1,2,3" bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Disabled,Enabled" group.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP Pointer Clear" "No effect,Cleared" bitfld.long 0x00 0. " BFPTRC ,Buffer Pointer Clear" "No effect,Cleared" group.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long 0x00 10.--31. 0x400 " TPADA1 ,Top address for Serial Flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long 0x04 10.--31. 0x400 " TPADA2 ,Top address for Serial Flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long 0x08 10.--31. 0x400 " TPADB1 ,Top address for Serial Flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long 0x0C 10.--31. 0x400 " TPADB2 ,Top address for Serial Flash B2" group.long 0x200++0x7F line.long 0x0 "RBDR0,RX Buffer Data Register 0" line.long 0x4 "RBDR1,RX Buffer Data Register 1" line.long 0x8 "RBDR2,RX Buffer Data Register 2" line.long 0xC "RBDR3,RX Buffer Data Register 3" line.long 0x10 "RBDR4,RX Buffer Data Register 4" line.long 0x14 "RBDR5,RX Buffer Data Register 5" line.long 0x18 "RBDR6,RX Buffer Data Register 6" line.long 0x1C "RBDR7,RX Buffer Data Register 7" line.long 0x20 "RBDR8,RX Buffer Data Register 8" line.long 0x24 "RBDR9,RX Buffer Data Register 9" line.long 0x28 "RBDR10,RX Buffer Data Register 10" line.long 0x2C "RBDR11,RX Buffer Data Register 11" line.long 0x30 "RBDR12,RX Buffer Data Register 12" line.long 0x34 "RBDR13,RX Buffer Data Register 13" line.long 0x38 "RBDR14,RX Buffer Data Register 14" line.long 0x3C "RBDR15,RX Buffer Data Register 15" line.long 0x40 "RBDR16,RX Buffer Data Register 16" line.long 0x44 "RBDR17,RX Buffer Data Register 17" line.long 0x48 "RBDR18,RX Buffer Data Register 18" line.long 0x4C "RBDR19,RX Buffer Data Register 19" line.long 0x50 "RBDR20,RX Buffer Data Register 20" line.long 0x54 "RBDR21,RX Buffer Data Register 21" line.long 0x58 "RBDR22,RX Buffer Data Register 22" line.long 0x5C "RBDR23,RX Buffer Data Register 23" line.long 0x60 "RBDR24,RX Buffer Data Register 24" line.long 0x64 "RBDR25,RX Buffer Data Register 25" line.long 0x68 "RBDR26,RX Buffer Data Register 26" line.long 0x6C "RBDR27,RX Buffer Data Register 27" line.long 0x70 "RBDR28,RX Buffer Data Register 28" line.long 0x74 "RBDR29,RX Buffer Data Register 29" line.long 0x78 "RBDR30,RX Buffer Data Register 30" line.long 0x7C "RBDR31,RX Buffer Data Register 31" group.long 0x300++0x07 line.long 0x00 "LUTKEY,LUT Key Register" line.long 0x04 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x04 1. " UNLOCK ,LUT unlock" "Locked,Unlocked" bitfld.long 0x04 0. " LOCK ,LUT lock" "Unlocked,Locked" tree "Look-up Tables" group.long 0x310++0x0FF line.long 0x0 "LUT0,Look-up Table register 0" bitfld.long 0x0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x4 "LUT1,Look-up Table register 1" bitfld.long 0x4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x8 "LUT2,Look-up Table register 2" bitfld.long 0x8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xC "LUT3,Look-up Table register 3" bitfld.long 0xC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x10 "LUT4,Look-up Table register 4" bitfld.long 0x10 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x10 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x10 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x10 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x14 "LUT5,Look-up Table register 5" bitfld.long 0x14 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x14 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x14 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x14 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x18 "LUT6,Look-up Table register 6" bitfld.long 0x18 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x18 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x18 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x18 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x1C "LUT7,Look-up Table register 7" bitfld.long 0x1C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x1C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x1C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x1C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x20 "LUT8,Look-up Table register 8" bitfld.long 0x20 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x20 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x20 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x20 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x24 "LUT9,Look-up Table register 9" bitfld.long 0x24 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x24 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x24 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x24 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x28 "LUT10,Look-up Table register 10" bitfld.long 0x28 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x28 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x28 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x28 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x2C "LUT11,Look-up Table register 11" bitfld.long 0x2C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x2C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x2C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x2C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x30 "LUT12,Look-up Table register 12" bitfld.long 0x30 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x30 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x30 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x30 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x34 "LUT13,Look-up Table register 13" bitfld.long 0x34 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x34 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x34 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x34 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x38 "LUT14,Look-up Table register 14" bitfld.long 0x38 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x38 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x38 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x38 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x3C "LUT15,Look-up Table register 15" bitfld.long 0x3C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x3C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x3C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x3C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x40 "LUT16,Look-up Table register 16" bitfld.long 0x40 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x40 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x40 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x40 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x44 "LUT17,Look-up Table register 17" bitfld.long 0x44 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x44 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x44 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x44 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x44 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x44 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x48 "LUT18,Look-up Table register 18" bitfld.long 0x48 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x48 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x48 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x48 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x48 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x48 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x4C "LUT19,Look-up Table register 19" bitfld.long 0x4C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x4C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x4C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x4C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x50 "LUT20,Look-up Table register 20" bitfld.long 0x50 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x50 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x50 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x50 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x50 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x50 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x54 "LUT21,Look-up Table register 21" bitfld.long 0x54 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x54 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x54 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x54 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x54 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x54 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x58 "LUT22,Look-up Table register 22" bitfld.long 0x58 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x58 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x58 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x58 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x58 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x58 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x5C "LUT23,Look-up Table register 23" bitfld.long 0x5C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x5C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x5C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x5C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x60 "LUT24,Look-up Table register 24" bitfld.long 0x60 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x60 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x60 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x60 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x60 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x60 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x64 "LUT25,Look-up Table register 25" bitfld.long 0x64 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x64 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x64 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x64 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x68 "LUT26,Look-up Table register 26" bitfld.long 0x68 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x68 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x68 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x68 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x68 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x68 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x6C "LUT27,Look-up Table register 27" bitfld.long 0x6C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x6C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x6C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x6C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x70 "LUT28,Look-up Table register 28" bitfld.long 0x70 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x70 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x70 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x70 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x70 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x70 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x74 "LUT29,Look-up Table register 29" bitfld.long 0x74 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x74 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x74 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x74 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x74 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x74 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x78 "LUT30,Look-up Table register 30" bitfld.long 0x78 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x78 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x78 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x78 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x78 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x78 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x7C "LUT31,Look-up Table register 31" bitfld.long 0x7C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x7C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x7C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x7C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x80 "LUT32,Look-up Table register 32" bitfld.long 0x80 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x80 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x80 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x80 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x80 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x80 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x84 "LUT33,Look-up Table register 33" bitfld.long 0x84 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x84 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x84 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x84 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x84 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x84 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x88 "LUT34,Look-up Table register 34" bitfld.long 0x88 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x88 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x88 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x88 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x88 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x88 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x8C "LUT35,Look-up Table register 35" bitfld.long 0x8C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x8C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x8C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x8C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x90 "LUT36,Look-up Table register 36" bitfld.long 0x90 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x90 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x90 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x90 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x90 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x90 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x94 "LUT37,Look-up Table register 37" bitfld.long 0x94 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x94 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x94 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x94 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x94 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x94 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x98 "LUT38,Look-up Table register 38" bitfld.long 0x98 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x98 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x98 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x98 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x98 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x98 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0x9C "LUT39,Look-up Table register 39" bitfld.long 0x9C 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9C 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0x9C 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0x9C 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9C 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0x9C 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xA0 "LUT40,Look-up Table register 40" bitfld.long 0xA0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xA0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xA0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xA0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xA4 "LUT41,Look-up Table register 41" bitfld.long 0xA4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xA4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xA4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xA4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xA8 "LUT42,Look-up Table register 42" bitfld.long 0xA8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xA8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xA8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xA8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xAC "LUT43,Look-up Table register 43" bitfld.long 0xAC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xAC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xAC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xAC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xB0 "LUT44,Look-up Table register 44" bitfld.long 0xB0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xB0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xB0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xB0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xB4 "LUT45,Look-up Table register 45" bitfld.long 0xB4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xB4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xB4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xB4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xB8 "LUT46,Look-up Table register 46" bitfld.long 0xB8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xB8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xB8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xB8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xBC "LUT47,Look-up Table register 47" bitfld.long 0xBC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xBC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xBC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xBC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xC0 "LUT48,Look-up Table register 48" bitfld.long 0xC0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xC0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xC0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xC0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xC4 "LUT49,Look-up Table register 49" bitfld.long 0xC4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xC4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xC4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xC4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xC8 "LUT50,Look-up Table register 50" bitfld.long 0xC8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xC8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xC8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xC8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xCC "LUT51,Look-up Table register 51" bitfld.long 0xCC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xCC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xCC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xCC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xD0 "LUT52,Look-up Table register 52" bitfld.long 0xD0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xD0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xD0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xD0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xD4 "LUT53,Look-up Table register 53" bitfld.long 0xD4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xD4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xD4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xD4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xD8 "LUT54,Look-up Table register 54" bitfld.long 0xD8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xD8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xD8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xD8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xDC "LUT55,Look-up Table register 55" bitfld.long 0xDC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xDC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xDC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xDC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xDC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xDC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xE0 "LUT56,Look-up Table register 56" bitfld.long 0xE0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xE0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xE0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xE0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xE4 "LUT57,Look-up Table register 57" bitfld.long 0xE4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xE4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xE4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xE4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xE8 "LUT58,Look-up Table register 58" bitfld.long 0xE8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xE8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xE8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xE8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xEC "LUT59,Look-up Table register 59" bitfld.long 0xEC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xEC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xEC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xEC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xEC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xEC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xF0 "LUT60,Look-up Table register 60" bitfld.long 0xF0 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF0 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xF0 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xF0 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF0 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xF0 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xF4 "LUT61,Look-up Table register 61" bitfld.long 0xF4 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF4 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xF4 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xF4 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF4 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xF4 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xF8 "LUT62,Look-up Table register 62" bitfld.long 0xF8 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF8 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xF8 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xF8 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF8 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xF8 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" line.long 0xFC "LUT63,Look-up Table register 63" bitfld.long 0xFC 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xFC 24.--25. " PAD1 ,Pad information for INSTR1" "1,2,4," hexmask.long.byte 0xFC 16.--23. 0x01 " OPRND1 ,Operand for INSTR1" textline " " bitfld.long 0xFC 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xFC 8.--9. " PAD0 ,Pad information for INSTR0" "1,2,4," hexmask.long.byte 0xFC 0.--7. 0x01 " OPRND0 ,Operand for INSTR0" tree.end width 12. tree.end tree.end tree.end tree "RDC (Resource Domain Controller)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020FC000 else base ad:0x420FC000 endif width 10. rgroup.long 0x00++0x03 line.long 0x00 "VIR,Version information" hexmask.long.byte 0x00 20.--27. 1. " NRGN ,Number of memory regions in this instance of the RDC" hexmask.long.byte 0x00 12.--19. 1. " NPER ,Number of peripherals that can be isolated or safe-shared" hexmask.long.byte 0x00 4.--11. 1. " NPER ,Indicates the number of masters supported by this instance of RDC" bitfld.long 0x00 0.--3. " NDID ,Number of Domains" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x0B line.long 0x00 "STAT,Status register" bitfld.long 0x00 8. " PDS ,Power Domain Status" "Off,On" bitfld.long 0x00 0.--3. " DID ,Domain ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "INTCTRL,Interrupt and Control register" bitfld.long 0x04 0. " RCI_EN ,Restoration Complete Interrupt" "Disabled,Enabled" line.long 0x08 "INTSTAT,Interrupt Status" eventfld.long 0x08 0. " INT ,State of interrupt signal for state restoration" "No interrupt,Interrupt" group.long 0x200++0x7F line.long 0x0 "MDA0,Master Domain Assignment Register 0x0" bitfld.long 0x0 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x0 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x4 "MDA1,Master Domain Assignment Register 0x4" bitfld.long 0x4 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x4 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x8 "MDA2,Master Domain Assignment Register 0x8" bitfld.long 0x8 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x8 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0xC "MDA3,Master Domain Assignment Register 0xC" bitfld.long 0xC 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0xC 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x10 "MDA4,Master Domain Assignment Register 0x10" bitfld.long 0x10 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x10 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x14 "MDA5,Master Domain Assignment Register 0x14" bitfld.long 0x14 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x14 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x18 "MDA6,Master Domain Assignment Register 0x18" bitfld.long 0x18 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x18 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x1C "MDA7,Master Domain Assignment Register 0x1C" bitfld.long 0x1C 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x1C 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x20 "MDA8,Master Domain Assignment Register 0x20" bitfld.long 0x20 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x20 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x24 "MDA9,Master Domain Assignment Register 0x24" bitfld.long 0x24 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x24 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x28 "MDA10,Master Domain Assignment Register 0x28" bitfld.long 0x28 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x28 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x2C "MDA11,Master Domain Assignment Register 0x2C" bitfld.long 0x2C 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x2C 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x30 "MDA12,Master Domain Assignment Register 0x30" bitfld.long 0x30 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x30 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x34 "MDA13,Master Domain Assignment Register 0x34" bitfld.long 0x34 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x34 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x38 "MDA14,Master Domain Assignment Register 0x38" bitfld.long 0x38 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x38 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x3C "MDA15,Master Domain Assignment Register 0x3C" bitfld.long 0x3C 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x3C 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x40 "MDA16,Master Domain Assignment Register 0x40" bitfld.long 0x40 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x40 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x44 "MDA17,Master Domain Assignment Register 0x44" bitfld.long 0x44 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x44 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x48 "MDA18,Master Domain Assignment Register 0x48" bitfld.long 0x48 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x48 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x4C "MDA19,Master Domain Assignment Register 0x4C" bitfld.long 0x4C 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x4C 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x50 "MDA20,Master Domain Assignment Register 0x50" bitfld.long 0x50 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x50 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x54 "MDA21,Master Domain Assignment Register 0x54" bitfld.long 0x54 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x54 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x58 "MDA22,Master Domain Assignment Register 0x58" bitfld.long 0x58 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x58 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x5C "MDA23,Master Domain Assignment Register 0x5C" bitfld.long 0x5C 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x5C 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x60 "MDA24,Master Domain Assignment Register 0x60" bitfld.long 0x60 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x60 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x64 "MDA25,Master Domain Assignment Register 0x64" bitfld.long 0x64 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x64 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x68 "MDA26,Master Domain Assignment Register 0x68" bitfld.long 0x68 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x68 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x6C "MDA27,Master Domain Assignment Register 0x6C" bitfld.long 0x6C 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x6C 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x70 "MDA28,Master Domain Assignment Register 0x70" bitfld.long 0x70 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x70 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x74 "MDA29,Master Domain Assignment Register 0x74" bitfld.long 0x74 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x74 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x78 "MDA30,Master Domain Assignment Register 0x78" bitfld.long 0x78 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x78 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x7C "MDA31,Master Domain Assignment Register 0x7C" bitfld.long 0x7C 31. " LCK ,Locked" "Not locked,Locked" bitfld.long 0x7C 0.--1. " DID ,Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" group.long 0x400++0x1B7 line.long 0x0 "PDAP0,Peripheral Domain Access Permissions 0x0" bitfld.long 0x0 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x0 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x0 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x0 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x0 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x0 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x0 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x0 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x0 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x0 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x4 "PDAP1,Peripheral Domain Access Permissions 0x4" bitfld.long 0x4 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x4 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x4 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x4 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x4 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x4 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x4 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x4 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x4 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x4 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x8 "PDAP2,Peripheral Domain Access Permissions 0x8" bitfld.long 0x8 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x8 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x8 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x8 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x8 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x8 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x8 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x8 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x8 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x8 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xC "PDAP3,Peripheral Domain Access Permissions 0xC" bitfld.long 0xC 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xC 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xC 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xC 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xC 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xC 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xC 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xC 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xC 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xC 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x10 "PDAP4,Peripheral Domain Access Permissions 0x10" bitfld.long 0x10 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x10 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x10 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x10 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x10 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x10 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x10 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x10 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x10 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x10 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x14 "PDAP5,Peripheral Domain Access Permissions 0x14" bitfld.long 0x14 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x14 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x14 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x14 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x14 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x14 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x14 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x14 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x14 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x14 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x18 "PDAP6,Peripheral Domain Access Permissions 0x18" bitfld.long 0x18 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x18 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x18 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x18 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x18 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x18 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x18 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x18 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x18 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x18 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x1C "PDAP7,Peripheral Domain Access Permissions 0x1C" bitfld.long 0x1C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x1C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x1C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x1C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x1C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x1C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x1C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x1C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x20 "PDAP8,Peripheral Domain Access Permissions 0x20" bitfld.long 0x20 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x20 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x20 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x20 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x20 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x20 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x20 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x20 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x20 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x20 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x24 "PDAP9,Peripheral Domain Access Permissions 0x24" bitfld.long 0x24 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x24 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x24 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x24 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x24 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x24 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x24 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x24 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x24 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x24 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x28 "PDAP10,Peripheral Domain Access Permissions 0x28" bitfld.long 0x28 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x28 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x28 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x28 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x28 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x28 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x28 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x28 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x28 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x28 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x2C "PDAP11,Peripheral Domain Access Permissions 0x2C" bitfld.long 0x2C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x2C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x2C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x2C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x2C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x2C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x2C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x2C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x2C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x2C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x30 "PDAP12,Peripheral Domain Access Permissions 0x30" bitfld.long 0x30 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x30 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x30 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x30 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x30 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x30 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x30 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x30 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x30 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x30 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x34 "PDAP13,Peripheral Domain Access Permissions 0x34" bitfld.long 0x34 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x34 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x34 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x34 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x34 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x34 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x34 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x34 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x34 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x34 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x38 "PDAP14,Peripheral Domain Access Permissions 0x38" bitfld.long 0x38 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x38 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x38 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x38 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x38 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x38 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x38 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x38 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x38 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x38 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x3C "PDAP15,Peripheral Domain Access Permissions 0x3C" bitfld.long 0x3C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x3C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x3C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x3C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x3C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x3C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x3C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x3C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x3C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x3C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x40 "PDAP16,Peripheral Domain Access Permissions 0x40" bitfld.long 0x40 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x40 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x40 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x40 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x40 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x40 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x40 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x40 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x40 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x40 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x44 "PDAP17,Peripheral Domain Access Permissions 0x44" bitfld.long 0x44 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x44 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x44 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x44 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x44 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x44 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x44 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x44 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x44 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x44 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x48 "PDAP18,Peripheral Domain Access Permissions 0x48" bitfld.long 0x48 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x48 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x48 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x48 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x48 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x48 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x48 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x48 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x48 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x48 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x4C "PDAP19,Peripheral Domain Access Permissions 0x4C" bitfld.long 0x4C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x4C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x4C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x4C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x4C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x4C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x4C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x4C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x4C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x4C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x50 "PDAP20,Peripheral Domain Access Permissions 0x50" bitfld.long 0x50 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x50 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x50 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x50 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x50 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x50 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x50 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x50 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x50 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x50 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x54 "PDAP21,Peripheral Domain Access Permissions 0x54" bitfld.long 0x54 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x54 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x54 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x54 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x54 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x54 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x54 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x54 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x54 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x54 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x58 "PDAP22,Peripheral Domain Access Permissions 0x58" bitfld.long 0x58 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x58 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x58 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x58 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x58 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x58 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x58 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x58 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x58 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x58 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x5C "PDAP23,Peripheral Domain Access Permissions 0x5C" bitfld.long 0x5C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x5C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x5C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x5C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x5C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x5C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x5C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x5C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x5C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x5C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x60 "PDAP24,Peripheral Domain Access Permissions 0x60" bitfld.long 0x60 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x60 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x60 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x60 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x60 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x60 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x60 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x60 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x60 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x60 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x64 "PDAP25,Peripheral Domain Access Permissions 0x64" bitfld.long 0x64 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x64 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x64 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x64 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x64 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x64 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x64 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x64 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x64 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x64 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x68 "PDAP26,Peripheral Domain Access Permissions 0x68" bitfld.long 0x68 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x68 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x68 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x68 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x68 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x68 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x68 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x68 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x68 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x68 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x6C "PDAP27,Peripheral Domain Access Permissions 0x6C" bitfld.long 0x6C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x6C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x6C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x6C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x6C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x6C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x6C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x6C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x6C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x6C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x70 "PDAP28,Peripheral Domain Access Permissions 0x70" bitfld.long 0x70 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x70 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x70 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x70 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x70 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x70 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x70 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x70 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x70 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x70 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x74 "PDAP29,Peripheral Domain Access Permissions 0x74" bitfld.long 0x74 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x74 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x74 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x74 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x74 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x74 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x74 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x74 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x74 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x74 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x78 "PDAP30,Peripheral Domain Access Permissions 0x78" bitfld.long 0x78 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x78 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x78 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x78 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x78 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x78 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x78 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x78 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x78 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x78 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x7C "PDAP31,Peripheral Domain Access Permissions 0x7C" bitfld.long 0x7C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x7C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x7C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x7C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x7C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x7C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x7C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x7C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x7C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x7C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x80 "PDAP32,Peripheral Domain Access Permissions 0x80" bitfld.long 0x80 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x80 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x80 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x80 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x80 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x80 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x80 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x80 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x80 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x80 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x84 "PDAP33,Peripheral Domain Access Permissions 0x84" bitfld.long 0x84 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x84 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x84 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x84 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x84 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x84 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x84 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x84 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x84 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x84 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x88 "PDAP34,Peripheral Domain Access Permissions 0x88" bitfld.long 0x88 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x88 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x88 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x88 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x88 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x88 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x88 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x88 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x88 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x88 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x8C "PDAP35,Peripheral Domain Access Permissions 0x8C" bitfld.long 0x8C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x8C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x8C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x8C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x8C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x8C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x8C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x8C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x8C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x8C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x90 "PDAP36,Peripheral Domain Access Permissions 0x90" bitfld.long 0x90 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x90 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x90 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x90 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x90 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x90 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x90 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x90 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x90 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x90 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x94 "PDAP37,Peripheral Domain Access Permissions 0x94" bitfld.long 0x94 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x94 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x94 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x94 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x94 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x94 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x94 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x94 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x94 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x94 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x98 "PDAP38,Peripheral Domain Access Permissions 0x98" bitfld.long 0x98 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x98 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x98 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x98 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x98 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x98 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x98 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x98 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x98 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x98 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x9C "PDAP39,Peripheral Domain Access Permissions 0x9C" bitfld.long 0x9C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x9C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x9C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x9C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x9C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x9C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x9C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x9C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x9C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x9C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xA0 "PDAP40,Peripheral Domain Access Permissions 0xA0" bitfld.long 0xA0 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xA0 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xA0 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xA0 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xA0 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xA0 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xA0 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xA0 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xA0 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xA0 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xA4 "PDAP41,Peripheral Domain Access Permissions 0xA4" bitfld.long 0xA4 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xA4 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xA4 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xA4 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xA4 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xA4 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xA4 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xA4 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xA4 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xA4 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xA8 "PDAP42,Peripheral Domain Access Permissions 0xA8" bitfld.long 0xA8 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xA8 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xA8 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xA8 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xA8 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xA8 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xA8 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xA8 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xA8 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xA8 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xAC "PDAP43,Peripheral Domain Access Permissions 0xAC" bitfld.long 0xAC 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xAC 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xAC 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xAC 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xAC 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xAC 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xAC 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xAC 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xAC 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xAC 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xB0 "PDAP44,Peripheral Domain Access Permissions 0xB0" bitfld.long 0xB0 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xB0 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xB0 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xB0 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xB0 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xB0 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xB0 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xB0 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xB0 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xB0 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xB4 "PDAP45,Peripheral Domain Access Permissions 0xB4" bitfld.long 0xB4 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xB4 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xB4 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xB4 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xB4 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xB4 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xB4 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xB4 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xB4 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xB4 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xB8 "PDAP46,Peripheral Domain Access Permissions 0xB8" bitfld.long 0xB8 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xB8 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xB8 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xB8 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xB8 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xB8 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xB8 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xB8 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xB8 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xB8 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xBC "PDAP47,Peripheral Domain Access Permissions 0xBC" bitfld.long 0xBC 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xBC 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xBC 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xBC 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xBC 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xBC 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xBC 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xBC 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xBC 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xBC 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xC0 "PDAP48,Peripheral Domain Access Permissions 0xC0" bitfld.long 0xC0 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xC0 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xC0 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xC0 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xC0 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xC0 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xC0 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xC0 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xC0 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xC0 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xC4 "PDAP49,Peripheral Domain Access Permissions 0xC4" bitfld.long 0xC4 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xC4 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xC4 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xC4 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xC4 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xC4 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xC4 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xC4 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xC4 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xC4 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xC8 "PDAP50,Peripheral Domain Access Permissions 0xC8" bitfld.long 0xC8 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xC8 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xC8 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xC8 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xC8 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xC8 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xC8 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xC8 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xC8 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xC8 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xCC "PDAP51,Peripheral Domain Access Permissions 0xCC" bitfld.long 0xCC 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xCC 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xCC 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xCC 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xCC 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xCC 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xCC 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xCC 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xCC 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xCC 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xD0 "PDAP52,Peripheral Domain Access Permissions 0xD0" bitfld.long 0xD0 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xD0 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xD0 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xD0 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xD0 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xD0 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xD0 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xD0 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xD0 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xD0 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xD4 "PDAP53,Peripheral Domain Access Permissions 0xD4" bitfld.long 0xD4 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xD4 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xD4 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xD4 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xD4 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xD4 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xD4 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xD4 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xD4 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xD4 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xD8 "PDAP54,Peripheral Domain Access Permissions 0xD8" bitfld.long 0xD8 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xD8 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xD8 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xD8 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xD8 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xD8 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xD8 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xD8 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xD8 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xD8 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xDC "PDAP55,Peripheral Domain Access Permissions 0xDC" bitfld.long 0xDC 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xDC 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xDC 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xDC 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xDC 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xDC 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xDC 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xDC 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xDC 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xDC 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xE0 "PDAP56,Peripheral Domain Access Permissions 0xE0" bitfld.long 0xE0 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xE0 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xE0 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xE0 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xE0 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xE0 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xE0 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xE0 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xE0 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xE0 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xE4 "PDAP57,Peripheral Domain Access Permissions 0xE4" bitfld.long 0xE4 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xE4 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xE4 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xE4 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xE4 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xE4 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xE4 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xE4 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xE4 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xE4 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xE8 "PDAP58,Peripheral Domain Access Permissions 0xE8" bitfld.long 0xE8 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xE8 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xE8 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xE8 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xE8 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xE8 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xE8 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xE8 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xE8 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xE8 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xEC "PDAP59,Peripheral Domain Access Permissions 0xEC" bitfld.long 0xEC 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xEC 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xEC 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xEC 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xEC 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xEC 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xEC 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xEC 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xEC 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xEC 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xF0 "PDAP60,Peripheral Domain Access Permissions 0xF0" bitfld.long 0xF0 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xF0 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xF0 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xF0 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xF0 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xF0 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xF0 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xF0 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xF0 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xF0 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xF4 "PDAP61,Peripheral Domain Access Permissions 0xF4" bitfld.long 0xF4 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xF4 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xF4 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xF4 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xF4 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xF4 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xF4 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xF4 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xF4 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xF4 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xF8 "PDAP62,Peripheral Domain Access Permissions 0xF8" bitfld.long 0xF8 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xF8 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xF8 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xF8 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xF8 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xF8 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xF8 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xF8 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xF8 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xF8 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0xFC "PDAP63,Peripheral Domain Access Permissions 0xFC" bitfld.long 0xFC 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0xFC 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0xFC 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0xFC 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xFC 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0xFC 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0xFC 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0xFC 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0xFC 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0xFC 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x100 "PDAP64,Peripheral Domain Access Permissions 0x100" bitfld.long 0x100 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x100 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x100 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x100 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x100 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x100 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x100 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x100 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x100 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x100 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x104 "PDAP65,Peripheral Domain Access Permissions 0x104" bitfld.long 0x104 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x104 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x104 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x104 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x104 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x104 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x104 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x104 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x104 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x104 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x108 "PDAP66,Peripheral Domain Access Permissions 0x108" bitfld.long 0x108 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x108 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x108 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x108 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x108 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x108 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x108 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x108 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x108 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x108 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x10C "PDAP67,Peripheral Domain Access Permissions 0x10C" bitfld.long 0x10C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x10C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x10C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x10C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x10C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x10C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x10C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x10C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x10C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x10C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x110 "PDAP68,Peripheral Domain Access Permissions 0x110" bitfld.long 0x110 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x110 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x110 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x110 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x110 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x110 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x110 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x110 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x110 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x110 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x114 "PDAP69,Peripheral Domain Access Permissions 0x114" bitfld.long 0x114 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x114 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x114 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x114 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x114 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x114 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x114 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x114 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x114 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x114 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x118 "PDAP70,Peripheral Domain Access Permissions 0x118" bitfld.long 0x118 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x118 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x118 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x118 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x118 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x118 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x118 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x118 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x118 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x118 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x11C "PDAP71,Peripheral Domain Access Permissions 0x11C" bitfld.long 0x11C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x11C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x11C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x11C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x11C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x11C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x11C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x11C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x11C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x11C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x120 "PDAP72,Peripheral Domain Access Permissions 0x120" bitfld.long 0x120 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x120 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x120 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x120 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x120 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x120 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x120 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x120 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x120 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x120 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x124 "PDAP73,Peripheral Domain Access Permissions 0x124" bitfld.long 0x124 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x124 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x124 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x124 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x124 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x124 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x124 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x124 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x124 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x124 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x128 "PDAP74,Peripheral Domain Access Permissions 0x128" bitfld.long 0x128 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x128 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x128 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x128 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x128 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x128 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x128 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x128 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x128 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x128 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x12C "PDAP75,Peripheral Domain Access Permissions 0x12C" bitfld.long 0x12C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x12C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x12C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x12C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x12C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x12C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x12C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x12C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x12C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x12C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x130 "PDAP76,Peripheral Domain Access Permissions 0x130" bitfld.long 0x130 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x130 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x130 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x130 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x130 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x130 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x130 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x130 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x130 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x130 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x134 "PDAP77,Peripheral Domain Access Permissions 0x134" bitfld.long 0x134 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x134 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x134 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x134 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x134 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x134 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x134 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x134 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x134 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x134 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x138 "PDAP78,Peripheral Domain Access Permissions 0x138" bitfld.long 0x138 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x138 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x138 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x138 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x138 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x138 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x138 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x138 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x138 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x138 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x13C "PDAP79,Peripheral Domain Access Permissions 0x13C" bitfld.long 0x13C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x13C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x13C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x13C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x13C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x13C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x13C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x13C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x13C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x13C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x140 "PDAP80,Peripheral Domain Access Permissions 0x140" bitfld.long 0x140 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x140 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x140 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x140 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x140 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x140 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x140 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x140 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x140 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x140 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x144 "PDAP81,Peripheral Domain Access Permissions 0x144" bitfld.long 0x144 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x144 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x144 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x144 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x144 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x144 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x144 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x144 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x144 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x144 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x148 "PDAP82,Peripheral Domain Access Permissions 0x148" bitfld.long 0x148 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x148 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x148 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x148 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x148 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x148 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x148 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x148 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x148 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x148 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x14C "PDAP83,Peripheral Domain Access Permissions 0x14C" bitfld.long 0x14C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x14C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x14C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x14C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x14C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x14C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x14C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x14C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x14C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x14C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x150 "PDAP84,Peripheral Domain Access Permissions 0x150" bitfld.long 0x150 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x150 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x150 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x150 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x150 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x150 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x150 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x150 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x150 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x150 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x154 "PDAP85,Peripheral Domain Access Permissions 0x154" bitfld.long 0x154 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x154 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x154 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x154 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x154 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x154 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x154 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x154 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x154 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x154 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x158 "PDAP86,Peripheral Domain Access Permissions 0x158" bitfld.long 0x158 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x158 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x158 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x158 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x158 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x158 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x158 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x158 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x158 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x158 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x15C "PDAP87,Peripheral Domain Access Permissions 0x15C" bitfld.long 0x15C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x15C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x15C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x15C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x15C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x15C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x15C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x15C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x15C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x15C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x160 "PDAP88,Peripheral Domain Access Permissions 0x160" bitfld.long 0x160 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x160 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x160 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x160 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x160 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x160 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x160 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x160 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x160 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x160 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x164 "PDAP89,Peripheral Domain Access Permissions 0x164" bitfld.long 0x164 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x164 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x164 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x164 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x164 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x164 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x164 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x164 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x164 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x164 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x168 "PDAP90,Peripheral Domain Access Permissions 0x168" bitfld.long 0x168 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x168 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x168 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x168 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x168 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x168 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x168 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x168 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x168 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x168 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x16C "PDAP91,Peripheral Domain Access Permissions 0x16C" bitfld.long 0x16C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x16C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x16C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x16C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x16C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x16C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x16C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x16C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x16C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x16C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x170 "PDAP92,Peripheral Domain Access Permissions 0x170" bitfld.long 0x170 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x170 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x170 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x170 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x170 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x170 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x170 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x170 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x170 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x170 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x174 "PDAP93,Peripheral Domain Access Permissions 0x174" bitfld.long 0x174 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x174 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x174 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x174 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x174 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x174 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x174 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x174 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x174 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x174 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x178 "PDAP94,Peripheral Domain Access Permissions 0x178" bitfld.long 0x178 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x178 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x178 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x178 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x178 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x178 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x178 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x178 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x178 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x178 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x17C "PDAP95,Peripheral Domain Access Permissions 0x17C" bitfld.long 0x17C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x17C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x17C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x17C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x17C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x17C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x17C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x17C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x17C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x17C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x180 "PDAP96,Peripheral Domain Access Permissions 0x180" bitfld.long 0x180 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x180 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x180 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x180 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x180 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x180 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x180 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x180 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x180 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x180 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x184 "PDAP97,Peripheral Domain Access Permissions 0x184" bitfld.long 0x184 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x184 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x184 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x184 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x184 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x184 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x184 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x184 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x184 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x184 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x188 "PDAP98,Peripheral Domain Access Permissions 0x188" bitfld.long 0x188 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x188 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x188 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x188 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x188 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x188 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x188 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x188 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x188 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x188 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x18C "PDAP99,Peripheral Domain Access Permissions 0x18C" bitfld.long 0x18C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x18C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x18C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x18C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x18C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x18C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x18C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x18C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x18C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x18C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x190 "PDAP100,Peripheral Domain Access Permissions 0x190" bitfld.long 0x190 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x190 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x190 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x190 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x190 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x190 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x190 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x190 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x190 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x190 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x194 "PDAP101,Peripheral Domain Access Permissions 0x194" bitfld.long 0x194 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x194 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x194 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x194 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x194 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x194 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x194 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x194 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x194 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x194 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x198 "PDAP102,Peripheral Domain Access Permissions 0x198" bitfld.long 0x198 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x198 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x198 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x198 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x198 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x198 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x198 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x198 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x198 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x198 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x19C "PDAP103,Peripheral Domain Access Permissions 0x19C" bitfld.long 0x19C 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x19C 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x19C 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x19C 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x19C 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x19C 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x19C 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x19C 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x19C 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x19C 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x1A0 "PDAP104,Peripheral Domain Access Permissions 0x1A0" bitfld.long 0x1A0 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x1A0 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x1A0 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x1A0 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1A0 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x1A0 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x1A0 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x1A0 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1A0 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x1A0 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x1A4 "PDAP105,Peripheral Domain Access Permissions 0x1A4" bitfld.long 0x1A4 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x1A4 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x1A4 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x1A4 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1A4 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x1A4 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x1A4 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x1A4 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1A4 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x1A4 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x1A8 "PDAP106,Peripheral Domain Access Permissions 0x1A8" bitfld.long 0x1A8 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x1A8 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x1A8 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x1A8 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1A8 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x1A8 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x1A8 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x1A8 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1A8 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x1A8 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x1AC "PDAP107,Peripheral Domain Access Permissions 0x1AC" bitfld.long 0x1AC 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x1AC 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x1AC 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x1AC 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1AC 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x1AC 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x1AC 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x1AC 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1AC 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x1AC 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x1B0 "PDAP108,Peripheral Domain Access Permissions 0x1B0" bitfld.long 0x1B0 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x1B0 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x1B0 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x1B0 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1B0 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x1B0 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x1B0 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x1B0 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1B0 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x1B0 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" line.long 0x1B4 "PDAP109,Peripheral Domain Access Permissions 0x1B4" bitfld.long 0x1B4 31. " LCK ,Peripheral Permissions Lock" "Not locked,Locked" bitfld.long 0x1B4 30. " SREQ ,Semaphore Required" "No effect,Enforced" bitfld.long 0x1B4 7. " D3R ,Domain 3 Read Access" "Not allowed,Allowed" bitfld.long 0x1B4 6. " D3W ,Domain 3 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1B4 5. " D2R ,Domain 2 Read Access" "Not allowed,Allowed" bitfld.long 0x1B4 4. " D2W ,Domain 2 Write Access" "Not allowed,Allowed" bitfld.long 0x1B4 3. " D1R ,Domain 1 Read Access" "Not allowed,Allowed" bitfld.long 0x1B4 2. " D1W ,Domain 1 Write Access" "Not allowed,Allowed" textline " " bitfld.long 0x1B4 1. " D0R ,Domain 0 Read Access" "Not allowed,Allowed" bitfld.long 0x1B4 0. " D0W ,Domain 0 Write Access" "Not allowed,Allowed" group.long 0x800++0x36F line.long 0x0 "MRSA0,Memory Region Start Address 0" hexmask.long 0x0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x4 "MREA0,Memory Region End Address 0" hexmask.long 0x4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x8 "MRC0,Memory Region Control 0" bitfld.long 0x8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0xC "MRVS0,Memory Region Violation Status 0" hexmask.long 0xC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0xC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0xC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x10 "MRSA1,Memory Region Start Address 1" hexmask.long 0x10 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x14 "MREA1,Memory Region End Address 1" hexmask.long 0x14 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x18 "MRC1,Memory Region Control 1" bitfld.long 0x18 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x18 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x18 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x18 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x18 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x18 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x18 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x18 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x18 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x18 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x1C "MRVS1,Memory Region Violation Status 1" hexmask.long 0x1C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x1C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x1C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x20 "MRSA2,Memory Region Start Address 2" hexmask.long 0x20 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x24 "MREA2,Memory Region End Address 2" hexmask.long 0x24 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x28 "MRC2,Memory Region Control 2" bitfld.long 0x28 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x28 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x28 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x28 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x28 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x28 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x28 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x28 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x28 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x28 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x2C "MRVS2,Memory Region Violation Status 2" hexmask.long 0x2C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x2C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x2C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x30 "MRSA3,Memory Region Start Address 3" hexmask.long 0x30 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x34 "MREA3,Memory Region End Address 3" hexmask.long 0x34 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x38 "MRC3,Memory Region Control 3" bitfld.long 0x38 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x38 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x38 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x38 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x38 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x38 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x38 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x38 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x38 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x38 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x3C "MRVS3,Memory Region Violation Status 3" hexmask.long 0x3C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x3C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x3C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x40 "MRSA4,Memory Region Start Address 4" hexmask.long 0x40 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x44 "MREA4,Memory Region End Address 4" hexmask.long 0x44 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x48 "MRC4,Memory Region Control 4" bitfld.long 0x48 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x48 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x48 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x48 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x48 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x48 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x48 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x48 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x48 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x48 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x4C "MRVS4,Memory Region Violation Status 4" hexmask.long 0x4C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x4C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x4C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x50 "MRSA5,Memory Region Start Address 5" hexmask.long 0x50 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x54 "MREA5,Memory Region End Address 5" hexmask.long 0x54 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x58 "MRC5,Memory Region Control 5" bitfld.long 0x58 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x58 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x58 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x58 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x58 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x58 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x58 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x58 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x58 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x58 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x5C "MRVS5,Memory Region Violation Status 5" hexmask.long 0x5C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x5C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x5C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x60 "MRSA6,Memory Region Start Address 6" hexmask.long 0x60 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x64 "MREA6,Memory Region End Address 6" hexmask.long 0x64 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x68 "MRC6,Memory Region Control 6" bitfld.long 0x68 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x68 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x68 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x68 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x68 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x68 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x68 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x68 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x68 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x68 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x6C "MRVS6,Memory Region Violation Status 6" hexmask.long 0x6C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x6C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x6C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x70 "MRSA7,Memory Region Start Address 7" hexmask.long 0x70 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x74 "MREA7,Memory Region End Address 7" hexmask.long 0x74 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x78 "MRC7,Memory Region Control 7" bitfld.long 0x78 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x78 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x78 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x78 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x78 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x78 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x78 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x78 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x78 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x78 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x7C "MRVS7,Memory Region Violation Status 7" hexmask.long 0x7C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x7C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x7C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x80 "MRSA8,Memory Region Start Address 8" hexmask.long 0x80 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x84 "MREA8,Memory Region End Address 8" hexmask.long 0x84 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x88 "MRC8,Memory Region Control 8" bitfld.long 0x88 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x88 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x88 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x88 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x88 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x88 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x88 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x88 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x88 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x88 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x8C "MRVS8,Memory Region Violation Status 8" hexmask.long 0x8C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x8C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x8C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x90 "MRSA9,Memory Region Start Address 9" hexmask.long 0x90 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x94 "MREA9,Memory Region End Address 9" hexmask.long 0x94 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x98 "MRC9,Memory Region Control 9" bitfld.long 0x98 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x98 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x98 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x98 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x98 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x98 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x98 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x98 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x98 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x98 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x9C "MRVS9,Memory Region Violation Status 9" hexmask.long 0x9C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x9C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x9C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0xA0 "MRSA10,Memory Region Start Address 10" hexmask.long 0xA0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0xA4 "MREA10,Memory Region End Address 10" hexmask.long 0xA4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0xA8 "MRC10,Memory Region Control 10" bitfld.long 0xA8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0xA8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0xA8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xA8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xA8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xA8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0xA8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xA8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xA8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xA8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0xAC "MRVS10,Memory Region Violation Status 10" hexmask.long 0xAC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0xAC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0xAC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0xB0 "MRSA11,Memory Region Start Address 11" hexmask.long 0xB0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0xB4 "MREA11,Memory Region End Address 11" hexmask.long 0xB4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0xB8 "MRC11,Memory Region Control 11" bitfld.long 0xB8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0xB8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0xB8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xB8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xB8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xB8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0xB8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xB8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xB8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xB8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0xBC "MRVS11,Memory Region Violation Status 11" hexmask.long 0xBC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0xBC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0xBC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0xC0 "MRSA12,Memory Region Start Address 12" hexmask.long 0xC0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0xC4 "MREA12,Memory Region End Address 12" hexmask.long 0xC4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0xC8 "MRC12,Memory Region Control 12" bitfld.long 0xC8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0xC8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0xC8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xC8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xC8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xC8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0xC8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xC8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xC8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xC8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0xCC "MRVS12,Memory Region Violation Status 12" hexmask.long 0xCC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0xCC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0xCC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0xD0 "MRSA13,Memory Region Start Address 13" hexmask.long 0xD0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0xD4 "MREA13,Memory Region End Address 13" hexmask.long 0xD4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0xD8 "MRC13,Memory Region Control 13" bitfld.long 0xD8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0xD8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0xD8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xD8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xD8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xD8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0xD8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xD8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xD8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xD8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0xDC "MRVS13,Memory Region Violation Status 13" hexmask.long 0xDC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0xDC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0xDC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0xE0 "MRSA14,Memory Region Start Address 14" hexmask.long 0xE0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0xE4 "MREA14,Memory Region End Address 14" hexmask.long 0xE4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0xE8 "MRC14,Memory Region Control 14" bitfld.long 0xE8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0xE8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0xE8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xE8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xE8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xE8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0xE8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xE8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xE8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xE8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0xEC "MRVS14,Memory Region Violation Status 14" hexmask.long 0xEC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0xEC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0xEC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0xF0 "MRSA15,Memory Region Start Address 15" hexmask.long 0xF0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0xF4 "MREA15,Memory Region End Address 15" hexmask.long 0xF4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0xF8 "MRC15,Memory Region Control 15" bitfld.long 0xF8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0xF8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0xF8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xF8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xF8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xF8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0xF8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xF8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0xF8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0xF8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0xFC "MRVS15,Memory Region Violation Status 15" hexmask.long 0xFC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0xFC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0xFC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x100 "MRSA16,Memory Region Start Address 16" hexmask.long 0x100 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x104 "MREA16,Memory Region End Address 16" hexmask.long 0x104 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x108 "MRC16,Memory Region Control 16" bitfld.long 0x108 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x108 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x108 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x108 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x108 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x108 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x108 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x108 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x108 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x108 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x10C "MRVS16,Memory Region Violation Status 16" hexmask.long 0x10C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x10C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x10C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x110 "MRSA17,Memory Region Start Address 17" hexmask.long 0x110 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x114 "MREA17,Memory Region End Address 17" hexmask.long 0x114 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x118 "MRC17,Memory Region Control 17" bitfld.long 0x118 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x118 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x118 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x118 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x118 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x118 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x118 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x118 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x118 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x118 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x11C "MRVS17,Memory Region Violation Status 17" hexmask.long 0x11C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x11C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x11C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x120 "MRSA18,Memory Region Start Address 18" hexmask.long 0x120 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x124 "MREA18,Memory Region End Address 18" hexmask.long 0x124 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x128 "MRC18,Memory Region Control 18" bitfld.long 0x128 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x128 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x128 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x128 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x128 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x128 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x128 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x128 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x128 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x128 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x12C "MRVS18,Memory Region Violation Status 18" hexmask.long 0x12C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x12C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x12C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x130 "MRSA19,Memory Region Start Address 19" hexmask.long 0x130 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x134 "MREA19,Memory Region End Address 19" hexmask.long 0x134 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x138 "MRC19,Memory Region Control 19" bitfld.long 0x138 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x138 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x138 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x138 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x138 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x138 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x138 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x138 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x138 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x138 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x13C "MRVS19,Memory Region Violation Status 19" hexmask.long 0x13C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x13C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x13C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x140 "MRSA20,Memory Region Start Address 20" hexmask.long 0x140 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x144 "MREA20,Memory Region End Address 20" hexmask.long 0x144 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x148 "MRC20,Memory Region Control 20" bitfld.long 0x148 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x148 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x148 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x148 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x148 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x148 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x148 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x148 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x148 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x148 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x14C "MRVS20,Memory Region Violation Status 20" hexmask.long 0x14C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x14C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x14C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x150 "MRSA21,Memory Region Start Address 21" hexmask.long 0x150 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x154 "MREA21,Memory Region End Address 21" hexmask.long 0x154 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x158 "MRC21,Memory Region Control 21" bitfld.long 0x158 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x158 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x158 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x158 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x158 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x158 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x158 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x158 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x158 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x158 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x15C "MRVS21,Memory Region Violation Status 21" hexmask.long 0x15C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x15C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x15C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x160 "MRSA22,Memory Region Start Address 22" hexmask.long 0x160 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x164 "MREA22,Memory Region End Address 22" hexmask.long 0x164 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x168 "MRC22,Memory Region Control 22" bitfld.long 0x168 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x168 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x168 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x168 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x168 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x168 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x168 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x168 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x168 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x168 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x16C "MRVS22,Memory Region Violation Status 22" hexmask.long 0x16C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x16C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x16C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x170 "MRSA23,Memory Region Start Address 23" hexmask.long 0x170 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x174 "MREA23,Memory Region End Address 23" hexmask.long 0x174 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x178 "MRC23,Memory Region Control 23" bitfld.long 0x178 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x178 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x178 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x178 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x178 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x178 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x178 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x178 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x178 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x178 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x17C "MRVS23,Memory Region Violation Status 23" hexmask.long 0x17C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x17C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x17C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x180 "MRSA24,Memory Region Start Address 24" hexmask.long 0x180 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x184 "MREA24,Memory Region End Address 24" hexmask.long 0x184 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x188 "MRC24,Memory Region Control 24" bitfld.long 0x188 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x188 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x188 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x188 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x188 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x188 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x188 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x188 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x188 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x188 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x18C "MRVS24,Memory Region Violation Status 24" hexmask.long 0x18C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x18C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x18C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x190 "MRSA25,Memory Region Start Address 25" hexmask.long 0x190 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x194 "MREA25,Memory Region End Address 25" hexmask.long 0x194 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x198 "MRC25,Memory Region Control 25" bitfld.long 0x198 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x198 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x198 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x198 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x198 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x198 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x198 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x198 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x198 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x198 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x19C "MRVS25,Memory Region Violation Status 25" hexmask.long 0x19C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x19C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x19C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x1A0 "MRSA26,Memory Region Start Address 26" hexmask.long 0x1A0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x1A4 "MREA26,Memory Region End Address 26" hexmask.long 0x1A4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x1A8 "MRC26,Memory Region Control 26" bitfld.long 0x1A8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x1A8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x1A8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1A8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1A8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1A8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x1A8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1A8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1A8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1A8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x1AC "MRVS26,Memory Region Violation Status 26" hexmask.long 0x1AC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x1AC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x1AC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x1B0 "MRSA27,Memory Region Start Address 27" hexmask.long 0x1B0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x1B4 "MREA27,Memory Region End Address 27" hexmask.long 0x1B4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x1B8 "MRC27,Memory Region Control 27" bitfld.long 0x1B8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x1B8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x1B8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1B8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1B8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1B8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x1B8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1B8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1B8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1B8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x1BC "MRVS27,Memory Region Violation Status 27" hexmask.long 0x1BC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x1BC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x1BC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x1C0 "MRSA28,Memory Region Start Address 28" hexmask.long 0x1C0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x1C4 "MREA28,Memory Region End Address 28" hexmask.long 0x1C4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x1C8 "MRC28,Memory Region Control 28" bitfld.long 0x1C8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x1C8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x1C8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1C8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1C8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1C8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x1C8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1C8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1C8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1C8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x1CC "MRVS28,Memory Region Violation Status 28" hexmask.long 0x1CC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x1CC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x1CC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x1D0 "MRSA29,Memory Region Start Address 29" hexmask.long 0x1D0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x1D4 "MREA29,Memory Region End Address 29" hexmask.long 0x1D4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x1D8 "MRC29,Memory Region Control 29" bitfld.long 0x1D8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x1D8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x1D8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1D8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1D8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1D8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x1D8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1D8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1D8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1D8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x1DC "MRVS29,Memory Region Violation Status 29" hexmask.long 0x1DC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x1DC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x1DC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x1E0 "MRSA30,Memory Region Start Address 30" hexmask.long 0x1E0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x1E4 "MREA30,Memory Region End Address 30" hexmask.long 0x1E4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x1E8 "MRC30,Memory Region Control 30" bitfld.long 0x1E8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x1E8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x1E8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1E8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1E8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1E8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x1E8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1E8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1E8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1E8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x1EC "MRVS30,Memory Region Violation Status 30" hexmask.long 0x1EC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x1EC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x1EC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x1F0 "MRSA31,Memory Region Start Address 31" hexmask.long 0x1F0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x1F4 "MREA31,Memory Region End Address 31" hexmask.long 0x1F4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x1F8 "MRC31,Memory Region Control 31" bitfld.long 0x1F8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x1F8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x1F8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1F8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1F8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1F8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x1F8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1F8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x1F8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x1F8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x1FC "MRVS31,Memory Region Violation Status 31" hexmask.long 0x1FC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x1FC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x1FC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x200 "MRSA32,Memory Region Start Address 32" hexmask.long 0x200 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x204 "MREA32,Memory Region End Address 32" hexmask.long 0x204 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x208 "MRC32,Memory Region Control 32" bitfld.long 0x208 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x208 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x208 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x208 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x208 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x208 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x208 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x208 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x208 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x208 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x20C "MRVS32,Memory Region Violation Status 32" hexmask.long 0x20C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x20C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x20C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x210 "MRSA33,Memory Region Start Address 33" hexmask.long 0x210 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x214 "MREA33,Memory Region End Address 33" hexmask.long 0x214 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x218 "MRC33,Memory Region Control 33" bitfld.long 0x218 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x218 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x218 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x218 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x218 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x218 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x218 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x218 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x218 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x218 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x21C "MRVS33,Memory Region Violation Status 33" hexmask.long 0x21C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x21C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x21C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x220 "MRSA34,Memory Region Start Address 34" hexmask.long 0x220 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x224 "MREA34,Memory Region End Address 34" hexmask.long 0x224 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x228 "MRC34,Memory Region Control 34" bitfld.long 0x228 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x228 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x228 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x228 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x228 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x228 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x228 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x228 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x228 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x228 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x22C "MRVS34,Memory Region Violation Status 34" hexmask.long 0x22C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x22C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x22C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x230 "MRSA35,Memory Region Start Address 35" hexmask.long 0x230 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x234 "MREA35,Memory Region End Address 35" hexmask.long 0x234 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x238 "MRC35,Memory Region Control 35" bitfld.long 0x238 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x238 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x238 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x238 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x238 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x238 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x238 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x238 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x238 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x238 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x23C "MRVS35,Memory Region Violation Status 35" hexmask.long 0x23C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x23C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x23C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x240 "MRSA36,Memory Region Start Address 36" hexmask.long 0x240 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x244 "MREA36,Memory Region End Address 36" hexmask.long 0x244 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x248 "MRC36,Memory Region Control 36" bitfld.long 0x248 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x248 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x248 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x248 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x248 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x248 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x248 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x248 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x248 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x248 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x24C "MRVS36,Memory Region Violation Status 36" hexmask.long 0x24C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x24C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x24C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x250 "MRSA37,Memory Region Start Address 37" hexmask.long 0x250 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x254 "MREA37,Memory Region End Address 37" hexmask.long 0x254 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x258 "MRC37,Memory Region Control 37" bitfld.long 0x258 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x258 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x258 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x258 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x258 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x258 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x258 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x258 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x258 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x258 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x25C "MRVS37,Memory Region Violation Status 37" hexmask.long 0x25C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x25C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x25C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x260 "MRSA38,Memory Region Start Address 38" hexmask.long 0x260 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x264 "MREA38,Memory Region End Address 38" hexmask.long 0x264 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x268 "MRC38,Memory Region Control 38" bitfld.long 0x268 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x268 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x268 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x268 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x268 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x268 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x268 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x268 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x268 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x268 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x26C "MRVS38,Memory Region Violation Status 38" hexmask.long 0x26C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x26C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x26C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x270 "MRSA39,Memory Region Start Address 39" hexmask.long 0x270 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x274 "MREA39,Memory Region End Address 39" hexmask.long 0x274 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x278 "MRC39,Memory Region Control 39" bitfld.long 0x278 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x278 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x278 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x278 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x278 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x278 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x278 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x278 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x278 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x278 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x27C "MRVS39,Memory Region Violation Status 39" hexmask.long 0x27C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x27C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x27C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x280 "MRSA40,Memory Region Start Address 40" hexmask.long 0x280 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x284 "MREA40,Memory Region End Address 40" hexmask.long 0x284 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x288 "MRC40,Memory Region Control 40" bitfld.long 0x288 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x288 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x288 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x288 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x288 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x288 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x288 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x288 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x288 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x288 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x28C "MRVS40,Memory Region Violation Status 40" hexmask.long 0x28C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x28C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x28C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x290 "MRSA41,Memory Region Start Address 41" hexmask.long 0x290 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x294 "MREA41,Memory Region End Address 41" hexmask.long 0x294 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x298 "MRC41,Memory Region Control 41" bitfld.long 0x298 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x298 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x298 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x298 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x298 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x298 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x298 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x298 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x298 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x298 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x29C "MRVS41,Memory Region Violation Status 41" hexmask.long 0x29C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x29C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x29C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x2A0 "MRSA42,Memory Region Start Address 42" hexmask.long 0x2A0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x2A4 "MREA42,Memory Region End Address 42" hexmask.long 0x2A4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x2A8 "MRC42,Memory Region Control 42" bitfld.long 0x2A8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x2A8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x2A8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2A8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2A8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2A8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x2A8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2A8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2A8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2A8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x2AC "MRVS42,Memory Region Violation Status 42" hexmask.long 0x2AC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x2AC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x2AC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x2B0 "MRSA43,Memory Region Start Address 43" hexmask.long 0x2B0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x2B4 "MREA43,Memory Region End Address 43" hexmask.long 0x2B4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x2B8 "MRC43,Memory Region Control 43" bitfld.long 0x2B8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x2B8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x2B8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2B8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2B8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2B8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x2B8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2B8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2B8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2B8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x2BC "MRVS43,Memory Region Violation Status 43" hexmask.long 0x2BC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x2BC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x2BC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x2C0 "MRSA44,Memory Region Start Address 44" hexmask.long 0x2C0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x2C4 "MREA44,Memory Region End Address 44" hexmask.long 0x2C4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x2C8 "MRC44,Memory Region Control 44" bitfld.long 0x2C8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x2C8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x2C8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2C8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2C8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2C8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x2C8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2C8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2C8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2C8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x2CC "MRVS44,Memory Region Violation Status 44" hexmask.long 0x2CC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x2CC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x2CC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x2D0 "MRSA45,Memory Region Start Address 45" hexmask.long 0x2D0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x2D4 "MREA45,Memory Region End Address 45" hexmask.long 0x2D4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x2D8 "MRC45,Memory Region Control 45" bitfld.long 0x2D8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x2D8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x2D8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2D8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2D8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2D8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x2D8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2D8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2D8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2D8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x2DC "MRVS45,Memory Region Violation Status 45" hexmask.long 0x2DC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x2DC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x2DC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x2E0 "MRSA46,Memory Region Start Address 46" hexmask.long 0x2E0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x2E4 "MREA46,Memory Region End Address 46" hexmask.long 0x2E4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x2E8 "MRC46,Memory Region Control 46" bitfld.long 0x2E8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x2E8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x2E8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2E8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2E8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2E8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x2E8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2E8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2E8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2E8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x2EC "MRVS46,Memory Region Violation Status 46" hexmask.long 0x2EC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x2EC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x2EC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x2F0 "MRSA47,Memory Region Start Address 47" hexmask.long 0x2F0 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x2F4 "MREA47,Memory Region End Address 47" hexmask.long 0x2F4 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x2F8 "MRC47,Memory Region Control 47" bitfld.long 0x2F8 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x2F8 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x2F8 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2F8 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2F8 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2F8 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x2F8 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2F8 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x2F8 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x2F8 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x2FC "MRVS47,Memory Region Violation Status 47" hexmask.long 0x2FC 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x2FC 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x2FC 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x300 "MRSA48,Memory Region Start Address 48" hexmask.long 0x300 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x304 "MREA48,Memory Region End Address 48" hexmask.long 0x304 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x308 "MRC48,Memory Region Control 48" bitfld.long 0x308 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x308 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x308 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x308 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x308 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x308 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x308 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x308 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x308 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x308 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x30C "MRVS48,Memory Region Violation Status 48" hexmask.long 0x30C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x30C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x30C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x310 "MRSA49,Memory Region Start Address 49" hexmask.long 0x310 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x314 "MREA49,Memory Region End Address 49" hexmask.long 0x314 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x318 "MRC49,Memory Region Control 49" bitfld.long 0x318 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x318 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x318 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x318 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x318 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x318 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x318 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x318 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x318 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x318 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x31C "MRVS49,Memory Region Violation Status 49" hexmask.long 0x31C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x31C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x31C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x320 "MRSA50,Memory Region Start Address 50" hexmask.long 0x320 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x324 "MREA50,Memory Region End Address 50" hexmask.long 0x324 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x328 "MRC50,Memory Region Control 50" bitfld.long 0x328 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x328 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x328 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x328 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x328 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x328 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x328 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x328 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x328 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x328 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x32C "MRVS50,Memory Region Violation Status 50" hexmask.long 0x32C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x32C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x32C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x330 "MRSA51,Memory Region Start Address 51" hexmask.long 0x330 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x334 "MREA51,Memory Region End Address 51" hexmask.long 0x334 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x338 "MRC51,Memory Region Control 51" bitfld.long 0x338 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x338 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x338 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x338 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x338 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x338 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x338 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x338 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x338 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x338 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x33C "MRVS51,Memory Region Violation Status 51" hexmask.long 0x33C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x33C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x33C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x340 "MRSA52,Memory Region Start Address 52" hexmask.long 0x340 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x344 "MREA52,Memory Region End Address 52" hexmask.long 0x344 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x348 "MRC52,Memory Region Control 52" bitfld.long 0x348 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x348 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x348 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x348 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x348 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x348 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x348 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x348 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x348 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x348 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x34C "MRVS52,Memory Region Violation Status 52" hexmask.long 0x34C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x34C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x34C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x350 "MRSA53,Memory Region Start Address 53" hexmask.long 0x350 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x354 "MREA53,Memory Region End Address 53" hexmask.long 0x354 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x358 "MRC53,Memory Region Control 53" bitfld.long 0x358 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x358 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x358 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x358 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x358 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x358 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x358 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x358 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x358 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x358 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x35C "MRVS53,Memory Region Violation Status 53" hexmask.long 0x35C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x35C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x35C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" line.long 0x360 "MRSA54,Memory Region Start Address 54" hexmask.long 0x360 7.--31. 0x80 " SADR ,Start address for memory region" line.long 0x364 "MREA54,Memory Region End Address 54" hexmask.long 0x364 7.--31. 0x80 " EADR ,End address for memory region" line.long 0x368 "MRC54,Memory Region Control 54" bitfld.long 0x368 31. " LCK ,Region lock" "No lock,Locked" bitfld.long 0x368 30. " ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x368 7. " D3R ,Domain 3 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x368 6. " D3W ,Domain 3 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x368 5. " D2R ,Domain 2 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x368 4. " D2W ,Domain 2 Write Access to Region" "Not allowed,Allowed" bitfld.long 0x368 3. " D1R ,Domain 1 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x368 2. " D1W ,Domain 1 Write Access to Region" "Not allowed,Allowed" textline " " bitfld.long 0x368 1. " D0R ,Domain 0 Read Access to Region" "Not allowed,Allowed" bitfld.long 0x368 0. " D0W ,Domain 0 Write Access to Region" "Not allowed,Allowed" line.long 0x36C "MRVS54,Memory Region Violation Status 54" hexmask.long 0x36C 5.--31. 0x20 " VADR ,Violating Address" eventfld.long 0x36C 4. " AD ,Access to a memory region" "Denied,Allowed" rbitfld.long 0x36C 0.--1. " VDID ,Violating Domain ID" "Domain 0,Domain 1,Domain 2,Domain 3" width 12. tree "RDC SEMA42" tree "Semaphore 1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020F4000 else base ad:0x420F4000 endif width 10. group.byte 0x0++0x00 line.byte 0x00 "GATE0,Gate Register 0" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1++0x00 line.byte 0x00 "GATE1,Gate Register 1" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2++0x00 line.byte 0x00 "GATE2,Gate Register 2" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3++0x00 line.byte 0x00 "GATE3,Gate Register 3" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x4++0x00 line.byte 0x00 "GATE4,Gate Register 4" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x5++0x00 line.byte 0x00 "GATE5,Gate Register 5" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x6++0x00 line.byte 0x00 "GATE6,Gate Register 6" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x7++0x00 line.byte 0x00 "GATE7,Gate Register 7" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x8++0x00 line.byte 0x00 "GATE8,Gate Register 8" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x9++0x00 line.byte 0x00 "GATE9,Gate Register 9" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xA++0x00 line.byte 0x00 "GATE10,Gate Register 10" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xB++0x00 line.byte 0x00 "GATE11,Gate Register 11" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xC++0x00 line.byte 0x00 "GATE12,Gate Register 12" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xD++0x00 line.byte 0x00 "GATE13,Gate Register 13" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xE++0x00 line.byte 0x00 "GATE14,Gate Register 14" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xF++0x00 line.byte 0x00 "GATE15,Gate Register 15" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x10++0x00 line.byte 0x00 "GATE16,Gate Register 16" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x11++0x00 line.byte 0x00 "GATE17,Gate Register 17" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x12++0x00 line.byte 0x00 "GATE18,Gate Register 18" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x13++0x00 line.byte 0x00 "GATE19,Gate Register 19" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x14++0x00 line.byte 0x00 "GATE20,Gate Register 20" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x15++0x00 line.byte 0x00 "GATE21,Gate Register 21" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x16++0x00 line.byte 0x00 "GATE22,Gate Register 22" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x17++0x00 line.byte 0x00 "GATE23,Gate Register 23" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x18++0x00 line.byte 0x00 "GATE24,Gate Register 24" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x19++0x00 line.byte 0x00 "GATE25,Gate Register 25" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1A++0x00 line.byte 0x00 "GATE26,Gate Register 26" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1B++0x00 line.byte 0x00 "GATE27,Gate Register 27" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1C++0x00 line.byte 0x00 "GATE28,Gate Register 28" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1D++0x00 line.byte 0x00 "GATE29,Gate Register 29" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1E++0x00 line.byte 0x00 "GATE30,Gate Register 30" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1F++0x00 line.byte 0x00 "GATE31,Gate Register 31" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x20++0x00 line.byte 0x00 "GATE32,Gate Register 32" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x21++0x00 line.byte 0x00 "GATE33,Gate Register 33" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x22++0x00 line.byte 0x00 "GATE34,Gate Register 34" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x23++0x00 line.byte 0x00 "GATE35,Gate Register 35" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x24++0x00 line.byte 0x00 "GATE36,Gate Register 36" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x25++0x00 line.byte 0x00 "GATE37,Gate Register 37" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x26++0x00 line.byte 0x00 "GATE38,Gate Register 38" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x27++0x00 line.byte 0x00 "GATE39,Gate Register 39" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x28++0x00 line.byte 0x00 "GATE40,Gate Register 40" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x29++0x00 line.byte 0x00 "GATE41,Gate Register 41" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2A++0x00 line.byte 0x00 "GATE42,Gate Register 42" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2B++0x00 line.byte 0x00 "GATE43,Gate Register 43" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2C++0x00 line.byte 0x00 "GATE44,Gate Register 44" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2D++0x00 line.byte 0x00 "GATE45,Gate Register 45" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2E++0x00 line.byte 0x00 "GATE46,Gate Register 46" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2F++0x00 line.byte 0x00 "GATE47,Gate Register 47" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x30++0x00 line.byte 0x00 "GATE48,Gate Register 48" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x31++0x00 line.byte 0x00 "GATE49,Gate Register 49" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x32++0x00 line.byte 0x00 "GATE50,Gate Register 50" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x33++0x00 line.byte 0x00 "GATE51,Gate Register 51" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x34++0x00 line.byte 0x00 "GATE52,Gate Register 52" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x35++0x00 line.byte 0x00 "GATE53,Gate Register 53" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x36++0x00 line.byte 0x00 "GATE54,Gate Register 54" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x37++0x00 line.byte 0x00 "GATE55,Gate Register 55" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x38++0x00 line.byte 0x00 "GATE56,Gate Register 56" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x39++0x00 line.byte 0x00 "GATE57,Gate Register 57" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3A++0x00 line.byte 0x00 "GATE58,Gate Register 58" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3B++0x00 line.byte 0x00 "GATE59,Gate Register 59" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3C++0x00 line.byte 0x00 "GATE60,Gate Register 60" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3D++0x00 line.byte 0x00 "GATE61,Gate Register 61" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3E++0x00 line.byte 0x00 "GATE62,Gate Register 62" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3F++0x00 line.byte 0x00 "GATE63,Gate Register 63" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.word 0x40++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset Gate Number" hexmask.word.byte 0x00 0.--7. 1. " RSTGDP ,Reset Gate Data Pattern" group.word 0x40++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset Gate Number" rbitfld.word 0x00 4.--5. " RSTGMS ,Reset Gate Finite State Machine" "Idle,Wait for 2nd data pattern write,2-write completed," rbitfld.word 0x00 0.--3. " RSTGBM ,Reset Gate Bus Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 12. tree.end tree "Semaphore 2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020F8000 else base ad:0x420F8000 endif width 10. group.byte 0x0++0x00 line.byte 0x00 "GATE0,Gate Register 0" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1++0x00 line.byte 0x00 "GATE1,Gate Register 1" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2++0x00 line.byte 0x00 "GATE2,Gate Register 2" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3++0x00 line.byte 0x00 "GATE3,Gate Register 3" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x4++0x00 line.byte 0x00 "GATE4,Gate Register 4" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x5++0x00 line.byte 0x00 "GATE5,Gate Register 5" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x6++0x00 line.byte 0x00 "GATE6,Gate Register 6" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x7++0x00 line.byte 0x00 "GATE7,Gate Register 7" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x8++0x00 line.byte 0x00 "GATE8,Gate Register 8" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x9++0x00 line.byte 0x00 "GATE9,Gate Register 9" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xA++0x00 line.byte 0x00 "GATE10,Gate Register 10" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xB++0x00 line.byte 0x00 "GATE11,Gate Register 11" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xC++0x00 line.byte 0x00 "GATE12,Gate Register 12" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xD++0x00 line.byte 0x00 "GATE13,Gate Register 13" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xE++0x00 line.byte 0x00 "GATE14,Gate Register 14" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0xF++0x00 line.byte 0x00 "GATE15,Gate Register 15" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x10++0x00 line.byte 0x00 "GATE16,Gate Register 16" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x11++0x00 line.byte 0x00 "GATE17,Gate Register 17" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x12++0x00 line.byte 0x00 "GATE18,Gate Register 18" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x13++0x00 line.byte 0x00 "GATE19,Gate Register 19" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x14++0x00 line.byte 0x00 "GATE20,Gate Register 20" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x15++0x00 line.byte 0x00 "GATE21,Gate Register 21" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x16++0x00 line.byte 0x00 "GATE22,Gate Register 22" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x17++0x00 line.byte 0x00 "GATE23,Gate Register 23" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x18++0x00 line.byte 0x00 "GATE24,Gate Register 24" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x19++0x00 line.byte 0x00 "GATE25,Gate Register 25" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1A++0x00 line.byte 0x00 "GATE26,Gate Register 26" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1B++0x00 line.byte 0x00 "GATE27,Gate Register 27" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1C++0x00 line.byte 0x00 "GATE28,Gate Register 28" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1D++0x00 line.byte 0x00 "GATE29,Gate Register 29" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1E++0x00 line.byte 0x00 "GATE30,Gate Register 30" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x1F++0x00 line.byte 0x00 "GATE31,Gate Register 31" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x20++0x00 line.byte 0x00 "GATE32,Gate Register 32" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x21++0x00 line.byte 0x00 "GATE33,Gate Register 33" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x22++0x00 line.byte 0x00 "GATE34,Gate Register 34" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x23++0x00 line.byte 0x00 "GATE35,Gate Register 35" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x24++0x00 line.byte 0x00 "GATE36,Gate Register 36" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x25++0x00 line.byte 0x00 "GATE37,Gate Register 37" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x26++0x00 line.byte 0x00 "GATE38,Gate Register 38" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x27++0x00 line.byte 0x00 "GATE39,Gate Register 39" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x28++0x00 line.byte 0x00 "GATE40,Gate Register 40" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x29++0x00 line.byte 0x00 "GATE41,Gate Register 41" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2A++0x00 line.byte 0x00 "GATE42,Gate Register 42" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2B++0x00 line.byte 0x00 "GATE43,Gate Register 43" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2C++0x00 line.byte 0x00 "GATE44,Gate Register 44" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2D++0x00 line.byte 0x00 "GATE45,Gate Register 45" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2E++0x00 line.byte 0x00 "GATE46,Gate Register 46" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x2F++0x00 line.byte 0x00 "GATE47,Gate Register 47" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x30++0x00 line.byte 0x00 "GATE48,Gate Register 48" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x31++0x00 line.byte 0x00 "GATE49,Gate Register 49" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x32++0x00 line.byte 0x00 "GATE50,Gate Register 50" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x33++0x00 line.byte 0x00 "GATE51,Gate Register 51" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x34++0x00 line.byte 0x00 "GATE52,Gate Register 52" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x35++0x00 line.byte 0x00 "GATE53,Gate Register 53" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x36++0x00 line.byte 0x00 "GATE54,Gate Register 54" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x37++0x00 line.byte 0x00 "GATE55,Gate Register 55" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x38++0x00 line.byte 0x00 "GATE56,Gate Register 56" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x39++0x00 line.byte 0x00 "GATE57,Gate Register 57" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3A++0x00 line.byte 0x00 "GATE58,Gate Register 58" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3B++0x00 line.byte 0x00 "GATE59,Gate Register 59" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3C++0x00 line.byte 0x00 "GATE60,Gate Register 60" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3D++0x00 line.byte 0x00 "GATE61,Gate Register 61" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3E++0x00 line.byte 0x00 "GATE62,Gate Register 62" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.byte 0x3F++0x00 line.byte 0x00 "GATE63,Gate Register 63" rbitfld.byte 0x00 5.--6. " LDOM ,Domain which had currently locked the gate" "Domain 0,Domain 1,Domain 2,Domain 3" bitfld.byte 0x00 0.--3. " GTFSM ,Index of a last processor that locked a gate" "Unlocked,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14" group.word 0x40++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset Gate Number" hexmask.word.byte 0x00 0.--7. 1. " RSTGDP ,Reset Gate Data Pattern" group.word 0x40++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x00 8.--15. 1. " RSTGTN ,Reset Gate Number" rbitfld.word 0x00 4.--5. " RSTGMS ,Reset Gate Finite State Machine" "Idle,Wait for 2nd data pattern write,2-write completed," rbitfld.word 0x00 0.--3. " RSTGBM ,Reset Gate Bus Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 12. tree.end tree.end tree.end tree "ROMC (ROM Controller with Patch)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021AC000 else base ad:0x421AC000 endif width 13. sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX6*")) group.long 0xD4++0x1F line.long 0x00 "ROMPATCH0D,ROMPATCH Data Register 0" line.long 0x04 "ROMPATCH1D,ROMPATCH Data Register 1" line.long 0x08 "ROMPATCH2D,ROMPATCH Data Register 2" line.long 0x0c "ROMPATCH3D,ROMPATCH Data Register 3" line.long 0x10 "ROMPATCH4D,ROMPATCH Data Register 4" line.long 0x14 "ROMPATCH5D,ROMPATCH Data Register 5" line.long 0x18 "ROMPATCH6D,ROMPATCH Data Register 6" line.long 0x1c "ROMPATCH7D,ROMPATCH Data Register 7" else group.long 0xD4++0x1F line.long 0x00 "ROMPATCHD7,ROMPATCH Data Register 7" line.long 0x04 "ROMPATCHD6,ROMPATCH Data Register 6" line.long 0x08 "ROMPATCHD5,ROMPATCH Data Register 5" line.long 0x0c "ROMPATCHD4,ROMPATCH Data Register 4" line.long 0x10 "ROMPATCHD3,ROMPATCH Data Register 3" line.long 0x14 "ROMPATCHD2,ROMPATCH Data Register 2" line.long 0x18 "ROMPATCHD1,ROMPATCH Data Register 1" line.long 0x1c "ROMPATCHD0,ROMPATCH Data Register 0" endif group.long 0xF4++0x03 line.long 0x00 "ROMPATCHCNT,ROMPATCH Control Register" bitfld.long 0x00 29. " DIS ,ROMPATCH Disable" "No effect,Disabled" bitfld.long 0x00 7. " DATAFIX[7] ,Data Fix Enable" "Opcode patch,Data fix" bitfld.long 0x00 6. " DATAFIX[6] ,Data Fix Enable" "Opcode patch,Data fix" bitfld.long 0x00 5. " DATAFIX[5] ,Data Fix Enable" "Opcode patch,Data fix" textline " " bitfld.long 0x00 4. " DATAFIX[4] ,Data Fix Enable" "Opcode patch,Data fix" bitfld.long 0x00 3. " DATAFIX[3] ,Data Fix Enable" "Opcode patch,Data fix" bitfld.long 0x00 2. " DATAFIX[2] ,Data Fix Enable" "Opcode patch,Data fix" bitfld.long 0x00 1. " DATAFIX[1] ,Data Fix Enable" "Opcode patch,Data fix" textline " " bitfld.long 0x00 0. " DATAFIX[0] ,Data Fix Enable" "Opcode patch,Data fix" hgroup.long 0xF8++0x03 hide.long 0x00 "ROMPATCHENH,ROMPATCH Enable Register High" group.long 0xFC++0x03 line.long 0x00 "ROMPATCHENL,ROMPATCH Enable Register Low" bitfld.long 0x00 15. " ENABLE[15] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 14. " ENABLE[14] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 13. " ENABLE[13] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 12. " ENABLE[12] ,Enable Address Comparator" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ENABLE[11] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 10. " ENABLE[10] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 9. " ENABLE[9] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 8. " ENABLE[8] ,Enable Address Comparator" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ENABLE[7] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE[6] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 5. " ENABLE[5] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 4. " ENABLE[4] ,Enable Address Comparator" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ENABLE[3] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLE[2] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE[1] ,Enable Address Comparator" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE[0] ,Enable Address Comparator" "Disabled,Enabled" sif (cpuis("IMX6*")) group.long 0x100++0x03 line.long 0x00 "ROMPATCHA0 ,ROMPATCH Address Register 0 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR0 ,Address Comparator" bitfld.long 0x00 0. " THUMB0 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x104++0x03 line.long 0x00 "ROMPATCHA1 ,ROMPATCH Address Register 1 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR1 ,Address Comparator" bitfld.long 0x00 0. " THUMB1 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x108++0x03 line.long 0x00 "ROMPATCHA2 ,ROMPATCH Address Register 2 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR2 ,Address Comparator" bitfld.long 0x00 0. " THUMB2 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x10C++0x03 line.long 0x00 "ROMPATCHA3 ,ROMPATCH Address Register 3 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR3 ,Address Comparator" bitfld.long 0x00 0. " THUMB3 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x110++0x03 line.long 0x00 "ROMPATCHA4 ,ROMPATCH Address Register 4 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR4 ,Address Comparator" bitfld.long 0x00 0. " THUMB4 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x114++0x03 line.long 0x00 "ROMPATCHA5 ,ROMPATCH Address Register 5 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR5 ,Address Comparator" bitfld.long 0x00 0. " THUMB5 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x118++0x03 line.long 0x00 "ROMPATCHA6 ,ROMPATCH Address Register 6 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR6 ,Address Comparator" bitfld.long 0x00 0. " THUMB6 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x11C++0x03 line.long 0x00 "ROMPATCHA7 ,ROMPATCH Address Register 7 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR7 ,Address Comparator" bitfld.long 0x00 0. " THUMB7 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x120++0x03 line.long 0x00 "ROMPATCHA8 ,ROMPATCH Address Register 8 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR8 ,Address Comparator" bitfld.long 0x00 0. " THUMB8 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x124++0x03 line.long 0x00 "ROMPATCHA9 ,ROMPATCH Address Register 9 " hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR9 ,Address Comparator" bitfld.long 0x00 0. " THUMB9 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x128++0x03 line.long 0x00 "ROMPATCHA10,ROMPATCH Address Register 10" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR10 ,Address Comparator" bitfld.long 0x00 0. " THUMB10 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x12C++0x03 line.long 0x00 "ROMPATCHA11,ROMPATCH Address Register 11" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR11 ,Address Comparator" bitfld.long 0x00 0. " THUMB11 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x130++0x03 line.long 0x00 "ROMPATCHA12,ROMPATCH Address Register 12" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR12 ,Address Comparator" bitfld.long 0x00 0. " THUMB12 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x134++0x03 line.long 0x00 "ROMPATCHA13,ROMPATCH Address Register 13" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR13 ,Address Comparator" bitfld.long 0x00 0. " THUMB13 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x138++0x03 line.long 0x00 "ROMPATCHA14,ROMPATCH Address Register 14" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR14 ,Address Comparator" bitfld.long 0x00 0. " THUMB14 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x13C++0x03 line.long 0x00 "ROMPATCHA15,ROMPATCH Address Register 15" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR15 ,Address Comparator" bitfld.long 0x00 0. " THUMB15 ,THUMB Comparator Select" "ARM,THUMB" else group.long 0x100++0x03 line.long 0x00 "ROMPATCHA0,ROMPATCH Address Register 0" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR0 ,Address Comparator" bitfld.long 0x00 0. " THUMB0 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x104++0x03 line.long 0x00 "ROMPATCHA1,ROMPATCH Address Register 1" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR1 ,Address Comparator" bitfld.long 0x00 0. " THUMB1 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x108++0x03 line.long 0x00 "ROMPATCHA2,ROMPATCH Address Register 2" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR2 ,Address Comparator" bitfld.long 0x00 0. " THUMB2 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x10C++0x03 line.long 0x00 "ROMPATCHA3,ROMPATCH Address Register 3" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR3 ,Address Comparator" bitfld.long 0x00 0. " THUMB3 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x110++0x03 line.long 0x00 "ROMPATCHA4,ROMPATCH Address Register 4" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR4 ,Address Comparator" bitfld.long 0x00 0. " THUMB4 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x114++0x03 line.long 0x00 "ROMPATCHA5,ROMPATCH Address Register 5" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR5 ,Address Comparator" bitfld.long 0x00 0. " THUMB5 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x118++0x03 line.long 0x00 "ROMPATCHA6,ROMPATCH Address Register 6" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR6 ,Address Comparator" bitfld.long 0x00 0. " THUMB6 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x11C++0x03 line.long 0x00 "ROMPATCHA7,ROMPATCH Address Register 7" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR7 ,Address Comparator" bitfld.long 0x00 0. " THUMB7 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x120++0x03 line.long 0x00 "ROMPATCHA8,ROMPATCH Address Register 8" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR8 ,Address Comparator" bitfld.long 0x00 0. " THUMB8 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x124++0x03 line.long 0x00 "ROMPATCHA9,ROMPATCH Address Register 9" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR9 ,Address Comparator" bitfld.long 0x00 0. " THUMB9 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x128++0x03 line.long 0x00 "ROMPATCHA10,ROMPATCH Address Register 10" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR10 ,Address Comparator" bitfld.long 0x00 0. " THUMB10 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x12C++0x03 line.long 0x00 "ROMPATCHA11,ROMPATCH Address Register 11" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR11 ,Address Comparator" bitfld.long 0x00 0. " THUMB11 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x130++0x03 line.long 0x00 "ROMPATCHA12,ROMPATCH Address Register 12" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR12 ,Address Comparator" bitfld.long 0x00 0. " THUMB12 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x134++0x03 line.long 0x00 "ROMPATCHA13,ROMPATCH Address Register 13" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR13 ,Address Comparator" bitfld.long 0x00 0. " THUMB13 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x138++0x03 line.long 0x00 "ROMPATCHA14,ROMPATCH Address Register 14" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR14 ,Address Comparator" bitfld.long 0x00 0. " THUMB14 ,THUMB Comparator Select" "ARM,THUMB" group.long 0x13C++0x03 line.long 0x00 "ROMPATCHA15,ROMPATCH Address Register 15" hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR15 ,Address Comparator" bitfld.long 0x00 0. " THUMB15 ,THUMB Comparator Select" "ARM,THUMB" endif group.long 0x208++0x03 line.long 0x00 "ROMPATCHSR,ROMPATCH Status Register" eventfld.long 0x00 17. " SW ,ROMC AHB Simultaneous Address Comparisons" "Not occurred,Occurred" rbitfld.long 0x00 0.--5. " SOURCE ,ROMPATCH Source Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "SAI (Synchronous Audio Interface)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021D4000 else base ad:0x421D4000 endif width 6. group.long 0x00++0x17 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" textline " " eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty" rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x04 0.--4. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x08 30.--31. " SYNC ,Synchronous Mode" "Asynchronous,Receiver,SAI transmitter,SAI receiver" bitfld.long 0x08 29. " BCS ,Bit Clock Swap" "Normal,Swapped" bitfld.long 0x08 28. " BCI ,Bit Clock Input" "No effect,External" bitfld.long 0x08 26.--27. " MSEL ,MCLK Select" "Master 1,Master 1,Master 2,Master 3" textline " " bitfld.long 0x08 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x08 24. " BCD ,Bit clock direction" "External,Internal" hexmask.long.byte 0x08 0.--7. 1. " DIV ,Bit clock divide" line.long 0x0C "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x0C 16. " TCE ,Transmit channel 0 enable" "Disabled,Enabled" bitfld.long 0x0C 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x10 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x10 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x10 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x10 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" bitfld.long 0x10 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" textline " " bitfld.long 0x10 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x10 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x14 "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x14 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long 0x20++0x07 line.long 0x00 "TDR0,SAI Transmit Data Register 0" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--21. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 1. " RFP ,Read FIFO pointer" else rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--19. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--3. 1. " RFP ,Read FIFO pointer" endif group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Mask bit[31]" "Not masked,Masked" bitfld.long 0x00 30. " TWM[30] ,Mask bit[30]" "Not masked,Masked" bitfld.long 0x00 29. " TWM[29] ,Mask bit[29]" "Not masked,Masked" bitfld.long 0x00 28. " TWM[28] ,Mask bit[28]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " TWM[27] ,Mask bit[27]" "Not masked,Masked" bitfld.long 0x00 26. " TWM[26] ,Mask bit[26]" "Not masked,Masked" bitfld.long 0x00 25. " TWM[25] ,Mask bit[25]" "Not masked,Masked" bitfld.long 0x00 24. " TWM[24] ,Mask bit[24]" "Not masked,Masked" textline " " bitfld.long 0x00 23. " TWM[23] ,Mask bit[23]" "Not masked,Masked" bitfld.long 0x00 22. " TWM[22] ,Mask bit[22]" "Not masked,Masked" bitfld.long 0x00 21. " TWM[21] ,Mask bit[21]" "Not masked,Masked" bitfld.long 0x00 20. " TWM[20] ,Mask bit[20]" "Not masked,Masked" textline " " bitfld.long 0x00 19. " TWM[19] ,Mask bit[19]" "Not masked,Masked" bitfld.long 0x00 18. " TWM[18] ,Mask bit[18]" "Not masked,Masked" bitfld.long 0x00 17. " TWM[17] ,Mask bit[17]" "Not masked,Masked" bitfld.long 0x00 16. " TWM[16] ,Mask bit[16]" "Not masked,Masked" textline " " bitfld.long 0x00 15. " TWM[15] ,Mask bit[15]" "Not masked,Masked" bitfld.long 0x00 14. " TWM[14] ,Mask bit[14]" "Not masked,Masked" bitfld.long 0x00 13. " TWM[13] ,Mask bit[13]" "Not masked,Masked" bitfld.long 0x00 12. " TWM[12] ,Mask bit[12]" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TWM[11] ,Mask bit[11]" "Not masked,Masked" bitfld.long 0x00 10. " TWM[10] ,Mask bit[10]" "Not masked,Masked" bitfld.long 0x00 9. " TWM[9] ,Mask bit[9]" "Not masked,Masked" bitfld.long 0x00 8. " TWM[8] ,Mask bit[8]" "Not masked,Masked" textline " " bitfld.long 0x00 7. " TWM[7] ,Mask bit[7]" "Not masked,Masked" bitfld.long 0x00 6. " TWM[6] ,Mask bit[6]" "Not masked,Masked" bitfld.long 0x00 5. " TWM[5] ,Mask bit[5]" "Not masked,Masked" bitfld.long 0x00 4. " TWM[4] ,Mask bit[4]" "Not masked,Masked" textline " " bitfld.long 0x00 3. " TWM[3] ,Mask bit[3]" "Not masked,Masked" bitfld.long 0x00 2. " TWM[2] ,Mask bit[2]" "Not masked,Masked" bitfld.long 0x00 1. " TWM[1] ,Mask bit[1]" "Not masked,Masked" bitfld.long 0x00 0. " TWM[0] ,Mask bit[0]" "Not masked,Masked" group.long 0x80++0x17 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" textline " " eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full" rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x04 0.--4. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x08 30.--31. " SYNC ,Synchronous Mode" "Asynchronous,Transmitter,SAI receiver,SAI transmitter" bitfld.long 0x08 29. " BCS ,Bit Clock Swap" "Normal,Swapped" bitfld.long 0x08 28. " BCI ,Bit Clock Input" "No effect,External" bitfld.long 0x08 26.--27. " MSEL ,MCLK Select" "Bus clock,Master 1,Master 2,Master 3" textline " " bitfld.long 0x08 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x08 24. " BCD ,Bit clock direction" "External,Internal" hexmask.long.byte 0x08 0.--7. 1. " DIV ,Bit clock divide" line.long 0x0C "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x0C 16. " RCE ,Receive channel 0 enable" "Disabled,Enabled" bitfld.long 0x0C 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x10 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x10 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x10 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x10 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x10 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" textline " " bitfld.long 0x10 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x10 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x14 "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x14 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xa0++0x03 line.long 0x00 "RDR0,SAI Receive Data 0 Register" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rgroup.long 0xC0++0x07 line.long 0x00 "RFR0,SAI Receive FIFO 0 Register" hexmask.long.byte 0x00 16.--21. 1. " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 1. " RFP ,Read FIFO pointer" else rgroup.long 0xC0++0x07 line.long 0x00 "RFR0,SAI Receive FIFO 0 Register" bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM31 ,Receive Mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " RWM30 ,Receive Mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " RWM29 ,Receive Mask bit 29" "Not masked,Masked" bitfld.long 0x00 28. " RWM28 ,Receive Mask bit 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " RWM27 ,Receive Mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " RWM26 ,Receive Mask bit 26" "Not masked,Masked" bitfld.long 0x00 25. " RWM25 ,Receive Mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " RWM24 ,Receive Mask bit 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " RWM23 ,Receive Mask bit 23" "Not masked,Masked" bitfld.long 0x00 22. " RWM22 ,Receive Mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " RWM21 ,Receive Mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " RWM20 ,Receive Mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " RWM19 ,Receive Mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " RWM18 ,Receive Mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " RWM17 ,Receive Mask bit 17" "Not masked,Masked" bitfld.long 0x00 16. " RWM16 ,Receive Mask bit 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " RWM15 ,Receive Mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " RWM14 ,Receive Mask bit 14" "Not masked,Masked" bitfld.long 0x00 13. " RWM13 ,Receive Mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " RWM12 ,Receive Mask bit 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " RWM11 ,Receive Mask bit 11" "Not masked,Masked" bitfld.long 0x00 10. " RWM10 ,Receive Mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " RWM9 ,Receive Mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " RWM8 ,Receive Mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " RWM7 ,Receive Mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " RWM6 ,Receive Mask bit 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " RWM5 ,Receive Mask bit 5" "Not masked,Masked" bitfld.long 0x00 4. " RWM4 ,Receive Mask bit 4" "Not masked,Masked" bitfld.long 0x00 3. " RWM3 ,Receive Mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " RWM2 ,Receive Mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " RWM1 ,Receive Mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " RWM0 ,Receive Mask bit 0" "Not masked,Masked" width 0x0B tree.end tree "SDMA (Smart Direct Memory Access Controller)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020EC000 else base ad:0x420EC000 endif width 13. group.long 0x00++0x0B line.long 0x00 "MC0PTR,AP Channel 0 Pointer Register" line.long 0x04 "INTR,Channel Interrupts Register" eventfld.long 0x04 31. " HI[31] ,AP HI[31] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 30. " HI[30] ,AP HI[30] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 29. " HI[29] ,AP HI[29] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 28. " HI[28] ,AP HI[28] Interrupt " "No interrupt,Interrupt" textline " " eventfld.long 0x04 27. " HI[27] ,AP HI[27] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 26. " HI[26] ,AP HI[26] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 25. " HI[25] ,AP HI[25] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 24. " HI[24] ,AP HI[24] Interrupt " "No interrupt,Interrupt" textline " " eventfld.long 0x04 23. " HI[23] ,AP HI[23] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 22. " HI[22] ,AP HI[22] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 21. " HI[21] ,AP HI[21] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 20. " HI[20] ,AP HI[20] Interrupt " "No interrupt,Interrupt" textline " " eventfld.long 0x04 19. " HI[19] ,AP HI[19] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 18. " HI[18] ,AP HI[18] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 17. " HI[17] ,AP HI[17] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 16. " HI[16] ,AP HI[16] Interrupt " "No interrupt,Interrupt" textline " " eventfld.long 0x04 15. " HI[15] ,AP HI[15] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 14. " HI[14] ,AP HI[14] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 13. " HI[13] ,AP HI[13] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 12. " HI[12] ,AP HI[12] Interrupt " "No interrupt,Interrupt" textline " " eventfld.long 0x04 11. " HI[11] ,AP HI[11] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 10. " HI[10] ,AP HI[10] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 9. " HI[9] ,AP HI[9] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 8. " HI[8] ,AP HI[8] Interrupt " "No interrupt,Interrupt" textline " " eventfld.long 0x04 7. " HI[7] ,AP HI[7] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 6. " HI[6] ,AP HI[6] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 5. " HI[5] ,AP HI[5] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 4. " HI[4] ,AP HI[4] Interrupt " "No interrupt,Interrupt" textline " " eventfld.long 0x04 3. " HI[3] ,AP HI[3] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 2. " HI[2] ,AP HI[2] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 1. " HI[1] ,AP HI[1] Interrupt " "No interrupt,Interrupt" eventfld.long 0x04 0. " HI[0] ,AP HI[0] Interrupt " "No interrupt,Interrupt" line.long 0x08 "STOP_STAT,Channel Stop/Channel Status Register" eventfld.long 0x08 31. " HE[31] ,HE[31] Stop/Status" "No access,Access" eventfld.long 0x08 30. " HE[30] ,HE[30] Stop/Status" "No access,Access" eventfld.long 0x08 29. " HE[29] ,HE[29] Stop/Status" "No access,Access" eventfld.long 0x08 28. " HE[28] ,HE[28] Stop/Status" "No access,Access" textline " " eventfld.long 0x08 27. " HE[27] ,HE[27] Stop/Status" "No access,Access" eventfld.long 0x08 26. " HE[26] ,HE[26] Stop/Status" "No access,Access" eventfld.long 0x08 25. " HE[25] ,HE[25] Stop/Status" "No access,Access" eventfld.long 0x08 24. " HE[24] ,HE[24] Stop/Status" "No access,Access" textline " " eventfld.long 0x08 23. " HE[23] ,HE[23] Stop/Status" "No access,Access" eventfld.long 0x08 22. " HE[22] ,HE[22] Stop/Status" "No access,Access" eventfld.long 0x08 21. " HE[21] ,HE[21] Stop/Status" "No access,Access" eventfld.long 0x08 20. " HE[20] ,HE[20] Stop/Status" "No access,Access" textline " " eventfld.long 0x08 19. " HE[19] ,HE[19] Stop/Status" "No access,Access" eventfld.long 0x08 18. " HE[18] ,HE[18] Stop/Status" "No access,Access" eventfld.long 0x08 17. " HE[17] ,HE[17] Stop/Status" "No access,Access" eventfld.long 0x08 16. " HE[16] ,HE[16] Stop/Status" "No access,Access" textline " " eventfld.long 0x08 15. " HE[15] ,HE[15] Stop/Status" "No access,Access" eventfld.long 0x08 14. " HE[14] ,HE[14] Stop/Status" "No access,Access" eventfld.long 0x08 13. " HE[13] ,HE[13] Stop/Status" "No access,Access" eventfld.long 0x08 12. " HE[12] ,HE[12] Stop/Status" "No access,Access" textline " " eventfld.long 0x08 11. " HE[11] ,HE[11] Stop/Status" "No access,Access" eventfld.long 0x08 10. " HE[10] ,HE[10] Stop/Status" "No access,Access" eventfld.long 0x08 9. " HE[9] ,HE[9] Stop/Status" "No access,Access" eventfld.long 0x08 8. " HE[8] ,HE[8] Stop/Status" "No access,Access" textline " " eventfld.long 0x08 7. " HE[7] ,HE[7] Stop/Status" "No access,Access" eventfld.long 0x08 6. " HE[6] ,HE[6] Stop/Status" "No access,Access" eventfld.long 0x08 5. " HE[5] ,HE[5] Stop/Status" "No access,Access" eventfld.long 0x08 4. " HE[4] ,HE[4] Stop/Status" "No access,Access" textline " " eventfld.long 0x08 3. " HE[3] ,HE[3] Stop/Status" "No access,Access" eventfld.long 0x08 2. " HE[2] ,HE[2] Stop/Status" "No access,Access" eventfld.long 0x08 1. " HE[1] ,HE[1] Stop/Status" "No access,Access" eventfld.long 0x08 0. " HE[0] ,HE[0] Stop/Status" "No access,Access" group.long 0x0c++0x7 line.long 0x00 "HSTART,Channel Start Register" eventfld.long 0x00 31. " HSTART[31] ,Channel 31 Enable" "Disabled,Enabled" eventfld.long 0x00 30. " HSTART[30] ,Channel 30 Enable" "Disabled,Enabled" eventfld.long 0x00 29. " HSTART[29] ,Channel 29 Enable" "Disabled,Enabled" eventfld.long 0x00 28. " HSTART[28] ,Channel 28 Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 27. " HSTART[27] ,Channel 27 Enable" "Disabled,Enabled" eventfld.long 0x00 26. " HSTART[26] ,Channel 26 Enable" "Disabled,Enabled" eventfld.long 0x00 25. " HSTART[25] ,Channel 25 Enable" "Disabled,Enabled" eventfld.long 0x00 24. " HSTART[24] ,Channel 24 Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 23. " HSTART[23] ,Channel 23 Enable" "Disabled,Enabled" eventfld.long 0x00 22. " HSTART[22] ,Channel 22 Enable" "Disabled,Enabled" eventfld.long 0x00 21. " HSTART[21] ,Channel 21 Enable" "Disabled,Enabled" eventfld.long 0x00 20. " HSTART[20] ,Channel 20 Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " HSTART[19] ,Channel 19 Enable" "Disabled,Enabled" eventfld.long 0x00 18. " HSTART[18] ,Channel 18 Enable" "Disabled,Enabled" eventfld.long 0x00 17. " HSTART[17] ,Channel 17 Enable" "Disabled,Enabled" eventfld.long 0x00 16. " HSTART[16] ,Channel 16 Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 15. " HSTART[15] ,Channel 15 Enable" "Disabled,Enabled" eventfld.long 0x00 14. " HSTART[14] ,Channel 14 Enable" "Disabled,Enabled" eventfld.long 0x00 13. " HSTART[13] ,Channel 13 Enable" "Disabled,Enabled" eventfld.long 0x00 12. " HSTART[12] ,Channel 12 Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 11. " HSTART[11] ,Channel 11 Enable" "Disabled,Enabled" eventfld.long 0x00 10. " HSTART[10] ,Channel 10 Enable" "Disabled,Enabled" eventfld.long 0x00 9. " HSTART[9] ,Channel 9 Enable" "Disabled,Enabled" eventfld.long 0x00 8. " HSTART[8] ,Channel 8 Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " HSTART[7] ,Channel 7 Enable" "Disabled,Enabled" eventfld.long 0x00 6. " HSTART[6] ,Channel 6 Enable" "Disabled,Enabled" eventfld.long 0x00 5. " HSTART[5] ,Channel 5 Enable" "Disabled,Enabled" eventfld.long 0x00 4. " HSTART[4] ,Channel 4 Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 3. " HSTART[3] ,Channel 3 Enable" "Disabled,Enabled" eventfld.long 0x00 2. " HSTART[2] ,Channel 2 Enable" "Disabled,Enabled" eventfld.long 0x00 1. " HSTART[1] ,Channel 1 Enable" "Disabled,Enabled" eventfld.long 0x00 0. " HSTART[0] ,Channel 0 Enable" "Disabled,Enabled" line.long 0x04 "EVTOVR,Channel Event Override Register" bitfld.long 0x04 31. " EO[31] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 30. " EO[30] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 29. " EO[29] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 28. " EO[28] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x04 27. " EO[27] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 26. " EO[26] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 25. " EO[25] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 24. " EO[24] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x04 23. " EO[23] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 22. " EO[22] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 21. " EO[21] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 20. " EO[20] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x04 19. " EO[19] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 18. " EO[18] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 17. " EO[17] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 16. " EO[16] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x04 15. " EO[15] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 14. " EO[14] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 13. " EO[13] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 12. " EO[12] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x04 11. " EO[11] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 10. " EO[10] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 9. " EO[9] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 8. " EO[8] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x04 7. " EO[7] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 6. " EO[6] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 5. " EO[5] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 4. " EO[4] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x04 3. " EO[3] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 2. " EO[2] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 1. " EO[1] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x04 0. " EO[0] ,DMA Request Ignored by SDMA" "Not ignored,Ignored" hgroup.long 0x14++0x03 hide.long 0x00 "DSPOVR,Channel BP Override Register" group.long 0x18++0x07 line.long 0x00 "HOSTOVR,Channel AP Override Register" bitfld.long 0x00 31. " HO[31] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 30. " HO[30] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 29. " HO[29] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 28. " HO[28] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 27. " HO[27] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 26. " HO[26] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 25. " HO[25] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 24. " HO[24] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 23. " HO[23] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 22. " HO[22] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 21. " HO[21] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 20. " HO[20] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 19. " HO[19] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 18. " HO[18] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 17. " HO[17] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 16. " HO[16] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 15. " HO[15] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 14. " HO[14] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 13. " HO[13] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 12. " HO[12] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 11. " HO[11] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 10. " HO[10] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 9. " HO[9] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 8. " HO[8] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 7. " HO[7] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 6. " HO[6] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 5. " HO[5] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 4. " HO[4] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " HO[3] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 2. " HO[2] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 1. " HO[1] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" bitfld.long 0x00 0. " HO[0] ,AP Enable Ignored by SDMA" "Not ignored,Ignored" line.long 0x04 "EVTPEND,Channel Event Pending Register" eventfld.long 0x04 31. " EP[31] ,Channel 31 Event Pending" "Not pending,Pending" eventfld.long 0x04 30. " EP[30] ,Channel 30 Event Pending" "Not pending,Pending" eventfld.long 0x04 29. " EP[29] ,Channel 29 Event Pending" "Not pending,Pending" eventfld.long 0x04 28. " EP[28] ,Channel 28 Event Pending" "Not pending,Pending" textline " " eventfld.long 0x04 27. " EP[27] ,Channel 27 Event Pending" "Not pending,Pending" eventfld.long 0x04 26. " EP[26] ,Channel 26 Event Pending" "Not pending,Pending" eventfld.long 0x04 25. " EP[25] ,Channel 25 Event Pending" "Not pending,Pending" eventfld.long 0x04 24. " EP[24] ,Channel 24 Event Pending" "Not pending,Pending" textline " " eventfld.long 0x04 23. " EP[23] ,Channel 23 Event Pending" "Not pending,Pending" eventfld.long 0x04 22. " EP[22] ,Channel 22 Event Pending" "Not pending,Pending" eventfld.long 0x04 21. " EP[21] ,Channel 21 Event Pending" "Not pending,Pending" eventfld.long 0x04 20. " EP[20] ,Channel 20 Event Pending" "Not pending,Pending" textline " " eventfld.long 0x04 19. " EP[19] ,Channel 19 Event Pending" "Not pending,Pending" eventfld.long 0x04 18. " EP[18] ,Channel 18 Event Pending" "Not pending,Pending" eventfld.long 0x04 17. " EP[17] ,Channel 17 Event Pending" "Not pending,Pending" eventfld.long 0x04 16. " EP[16] ,Channel 16 Event Pending" "Not pending,Pending" textline " " eventfld.long 0x04 15. " EP[15] ,Channel 15 Event Pending" "Not pending,Pending" eventfld.long 0x04 14. " EP[14] ,Channel 14 Event Pending" "Not pending,Pending" eventfld.long 0x04 13. " EP[13] ,Channel 13 Event Pending" "Not pending,Pending" eventfld.long 0x04 12. " EP[12] ,Channel 12 Event Pending" "Not pending,Pending" textline " " eventfld.long 0x04 11. " EP[11] ,Channel 11 Event Pending" "Not pending,Pending" eventfld.long 0x04 10. " EP[10] ,Channel 10 Event Pending" "Not pending,Pending" eventfld.long 0x04 9. " EP[9] ,Channel 9 Event Pending" "Not pending,Pending" eventfld.long 0x04 8. " EP[8] ,Channel 8 Event Pending" "Not pending,Pending" textline " " eventfld.long 0x04 7. " EP[7] ,Channel 7 Event Pending" "Not pending,Pending" eventfld.long 0x04 6. " EP[6] ,Channel 6 Event Pending" "Not pending,Pending" eventfld.long 0x04 5. " EP[5] ,Channel 5 Event Pending" "Not pending,Pending" eventfld.long 0x04 4. " EP[4] ,Channel 4 Event Pending" "Not pending,Pending" textline " " eventfld.long 0x04 3. " EP[3] ,Channel 3 Event Pending" "Not pending,Pending" eventfld.long 0x04 2. " EP[2] ,Channel 2 Event Pending" "Not pending,Pending" eventfld.long 0x04 1. " EP[1] ,Channel 1 Event Pending" "Not pending,Pending" eventfld.long 0x04 0. " EP[0] ,Channel 0 Event Pending" "Not pending,Pending" rgroup.long 0x24++0x3 line.long 0x00 "RESET,Reset Register" bitfld.long 0x00 1. " RESCHED ,SDMA Reschedule as If a Script had Executed a Done Instruction" "Off,On" bitfld.long 0x00 0. " RESET ,Software Reset" "No effect,Reset" hgroup.long 0x28++0x03 hide.long 0x00 "EVTERR,DMA Request Error Register" in group.long 0x2C++0x03 line.long 0x00 "INTRMASK,Channel AP Interrupt Mask Flags Register" bitfld.long 0x00 31. " HIMASK[31] ,Channel 31 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 30. " HIMASK[30] ,Channel 30 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 29. " HIMASK[29] ,Channel 29 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 28. " HIMASK[28] ,Channel 28 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " HIMASK[27] ,Channel 27 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 26. " HIMASK[26] ,Channel 26 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 25. " HIMASK[25] ,Channel 25 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 24. " HIMASK[24] ,Channel 24 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " HIMASK[23] ,Channel 23 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 22. " HIMASK[22] ,Channel 22 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 21. " HIMASK[21] ,Channel 21 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 20. " HIMASK[20] ,Channel 20 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " HIMASK[19] ,Channel 19 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 18. " HIMASK[18] ,Channel 18 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 17. " HIMASK[17] ,Channel 17 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 16. " HIMASK[16] ,Channel 16 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " HIMASK[15] ,Channel 15 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 14. " HIMASK[14] ,Channel 14 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 13. " HIMASK[13] ,Channel 13 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 12. " HIMASK[12] ,Channel 12 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " HIMASK[11] ,Channel 11 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 10. " HIMASK[10] ,Channel 10 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 9. " HIMASK[9] ,Channel 9 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 8. " HIMASK[8] ,Channel 8 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " HIMASK[7] ,Channel 7 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 6. " HIMASK[6] ,Channel 6 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 5. " HIMASK[5] ,Channel 5 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 4. " HIMASK[4] ,Channel 4 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " HIMASK[3] ,Channel 3 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 2. " HIMASK[2] ,Channel 2 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 1. " HIMASK[1] ,Channel 1 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 0. " HIMASK[0] ,Channel 0 Interrupt Mask" "Masked,Not masked" rgroup.long 0x30++0x7 line.long 0x00 "PSW,Schedule Status Register" bitfld.long 0x00 13.--15. " NCP[2:0] ,Next Channel Priority" "No running channel,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " NCR[4:0] ,Next Channel Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " CCP[2:0] ,Current Channel Priority" "o running channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CCR[4:0] ,Current Channel Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EVTERRDBG,DMA Request Error Register for Debug" bitfld.long 0x04 31. " CHNERR[31] ,Channel 31 Error" "No error,Error" bitfld.long 0x04 30. " CHNERR[30] ,Channel 30 Error" "No error,Error" bitfld.long 0x04 29. " CHNERR[29] ,Channel 29 Error" "No error,Error" bitfld.long 0x04 28. " CHNERR[28] ,Channel 28 Error" "No error,Error" textline " " bitfld.long 0x04 27. " CHNERR[27] ,Channel 27 Error" "No error,Error" bitfld.long 0x04 26. " CHNERR[26] ,Channel 26 Error" "No error,Error" bitfld.long 0x04 25. " CHNERR[25] ,Channel 25 Error" "No error,Error" bitfld.long 0x04 24. " CHNERR[24] ,Channel 24 Error" "No error,Error" textline " " bitfld.long 0x04 23. " CHNERR[23] ,Channel 23 Error" "No error,Error" bitfld.long 0x04 22. " CHNERR[22] ,Channel 22 Error" "No error,Error" bitfld.long 0x04 21. " CHNERR[21] ,Channel 21 Error" "No error,Error" bitfld.long 0x04 20. " CHNERR[20] ,Channel 20 Error" "No error,Error" textline " " bitfld.long 0x04 19. " CHNERR[19] ,Channel 19 Error" "No error,Error" bitfld.long 0x04 18. " CHNERR[18] ,Channel 18 Error" "No error,Error" bitfld.long 0x04 17. " CHNERR[17] ,Channel 17 Error" "No error,Error" bitfld.long 0x04 16. " CHNERR[16] ,Channel 16 Error" "No error,Error" textline " " bitfld.long 0x04 15. " CHNERR[15] ,Channel 15 Error" "No error,Error" bitfld.long 0x04 14. " CHNERR[14] ,Channel 14 Error" "No error,Error" bitfld.long 0x04 13. " CHNERR[13] ,Channel 13 Error" "No error,Error" bitfld.long 0x04 12. " CHNERR[12] ,Channel 12 Error" "No error,Error" textline " " bitfld.long 0x04 11. " CHNERR[11] ,Channel 11 Error" "No error,Error" bitfld.long 0x04 10. " CHNERR[10] ,Channel 10 Error" "No error,Error" bitfld.long 0x04 9. " CHNERR[9] ,Channel 9 Error" "No error,Error" bitfld.long 0x04 8. " CHNERR[8] ,Channel 8 Error" "No error,Error" textline " " bitfld.long 0x04 7. " CHNERR[7] ,Channel 7 Error" "No error,Error" bitfld.long 0x04 6. " CHNERR[6] ,Channel 6 Error" "No error,Error" bitfld.long 0x04 5. " CHNERR[5] ,Channel 5 Error" "No error,Error" bitfld.long 0x04 4. " CHNERR[4] ,Channel 4 Error" "No error,Error" textline " " bitfld.long 0x04 3. " CHNERR[3] ,Channel 3 Error" "No error,Error" bitfld.long 0x04 2. " CHNERR[2] ,Channel 2 Error" "No error,Error" bitfld.long 0x04 1. " CHNERR[1] ,Channel 1 Error" "No error,Error" bitfld.long 0x04 0. " CHNERR[0] ,Channel 0 Error" "No error,Error" textline " " group.long 0x38++0x13 line.long 0x00 "CONFIG,Configuration Register" bitfld.long 0x00 12. " DSPDMA ,SDMA control mode" "Reset," bitfld.long 0x00 11. " RTDOBS ,Real-Time Debug Pins are Used" "Not used,Used" bitfld.long 0x00 4. " ACR ,AHB/SDMA Core Clock Ratio" "2x core freq,Core freq" bitfld.long 0x00 0.--1. " CSM ,Selects the Context Switch Mode" "Static,Dynamic low power,Dynamic with no loop,Dynamic" line.long 0x04 "SDMA_LOCK,SDMA Lock Register" bitfld.long 0x04 1. " SRESET_LOCK_CLR ,LOCK bit is cleared on a software reset" "Not cleared,Cleared" bitfld.long 0x04 0. " LOCK ,Access to update SDMA script memory" "Not locked,Locked" line.long 0x08 "ONCE_ENB,OnCE Enable Register" bitfld.long 0x08 0. " ENB ,OnCE Enable" "Disabled,Enabled" line.long 0x0c "ONCE_DATA,OnCE Data Register" line.long 0x10 "ONCE_INSTR,OnCE Instruction Register" hexmask.long.word 0x10 0.--15. 1. " INSTR ,Instruction Register of the OnCE JTAG Controller" rgroup.long 0x4c++0x03 line.long 0x00 "ONCE_STAT,OnCE Status Register" bitfld.long 0x00 12.--15. " PST[3:0] ,Processor Status" "Program,Data,Change of flow,Change of flow in loop,Debug,Functional unit,Sleep,Save,Program in sleep,Data in sleep,Change of flow in sleep,Change flow in loop in sleep,Debug in sleep,Functional unit in sleep,Sleep after reset,Restore" bitfld.long 0x00 11. " RCV ,RCV Flag" "Cleared,Set" bitfld.long 0x00 10. " EDR ,SDMA has Entered Debug Mode After an External Debug Request" "Normal,Debug" bitfld.long 0x00 9. " ODR ,SDMA has Entered Debug Mode After a OnCE Debug Request" "Normal,Debug" textline " " bitfld.long 0x00 8. " SWB ,SDMA has Entered Debug Mode After a Software Breakpoint" "Normal,Degug" bitfld.long 0x00 7. " MST ,OnCE is Controlled from the AP Peripheral Interface" "JTAG,AP" bitfld.long 0x00 2. " ECDR[2] ,Event Cell Debug Request from data_cond" "Not requested,Requested" bitfld.long 0x00 1. " ECDR[1] ,Event Cell Debug Request from addrb_cond" "Not requested,Requested" textline " " bitfld.long 0x00 0. " ECDR[0] ,Event Cell Debug Request from addra_cond" "Not requested,Requested" group.long 0x50++0x03 line.long 0x00 "ONCE_CMD,OnCE Command Register" bitfld.long 0x00 0.--3. " CMD ,Command" "Rstatus,Dmov,Exec_once,Run_core,Exec_core,Debug_rqst,Rbuffer,,,,,,,,," group.long 0x58++0x7 line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address Register" hexmask.long.word 0x00 0.--13. 1. " ILLINSTADDR ,Illegal Instruction Trap Address" line.long 0x04 "CHN0ADDR,Channel 0 Boot Address Register" bitfld.long 0x04 14. " SMSZ ,Scratch Memory Size" "24,32" hexmask.long.word 0x04 0.--13. 1. " CHN0ADDR ,Channel 0 Boot Address" textline " " rgroup.long 0x60++0x07 line.long 0x00 "EVT_MIRROR,DMA Requests Register" bitfld.long 0x00 31. " EVENTS[31] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 30. " EVENTS[30] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 29. " EVENTS[29] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 28. " EVENTS[28] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x00 27. " EVENTS[27] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 26. " EVENTS[26] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 25. " EVENTS[25] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 24. " EVENTS[24] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x00 23. " EVENTS[23] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 22. " EVENTS[22] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 21. " EVENTS[21] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 20. " EVENTS[20] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x00 19. " EVENTS[19] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 18. " EVENTS[18] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 17. " EVENTS[17] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 16. " EVENTS[16] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x00 15. " EVENTS[15] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 14. " EVENTS[14] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 13. " EVENTS[13] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 12. " EVENTS[12] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x00 11. " EVENTS[11] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 10. " EVENTS[10] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 9. " EVENTS[9] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 8. " EVENTS[8] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x00 7. " EVENTS[7] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 6. " EVENTS[6] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 5. " EVENTS[5] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 4. " EVENTS[4] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x00 3. " EVENTS[3] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 2. " EVENTS[2] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 1. " EVENTS[1] ,DMA Request" "Not requested,Requested" bitfld.long 0x00 0. " EVENTS[0] ,DMA Request" "Not requested,Requested" line.long 0x04 "EVT_MIRROR2,DMA Requests 2 Register" bitfld.long 0x04 15. " EVENTS[47] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 14. " EVENTS[46] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 13. " EVENTS[45] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 12. " EVENTS[44] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 11. " EVENTS[43] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 10. " EVENTS[42] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 9. " EVENTS[41] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 8. " EVENTS[40] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 7. " EVENTS[39] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 6. " EVENTS[38] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 5. " EVENTS[37] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 4. " EVENTS[36] ,DMA Request" "Not requested,Requested" textline " " bitfld.long 0x04 3. " EVENTS[35] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 2. " EVENTS[34] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 1. " EVENTS[33] ,DMA Request" "Not requested,Requested" bitfld.long 0x04 0. " EVENTS[32] ,DMA Request" "Not requested,Requested" group.long 0x70++0x7 line.long 0x00 "XTRIG_CONF1,Cross-Trigger Events Configuration Register 1" bitfld.long 0x00 30. " CNF3 ,Configuration of the SDMA" "Channel,DMA request" bitfld.long 0x00 24.--29. " NUM3[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22. " CNF2 ,Configuration of the SDMA" "Channel,DMA request" bitfld.long 0x00 16.--21. " NUM2[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 14. " CNF1 ,Configuration of the SDMA" "Channel,DMA request" bitfld.long 0x00 8.--13. " NUM1[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. " CNF0 ,Configuration of the SDMA" "Channel,DMA request" bitfld.long 0x00 0.--5. " NUM0[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "XTRIG_CONF2,Cross-Trigger Events Configuration Register 2" bitfld.long 0x04 30. " CNF7 ,Configuration of the SDMA" "Channel,DMA request" bitfld.long 0x04 24.--29. " NUM7[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 22. " CNF6 ,Configuration of the SDMA" "Channel,DMA request" bitfld.long 0x04 16.--21. " NUM6[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x04 14. " CNF5 ,Configuration of the SDMA" "Channel,DMA request" bitfld.long 0x04 8.--13. " NUM5[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 6. " CNF4 ,Configuration of the SDMA" "Channel,DMA request" bitfld.long 0x04 0.--5. " NUM4[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("iMX6*")) tree "Channel Priority Registers" group.long 0x100++0x7F line.long 0x0 "CHNPRI0 ,Channel Priority 0 Register" bitfld.long 0x0 0.--2. " CHNPRI0 ,Channel 0 priority" ",1,2,3,4,5,6,7" line.long 0x4 "CHNPRI1 ,Channel Priority 1 Register" bitfld.long 0x4 0.--2. " CHNPRI1 ,Channel 1 priority" ",1,2,3,4,5,6,7" line.long 0x8 "CHNPRI2 ,Channel Priority 2 Register" bitfld.long 0x8 0.--2. " CHNPRI2 ,Channel 2 priority" ",1,2,3,4,5,6,7" line.long 0xC "CHNPRI3 ,Channel Priority 3 Register" bitfld.long 0xC 0.--2. " CHNPRI3 ,Channel 3 priority" ",1,2,3,4,5,6,7" line.long 0x10 "CHNPRI4 ,Channel Priority 4 Register" bitfld.long 0x10 0.--2. " CHNPRI4 ,Channel 4 priority" ",1,2,3,4,5,6,7" line.long 0x14 "CHNPRI5 ,Channel Priority 5 Register" bitfld.long 0x14 0.--2. " CHNPRI5 ,Channel 5 priority" ",1,2,3,4,5,6,7" line.long 0x18 "CHNPRI6 ,Channel Priority 6 Register" bitfld.long 0x18 0.--2. " CHNPRI6 ,Channel 6 priority" ",1,2,3,4,5,6,7" line.long 0x1C "CHNPRI7 ,Channel Priority 7 Register" bitfld.long 0x1C 0.--2. " CHNPRI7 ,Channel 7 priority" ",1,2,3,4,5,6,7" line.long 0x20 "CHNPRI8 ,Channel Priority 8 Register" bitfld.long 0x20 0.--2. " CHNPRI8 ,Channel 8 priority" ",1,2,3,4,5,6,7" line.long 0x24 "CHNPRI9 ,Channel Priority 9 Register" bitfld.long 0x24 0.--2. " CHNPRI9 ,Channel 9 priority" ",1,2,3,4,5,6,7" line.long 0x28 "CHNPRI10,Channel Priority 10 Register" bitfld.long 0x28 0.--2. " CHNPRI10 ,Channel 10 priority" ",1,2,3,4,5,6,7" line.long 0x2C "CHNPRI11,Channel Priority 11 Register" bitfld.long 0x2C 0.--2. " CHNPRI11 ,Channel 11 priority" ",1,2,3,4,5,6,7" line.long 0x30 "CHNPRI12,Channel Priority 12 Register" bitfld.long 0x30 0.--2. " CHNPRI12 ,Channel 12 priority" ",1,2,3,4,5,6,7" line.long 0x34 "CHNPRI13,Channel Priority 13 Register" bitfld.long 0x34 0.--2. " CHNPRI13 ,Channel 13 priority" ",1,2,3,4,5,6,7" line.long 0x38 "CHNPRI14,Channel Priority 14 Register" bitfld.long 0x38 0.--2. " CHNPRI14 ,Channel 14 priority" ",1,2,3,4,5,6,7" line.long 0x3C "CHNPRI15,Channel Priority 15 Register" bitfld.long 0x3C 0.--2. " CHNPRI15 ,Channel 15 priority" ",1,2,3,4,5,6,7" line.long 0x40 "CHNPRI16,Channel Priority 16 Register" bitfld.long 0x40 0.--2. " CHNPRI16 ,Channel 16 priority" ",1,2,3,4,5,6,7" line.long 0x44 "CHNPRI17,Channel Priority 17 Register" bitfld.long 0x44 0.--2. " CHNPRI17 ,Channel 17 priority" ",1,2,3,4,5,6,7" line.long 0x48 "CHNPRI18,Channel Priority 18 Register" bitfld.long 0x48 0.--2. " CHNPRI18 ,Channel 18 priority" ",1,2,3,4,5,6,7" line.long 0x4C "CHNPRI19,Channel Priority 19 Register" bitfld.long 0x4C 0.--2. " CHNPRI19 ,Channel 19 priority" ",1,2,3,4,5,6,7" line.long 0x50 "CHNPRI20,Channel Priority 20 Register" bitfld.long 0x50 0.--2. " CHNPRI20 ,Channel 20 priority" ",1,2,3,4,5,6,7" line.long 0x54 "CHNPRI21,Channel Priority 21 Register" bitfld.long 0x54 0.--2. " CHNPRI21 ,Channel 21 priority" ",1,2,3,4,5,6,7" line.long 0x58 "CHNPRI22,Channel Priority 22 Register" bitfld.long 0x58 0.--2. " CHNPRI22 ,Channel 22 priority" ",1,2,3,4,5,6,7" line.long 0x5C "CHNPRI23,Channel Priority 23 Register" bitfld.long 0x5C 0.--2. " CHNPRI23 ,Channel 23 priority" ",1,2,3,4,5,6,7" line.long 0x60 "CHNPRI24,Channel Priority 24 Register" bitfld.long 0x60 0.--2. " CHNPRI24 ,Channel 24 priority" ",1,2,3,4,5,6,7" line.long 0x64 "CHNPRI25,Channel Priority 25 Register" bitfld.long 0x64 0.--2. " CHNPRI25 ,Channel 25 priority" ",1,2,3,4,5,6,7" line.long 0x68 "CHNPRI26,Channel Priority 26 Register" bitfld.long 0x68 0.--2. " CHNPRI26 ,Channel 26 priority" ",1,2,3,4,5,6,7" line.long 0x6C "CHNPRI27,Channel Priority 27 Register" bitfld.long 0x6C 0.--2. " CHNPRI27 ,Channel 27 priority" ",1,2,3,4,5,6,7" line.long 0x70 "CHNPRI28,Channel Priority 28 Register" bitfld.long 0x70 0.--2. " CHNPRI28 ,Channel 28 priority" ",1,2,3,4,5,6,7" line.long 0x74 "CHNPRI29,Channel Priority 29 Register" bitfld.long 0x74 0.--2. " CHNPRI29 ,Channel 29 priority" ",1,2,3,4,5,6,7" line.long 0x78 "CHNPRI30,Channel Priority 30 Register" bitfld.long 0x78 0.--2. " CHNPRI30 ,Channel 30 priority" ",1,2,3,4,5,6,7" line.long 0x7C "CHNPRI31,Channel Priority 31 Register" bitfld.long 0x7C 0.--2. " CHNPRI31 ,Channel 31 priority" ",1,2,3,4,5,6,7" tree.end endif tree "Channel Enable RAM Registers" group.long 0x200++0xBF line.long 0x0 "CHNENBL0 ,Channel 0 Enable RAM" bitfld.long 0x0 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 0 " "Disabled,Enabled" textline " " bitfld.long 0x0 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 0 " "Disabled,Enabled" textline " " bitfld.long 0x0 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 0 " "Disabled,Enabled" textline " " bitfld.long 0x0 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 0 " "Disabled,Enabled" textline " " bitfld.long 0x0 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 0 " "Disabled,Enabled" textline " " bitfld.long 0x0 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 0 " "Disabled,Enabled" textline " " bitfld.long 0x0 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 0 " "Disabled,Enabled" textline " " bitfld.long 0x0 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 0 " "Disabled,Enabled" bitfld.long 0x0 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 0 " "Disabled,Enabled" line.long 0x4 "CHNENBL1 ,Channel 1 Enable RAM" bitfld.long 0x4 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 1 " "Disabled,Enabled" textline " " bitfld.long 0x4 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 1 " "Disabled,Enabled" textline " " bitfld.long 0x4 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 1 " "Disabled,Enabled" textline " " bitfld.long 0x4 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 1 " "Disabled,Enabled" textline " " bitfld.long 0x4 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 1 " "Disabled,Enabled" textline " " bitfld.long 0x4 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 1 " "Disabled,Enabled" textline " " bitfld.long 0x4 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 1 " "Disabled,Enabled" textline " " bitfld.long 0x4 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 1 " "Disabled,Enabled" bitfld.long 0x4 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 1 " "Disabled,Enabled" line.long 0x8 "CHNENBL2 ,Channel 2 Enable RAM" bitfld.long 0x8 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 2 " "Disabled,Enabled" textline " " bitfld.long 0x8 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 2 " "Disabled,Enabled" textline " " bitfld.long 0x8 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 2 " "Disabled,Enabled" textline " " bitfld.long 0x8 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 2 " "Disabled,Enabled" textline " " bitfld.long 0x8 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 2 " "Disabled,Enabled" textline " " bitfld.long 0x8 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 2 " "Disabled,Enabled" textline " " bitfld.long 0x8 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 2 " "Disabled,Enabled" textline " " bitfld.long 0x8 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 2 " "Disabled,Enabled" bitfld.long 0x8 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 2 " "Disabled,Enabled" line.long 0xC "CHNENBL3 ,Channel 3 Enable RAM" bitfld.long 0xC 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 3 " "Disabled,Enabled" textline " " bitfld.long 0xC 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 3 " "Disabled,Enabled" textline " " bitfld.long 0xC 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 3 " "Disabled,Enabled" textline " " bitfld.long 0xC 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 3 " "Disabled,Enabled" textline " " bitfld.long 0xC 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 3 " "Disabled,Enabled" textline " " bitfld.long 0xC 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 3 " "Disabled,Enabled" textline " " bitfld.long 0xC 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 3 " "Disabled,Enabled" textline " " bitfld.long 0xC 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 3 " "Disabled,Enabled" bitfld.long 0xC 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 3 " "Disabled,Enabled" line.long 0x10 "CHNENBL4 ,Channel 4 Enable RAM" bitfld.long 0x10 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 4 " "Disabled,Enabled" textline " " bitfld.long 0x10 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 4 " "Disabled,Enabled" textline " " bitfld.long 0x10 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 4 " "Disabled,Enabled" textline " " bitfld.long 0x10 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 4 " "Disabled,Enabled" textline " " bitfld.long 0x10 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 4 " "Disabled,Enabled" textline " " bitfld.long 0x10 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 4 " "Disabled,Enabled" textline " " bitfld.long 0x10 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 4 " "Disabled,Enabled" textline " " bitfld.long 0x10 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 4 " "Disabled,Enabled" bitfld.long 0x10 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 4 " "Disabled,Enabled" line.long 0x14 "CHNENBL5 ,Channel 5 Enable RAM" bitfld.long 0x14 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 5 " "Disabled,Enabled" textline " " bitfld.long 0x14 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 5 " "Disabled,Enabled" textline " " bitfld.long 0x14 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 5 " "Disabled,Enabled" textline " " bitfld.long 0x14 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 5 " "Disabled,Enabled" textline " " bitfld.long 0x14 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 5 " "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 5 " "Disabled,Enabled" textline " " bitfld.long 0x14 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 5 " "Disabled,Enabled" textline " " bitfld.long 0x14 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 5 " "Disabled,Enabled" bitfld.long 0x14 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 5 " "Disabled,Enabled" line.long 0x18 "CHNENBL6 ,Channel 6 Enable RAM" bitfld.long 0x18 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 6 " "Disabled,Enabled" textline " " bitfld.long 0x18 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 6 " "Disabled,Enabled" textline " " bitfld.long 0x18 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 6 " "Disabled,Enabled" textline " " bitfld.long 0x18 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 6 " "Disabled,Enabled" textline " " bitfld.long 0x18 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 6 " "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 6 " "Disabled,Enabled" textline " " bitfld.long 0x18 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 6 " "Disabled,Enabled" textline " " bitfld.long 0x18 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 6 " "Disabled,Enabled" bitfld.long 0x18 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 6 " "Disabled,Enabled" line.long 0x1C "CHNENBL7 ,Channel 7 Enable RAM" bitfld.long 0x1C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 7 " "Disabled,Enabled" textline " " bitfld.long 0x1C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 7 " "Disabled,Enabled" textline " " bitfld.long 0x1C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 7 " "Disabled,Enabled" textline " " bitfld.long 0x1C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 7 " "Disabled,Enabled" textline " " bitfld.long 0x1C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 7 " "Disabled,Enabled" textline " " bitfld.long 0x1C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 7 " "Disabled,Enabled" textline " " bitfld.long 0x1C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 7 " "Disabled,Enabled" textline " " bitfld.long 0x1C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 7 " "Disabled,Enabled" bitfld.long 0x1C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 7 " "Disabled,Enabled" line.long 0x20 "CHNENBL8 ,Channel 8 Enable RAM" bitfld.long 0x20 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 8 " "Disabled,Enabled" textline " " bitfld.long 0x20 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 8 " "Disabled,Enabled" textline " " bitfld.long 0x20 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 8 " "Disabled,Enabled" textline " " bitfld.long 0x20 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 8 " "Disabled,Enabled" textline " " bitfld.long 0x20 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 8 " "Disabled,Enabled" textline " " bitfld.long 0x20 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 8 " "Disabled,Enabled" textline " " bitfld.long 0x20 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 8 " "Disabled,Enabled" textline " " bitfld.long 0x20 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 8 " "Disabled,Enabled" bitfld.long 0x20 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 8 " "Disabled,Enabled" line.long 0x24 "CHNENBL9 ,Channel 9 Enable RAM" bitfld.long 0x24 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 9 " "Disabled,Enabled" textline " " bitfld.long 0x24 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 9 " "Disabled,Enabled" textline " " bitfld.long 0x24 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 9 " "Disabled,Enabled" textline " " bitfld.long 0x24 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 9 " "Disabled,Enabled" textline " " bitfld.long 0x24 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 9 " "Disabled,Enabled" textline " " bitfld.long 0x24 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 9 " "Disabled,Enabled" textline " " bitfld.long 0x24 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 9 " "Disabled,Enabled" textline " " bitfld.long 0x24 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 9 " "Disabled,Enabled" bitfld.long 0x24 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 9 " "Disabled,Enabled" line.long 0x28 "CHNENBL10,Channel 10 Enable RAM" bitfld.long 0x28 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 10" "Disabled,Enabled" textline " " bitfld.long 0x28 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 10" "Disabled,Enabled" textline " " bitfld.long 0x28 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 10" "Disabled,Enabled" textline " " bitfld.long 0x28 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 10" "Disabled,Enabled" textline " " bitfld.long 0x28 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 10" "Disabled,Enabled" textline " " bitfld.long 0x28 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 10" "Disabled,Enabled" textline " " bitfld.long 0x28 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 10" "Disabled,Enabled" textline " " bitfld.long 0x28 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 10" "Disabled,Enabled" bitfld.long 0x28 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 10" "Disabled,Enabled" line.long 0x2C "CHNENBL11,Channel 11 Enable RAM" bitfld.long 0x2C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 11" "Disabled,Enabled" textline " " bitfld.long 0x2C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 11" "Disabled,Enabled" textline " " bitfld.long 0x2C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 11" "Disabled,Enabled" textline " " bitfld.long 0x2C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 11" "Disabled,Enabled" textline " " bitfld.long 0x2C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 11" "Disabled,Enabled" textline " " bitfld.long 0x2C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 11" "Disabled,Enabled" textline " " bitfld.long 0x2C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 11" "Disabled,Enabled" textline " " bitfld.long 0x2C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 11" "Disabled,Enabled" bitfld.long 0x2C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 11" "Disabled,Enabled" line.long 0x30 "CHNENBL12,Channel 12 Enable RAM" bitfld.long 0x30 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 12" "Disabled,Enabled" textline " " bitfld.long 0x30 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 12" "Disabled,Enabled" textline " " bitfld.long 0x30 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 12" "Disabled,Enabled" textline " " bitfld.long 0x30 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 12" "Disabled,Enabled" textline " " bitfld.long 0x30 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 12" "Disabled,Enabled" textline " " bitfld.long 0x30 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 12" "Disabled,Enabled" textline " " bitfld.long 0x30 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 12" "Disabled,Enabled" textline " " bitfld.long 0x30 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 12" "Disabled,Enabled" bitfld.long 0x30 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 12" "Disabled,Enabled" line.long 0x34 "CHNENBL13,Channel 13 Enable RAM" bitfld.long 0x34 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 13" "Disabled,Enabled" textline " " bitfld.long 0x34 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 13" "Disabled,Enabled" textline " " bitfld.long 0x34 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 13" "Disabled,Enabled" textline " " bitfld.long 0x34 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 13" "Disabled,Enabled" textline " " bitfld.long 0x34 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 13" "Disabled,Enabled" textline " " bitfld.long 0x34 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 13" "Disabled,Enabled" textline " " bitfld.long 0x34 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 13" "Disabled,Enabled" textline " " bitfld.long 0x34 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 13" "Disabled,Enabled" bitfld.long 0x34 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 13" "Disabled,Enabled" line.long 0x38 "CHNENBL14,Channel 14 Enable RAM" bitfld.long 0x38 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 14" "Disabled,Enabled" textline " " bitfld.long 0x38 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 14" "Disabled,Enabled" textline " " bitfld.long 0x38 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 14" "Disabled,Enabled" textline " " bitfld.long 0x38 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 14" "Disabled,Enabled" textline " " bitfld.long 0x38 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 14" "Disabled,Enabled" textline " " bitfld.long 0x38 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 14" "Disabled,Enabled" textline " " bitfld.long 0x38 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 14" "Disabled,Enabled" textline " " bitfld.long 0x38 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 14" "Disabled,Enabled" bitfld.long 0x38 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 14" "Disabled,Enabled" line.long 0x3C "CHNENBL15,Channel 15 Enable RAM" bitfld.long 0x3C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 15" "Disabled,Enabled" textline " " bitfld.long 0x3C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 15" "Disabled,Enabled" textline " " bitfld.long 0x3C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 15" "Disabled,Enabled" textline " " bitfld.long 0x3C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 15" "Disabled,Enabled" textline " " bitfld.long 0x3C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 15" "Disabled,Enabled" textline " " bitfld.long 0x3C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 15" "Disabled,Enabled" textline " " bitfld.long 0x3C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 15" "Disabled,Enabled" textline " " bitfld.long 0x3C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 15" "Disabled,Enabled" bitfld.long 0x3C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 15" "Disabled,Enabled" line.long 0x40 "CHNENBL16,Channel 16 Enable RAM" bitfld.long 0x40 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 16" "Disabled,Enabled" textline " " bitfld.long 0x40 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 16" "Disabled,Enabled" textline " " bitfld.long 0x40 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 16" "Disabled,Enabled" textline " " bitfld.long 0x40 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 16" "Disabled,Enabled" textline " " bitfld.long 0x40 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 16" "Disabled,Enabled" textline " " bitfld.long 0x40 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 16" "Disabled,Enabled" textline " " bitfld.long 0x40 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 16" "Disabled,Enabled" textline " " bitfld.long 0x40 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 16" "Disabled,Enabled" bitfld.long 0x40 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 16" "Disabled,Enabled" line.long 0x44 "CHNENBL17,Channel 17 Enable RAM" bitfld.long 0x44 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 17" "Disabled,Enabled" textline " " bitfld.long 0x44 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 17" "Disabled,Enabled" textline " " bitfld.long 0x44 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 17" "Disabled,Enabled" textline " " bitfld.long 0x44 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 17" "Disabled,Enabled" textline " " bitfld.long 0x44 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 17" "Disabled,Enabled" textline " " bitfld.long 0x44 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 17" "Disabled,Enabled" textline " " bitfld.long 0x44 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 17" "Disabled,Enabled" textline " " bitfld.long 0x44 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 17" "Disabled,Enabled" bitfld.long 0x44 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 17" "Disabled,Enabled" line.long 0x48 "CHNENBL18,Channel 18 Enable RAM" bitfld.long 0x48 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 18" "Disabled,Enabled" textline " " bitfld.long 0x48 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 18" "Disabled,Enabled" textline " " bitfld.long 0x48 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 18" "Disabled,Enabled" textline " " bitfld.long 0x48 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 18" "Disabled,Enabled" textline " " bitfld.long 0x48 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 18" "Disabled,Enabled" textline " " bitfld.long 0x48 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 18" "Disabled,Enabled" textline " " bitfld.long 0x48 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 18" "Disabled,Enabled" textline " " bitfld.long 0x48 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 18" "Disabled,Enabled" bitfld.long 0x48 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 18" "Disabled,Enabled" line.long 0x4C "CHNENBL19,Channel 19 Enable RAM" bitfld.long 0x4C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 19" "Disabled,Enabled" textline " " bitfld.long 0x4C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 19" "Disabled,Enabled" textline " " bitfld.long 0x4C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 19" "Disabled,Enabled" textline " " bitfld.long 0x4C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 19" "Disabled,Enabled" textline " " bitfld.long 0x4C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 19" "Disabled,Enabled" textline " " bitfld.long 0x4C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 19" "Disabled,Enabled" textline " " bitfld.long 0x4C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 19" "Disabled,Enabled" textline " " bitfld.long 0x4C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 19" "Disabled,Enabled" bitfld.long 0x4C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 19" "Disabled,Enabled" line.long 0x50 "CHNENBL20,Channel 20 Enable RAM" bitfld.long 0x50 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 20" "Disabled,Enabled" textline " " bitfld.long 0x50 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 20" "Disabled,Enabled" textline " " bitfld.long 0x50 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 20" "Disabled,Enabled" textline " " bitfld.long 0x50 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 20" "Disabled,Enabled" textline " " bitfld.long 0x50 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 20" "Disabled,Enabled" textline " " bitfld.long 0x50 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 20" "Disabled,Enabled" textline " " bitfld.long 0x50 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 20" "Disabled,Enabled" textline " " bitfld.long 0x50 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 20" "Disabled,Enabled" bitfld.long 0x50 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 20" "Disabled,Enabled" line.long 0x54 "CHNENBL21,Channel 21 Enable RAM" bitfld.long 0x54 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 21" "Disabled,Enabled" textline " " bitfld.long 0x54 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 21" "Disabled,Enabled" textline " " bitfld.long 0x54 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 21" "Disabled,Enabled" textline " " bitfld.long 0x54 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 21" "Disabled,Enabled" textline " " bitfld.long 0x54 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 21" "Disabled,Enabled" textline " " bitfld.long 0x54 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 21" "Disabled,Enabled" textline " " bitfld.long 0x54 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 21" "Disabled,Enabled" textline " " bitfld.long 0x54 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 21" "Disabled,Enabled" bitfld.long 0x54 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 21" "Disabled,Enabled" line.long 0x58 "CHNENBL22,Channel 22 Enable RAM" bitfld.long 0x58 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 22" "Disabled,Enabled" textline " " bitfld.long 0x58 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 22" "Disabled,Enabled" textline " " bitfld.long 0x58 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 22" "Disabled,Enabled" textline " " bitfld.long 0x58 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 22" "Disabled,Enabled" textline " " bitfld.long 0x58 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 22" "Disabled,Enabled" textline " " bitfld.long 0x58 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 22" "Disabled,Enabled" textline " " bitfld.long 0x58 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 22" "Disabled,Enabled" textline " " bitfld.long 0x58 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 22" "Disabled,Enabled" bitfld.long 0x58 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 22" "Disabled,Enabled" line.long 0x5C "CHNENBL23,Channel 23 Enable RAM" bitfld.long 0x5C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 23" "Disabled,Enabled" textline " " bitfld.long 0x5C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 23" "Disabled,Enabled" textline " " bitfld.long 0x5C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 23" "Disabled,Enabled" textline " " bitfld.long 0x5C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 23" "Disabled,Enabled" textline " " bitfld.long 0x5C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 23" "Disabled,Enabled" textline " " bitfld.long 0x5C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 23" "Disabled,Enabled" textline " " bitfld.long 0x5C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 23" "Disabled,Enabled" textline " " bitfld.long 0x5C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 23" "Disabled,Enabled" bitfld.long 0x5C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 23" "Disabled,Enabled" line.long 0x60 "CHNENBL24,Channel 24 Enable RAM" bitfld.long 0x60 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 24" "Disabled,Enabled" textline " " bitfld.long 0x60 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 24" "Disabled,Enabled" textline " " bitfld.long 0x60 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 24" "Disabled,Enabled" textline " " bitfld.long 0x60 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 24" "Disabled,Enabled" textline " " bitfld.long 0x60 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 24" "Disabled,Enabled" textline " " bitfld.long 0x60 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 24" "Disabled,Enabled" textline " " bitfld.long 0x60 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 24" "Disabled,Enabled" textline " " bitfld.long 0x60 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 24" "Disabled,Enabled" bitfld.long 0x60 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 24" "Disabled,Enabled" line.long 0x64 "CHNENBL25,Channel 25 Enable RAM" bitfld.long 0x64 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 25" "Disabled,Enabled" textline " " bitfld.long 0x64 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 25" "Disabled,Enabled" textline " " bitfld.long 0x64 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 25" "Disabled,Enabled" textline " " bitfld.long 0x64 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 25" "Disabled,Enabled" textline " " bitfld.long 0x64 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 25" "Disabled,Enabled" textline " " bitfld.long 0x64 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 25" "Disabled,Enabled" textline " " bitfld.long 0x64 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 25" "Disabled,Enabled" textline " " bitfld.long 0x64 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 25" "Disabled,Enabled" bitfld.long 0x64 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 25" "Disabled,Enabled" line.long 0x68 "CHNENBL26,Channel 26 Enable RAM" bitfld.long 0x68 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 26" "Disabled,Enabled" textline " " bitfld.long 0x68 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 26" "Disabled,Enabled" textline " " bitfld.long 0x68 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 26" "Disabled,Enabled" textline " " bitfld.long 0x68 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 26" "Disabled,Enabled" textline " " bitfld.long 0x68 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 26" "Disabled,Enabled" textline " " bitfld.long 0x68 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 26" "Disabled,Enabled" textline " " bitfld.long 0x68 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 26" "Disabled,Enabled" textline " " bitfld.long 0x68 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 26" "Disabled,Enabled" bitfld.long 0x68 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 26" "Disabled,Enabled" line.long 0x6C "CHNENBL27,Channel 27 Enable RAM" bitfld.long 0x6C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 27" "Disabled,Enabled" textline " " bitfld.long 0x6C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 27" "Disabled,Enabled" textline " " bitfld.long 0x6C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 27" "Disabled,Enabled" textline " " bitfld.long 0x6C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 27" "Disabled,Enabled" textline " " bitfld.long 0x6C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 27" "Disabled,Enabled" textline " " bitfld.long 0x6C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 27" "Disabled,Enabled" textline " " bitfld.long 0x6C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 27" "Disabled,Enabled" textline " " bitfld.long 0x6C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 27" "Disabled,Enabled" bitfld.long 0x6C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 27" "Disabled,Enabled" line.long 0x70 "CHNENBL28,Channel 28 Enable RAM" bitfld.long 0x70 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 28" "Disabled,Enabled" textline " " bitfld.long 0x70 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 28" "Disabled,Enabled" textline " " bitfld.long 0x70 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 28" "Disabled,Enabled" textline " " bitfld.long 0x70 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 28" "Disabled,Enabled" textline " " bitfld.long 0x70 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 28" "Disabled,Enabled" textline " " bitfld.long 0x70 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 28" "Disabled,Enabled" textline " " bitfld.long 0x70 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 28" "Disabled,Enabled" textline " " bitfld.long 0x70 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 28" "Disabled,Enabled" bitfld.long 0x70 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 28" "Disabled,Enabled" line.long 0x74 "CHNENBL29,Channel 29 Enable RAM" bitfld.long 0x74 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 29" "Disabled,Enabled" textline " " bitfld.long 0x74 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 29" "Disabled,Enabled" textline " " bitfld.long 0x74 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 29" "Disabled,Enabled" textline " " bitfld.long 0x74 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 29" "Disabled,Enabled" textline " " bitfld.long 0x74 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 29" "Disabled,Enabled" textline " " bitfld.long 0x74 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 29" "Disabled,Enabled" textline " " bitfld.long 0x74 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 29" "Disabled,Enabled" textline " " bitfld.long 0x74 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 29" "Disabled,Enabled" bitfld.long 0x74 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 29" "Disabled,Enabled" line.long 0x78 "CHNENBL30,Channel 30 Enable RAM" bitfld.long 0x78 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 30" "Disabled,Enabled" textline " " bitfld.long 0x78 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 30" "Disabled,Enabled" textline " " bitfld.long 0x78 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 30" "Disabled,Enabled" textline " " bitfld.long 0x78 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 30" "Disabled,Enabled" textline " " bitfld.long 0x78 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 30" "Disabled,Enabled" textline " " bitfld.long 0x78 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 30" "Disabled,Enabled" textline " " bitfld.long 0x78 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 30" "Disabled,Enabled" textline " " bitfld.long 0x78 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 30" "Disabled,Enabled" bitfld.long 0x78 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 30" "Disabled,Enabled" line.long 0x7C "CHNENBL31,Channel 31 Enable RAM" bitfld.long 0x7C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 31" "Disabled,Enabled" textline " " bitfld.long 0x7C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 31" "Disabled,Enabled" textline " " bitfld.long 0x7C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 31" "Disabled,Enabled" textline " " bitfld.long 0x7C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 31" "Disabled,Enabled" textline " " bitfld.long 0x7C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 31" "Disabled,Enabled" textline " " bitfld.long 0x7C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 31" "Disabled,Enabled" textline " " bitfld.long 0x7C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 31" "Disabled,Enabled" textline " " bitfld.long 0x7C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 31" "Disabled,Enabled" bitfld.long 0x7C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 31" "Disabled,Enabled" line.long 0x80 "CHNENBL32,Channel 32 Enable RAM" bitfld.long 0x80 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 32" "Disabled,Enabled" textline " " bitfld.long 0x80 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 32" "Disabled,Enabled" textline " " bitfld.long 0x80 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 32" "Disabled,Enabled" textline " " bitfld.long 0x80 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 32" "Disabled,Enabled" textline " " bitfld.long 0x80 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 32" "Disabled,Enabled" textline " " bitfld.long 0x80 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 32" "Disabled,Enabled" textline " " bitfld.long 0x80 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 32" "Disabled,Enabled" textline " " bitfld.long 0x80 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 32" "Disabled,Enabled" bitfld.long 0x80 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 32" "Disabled,Enabled" line.long 0x84 "CHNENBL33,Channel 33 Enable RAM" bitfld.long 0x84 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 33" "Disabled,Enabled" textline " " bitfld.long 0x84 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 33" "Disabled,Enabled" textline " " bitfld.long 0x84 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 33" "Disabled,Enabled" textline " " bitfld.long 0x84 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 33" "Disabled,Enabled" textline " " bitfld.long 0x84 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 33" "Disabled,Enabled" textline " " bitfld.long 0x84 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 33" "Disabled,Enabled" textline " " bitfld.long 0x84 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 33" "Disabled,Enabled" textline " " bitfld.long 0x84 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 33" "Disabled,Enabled" bitfld.long 0x84 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 33" "Disabled,Enabled" line.long 0x88 "CHNENBL34,Channel 34 Enable RAM" bitfld.long 0x88 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 34" "Disabled,Enabled" textline " " bitfld.long 0x88 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 34" "Disabled,Enabled" textline " " bitfld.long 0x88 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 34" "Disabled,Enabled" textline " " bitfld.long 0x88 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 34" "Disabled,Enabled" textline " " bitfld.long 0x88 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 34" "Disabled,Enabled" textline " " bitfld.long 0x88 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 34" "Disabled,Enabled" textline " " bitfld.long 0x88 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 34" "Disabled,Enabled" textline " " bitfld.long 0x88 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 34" "Disabled,Enabled" bitfld.long 0x88 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 34" "Disabled,Enabled" line.long 0x8C "CHNENBL35,Channel 35 Enable RAM" bitfld.long 0x8C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 35" "Disabled,Enabled" textline " " bitfld.long 0x8C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 35" "Disabled,Enabled" textline " " bitfld.long 0x8C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 35" "Disabled,Enabled" textline " " bitfld.long 0x8C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 35" "Disabled,Enabled" textline " " bitfld.long 0x8C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 35" "Disabled,Enabled" textline " " bitfld.long 0x8C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 35" "Disabled,Enabled" textline " " bitfld.long 0x8C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 35" "Disabled,Enabled" textline " " bitfld.long 0x8C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 35" "Disabled,Enabled" bitfld.long 0x8C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 35" "Disabled,Enabled" line.long 0x90 "CHNENBL36,Channel 36 Enable RAM" bitfld.long 0x90 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 36" "Disabled,Enabled" textline " " bitfld.long 0x90 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 36" "Disabled,Enabled" textline " " bitfld.long 0x90 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 36" "Disabled,Enabled" textline " " bitfld.long 0x90 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 36" "Disabled,Enabled" textline " " bitfld.long 0x90 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 36" "Disabled,Enabled" textline " " bitfld.long 0x90 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 36" "Disabled,Enabled" textline " " bitfld.long 0x90 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 36" "Disabled,Enabled" textline " " bitfld.long 0x90 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 36" "Disabled,Enabled" bitfld.long 0x90 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 36" "Disabled,Enabled" line.long 0x94 "CHNENBL37,Channel 37 Enable RAM" bitfld.long 0x94 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 37" "Disabled,Enabled" textline " " bitfld.long 0x94 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 37" "Disabled,Enabled" textline " " bitfld.long 0x94 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 37" "Disabled,Enabled" textline " " bitfld.long 0x94 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 37" "Disabled,Enabled" textline " " bitfld.long 0x94 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 37" "Disabled,Enabled" textline " " bitfld.long 0x94 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 37" "Disabled,Enabled" textline " " bitfld.long 0x94 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 37" "Disabled,Enabled" textline " " bitfld.long 0x94 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 37" "Disabled,Enabled" bitfld.long 0x94 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 37" "Disabled,Enabled" line.long 0x98 "CHNENBL38,Channel 38 Enable RAM" bitfld.long 0x98 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 38" "Disabled,Enabled" textline " " bitfld.long 0x98 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 38" "Disabled,Enabled" textline " " bitfld.long 0x98 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 38" "Disabled,Enabled" textline " " bitfld.long 0x98 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 38" "Disabled,Enabled" textline " " bitfld.long 0x98 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 38" "Disabled,Enabled" textline " " bitfld.long 0x98 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 38" "Disabled,Enabled" textline " " bitfld.long 0x98 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 38" "Disabled,Enabled" textline " " bitfld.long 0x98 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 38" "Disabled,Enabled" bitfld.long 0x98 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 38" "Disabled,Enabled" line.long 0x9C "CHNENBL39,Channel 39 Enable RAM" bitfld.long 0x9C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 39" "Disabled,Enabled" textline " " bitfld.long 0x9C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 39" "Disabled,Enabled" textline " " bitfld.long 0x9C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 39" "Disabled,Enabled" textline " " bitfld.long 0x9C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 39" "Disabled,Enabled" textline " " bitfld.long 0x9C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 39" "Disabled,Enabled" textline " " bitfld.long 0x9C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 39" "Disabled,Enabled" textline " " bitfld.long 0x9C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 39" "Disabled,Enabled" textline " " bitfld.long 0x9C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 39" "Disabled,Enabled" bitfld.long 0x9C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 39" "Disabled,Enabled" line.long 0xA0 "CHNENBL40,Channel 40 Enable RAM" bitfld.long 0xA0 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 40" "Disabled,Enabled" textline " " bitfld.long 0xA0 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 40" "Disabled,Enabled" textline " " bitfld.long 0xA0 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 40" "Disabled,Enabled" textline " " bitfld.long 0xA0 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 40" "Disabled,Enabled" textline " " bitfld.long 0xA0 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 40" "Disabled,Enabled" textline " " bitfld.long 0xA0 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 40" "Disabled,Enabled" textline " " bitfld.long 0xA0 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 40" "Disabled,Enabled" textline " " bitfld.long 0xA0 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 40" "Disabled,Enabled" bitfld.long 0xA0 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 40" "Disabled,Enabled" line.long 0xA4 "CHNENBL41,Channel 41 Enable RAM" bitfld.long 0xA4 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 41" "Disabled,Enabled" textline " " bitfld.long 0xA4 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 41" "Disabled,Enabled" textline " " bitfld.long 0xA4 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 41" "Disabled,Enabled" textline " " bitfld.long 0xA4 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 41" "Disabled,Enabled" textline " " bitfld.long 0xA4 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 41" "Disabled,Enabled" textline " " bitfld.long 0xA4 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 41" "Disabled,Enabled" textline " " bitfld.long 0xA4 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 41" "Disabled,Enabled" textline " " bitfld.long 0xA4 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 41" "Disabled,Enabled" bitfld.long 0xA4 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 41" "Disabled,Enabled" line.long 0xA8 "CHNENBL42,Channel 42 Enable RAM" bitfld.long 0xA8 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 42" "Disabled,Enabled" textline " " bitfld.long 0xA8 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 42" "Disabled,Enabled" textline " " bitfld.long 0xA8 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 42" "Disabled,Enabled" textline " " bitfld.long 0xA8 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 42" "Disabled,Enabled" textline " " bitfld.long 0xA8 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 42" "Disabled,Enabled" textline " " bitfld.long 0xA8 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 42" "Disabled,Enabled" textline " " bitfld.long 0xA8 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 42" "Disabled,Enabled" textline " " bitfld.long 0xA8 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 42" "Disabled,Enabled" bitfld.long 0xA8 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 42" "Disabled,Enabled" line.long 0xAC "CHNENBL43,Channel 43 Enable RAM" bitfld.long 0xAC 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 43" "Disabled,Enabled" textline " " bitfld.long 0xAC 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 43" "Disabled,Enabled" textline " " bitfld.long 0xAC 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 43" "Disabled,Enabled" textline " " bitfld.long 0xAC 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 43" "Disabled,Enabled" textline " " bitfld.long 0xAC 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 43" "Disabled,Enabled" textline " " bitfld.long 0xAC 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 43" "Disabled,Enabled" textline " " bitfld.long 0xAC 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 43" "Disabled,Enabled" textline " " bitfld.long 0xAC 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 43" "Disabled,Enabled" bitfld.long 0xAC 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 43" "Disabled,Enabled" line.long 0xB0 "CHNENBL44,Channel 44 Enable RAM" bitfld.long 0xB0 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 44" "Disabled,Enabled" textline " " bitfld.long 0xB0 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 44" "Disabled,Enabled" textline " " bitfld.long 0xB0 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 44" "Disabled,Enabled" textline " " bitfld.long 0xB0 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 44" "Disabled,Enabled" textline " " bitfld.long 0xB0 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 44" "Disabled,Enabled" textline " " bitfld.long 0xB0 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 44" "Disabled,Enabled" textline " " bitfld.long 0xB0 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 44" "Disabled,Enabled" textline " " bitfld.long 0xB0 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 44" "Disabled,Enabled" bitfld.long 0xB0 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 44" "Disabled,Enabled" line.long 0xB4 "CHNENBL45,Channel 45 Enable RAM" bitfld.long 0xB4 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 45" "Disabled,Enabled" textline " " bitfld.long 0xB4 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 45" "Disabled,Enabled" textline " " bitfld.long 0xB4 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 45" "Disabled,Enabled" textline " " bitfld.long 0xB4 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 45" "Disabled,Enabled" textline " " bitfld.long 0xB4 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 45" "Disabled,Enabled" textline " " bitfld.long 0xB4 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 45" "Disabled,Enabled" textline " " bitfld.long 0xB4 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 45" "Disabled,Enabled" textline " " bitfld.long 0xB4 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 45" "Disabled,Enabled" bitfld.long 0xB4 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 45" "Disabled,Enabled" line.long 0xB8 "CHNENBL46,Channel 46 Enable RAM" bitfld.long 0xB8 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 46" "Disabled,Enabled" textline " " bitfld.long 0xB8 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 46" "Disabled,Enabled" textline " " bitfld.long 0xB8 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 46" "Disabled,Enabled" textline " " bitfld.long 0xB8 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 46" "Disabled,Enabled" textline " " bitfld.long 0xB8 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 46" "Disabled,Enabled" textline " " bitfld.long 0xB8 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 46" "Disabled,Enabled" textline " " bitfld.long 0xB8 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 46" "Disabled,Enabled" textline " " bitfld.long 0xB8 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 46" "Disabled,Enabled" bitfld.long 0xB8 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 46" "Disabled,Enabled" line.long 0xBC "CHNENBL47,Channel 47 Enable RAM" bitfld.long 0xBC 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 47" "Disabled,Enabled" textline " " bitfld.long 0xBC 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 47" "Disabled,Enabled" textline " " bitfld.long 0xBC 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 47" "Disabled,Enabled" textline " " bitfld.long 0xBC 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 47" "Disabled,Enabled" textline " " bitfld.long 0xBC 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 47" "Disabled,Enabled" textline " " bitfld.long 0xBC 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 47" "Disabled,Enabled" textline " " bitfld.long 0xBC 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 47" "Disabled,Enabled" textline " " bitfld.long 0xBC 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 47" "Disabled,Enabled" bitfld.long 0xBC 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 47" "Disabled,Enabled" tree.end tree "BP registers" group.long 0x00++0x0B line.long 0x00 "DC0PTR,Channel 0 Pointer" line.long 0x04 "INTR,Channel Interrupts" eventfld.long 0x04 31. " DI[31] ,Channel 31 Interrupt request" "Not requested,Requested" eventfld.long 0x04 30. " DI[30] ,Channel 30 Interrupt request" "Not requested,Requested" eventfld.long 0x04 29. " DI[29] ,Channel 29 Interrupt request" "Not requested,Requested" eventfld.long 0x04 28. " DI[28] ,Channel 28 Interrupt request" "Not requested,Requested" textline " " eventfld.long 0x04 27. " DI[27] ,Channel 27 Interrupt request" "Not requested,Requested" eventfld.long 0x04 26. " DI[26] ,Channel 26 Interrupt request" "Not requested,Requested" eventfld.long 0x04 25. " DI[25] ,Channel 25 Interrupt request" "Not requested,Requested" eventfld.long 0x04 24. " DI[24] ,Channel 24 Interrupt request" "Not requested,Requested" textline " " eventfld.long 0x04 23. " DI[23] ,Channel 23 Interrupt request" "Not requested,Requested" eventfld.long 0x04 22. " DI[22] ,Channel 22 Interrupt request" "Not requested,Requested" eventfld.long 0x04 21. " DI[21] ,Channel 21 Interrupt request" "Not requested,Requested" eventfld.long 0x04 20. " DI[20] ,Channel 20 Interrupt request" "Not requested,Requested" textline " " eventfld.long 0x04 19. " DI[19] ,Channel 19 Interrupt request" "Not requested,Requested" eventfld.long 0x04 18. " DI[18] ,Channel 18 Interrupt request" "Not requested,Requested" eventfld.long 0x04 17. " DI[17] ,Channel 17 Interrupt request" "Not requested,Requested" eventfld.long 0x04 16. " DI[16] ,Channel 16 Interrupt request" "Not requested,Requested" textline " " eventfld.long 0x04 15. " DI[15] ,Channel 15 Interrupt request" "Not requested,Requested" eventfld.long 0x04 14. " DI[14] ,Channel 14 Interrupt request" "Not requested,Requested" eventfld.long 0x04 13. " DI[13] ,Channel 13 Interrupt request" "Not requested,Requested" eventfld.long 0x04 12. " DI[12] ,Channel 12 Interrupt request" "Not requested,Requested" textline " " eventfld.long 0x04 11. " DI[11] ,Channel 11 Interrupt request" "Not requested,Requested" eventfld.long 0x04 10. " DI[10] ,Channel 10 Interrupt request" "Not requested,Requested" eventfld.long 0x04 9. " DI[09] ,Channel 9 Interrupt request" "Not requested,Requested" eventfld.long 0x04 8. " DI[08] ,Channel 8 Interrupt request" "Not requested,Requested" textline " " eventfld.long 0x04 7. " DI[07] ,Channel 7 Interrupt request" "Not requested,Requested" eventfld.long 0x04 6. " DI[06] ,Channel 6 Interrupt request" "Not requested,Requested" eventfld.long 0x04 5. " DI[05] ,Channel 5 Interrupt request" "Not requested,Requested" eventfld.long 0x04 4. " DI[04] ,Channel 4 Interrupt request" "Not requested,Requested" textline " " eventfld.long 0x04 3. " DI[03] ,Channel 3 Interrupt request" "Not requested,Requested" eventfld.long 0x04 2. " DI[02] ,Channel 2 Interrupt request" "Not requested,Requested" eventfld.long 0x04 1. " DI[01] ,Channel 1 Interrupt request" "Not requested,Requested" eventfld.long 0x04 0. " DI[00] ,Channel 0 Interrupt request" "Not requested,Requested" line.long 0x08 "STOP_STAT,Channel Stop/Channel Status" eventfld.long 0x08 31. " DE[31] ,Channel 31 Stop/Status" "Not active,Active" eventfld.long 0x08 30. " DE[30] ,Channel 30 Stop/Status" "Not active,Active" eventfld.long 0x08 29. " DE[29] ,Channel 29 Stop/Status" "Not active,Active" eventfld.long 0x08 28. " DE[28] ,Channel 28 Stop/Status" "Not active,Active" textline " " eventfld.long 0x08 27. " DE[27] ,Channel 27 Stop/Status" "Not active,Active" eventfld.long 0x08 26. " DE[26] ,Channel 26 Stop/Status" "Not active,Active" eventfld.long 0x08 25. " DE[25] ,Channel 25 Stop/Status" "Not active,Active" eventfld.long 0x08 24. " DE[24] ,Channel 24 Stop/Status" "Not active,Active" textline " " eventfld.long 0x08 23. " DE[23] ,Channel 23 Stop/Status" "Not active,Active" eventfld.long 0x08 22. " DE[22] ,Channel 22 Stop/Status" "Not active,Active" eventfld.long 0x08 21. " DE[21] ,Channel 21 Stop/Status" "Not active,Active" eventfld.long 0x08 20. " DE[20] ,Channel 20 Stop/Status" "Not active,Active" textline " " eventfld.long 0x08 19. " DE[19] ,Channel 19 Stop/Status" "Not active,Active" eventfld.long 0x08 18. " DE[18] ,Channel 18 Stop/Status" "Not active,Active" eventfld.long 0x08 17. " DE[17] ,Channel 17 Stop/Status" "Not active,Active" eventfld.long 0x08 16. " DE[16] ,Channel 16 Stop/Status" "Not active,Active" textline " " eventfld.long 0x08 15. " DE[15] ,Channel 15 Stop/Status" "Not active,Active" eventfld.long 0x08 14. " DE[14] ,Channel 14 Stop/Status" "Not active,Active" eventfld.long 0x08 13. " DE[13] ,Channel 13 Stop/Status" "Not active,Active" eventfld.long 0x08 12. " DE[12] ,Channel 12 Stop/Status" "Not active,Active" textline " " eventfld.long 0x08 11. " DE[11] ,Channel 11 Stop/Status" "Not active,Active" eventfld.long 0x08 10. " DE[10] ,Channel 10 Stop/Status" "Not active,Active" eventfld.long 0x08 9. " DE[09] ,Channel 9 Stop/Status" "Not active,Active" eventfld.long 0x08 8. " DE[08] ,Channel 8 Stop/Status" "Not active,Active" textline " " eventfld.long 0x08 7. " DE[07] ,Channel 7 Stop/Status" "Not active,Active" eventfld.long 0x08 6. " DE[06] ,Channel 6 Stop/Status" "Not active,Active" eventfld.long 0x08 5. " DE[05] ,Channel 5 Stop/Status" "Not active,Active" eventfld.long 0x08 4. " DE[04] ,Channel 4 Stop/Status" "Not active,Active" textline " " eventfld.long 0x08 3. " DE[03] ,Channel 3 Stop/Status" "Not active,Active" eventfld.long 0x08 2. " DE[02] ,Channel 2 Stop/Status" "Not active,Active" eventfld.long 0x08 1. " DE[01] ,Channel 1 Stop/Status" "Not active,Active" eventfld.long 0x08 0. " DE[00] ,Channel 0 Stop/Status" "Not active,Active" rgroup.long 0x0C++0x03 line.long 0x00 "DSTART,Channel Start" bitfld.long 0x00 31. " DSTART_DE[31] ,Channel 31 Start" "Disabled,Enabled" bitfld.long 0x00 30. " DSTART_DE[30] ,Channel 30 Start" "Disabled,Enabled" bitfld.long 0x00 29. " DSTART_DE[29] ,Channel 29 Start" "Disabled,Enabled" bitfld.long 0x00 28. " DSTART_DE[28] ,Channel 28 Start" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " DSTART_DE[27] ,Channel 27 Start" "Disabled,Enabled" bitfld.long 0x00 26. " DSTART_DE[26] ,Channel 26 Start" "Disabled,Enabled" bitfld.long 0x00 25. " DSTART_DE[25] ,Channel 25 Start" "Disabled,Enabled" bitfld.long 0x00 24. " DSTART_DE[24] ,Channel 24 Start" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DSTART_DE[23] ,Channel 23 Start" "Disabled,Enabled" bitfld.long 0x00 22. " DSTART_DE[22] ,Channel 22 Start" "Disabled,Enabled" bitfld.long 0x00 21. " DSTART_DE[21] ,Channel 21 Start" "Disabled,Enabled" bitfld.long 0x00 20. " DSTART_DE[20] ,Channel 20 Start" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DSTART_DE[19] ,Channel 19 Start" "Disabled,Enabled" bitfld.long 0x00 18. " DSTART_DE[18] ,Channel 18 Start" "Disabled,Enabled" bitfld.long 0x00 17. " DSTART_DE[17] ,Channel 17 Start" "Disabled,Enabled" bitfld.long 0x00 16. " DSTART_DE[16] ,Channel 16 Start" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DSTART_DE[15] ,Channel 15 Start" "Disabled,Enabled" bitfld.long 0x00 14. " DSTART_DE[14] ,Channel 14 Start" "Disabled,Enabled" bitfld.long 0x00 13. " DSTART_DE[13] ,Channel 13 Start" "Disabled,Enabled" bitfld.long 0x00 12. " DSTART_DE[12] ,Channel 12 Start" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DSTART_DE[11] ,Channel 11 Start" "Disabled,Enabled" bitfld.long 0x00 10. " DSTART_DE[10] ,Channel 10 Start" "Disabled,Enabled" bitfld.long 0x00 9. " DSTART_DE[9] ,Channel 9 Start" "Disabled,Enabled" bitfld.long 0x00 8. " DSTART_DE[8] ,Channel 8 Start" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DSTART_DE[7] ,Channel 7 Start" "Disabled,Enabled" bitfld.long 0x00 6. " DSTART_DE[6] ,Channel 6 Start" "Disabled,Enabled" bitfld.long 0x00 5. " DSTART_DE[5] ,Channel 5 Start" "Disabled,Enabled" bitfld.long 0x00 4. " DSTART_DE[4] ,Channel 4 Start" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DSTART_DE[3] ,Channel 3 Start" "Disabled,Enabled" bitfld.long 0x00 2. " DSTART_DE[2] ,Channel 2 Start" "Disabled,Enabled" bitfld.long 0x00 1. " DSTART_DE[1] ,Channel 1 Start" "Disabled,Enabled" bitfld.long 0x00 0. " DSTART_DE[0] ,Channel 0 Start" "Disabled,Enabled" hgroup.long 0x28++0x03 hide.long 0x00 "EVTERR,DMA Request Error Register" in group.long 0x2C++0x03 line.long 0x00 "INTRMASK,Channel DSP Interrupt Mask" bitfld.long 0x00 31. " DIMASK[31] ,Interrupt mask for channel 31" "Masked,Not masked" bitfld.long 0x00 30. " DIMASK[30] ,Interrupt mask for channel 30" "Masked,Not masked" bitfld.long 0x00 29. " DIMASK[29] ,Interrupt mask for channel 29" "Masked,Not masked" bitfld.long 0x00 28. " DIMASK[28] ,Interrupt mask for channel 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " DIMASK[27] ,Interrupt mask for channel 27" "Masked,Not masked" bitfld.long 0x00 26. " DIMASK[26] ,Interrupt mask for channel 26" "Masked,Not masked" bitfld.long 0x00 25. " DIMASK[25] ,Interrupt mask for channel 25" "Masked,Not masked" bitfld.long 0x00 24. " DIMASK[24] ,Interrupt mask for channel 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " DIMASK[23] ,Interrupt mask for channel 23" "Masked,Not masked" bitfld.long 0x00 22. " DIMASK[22] ,Interrupt mask for channel 22" "Masked,Not masked" bitfld.long 0x00 21. " DIMASK[21] ,Interrupt mask for channel 21" "Masked,Not masked" bitfld.long 0x00 20. " DIMASK[20] ,Interrupt mask for channel 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " DIMASK[19] ,Interrupt mask for channel 19" "Masked,Not masked" bitfld.long 0x00 18. " DIMASK[18] ,Interrupt mask for channel 18" "Masked,Not masked" bitfld.long 0x00 17. " DIMASK[17] ,Interrupt mask for channel 17" "Masked,Not masked" bitfld.long 0x00 16. " DIMASK[16] ,Interrupt mask for channel 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " DIMASK[15] ,Interrupt mask for channel 15" "Masked,Not masked" bitfld.long 0x00 14. " DIMASK[14] ,Interrupt mask for channel 14" "Masked,Not masked" bitfld.long 0x00 13. " DIMASK[13] ,Interrupt mask for channel 13" "Masked,Not masked" bitfld.long 0x00 12. " DIMASK[12] ,Interrupt mask for channel 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " DIMASK[11] ,Interrupt mask for channel 11" "Masked,Not masked" bitfld.long 0x00 10. " DIMASK[10] ,Interrupt mask for channel 10" "Masked,Not masked" bitfld.long 0x00 9. " DIMASK[9] ,Interrupt mask for channel 9" "Masked,Not masked" bitfld.long 0x00 8. " DIMASK[8] ,Interrupt mask for channel 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " DIMASK[7] ,Interrupt mask for channel 7" "Masked,Not masked" bitfld.long 0x00 6. " DIMASK[6] ,Interrupt mask for channel 6" "Masked,Not masked" bitfld.long 0x00 5. " DIMASK[5] ,Interrupt mask for channel 5" "Masked,Not masked" bitfld.long 0x00 4. " DIMASK[4] ,Interrupt mask for channel 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " DIMASK[3] ,Interrupt mask for channel 3" "Masked,Not masked" bitfld.long 0x00 2. " DIMASK[2] ,Interrupt mask for channel 2" "Masked,Not masked" bitfld.long 0x00 1. " DIMASK[1] ,Interrupt mask for channel 1" "Masked,Not masked" bitfld.long 0x00 0. " DIMASK[0] ,Interrupt mask for channel 0" "Masked,Not masked" group.long 0x34++0x03 line.long 0x00 "EVTERRDBG,DMA Request Error Register" bitfld.long 0x00 31. " CHNERR[31] ,Interrupt error for channel 31" "No error,Error" bitfld.long 0x00 30. " CHNERR[30] ,Interrupt error for channel 30" "No error,Error" bitfld.long 0x00 29. " CHNERR[29] ,Interrupt error for channel 29" "No error,Error" bitfld.long 0x00 28. " CHNERR[28] ,Interrupt error for channel 28" "No error,Error" textline " " bitfld.long 0x00 27. " CHNERR[27] ,Interrupt error for channel 27" "No error,Error" bitfld.long 0x00 26. " CHNERR[26] ,Interrupt error for channel 26" "No error,Error" bitfld.long 0x00 25. " CHNERR[25] ,Interrupt error for channel 25" "No error,Error" bitfld.long 0x00 24. " CHNERR[24] ,Interrupt error for channel 24" "No error,Error" textline " " bitfld.long 0x00 23. " CHNERR[23] ,Interrupt error for channel 23" "No error,Error" bitfld.long 0x00 22. " CHNERR[22] ,Interrupt error for channel 22" "No error,Error" bitfld.long 0x00 21. " CHNERR[21] ,Interrupt error for channel 21" "No error,Error" bitfld.long 0x00 20. " CHNERR[20] ,Interrupt error for channel 20" "No error,Error" textline " " bitfld.long 0x00 19. " CHNERR[19] ,Interrupt error for channel 19" "No error,Error" bitfld.long 0x00 18. " CHNERR[18] ,Interrupt error for channel 18" "No error,Error" bitfld.long 0x00 17. " CHNERR[17] ,Interrupt error for channel 17" "No error,Error" bitfld.long 0x00 16. " CHNERR[16] ,Interrupt error for channel 16" "No error,Error" textline " " bitfld.long 0x00 15. " CHNERR[15] ,Interrupt error for channel 15" "No error,Error" bitfld.long 0x00 14. " CHNERR[14] ,Interrupt error for channel 14" "No error,Error" bitfld.long 0x00 13. " CHNERR[13] ,Interrupt error for channel 13" "No error,Error" bitfld.long 0x00 12. " CHNERR[12] ,Interrupt error for channel 12" "No error,Error" textline " " bitfld.long 0x00 11. " CHNERR[11] ,Interrupt error for channel 11" "No error,Error" bitfld.long 0x00 10. " CHNERR[10] ,Interrupt error for channel 10" "No error,Error" bitfld.long 0x00 9. " CHNERR[9] ,Interrupt error for channel 9" "No error,Error" bitfld.long 0x00 8. " CHNERR[8] ,Interrupt error for channel 8" "No error,Error" textline " " bitfld.long 0x00 7. " CHNERR[7] ,Interrupt error for channel 7" "No error,Error" bitfld.long 0x00 6. " CHNERR[6] ,Interrupt error for channel 6" "No error,Error" bitfld.long 0x00 5. " CHNERR[5] ,Interrupt error for channel 5" "No error,Error" bitfld.long 0x00 4. " CHNERR[4] ,Interrupt error for channel 4" "No error,Error" textline " " bitfld.long 0x00 3. " CHNERR[3] ,Interrupt error for channel 3" "No error,Error" bitfld.long 0x00 2. " CHNERR[2] ,Interrupt error for channel 2" "No error,Error" bitfld.long 0x00 1. " CHNERR[1] ,Interrupt error for channel 1" "No error,Error" bitfld.long 0x00 0. " CHNERR[0] ,Interrupt error for channel 0" "No error,Error" tree.end width 0xb tree.end tree "SEMA4 (Semaphore)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02290000 else base ad:0x42290000 endif width 8. group.byte 0x0++0x0F line.byte 0x0 "GATE0,Semaphores Gate 0 Register" bitfld.byte 0x0 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0x1 "GATE1,Semaphores Gate 1 Register" bitfld.byte 0x1 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0x2 "GATE2,Semaphores Gate 2 Register" bitfld.byte 0x2 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0x3 "GATE3,Semaphores Gate 3 Register" bitfld.byte 0x3 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0x4 "GATE4,Semaphores Gate 4 Register" bitfld.byte 0x4 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0x5 "GATE5,Semaphores Gate 5 Register" bitfld.byte 0x5 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0x6 "GATE6,Semaphores Gate 6 Register" bitfld.byte 0x6 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0x7 "GATE7,Semaphores Gate 7 Register" bitfld.byte 0x7 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0x8 "GATE8,Semaphores Gate 8 Register" bitfld.byte 0x8 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0x9 "GATE9,Semaphores Gate 9 Register" bitfld.byte 0x9 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0xA "GATE10,Semaphores Gate 10 Register" bitfld.byte 0xA 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0xB "GATE11,Semaphores Gate 11 Register" bitfld.byte 0xB 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0xC "GATE12,Semaphores Gate 12 Register" bitfld.byte 0xC 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0xD "GATE13,Semaphores Gate 13 Register" bitfld.byte 0xD 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0xE "GATE14,Semaphores Gate 14 Register" bitfld.byte 0xE 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." line.byte 0xF "GATE15,Semaphores Gate 15 Register" bitfld.byte 0xF 0.--1. " GTFSM ,Gate Finite State Machine" "Unlocked(free),Locked by processor 0,Locked by processor 1,?..." group.word 0x40++0x1 line.word 0x00 "CP0INE,Semaphores Processor n IRQ Notification Enable" bitfld.word 0x00 15. " INE0 ,The generation of the notification interrupt" "Disabled,Enabled" bitfld.word 0x00 14. " INE1 ,The generation of the notification interrupt" "Disabled,Enabled" bitfld.word 0x00 13. " INE2 ,The generation of the notification interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " INE3 ,The generation of the notification interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " INE4 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 10. " INE5 ,Interrupt Request Notification Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " INE6 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 8. " INE7 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 7. " INE8 ,Interrupt Request Notification Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " INE9 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 5. " INE10 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 4. " INE11 ,Interrupt Request Notification Enable " "Disabled,Enabled" textline " " bitfld.word 0x00 3. " INE12 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 2. " INE13 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 1. " INE14 ,Interrupt Request Notification Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " INE15 ,Interrupt Request Notification Enable" "Disabled,Enabled" group.word 0x48++0x01 line.word 0x00 "CP1INE,Semaphores Processor n IRQ Notification Enable" bitfld.word 0x00 15. " INE0 ,The generation of the notification interrupt" "Disabled,Enabled" bitfld.word 0x00 14. " INE1 ,The generation of the notification interrupt" "Disabled,Enabled" bitfld.word 0x00 13. " INE2 ,The generation of the notification interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " INE3 ,The generation of the notification interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " INE4 ,Interrupt Request Notification Enablet" "Disabled,Enabled" bitfld.word 0x00 10. " INE5 ,Interrupt Request Notification Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " INE6 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 8. " INE7 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 7. " INE8 ,Interrupt Request Notification Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " INE9 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 5. " INE10 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 4. " INE11 ,Interrupt Request Notification Enable " "Disabled,Enabled" textline " " bitfld.word 0x00 3. " INE12 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 2. " INE13 ,Interrupt Request Notification Enable" "Disabled,Enabled" bitfld.word 0x00 1. " INE14 ,Interrupt Request Notification Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " INE15 ,Interrupt Request Notification Enable" "Disabled,Enabled" rgroup.word 0x80++0x1 line.word 0x00 "CP0NTF,Semaphores Processor n IRQ Notification" rgroup.word 0x88++0x1 line.word 0x00 "CP1NTF,Semaphores Processor n IRQ Notification" group.word 0x100++0x1 line.word 0x00 "RSTGT,Semaphores (Secure) Reset Gate n" hexmask.word.byte 0x00 8.--15. 1. " RSTGDP_WO ,Reset Gate Data Pattern (Write only)" rbitfld.word 0x00 4.--5. " RSTGSM_RO ,Reset Gate Finite State Machine (Read only)" "Waiting for 1st,Waiting for 2nd,Completed,?..." rbitfld.word 0x00 0.--2. " RSTGMS_RO ,Reset Gate Bus Master (Read only)" "0,1,2,3,4,5,6,7" textline " " hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,Reset Gate Number" group.word 0x104++0x1 line.word 0x00 "RSTNTF,Semaphores (Secure) Reset IRQ Notification" hexmask.word.byte 0x00 8.--15. 1. " RSTNDP_WO ,Reset Notification Data Pattern (Write only)" rbitfld.word 0x00 4.--5. " RSTNSM_RO ,Reset Notification Finite State Machine (Read only)" "Waiting for 1st,Waiting for 2nd,Completed,?..." rbitfld.word 0x00 0.--2. " RSTNMS_RO ,Reset Notification Bus Master (Read only)" "0,1,2,3,4,5,6,7" textline " " hexmask.word.byte 0x00 0.--7. 1. " RSTNTN ,Reset Notification Number" width 0xB tree.end tree "SVNS (Secure Non-Volatile Storage)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020CC000 else base ad:0x420CC000 endif width 9. group.long 0x00++0x0B line.long 0x00 "HPLR,HP Lock Register" bitfld.long 0x00 5. " GPR_SL ,Write access" "Not locked,Locked" bitfld.long 0x00 4. " MC_SL ,Write access (increment)" "Not locked,Locked" line.long 0x04 "HPCOMR,HP Command Register" bitfld.long 0x04 31. " NPSWA_EN ,Non-Privileged Software Access Enable" "Disabled,Enabled" bitfld.long 0x04 5. " LP_SWR_DIS ,LP Software Reset Disable" "No,Yes" bitfld.long 0x04 4. " LP_SWR ,LP Software Reset" "No action,Reset" line.long 0x08 "HPCR,HP Control Register" bitfld.long 0x08 27. " BTN_MASK ,Button interrupt mask" "Disabled,Enabled" bitfld.long 0x08 24.--26. " BTN_CONFIG ,Button Configuration" "Active low,Active high,Active rising edge,Active falling edge,Active both edges,..." bitfld.long 0x08 10.--14. " HPCALB_VAL ,HP Calibration Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x08 8. " HPCALB_EN ,HP Real Time Counter Calibration Enabled" "Disabled,Enabled" textline " " bitfld.long 0x08 4.--7. " PI_FREQ ,Number of bit responsible for generating periodic interrupt during its transition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3. " PI_EN ,HP Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " HPTA_EN ,HP Time Alarm Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " RTC_EN ,HP Real Time Counter Enable" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "HPSR,HP Status Register" eventfld.long 0x00 7. " BI ,Button interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 6. " BTN ,BTN input state" "Not pressed,Pressed" group.long 0x24++0x17 line.long 0x00 "HPRTCMR,HP Real Time Counter MSB Register" line.long 0x04 "HPRTCLR,HP Real Time Counter LSB Register" line.long 0x08 "HPTAMR,HP Time Alarm MSB Register" hexmask.long.word 0x08 0.--14. 1. " HPTA ,HP Time Alarm" line.long 0x0C "HPTALR,HP Time Alarm LSB Registerr" line.long 0x10 "LPLR,LP Lock Register" bitfld.long 0x10 5. " GPR_HL ,General Purpose Register Hard Lock" "Not locked,Locked" bitfld.long 0x10 4. " MC_HL ,Monotonic Counter Hard Lock" "Not locked,Locked" line.long 0x14 "LPCR,LP Control Register" bitfld.long 0x14 23. " PK_OVERRIDE ,PMIC On Request Override" "Not overridden,Overridden" bitfld.long 0x14 22. " PK_EN ,PMIC On Request Enable" "Disabled,Enabled" bitfld.long 0x14 20.--21. " ON_TIME ,Period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoCpower" "500 msec,50 msec,100 msec,0 msec" bitfld.long 0x14 18.--19. " DEBOUNCE ,Amount of debounce time for the BTN input signal" "50 msec,100 msec,500 msec,0 msec" textline " " bitfld.long 0x14 16.--17. " BTN_PRESS_TIME ,Button press time out values for PMIC Logic" "5 sec,10 sec,15 sec,Long press disabled" bitfld.long 0x14 7. " PWR_GLITCH_EN ,Power glitch event for the PMIC" "Enabled,Disabled" bitfld.long 0x14 6. " TOP ,Turn off System Power" "Power on,Power off" bitfld.long 0x14 5. " DP_EN ,Decides whether Dumb or Smart PMIC is enabled" "Smart,Dumb" textline " " bitfld.long 0x14 2. " MC_ENV ,Monotonic Counter Enable and Valid" "Disabled/invalid,Enabled/valid" group.long 0x4C++0x03 line.long 0x00 "LPSR,LP Status Register" eventfld.long 0x00 18. " SPO ,Emergency Off detection" "Not detected,Detected" eventfld.long 0x00 17. " EO ,Power Off request" "Not requested,Requested" eventfld.long 0x00 2. " MCR ,Monotonic Counter Rollover" "Not occurred,Occurred" group.long 0x5C++0x07 line.long 0x00 "LPSMCMR,LP Secure Monotonic Counter MSB Register" hexmask.long.word 0x00 16.--31. 1. " MC_ERA_BITS ,Monotonic Counter Era Bits" hexmask.long.word 0x00 0.--15. 1. " MON_COUNTER ,Monotonic Counter Most Significant 16 Bits" line.long 0x04 "LPSMCLR,LP Secure Monotonic Counter LSB Register" group.long 0x68++0x03 line.long 0x00 "LPGPR,LP General Purpose Register" group.long 0xBF8++0x007 line.long 0x00 "HPVIDR1,HP Version ID Register 1" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,SNVS block ID" hexmask.long.byte 0x00 8.--15. 1. " MAJOR_REV ,SNVS block major version number" hexmask.long.byte 0x00 0.--7. 1. " MINOR_REV ,SNVS block minor version number" line.long 0x04 "HPVIDR2,HP Version ID Register 2" hexmask.long.byte 0x04 24.--31. 1. " IP_ERA ,Era of the IP design" hexmask.long.byte 0x04 16.--23. 1. " INTG_OPT ,SNVS Integration Option" hexmask.long.byte 0x04 8.--15. 1. " ECO_REV ,SNVS ECO Revision" hexmask.long.byte 0x04 0.--7. 1. " CONFIG_OPT ,SNVS Configuration Option" width 12. tree.end tree "SPBA (Shared Peripheral Bus Arbiter)" tree "AIPS1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0203C000 else base ad:0x4203C000 endif width 7. group.long 0x0++0x27 line.long 0x00 "PRR0,Peripheral Right Register 0" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x4++0x27 line.long 0x00 "PRR1,Peripheral Right Register 1" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x8++0x27 line.long 0x00 "PRR2,Peripheral Right Register 2" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0xC++0x27 line.long 0x00 "PRR3,Peripheral Right Register 3" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x10++0x27 line.long 0x00 "PRR4,Peripheral Right Register 4" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x14++0x27 line.long 0x00 "PRR5,Peripheral Right Register 5" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x18++0x27 line.long 0x00 "PRR6,Peripheral Right Register 6" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x1C++0x27 line.long 0x00 "PRR7,Peripheral Right Register 7" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x20++0x27 line.long 0x00 "PRR8,Peripheral Right Register 8" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x24++0x27 line.long 0x00 "PRR9,Peripheral Right Register 9" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x28++0x57 line.long 0x00 "PRR10,Peripheral Right Register 10" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x2C++0x57 line.long 0x00 "PRR11,Peripheral Right Register 11" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x30++0x57 line.long 0x00 "PRR12,Peripheral Right Register 12" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x34++0x57 line.long 0x00 "PRR13,Peripheral Right Register 13" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x38++0x57 line.long 0x00 "PRR14,Peripheral Right Register 14" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x3C++0x57 line.long 0x00 "PRR15,Peripheral Right Register 15" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x40++0x57 line.long 0x00 "PRR16,Peripheral Right Register 16" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x44++0x57 line.long 0x00 "PRR17,Peripheral Right Register 17" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x48++0x57 line.long 0x00 "PRR18,Peripheral Right Register 18" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x4C++0x57 line.long 0x00 "PRR19,Peripheral Right Register 19" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x50++0x57 line.long 0x00 "PRR20,Peripheral Right Register 20" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x54++0x57 line.long 0x00 "PRR21,Peripheral Right Register 21" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x58++0x57 line.long 0x00 "PRR22,Peripheral Right Register 22" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x5C++0x57 line.long 0x00 "PRR23,Peripheral Right Register 23" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x60++0x57 line.long 0x00 "PRR24,Peripheral Right Register 24" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x64++0x57 line.long 0x00 "PRR25,Peripheral Right Register 25" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x68++0x57 line.long 0x00 "PRR26,Peripheral Right Register 26" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x6C++0x57 line.long 0x00 "PRR27,Peripheral Right Register 27" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x70++0x57 line.long 0x00 "PRR28,Peripheral Right Register 28" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x74++0x57 line.long 0x00 "PRR29,Peripheral Right Register 29" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x78++0x57 line.long 0x00 "PRR30,Peripheral Right Register 30" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x7C++0x57 line.long 0x00 "PRR31,Peripheral Right Register 31" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" width 0x0B tree.end tree "AIPS3" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0223C000 else base ad:0x4223C000 endif width 7. group.long 0x0++0x27 line.long 0x00 "PRR0,Peripheral Right Register 0" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x4++0x27 line.long 0x00 "PRR1,Peripheral Right Register 1" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x8++0x27 line.long 0x00 "PRR2,Peripheral Right Register 2" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0xC++0x27 line.long 0x00 "PRR3,Peripheral Right Register 3" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x10++0x27 line.long 0x00 "PRR4,Peripheral Right Register 4" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x14++0x27 line.long 0x00 "PRR5,Peripheral Right Register 5" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x18++0x27 line.long 0x00 "PRR6,Peripheral Right Register 6" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x1C++0x27 line.long 0x00 "PRR7,Peripheral Right Register 7" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x20++0x27 line.long 0x00 "PRR8,Peripheral Right Register 8" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x24++0x27 line.long 0x00 "PRR9,Peripheral Right Register 9" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x28++0x57 line.long 0x00 "PRR10,Peripheral Right Register 10" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x2C++0x57 line.long 0x00 "PRR11,Peripheral Right Register 11" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x30++0x57 line.long 0x00 "PRR12,Peripheral Right Register 12" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x34++0x57 line.long 0x00 "PRR13,Peripheral Right Register 13" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x38++0x57 line.long 0x00 "PRR14,Peripheral Right Register 14" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x3C++0x57 line.long 0x00 "PRR15,Peripheral Right Register 15" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x40++0x57 line.long 0x00 "PRR16,Peripheral Right Register 16" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x44++0x57 line.long 0x00 "PRR17,Peripheral Right Register 17" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x48++0x57 line.long 0x00 "PRR18,Peripheral Right Register 18" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x4C++0x57 line.long 0x00 "PRR19,Peripheral Right Register 19" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x50++0x57 line.long 0x00 "PRR20,Peripheral Right Register 20" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x54++0x57 line.long 0x00 "PRR21,Peripheral Right Register 21" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x58++0x57 line.long 0x00 "PRR22,Peripheral Right Register 22" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x5C++0x57 line.long 0x00 "PRR23,Peripheral Right Register 23" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x60++0x57 line.long 0x00 "PRR24,Peripheral Right Register 24" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x64++0x57 line.long 0x00 "PRR25,Peripheral Right Register 25" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x68++0x57 line.long 0x00 "PRR26,Peripheral Right Register 26" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x6C++0x57 line.long 0x00 "PRR27,Peripheral Right Register 27" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x70++0x57 line.long 0x00 "PRR28,Peripheral Right Register 28" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x74++0x57 line.long 0x00 "PRR29,Peripheral Right Register 29" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x78++0x57 line.long 0x00 "PRR30,Peripheral Right Register 30" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x7C++0x57 line.long 0x00 "PRR31,Peripheral Right Register 31" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" width 0x0B tree.end tree.end tree "SPDIF (Sony/Philips Digital Interface)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02004000 width 9. group.long 0x00++0x07 line.long 0x0 "SCR,Configuration Register" bitfld.long 0x00 23. " RXFIFO_CTRL ,Receive FIFO operation mode" "Normal,Read zero" bitfld.long 0x00 22. " RXFIFO_OFF/ON ,SPDIF Receive FIFO enable" "Enabled,Disabled" bitfld.long 0x00 21. " RXFIFO_RST ,Receive FIFO reset" "No reset,Reset" textline " " bitfld.long 0x00 19.--20. " RXFIFOFULL_SEL ,Receive FIFO full interrupt select" "1,4,8,16" bitfld.long 0x00 18. " RXAUTOSYNC ,Receive FIFO auto sync enable" "Disabled,Enabled" bitfld.long 0x0 17. " TXAUTOSYNC ,Transmit FIFO Auto Sync Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 15.--16. " TXFIFOEMPTY_SEL ,Transmit FIFO Empty interrupt select" "0,4,8,12" bitfld.long 0x0 13. " LOW_POWER ,SPDIF low-power mode" "Disabled,Enabled" bitfld.long 0x0 12. " SOFT_RESET ,SPDIF software reset" "No reset,Reset" textline " " bitfld.long 0x0 10.--11. " TXFIFO_CTRL ,Transmit FIFO Control" "Tx Digital 0,Normal,Reset to 1 samp," bitfld.long 0x0 9. " DMA_RX_EN ,DMA Receive Request enable" "Disabled,Enabled" bitfld.long 0x0 8. " DMA_TX_EN ,DMA Transmit Request enable" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " VALCTRL ,Outingoing Validity" "Set,Clear" bitfld.long 0x0 2.--4. " TXSEL ,Transmit Select" "0ff and output 0,SPDIFIN,,,,Normal,," bitfld.long 0x0 0.--1. " USRC_SEL ,Receive channel U select" "No embedded,SPDIF receive block,,On chip transmitter" line.long 0x04 "SRCD,CDText Control Register" bitfld.long 0x04 1. " USYNCMODE , U sync mode" "Non-CD data,CD user channel subcode" if (((per.l(ad:0x02004000+0x08))&0x40)==0x40) group.long 0x08++0x03 line.long 0x00 "SRPC,PhaseConfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "SPDIF_RxClk,SPDIF_RxClk,SPDIF_RxClk,SPDIF_RxClk,SPDIF_Rxclk,REF_CLK_32K,Tx_clk,Asrc_clk,SPDIF_EXT_CLK,ESAI_HCKT,SPDIF_RxClk,SPDIF_RxClk,MLB Clock,MLB PHY Clock,," rbitfld.long 0x00 6. " LOCK ,Internal DPLL lock" "Not locked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10)," else group.long 0x08++0x03 line.long 0x00 "SRPC,PhaseConfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "REF_CLK_32K,Tx_clk,ASRC_EXT_CLK,SPDIF_EXT_CLK,ESAI_HCKT,REF_CLK_32K,Tx_clk,Asrc_clk,SPDIF_EXT_CLK,ESAI_HCKT,MLB Clock,MLB PHY Clock,MLB Clock,MLB PHY Clock,," rbitfld.long 0x00 6. " LOCK ,Internal DPLL lock" "Not locked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10)," endif group.long 0x0c++0x03 line.long 0x0 "SIE,Interrupt Enable Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " TXUNOV ,SPDIF transmit FIFO under/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " TXRESYN ,SPDIF transmit FIFO resync interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel" "Disabled,Enabled" bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " URXFUL ,U channel receive register full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RXFIFOUNOV ,RX FIFO underrun/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " RXFIFORESYN ,RX FIFO resync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXEM ,SPDIF transmit FIFO empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF receive FIFO full interrupt enable" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "SIS/SIC,Interrupt Status Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 19. " TXUNOV ,SPDIF transmit FIFO under/overrun interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 18. " TXRESYN ,SPDIF transmit FIFO resync interrupt" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 10. " URXFUL ,U channel receive register full interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 4. " RXFIFOUNOV ,RX FIFO underrun/overrun interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 3. " RXFIFORESYN ,RX FIFO resync interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 1. " TXEM ,SPDIF transmit FIFO empty interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF RX FIFO full interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" rgroup.long 0x14++0x0F line.long 0x00 "SRL,SPDIF Rx Left Regsiter" hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA_L ,Processor receive SPDIF data left" line.long 0x04 "SRR,SPDIF Rx Right Regsiter" hexmask.long.tbyte 0x04 0.--23. 1. " RXDATA_R ,Processor receive SPDIF data right" line.long 0x08 "SRCSH,SPDIF RxC Channel_h Register" hexmask.long.tbyte 0x08 0.--23. 1. " RXCCH_H ,SPDIF receive C channel register (high bits)" line.long 0x0C "SRCSL,SPDIF RxC Channel_l Register" hexmask.long.tbyte 0x0C 0.--23. 1. " RXCCH_L ,SPDIF receive C channel register (low bits)" rgroup.long 0x24++0x07 line.long 0x00 "SRU,Uchannel Rx Register" hexmask.long.tbyte 0x00 0.--23. 1. " RxUChannel ,SPDIF receive U channel register, contains next 3 U channel bytes" line.long 0x04 "SRQ,Qchannel Rx Register" hexmask.long.tbyte 0x04 0.--23. 1. " RxQChannel ,SPDIF receive Q channel register, contains next 3 Q channel bytes" wgroup.long 0x2C++0x07 line.long 0x00 "STL,SPDIF Left Channel Data Transmitter" hexmask.long.tbyte 0x00 0.--23. 1. " TXDATALEFT ,SPDIF transmit left channel data" line.long 0x04 "STR,SPDIF Right Channel Data Transmitter" hexmask.long.tbyte 0x04 0.--23. 1. " TXDATARIGHT ,SPDIF transmit right channel data" group.long 0x34++0x07 line.long 0x00 "STCSCH,SPDIF Tx Consumer Channel Status High Register" hexmask.long.tbyte 0x0 0.--23. 1. " TXCCHANNELCONS_H ,SPDIF transmit Cons. C channel data" line.long 0x04 "STCSCL,SPDIF Tx Consumer Channel Status Low Register" hexmask.long.tbyte 0x4 0.--23. 1. " TXCCHANNELCONS_L ,SPDIF transmit Cons. C channel data" rgroup.long 0x44++0x03 line.long 0x00 "SRFM,Frequency Measurement Data Register" hexmask.long.tbyte 0x0 0.--23. 1. " FREQ_MEAS ,Frequency measurement data" group.long 0x50++0x3 line.long 0x0 "STC,Transmit Clock Control Register" hexmask.long.word 0x00 11.--19. 1. " SYSCLK_DF ,System clock divider factor 2-512" bitfld.long 0x00 8.--10. " TXCLK_SOURCE ,Tx clock source" "REF_CLK_32K,Tx_clk,ASRC_EXT_CLK,SPDIF_EXT_CLK,ESAI_HCKT,Ipg_clk,MLB clock,MLB PHY clock" bitfld.long 0x00 7. " TX_ALL_CLK_EN ,Spdif transfer clock enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--6. 1. " TXCLK_DF ,Divider factor (1-128)" width 0xb else base ad:0x42004000 width 9. group.long 0x00++0x07 line.long 0x0 "SCR,Configuration Register" bitfld.long 0x00 23. " RXFIFO_CTRL ,Receive FIFO operation mode" "Normal,Read zero" bitfld.long 0x00 22. " RXFIFO_OFF/ON ,SPDIF Receive FIFO enable" "Enabled,Disabled" bitfld.long 0x00 21. " RXFIFO_RST ,Receive FIFO reset" "No reset,Reset" textline " " bitfld.long 0x00 19.--20. " RXFIFOFULL_SEL ,Receive FIFO full interrupt select" "1,4,8,16" bitfld.long 0x00 18. " RXAUTOSYNC ,Receive FIFO auto sync enable" "Disabled,Enabled" bitfld.long 0x0 17. " TXAUTOSYNC ,Transmit FIFO Auto Sync Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 15.--16. " TXFIFOEMPTY_SEL ,Transmit FIFO Empty interrupt select" "0,4,8,12" bitfld.long 0x0 13. " LOW_POWER ,SPDIF low-power mode" "Disabled,Enabled" bitfld.long 0x0 12. " SOFT_RESET ,SPDIF software reset" "No reset,Reset" textline " " bitfld.long 0x0 10.--11. " TXFIFO_CTRL ,Transmit FIFO Control" "Tx Digital 0,Normal,Reset to 1 samp," bitfld.long 0x0 9. " DMA_RX_EN ,DMA Receive Request enable" "Disabled,Enabled" bitfld.long 0x0 8. " DMA_TX_EN ,DMA Transmit Request enable" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " VALCTRL ,Outingoing Validity" "Set,Clear" bitfld.long 0x0 2.--4. " TXSEL ,Transmit Select" "0ff and output 0,SPDIFIN,,,,Normal,," bitfld.long 0x0 0.--1. " USRC_SEL ,Receive channel U select" "No embedded,SPDIF receive block,,On chip transmitter" line.long 0x04 "SRCD,CDText Control Register" bitfld.long 0x04 1. " USYNCMODE , U sync mode" "Non-CD data,CD user channel subcode" if (((per.l(ad:0x42004000+0x08))&0x40)==0x40) group.long 0x08++0x03 line.long 0x00 "SRPC,PhaseConfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "SPDIF_RxClk,SPDIF_RxClk,SPDIF_RxClk,SPDIF_RxClk,SPDIF_Rxclk,REF_CLK_32K,Tx_clk,Asrc_clk,SPDIF_EXT_CLK,ESAI_HCKT,SPDIF_RxClk,SPDIF_RxClk,MLB Clock,MLB PHY Clock,," rbitfld.long 0x00 6. " LOCK ,Internal DPLL lock" "Not locked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10)," else group.long 0x08++0x03 line.long 0x00 "SRPC,PhaseConfig Register" bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "REF_CLK_32K,Tx_clk,ASRC_EXT_CLK,SPDIF_EXT_CLK,ESAI_HCKT,REF_CLK_32K,Tx_clk,Asrc_clk,SPDIF_EXT_CLK,ESAI_HCKT,MLB Clock,MLB PHY Clock,MLB Clock,MLB PHY Clock,," rbitfld.long 0x00 6. " LOCK ,Internal DPLL lock" "Not locked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10)," endif group.long 0x0c++0x03 line.long 0x0 "SIE,Interrupt Enable Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " TXUNOV ,SPDIF transmit FIFO under/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " TXRESYN ,SPDIF transmit FIFO resync interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel" "Disabled,Enabled" bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " URXFUL ,U channel receive register full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RXFIFOUNOV ,RX FIFO underrun/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " RXFIFORESYN ,RX FIFO resync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXEM ,SPDIF transmit FIFO empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF receive FIFO full interrupt enable" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "SIS/SIC,Interrupt Status Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 19. " TXUNOV ,SPDIF transmit FIFO under/overrun interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 18. " TXRESYN ,SPDIF transmit FIFO resync interrupt" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 10. " URXFUL ,U channel receive register full interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 4. " RXFIFOUNOV ,RX FIFO underrun/overrun interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 3. " RXFIFORESYN ,RX FIFO resync interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" textline " " bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 1. " TXEM ,SPDIF transmit FIFO empty interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF RX FIFO full interrupt [read/write]" "No interrupt/No effect,Interrupt/Clear" rgroup.long 0x14++0x0F line.long 0x00 "SRL,SPDIF Rx Left Regsiter" hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA_L ,Processor receive SPDIF data left" line.long 0x04 "SRR,SPDIF Rx Right Regsiter" hexmask.long.tbyte 0x04 0.--23. 1. " RXDATA_R ,Processor receive SPDIF data right" line.long 0x08 "SRCSH,SPDIF RxC Channel_h Register" hexmask.long.tbyte 0x08 0.--23. 1. " RXCCH_H ,SPDIF receive C channel register (high bits)" line.long 0x0C "SRCSL,SPDIF RxC Channel_l Register" hexmask.long.tbyte 0x0C 0.--23. 1. " RXCCH_L ,SPDIF receive C channel register (low bits)" rgroup.long 0x24++0x07 line.long 0x00 "SRU,Uchannel Rx Register" hexmask.long.tbyte 0x00 0.--23. 1. " RxUChannel ,SPDIF receive U channel register, contains next 3 U channel bytes" line.long 0x04 "SRQ,Qchannel Rx Register" hexmask.long.tbyte 0x04 0.--23. 1. " RxQChannel ,SPDIF receive Q channel register, contains next 3 Q channel bytes" wgroup.long 0x2C++0x07 line.long 0x00 "STL,SPDIF Left Channel Data Transmitter" hexmask.long.tbyte 0x00 0.--23. 1. " TXDATALEFT ,SPDIF transmit left channel data" line.long 0x04 "STR,SPDIF Right Channel Data Transmitter" hexmask.long.tbyte 0x04 0.--23. 1. " TXDATARIGHT ,SPDIF transmit right channel data" group.long 0x34++0x07 line.long 0x00 "STCSCH,SPDIF Tx Consumer Channel Status High Register" hexmask.long.tbyte 0x0 0.--23. 1. " TXCCHANNELCONS_H ,SPDIF transmit Cons. C channel data" line.long 0x04 "STCSCL,SPDIF Tx Consumer Channel Status Low Register" hexmask.long.tbyte 0x4 0.--23. 1. " TXCCHANNELCONS_L ,SPDIF transmit Cons. C channel data" rgroup.long 0x44++0x03 line.long 0x00 "SRFM,Frequency Measurement Data Register" hexmask.long.tbyte 0x0 0.--23. 1. " FREQ_MEAS ,Frequency measurement data" group.long 0x50++0x3 line.long 0x0 "STC,Transmit Clock Control Register" hexmask.long.word 0x00 11.--19. 1. " SYSCLK_DF ,System clock divider factor 2-512" bitfld.long 0x00 8.--10. " TXCLK_SOURCE ,Tx clock source" "REF_CLK_32K,Tx_clk,ASRC_EXT_CLK,SPDIF_EXT_CLK,ESAI_HCKT,Ipg_clk,MLB clock,MLB PHY clock" bitfld.long 0x00 7. " TX_ALL_CLK_EN ,Spdif transfer clock enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--6. 1. " TXCLK_DF ,Divider factor (1-128)" width 0xb endif tree.end tree "SRC (System Reset Controller)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020D8000 else base ad:0x420D8000 endif width 7. group.long 0x00++0x03 line.long 0x00 "SCR,System Reset Controller" bitfld.long 0x00 28.--31. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" "Not masked,Not masked,Not masked,Not masked,Not masked,Masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked" bitfld.long 0x00 26.--27. " MIX_RST_STRCH ,Power up reset stretch mix reset width" "88 ipg_cycle cycles,2*88 ipg_cycle cycles,3*88 ipg_cycle cycles,4*88 ipg_cycle cycles" bitfld.long 0x00 25. " DBG_RST_MSK_PG ,Debug reset mask" "Unmasked,Masked" textline " " bitfld.long 0x00 24. " WDOG3_RST_OPTN ,Wdog3_rst_b option" "Global reset,M4 reset" bitfld.long 0x00 23. " WDOG3_RST_OPTN_M4 ,Wdog3_rst_b option for M4" "Reset M4 core only,Reset M4 + platform" bitfld.long 0x00 22. " M4_ENABLE ,Enable M4 core" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " CORES_DBG_RST ,Software reset for debug of arm platform only" "No reset,Reset" bitfld.long 0x00 18.--20. " MASK_TEMPSENSE_RESET ,Mask tempsense_reset source" "Not masked,Not masked,Not masked,Not masked,Not masked,Masked,Not masked,Not masked" bitfld.long 0x00 17. " CORE0_DBG_RST ,Software reset for core0 debug only" "No reset,Reset" textline " " bitfld.long 0x00 13. " CORE0_RST ,Software reset for core0 only" "No reset,Reset" bitfld.long 0x00 12. " MP4_RST ,Self-clearing SW reset for M4 platform" "No reset,Reset" bitfld.long 0x00 11. " EIM_RST ,EIM Reset" "No reset,Reset" textline " " bitfld.long 0x00 7.--10. " MASK_WDOG_RST ,Mask wdog_rst_b source" "Not masked,Not masked,Not masked,Not masked,Not masked,Masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked" bitfld.long 0x00 5.--6. " WARM_RST_BYPASS_COUNT ,Ckil cycles to count before bypassing the MMDC ack for warm reset" "Disabled,16 XTALI cycles,32 XTALI cycles,64 XTALI cycles" bitfld.long 0x00 4. " M4C_NON_SCLR_RST ,Non-self-clearing SW reset for M4 core" "No reset,Reset" textline " " bitfld.long 0x00 3. " M4C_RST ,Self-clearing SW reset for M4 core" "No reset,Reset" bitfld.long 0x00 1. " SW_GPU_RST ,Software reset for gpu" "No reset,Reset" bitfld.long 0x00 0. " WARM_RESET_ENABLE ,Warm reset enable bit" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SBMR1,SRC Boot Mode Register" hexmask.long.byte 0x00 24.--31. 1. " BOOT_CFG4 ,Boot configuration4" hexmask.long.byte 0x00 16.--23. 1. " BOOT_CFG3 ,Boot configuration3" hexmask.long.byte 0x00 8.--15. 1. " BOOT_CFG2 ,Boot configuration2" textline " " hexmask.long.byte 0x00 0.--7. 1. " BOOT_CFG1 ,Boot configuration1" group.long 0x08++0x03 line.long 0x00 "SRSR,SRC Reset Status Register" bitfld.long 0x00 16. " WARM_BOOT ,Warm boot indication" "Not initiated,Initiated" bitfld.long 0x00 8. " TEMSENSE_RST_B ,Indicates whether the reset was the result of software reset from on-chip Temperature Sensor" "No,Yes" eventfld.long 0x00 7. " WDOG3_RST_B ,Indicates whether the reset was the result of the watchdog3 time-out event" "No,Yes" textline " " eventfld.long 0x00 6. " JTAG_SW_RST ,Reset via JTAG SW" "No,Yes" eventfld.long 0x00 5. " JTAG_RST_B ,Reset via HIGH-Z JTAG" "No,Yes" eventfld.long 0x00 4. " WDOG_RST_B ,IC Watchdog Time-out reset" "No,Yes" textline " " eventfld.long 0x00 3. " IPP_USER_RESET_B ,Reset via ipp_user_reset_b qulified" "No,Yes" eventfld.long 0x00 2. " CSU_RESET_B ,Reset via csu_reset_b input" "No,Yes" eventfld.long 0x00 0. " IPP_RESET_B ,Reset via ipp_reset_b pin" "No,Yes" rgroup.long 0x014++0x03 line.long 0x00 "SISR,SRC Interrupt Status Register" bitfld.long 0x00 5. " CORE0_WDOG_RST_REQ ,Wdog reset request from CPU core0" "Not requested,Requested" bitfld.long 0x00 4. " M4P_PASSED_RESET ,Interrupt generated to indicate that M4 platform passed software reset and is ready to be used" "No interrupt,Interrupt" bitfld.long 0x00 3. " OPEN_VG_PASSED_RESET ,Interrupt generated to indicate that open_vg passed software reset and is ready to be used" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " IPU1_PASSED_RESET ,Interrupt generated to indicate that ipu passed software reset and is ready to be used" "No interrupt,Interrupt" bitfld.long 0x00 0. " GPU_PASSED_RESET ,Interrupt generated to indicate that gpu passed software reset and is ready to be used" "No interrupt,Interrupt" group.long 0x018++0x03 line.long 0x00 "SIMR,SRC Interrupt Mask Register" bitfld.long 0x00 3. " MASK_OPEN_VG_PASSED_RESET ,Mask interrupt generation due to open_vg passed reset" "Not masked,Masked" bitfld.long 0x00 0. " MASK_GPU_PASSED_RESET ,Mask interrupt generation due to gpu passed reset" "Not masked,Masked" rgroup.long 0x1C++0x03 line.long 0x00 "SBMR2,SRC Boot Mode Register 2" bitfld.long 0x00 24.--25. " BMOD ,Boot mode" "0,1,2,3" bitfld.long 0x00 4. " BT_FUSE_SEL ,Boot fuse selection" "0,1" bitfld.long 0x00 3. " DIR_BT_DIS ,DIR_BT_DIS" "0,1" textline " " bitfld.long 0x00 0.--1. " SEC_CONFIG ,SEC_CONFIG" "0,1,2,3" group.long 0x20++0x03 line.long 0x00 "GPR1,SRC General Purpose Register 1" group.long 0x20++0x03 line.long 0x00 "GPR2,SRC General Purpose Register 2" group.long 0x20++0x03 line.long 0x00 "GPR3,SRC General Purpose Register 3" group.long 0x20++0x03 line.long 0x00 "GPR4,SRC General Purpose Register 4" group.long 0x20++0x03 line.long 0x00 "GPR5,SRC General Purpose Register 5" group.long 0x20++0x03 line.long 0x00 "GPR6,SRC General Purpose Register 6" group.long 0x20++0x03 line.long 0x00 "GPR7,SRC General Purpose Register 7" group.long 0x20++0x03 line.long 0x00 "GPR8,SRC General Purpose Register 8" group.long 0x44++0x03 line.long 0x00 "GPR10,SRC General Purpose Register 10" hexmask.long.byte 0x00 26.--31. 0x01 " GPR10 ,GPR10" hexmask.long 0x00 0.--24. 0x01 " GPR10 ,GPR10" width 0xb tree.end tree.open "SSI (Synchronous Serial Interface)" tree "SSI1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02028000 width 8. group.long 0x00++0x07 line.long 0x00 "STX0,Transmit Data Register 0" line.long 0x04 "STX1,Transmit Data Register 1" rgroup.long 0x08++0x07 line.long 0x00 "SRX0,Receive Data Register 0" line.long 0x04 "SRX1,Receive Data Register 1" group.long 0x10++0x13 line.long 0x00 "SCR,SSI Control Register" bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched" bitfld.long 0x00 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes" bitfld.long 0x00 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes" bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "0,1" newline bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal" bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected" bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled" line.long 0x04 "SISR,SSI Interrupt Status Register" bitfld.long 0x04 24. " RFRC ,Receive Frame Complete" "Not reached,Reached" bitfld.long 0x04 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached" bitfld.long 0x04 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated" bitfld.long 0x04 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated" newline bitfld.long 0x04 16. " RXT ,Receive Tag Updated" "Not updated,Updated" bitfld.long 0x04 15. " RDR1 ,Receive Data Ready 1" "No new data,New data" bitfld.long 0x04 14. " RDR0 ,Receive Data Ready 0" "No new data,New data" bitfld.long 0x04 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty" newline bitfld.long 0x04 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty" eventfld.long 0x04 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error" eventfld.long 0x04 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error" eventfld.long 0x04 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error" newline eventfld.long 0x04 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error" bitfld.long 0x04 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 5. " TLS ,Transmit Last Time Slot" "No,Yes" newline bitfld.long 0x04 4. " RLS ,Receive Last Time Slot" "No,Yes" bitfld.long 0x04 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full" bitfld.long 0x04 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full" bitfld.long 0x04 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty" newline bitfld.long 0x04 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty" line.long 0x08 "SIER,SSI Interrupt Enable Register" bitfld.long 0x08 24. " RFRCIE ,Receive Frame Complete" "Disabled,Enabled" bitfld.long 0x08 23. " TFRCIE ,Transmit Frame Complete" "Disabled,Enabled" bitfld.long 0x08 22. " RDMAE ,SSI Receiver DMA requests" "Disabled,Enabled" bitfld.long 0x08 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x08 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " CMDAUIE ,Command Address Register Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 17. " CMDDUIE ,Command Data Register Updated Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RXTIE ,Receive Tag Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 15. " RDR1IE ,Receive Data Ready 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 14. " RDR0IE ,Receive Data Ready 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 13. " TDE1IE ,Transmit Data Register Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " TDE0IE ,Transmit Data Register Empty 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 11. " ROE1IE ,Receiver Overrun Error 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ROE0IE ,Receiver Overrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 9. " TUE1IE ,Transmitter Underrun Error 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " TUE0IE ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " TFSIE ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 6. " RFSIE ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x08 5. " TLSIE ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " RLSIE ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 3. " RFF1IE ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " RFF0IE ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " TFE1IE ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled" line.long 0x0C "STCR,SSI Transmit Configuration Register" bitfld.long 0x0C 9. " TXBIT0 ,Transmit Bit 0" "MSB,LSB" bitfld.long 0x0C 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x0C 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled" bitfld.long 0x0C 6. " TFDIR ,Transmit Frame Direction" "External,Internal" newline bitfld.long 0x0C 5. " TXDIR ,Transmit Clock Direction" "External,Internal" bitfld.long 0x0C 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first" bitfld.long 0x0C 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x0C 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low" newline bitfld.long 0x0C 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x0C 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before" line.long 0x10 "SRCR,SSI Receive Configuration Register" bitfld.long 0x10 10. " RXEXT ,Receive Data Extension" "Not extended,Extended" bitfld.long 0x10 9. " RXBIT0 ,Receive Bit 0" "MSB,LSB" bitfld.long 0x10 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x10 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled" newline bitfld.long 0x10 6. " RFDIR ,Receive Frame Direction" "External,Internal" bitfld.long 0x10 5. " RXDIR ,Receive Clock Direction" "External,Internal" bitfld.long 0x10 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first" bitfld.long 0x10 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge" newline bitfld.long 0x10 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low" bitfld.long 0x10 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x10 0. " REFS ,Receive Early Frame Sync" "First bit,One before" if (((per.l(ad:0x02028000+0x10))&0x08)==0x08) group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" else group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" endif group.long 0x2C++0x03 line.long 0x00 "SFCSR,SSI FIFO Control/Status Register" bitfld.long 0x00 28.--31. " RFCNT1 ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TFCNT1 ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RFWM1 ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 16.--19. " TFWM1 ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" newline bitfld.long 0x00 12.--15. " RFCNT0 ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFCNT0 ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RFWM0 ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 0.--3. " TFWM0 ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" group.long 0x38++0x17 line.long 0x00 "SACNT,SSI AC97 Control Register" hexmask.long.byte 0x00 5.--10. 1. " FRDIV ,Frame Rate Divider" bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached" bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached" bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0" newline bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable" bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled" line.long 0x04 "SACADD,SSI AC97 Command Address Register" hexmask.long.tbyte 0x04 0.--18. 0x01 " SACADD ,AC97 Command Address" line.long 0x08 "SACDAT,SSI AC97 Command Data Register" hexmask.long.tbyte 0x08 0.--19. 1. " SACDAT ,AC97 Command Data" line.long 0x0C "SATAG,SSI AC97 Tag Register" hexmask.long.word 0x0C 0.--15. 1. " SATAG ,AC97 Tag Value" line.long 0x10 "STMSK,SSI Transmit Time Slot Mask Register" bitfld.long 0x10 31. " STMSK ,Transmit Mask Bit 31" "0,1" bitfld.long 0x10 30. ",Transmit Mask Bit 30" "0,1" bitfld.long 0x10 29. ",Transmit Mask Bit 29" "0,1" bitfld.long 0x10 28. ",Transmit Mask Bit 28" "0,1" bitfld.long 0x10 27. ",Transmit Mask Bit 27" "0,1" bitfld.long 0x10 26. ",Transmit Mask Bit 26" "0,1" bitfld.long 0x10 25. ",Transmit Mask Bit 25" "0,1" bitfld.long 0x10 24. ",Transmit Mask Bit 24" "0,1" bitfld.long 0x10 23. ",Transmit Mask Bit 23" "0,1" bitfld.long 0x10 22. ",Transmit Mask Bit 22" "0,1" bitfld.long 0x10 21. ",Transmit Mask Bit 21" "0,1" bitfld.long 0x10 20. ",Transmit Mask Bit 20" "0,1" bitfld.long 0x10 19. ",Transmit Mask Bit 19" "0,1" bitfld.long 0x10 18. ",Transmit Mask Bit 18" "0,1" bitfld.long 0x10 17. ",Transmit Mask Bit 17" "0,1" bitfld.long 0x10 16. ",Transmit Mask Bit 16" "0,1" bitfld.long 0x10 15. ",Transmit Mask Bit 15" "0,1" bitfld.long 0x10 14. ",Transmit Mask Bit 14" "0,1" bitfld.long 0x10 13. ",Transmit Mask Bit 13" "0,1" bitfld.long 0x10 12. ",Transmit Mask Bit 12" "0,1" bitfld.long 0x10 11. ",Transmit Mask Bit 11" "0,1" bitfld.long 0x10 10. ",Transmit Mask Bit 10" "0,1" bitfld.long 0x10 9. ",Transmit Mask Bit 9" "0,1" bitfld.long 0x10 8. ",Transmit Mask Bit 8" "0,1" bitfld.long 0x10 7. ",Transmit Mask Bit 7" "0,1" bitfld.long 0x10 6. ",Transmit Mask Bit 6" "0,1" bitfld.long 0x10 5. ",Transmit Mask Bit 5" "0,1" bitfld.long 0x10 4. ",Transmit Mask Bit 4" "0,1" bitfld.long 0x10 3. ",Transmit Mask Bit 3" "0,1" bitfld.long 0x10 2. ",Transmit Mask Bit 2" "0,1" bitfld.long 0x10 1. ",Transmit Mask Bit 1" "0,1" bitfld.long 0x10 0. ",Transmit Mask Bit 0" "0,1" line.long 0x14 "SRMSK,SSI Receive Time Slot Mask Register" bitfld.long 0x14 31. " SRMSK ,Receive Mask Bit 31" "0,1" bitfld.long 0x14 30. ",Receive Mask Bit 30" "0,1" bitfld.long 0x14 29. ",Receive Mask Bit 29" "0,1" bitfld.long 0x14 28. ",Receive Mask Bit 28" "0,1" bitfld.long 0x14 27. ",Receive Mask Bit 27" "0,1" bitfld.long 0x14 26. ",Receive Mask Bit 26" "0,1" bitfld.long 0x14 25. ",Receive Mask Bit 25" "0,1" bitfld.long 0x14 24. ",Receive Mask Bit 24" "0,1" bitfld.long 0x14 23. ",Receive Mask Bit 23" "0,1" bitfld.long 0x14 22. ",Receive Mask Bit 22" "0,1" bitfld.long 0x14 21. ",Receive Mask Bit 21" "0,1" bitfld.long 0x14 20. ",Receive Mask Bit 20" "0,1" bitfld.long 0x14 19. ",Receive Mask Bit 19" "0,1" bitfld.long 0x14 18. ",Receive Mask Bit 18" "0,1" bitfld.long 0x14 17. ",Receive Mask Bit 17" "0,1" bitfld.long 0x14 16. ",Receive Mask Bit 16" "0,1" bitfld.long 0x14 15. ",Receive Mask Bit 15" "0,1" bitfld.long 0x14 14. ",Receive Mask Bit 14" "0,1" bitfld.long 0x14 13. ",Receive Mask Bit 13" "0,1" bitfld.long 0x14 12. ",Receive Mask Bit 12" "0,1" bitfld.long 0x14 11. ",Receive Mask Bit 11" "0,1" bitfld.long 0x14 10. ",Receive Mask Bit 10" "0,1" bitfld.long 0x14 9. ",Receive Mask Bit 9" "0,1" bitfld.long 0x14 8. ",Receive Mask Bit 8" "0,1" bitfld.long 0x14 7. ",Receive Mask Bit 7" "0,1" bitfld.long 0x14 6. ",Receive Mask Bit 6" "0,1" bitfld.long 0x14 5. ",Receive Mask Bit 5" "0,1" bitfld.long 0x14 4. ",Receive Mask Bit 4" "0,1" bitfld.long 0x14 3. ",Receive Mask Bit 3" "0,1" bitfld.long 0x14 2. ",Receive Mask Bit 2" "0,1" bitfld.long 0x14 1. ",Receive Mask Bit 1" "0,1" bitfld.long 0x14 0. ",Receive Mask Bit 0" "0,1" newline width 16. group.long 0x50++0x03 line.long 0x00 "SACCST_SET/CLR,SSI AC97 Channel SET/CLR Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SACCST9_SET/CLR ,AC97 Channel Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SACCST8_SET/CLR ,AC97 Channel Status 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SACCST7_SET/CLR ,AC97 Channel Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SACCST6_SET/CLR ,AC97 Channel Status 6" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SACCST5_SET/CLR ,AC97 Channel Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SACCST4_SET/CLR ,AC97 Channel Status 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SACCST3_SET/CLR ,AC97 Channel Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SACCST2_SET/CLR ,AC97 Channel Status 2" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SACCST1_SET/CLR ,AC97 Channel Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SACCST0_SET/CLR ,AC97 Channel Status 0" "Disabled,Enabled" width 0x0B else base ad:0x42028000 width 8. group.long 0x00++0x07 line.long 0x00 "STX0,Transmit Data Register 0" line.long 0x04 "STX1,Transmit Data Register 1" rgroup.long 0x08++0x07 line.long 0x00 "SRX0,Receive Data Register 0" line.long 0x04 "SRX1,Receive Data Register 1" group.long 0x10++0x13 line.long 0x00 "SCR,SSI Control Register" bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched" bitfld.long 0x00 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes" bitfld.long 0x00 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes" bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "0,1" newline bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal" bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected" bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled" line.long 0x04 "SISR,SSI Interrupt Status Register" bitfld.long 0x04 24. " RFRC ,Receive Frame Complete" "Not reached,Reached" bitfld.long 0x04 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached" bitfld.long 0x04 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated" bitfld.long 0x04 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated" newline bitfld.long 0x04 16. " RXT ,Receive Tag Updated" "Not updated,Updated" bitfld.long 0x04 15. " RDR1 ,Receive Data Ready 1" "No new data,New data" bitfld.long 0x04 14. " RDR0 ,Receive Data Ready 0" "No new data,New data" bitfld.long 0x04 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty" newline bitfld.long 0x04 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty" eventfld.long 0x04 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error" eventfld.long 0x04 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error" eventfld.long 0x04 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error" newline eventfld.long 0x04 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error" bitfld.long 0x04 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 5. " TLS ,Transmit Last Time Slot" "No,Yes" newline bitfld.long 0x04 4. " RLS ,Receive Last Time Slot" "No,Yes" bitfld.long 0x04 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full" bitfld.long 0x04 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full" bitfld.long 0x04 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty" newline bitfld.long 0x04 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty" line.long 0x08 "SIER,SSI Interrupt Enable Register" bitfld.long 0x08 24. " RFRCIE ,Receive Frame Complete" "Disabled,Enabled" bitfld.long 0x08 23. " TFRCIE ,Transmit Frame Complete" "Disabled,Enabled" bitfld.long 0x08 22. " RDMAE ,SSI Receiver DMA requests" "Disabled,Enabled" bitfld.long 0x08 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x08 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " CMDAUIE ,Command Address Register Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 17. " CMDDUIE ,Command Data Register Updated Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RXTIE ,Receive Tag Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 15. " RDR1IE ,Receive Data Ready 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 14. " RDR0IE ,Receive Data Ready 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 13. " TDE1IE ,Transmit Data Register Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " TDE0IE ,Transmit Data Register Empty 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 11. " ROE1IE ,Receiver Overrun Error 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ROE0IE ,Receiver Overrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 9. " TUE1IE ,Transmitter Underrun Error 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " TUE0IE ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " TFSIE ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 6. " RFSIE ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x08 5. " TLSIE ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " RLSIE ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 3. " RFF1IE ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " RFF0IE ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " TFE1IE ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled" line.long 0x0C "STCR,SSI Transmit Configuration Register" bitfld.long 0x0C 9. " TXBIT0 ,Transmit Bit 0" "MSB,LSB" bitfld.long 0x0C 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x0C 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled" bitfld.long 0x0C 6. " TFDIR ,Transmit Frame Direction" "External,Internal" newline bitfld.long 0x0C 5. " TXDIR ,Transmit Clock Direction" "External,Internal" bitfld.long 0x0C 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first" bitfld.long 0x0C 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x0C 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low" newline bitfld.long 0x0C 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x0C 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before" line.long 0x10 "SRCR,SSI Receive Configuration Register" bitfld.long 0x10 10. " RXEXT ,Receive Data Extension" "Not extended,Extended" bitfld.long 0x10 9. " RXBIT0 ,Receive Bit 0" "MSB,LSB" bitfld.long 0x10 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x10 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled" newline bitfld.long 0x10 6. " RFDIR ,Receive Frame Direction" "External,Internal" bitfld.long 0x10 5. " RXDIR ,Receive Clock Direction" "External,Internal" bitfld.long 0x10 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first" bitfld.long 0x10 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge" newline bitfld.long 0x10 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low" bitfld.long 0x10 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x10 0. " REFS ,Receive Early Frame Sync" "First bit,One before" if (((per.l(ad:0x42028000+0x10))&0x08)==0x08) group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" else group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" endif group.long 0x2C++0x03 line.long 0x00 "SFCSR,SSI FIFO Control/Status Register" bitfld.long 0x00 28.--31. " RFCNT1 ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TFCNT1 ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RFWM1 ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 16.--19. " TFWM1 ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" newline bitfld.long 0x00 12.--15. " RFCNT0 ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFCNT0 ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RFWM0 ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 0.--3. " TFWM0 ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" group.long 0x38++0x17 line.long 0x00 "SACNT,SSI AC97 Control Register" hexmask.long.byte 0x00 5.--10. 1. " FRDIV ,Frame Rate Divider" bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached" bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached" bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0" newline bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable" bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled" line.long 0x04 "SACADD,SSI AC97 Command Address Register" hexmask.long.tbyte 0x04 0.--18. 0x01 " SACADD ,AC97 Command Address" line.long 0x08 "SACDAT,SSI AC97 Command Data Register" hexmask.long.tbyte 0x08 0.--19. 1. " SACDAT ,AC97 Command Data" line.long 0x0C "SATAG,SSI AC97 Tag Register" hexmask.long.word 0x0C 0.--15. 1. " SATAG ,AC97 Tag Value" line.long 0x10 "STMSK,SSI Transmit Time Slot Mask Register" bitfld.long 0x10 31. " STMSK ,Transmit Mask Bit 31" "0,1" bitfld.long 0x10 30. ",Transmit Mask Bit 30" "0,1" bitfld.long 0x10 29. ",Transmit Mask Bit 29" "0,1" bitfld.long 0x10 28. ",Transmit Mask Bit 28" "0,1" bitfld.long 0x10 27. ",Transmit Mask Bit 27" "0,1" bitfld.long 0x10 26. ",Transmit Mask Bit 26" "0,1" bitfld.long 0x10 25. ",Transmit Mask Bit 25" "0,1" bitfld.long 0x10 24. ",Transmit Mask Bit 24" "0,1" bitfld.long 0x10 23. ",Transmit Mask Bit 23" "0,1" bitfld.long 0x10 22. ",Transmit Mask Bit 22" "0,1" bitfld.long 0x10 21. ",Transmit Mask Bit 21" "0,1" bitfld.long 0x10 20. ",Transmit Mask Bit 20" "0,1" bitfld.long 0x10 19. ",Transmit Mask Bit 19" "0,1" bitfld.long 0x10 18. ",Transmit Mask Bit 18" "0,1" bitfld.long 0x10 17. ",Transmit Mask Bit 17" "0,1" bitfld.long 0x10 16. ",Transmit Mask Bit 16" "0,1" bitfld.long 0x10 15. ",Transmit Mask Bit 15" "0,1" bitfld.long 0x10 14. ",Transmit Mask Bit 14" "0,1" bitfld.long 0x10 13. ",Transmit Mask Bit 13" "0,1" bitfld.long 0x10 12. ",Transmit Mask Bit 12" "0,1" bitfld.long 0x10 11. ",Transmit Mask Bit 11" "0,1" bitfld.long 0x10 10. ",Transmit Mask Bit 10" "0,1" bitfld.long 0x10 9. ",Transmit Mask Bit 9" "0,1" bitfld.long 0x10 8. ",Transmit Mask Bit 8" "0,1" bitfld.long 0x10 7. ",Transmit Mask Bit 7" "0,1" bitfld.long 0x10 6. ",Transmit Mask Bit 6" "0,1" bitfld.long 0x10 5. ",Transmit Mask Bit 5" "0,1" bitfld.long 0x10 4. ",Transmit Mask Bit 4" "0,1" bitfld.long 0x10 3. ",Transmit Mask Bit 3" "0,1" bitfld.long 0x10 2. ",Transmit Mask Bit 2" "0,1" bitfld.long 0x10 1. ",Transmit Mask Bit 1" "0,1" bitfld.long 0x10 0. ",Transmit Mask Bit 0" "0,1" line.long 0x14 "SRMSK,SSI Receive Time Slot Mask Register" bitfld.long 0x14 31. " SRMSK ,Receive Mask Bit 31" "0,1" bitfld.long 0x14 30. ",Receive Mask Bit 30" "0,1" bitfld.long 0x14 29. ",Receive Mask Bit 29" "0,1" bitfld.long 0x14 28. ",Receive Mask Bit 28" "0,1" bitfld.long 0x14 27. ",Receive Mask Bit 27" "0,1" bitfld.long 0x14 26. ",Receive Mask Bit 26" "0,1" bitfld.long 0x14 25. ",Receive Mask Bit 25" "0,1" bitfld.long 0x14 24. ",Receive Mask Bit 24" "0,1" bitfld.long 0x14 23. ",Receive Mask Bit 23" "0,1" bitfld.long 0x14 22. ",Receive Mask Bit 22" "0,1" bitfld.long 0x14 21. ",Receive Mask Bit 21" "0,1" bitfld.long 0x14 20. ",Receive Mask Bit 20" "0,1" bitfld.long 0x14 19. ",Receive Mask Bit 19" "0,1" bitfld.long 0x14 18. ",Receive Mask Bit 18" "0,1" bitfld.long 0x14 17. ",Receive Mask Bit 17" "0,1" bitfld.long 0x14 16. ",Receive Mask Bit 16" "0,1" bitfld.long 0x14 15. ",Receive Mask Bit 15" "0,1" bitfld.long 0x14 14. ",Receive Mask Bit 14" "0,1" bitfld.long 0x14 13. ",Receive Mask Bit 13" "0,1" bitfld.long 0x14 12. ",Receive Mask Bit 12" "0,1" bitfld.long 0x14 11. ",Receive Mask Bit 11" "0,1" bitfld.long 0x14 10. ",Receive Mask Bit 10" "0,1" bitfld.long 0x14 9. ",Receive Mask Bit 9" "0,1" bitfld.long 0x14 8. ",Receive Mask Bit 8" "0,1" bitfld.long 0x14 7. ",Receive Mask Bit 7" "0,1" bitfld.long 0x14 6. ",Receive Mask Bit 6" "0,1" bitfld.long 0x14 5. ",Receive Mask Bit 5" "0,1" bitfld.long 0x14 4. ",Receive Mask Bit 4" "0,1" bitfld.long 0x14 3. ",Receive Mask Bit 3" "0,1" bitfld.long 0x14 2. ",Receive Mask Bit 2" "0,1" bitfld.long 0x14 1. ",Receive Mask Bit 1" "0,1" bitfld.long 0x14 0. ",Receive Mask Bit 0" "0,1" newline width 16. group.long 0x50++0x03 line.long 0x00 "SACCST_SET/CLR,SSI AC97 Channel SET/CLR Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SACCST9_SET/CLR ,AC97 Channel Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SACCST8_SET/CLR ,AC97 Channel Status 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SACCST7_SET/CLR ,AC97 Channel Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SACCST6_SET/CLR ,AC97 Channel Status 6" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SACCST5_SET/CLR ,AC97 Channel Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SACCST4_SET/CLR ,AC97 Channel Status 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SACCST3_SET/CLR ,AC97 Channel Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SACCST2_SET/CLR ,AC97 Channel Status 2" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SACCST1_SET/CLR ,AC97 Channel Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SACCST0_SET/CLR ,AC97 Channel Status 0" "Disabled,Enabled" width 0x0B endif tree.end tree "SSI2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0202C000 width 8. group.long 0x00++0x07 line.long 0x00 "STX0,Transmit Data Register 0" line.long 0x04 "STX1,Transmit Data Register 1" rgroup.long 0x08++0x07 line.long 0x00 "SRX0,Receive Data Register 0" line.long 0x04 "SRX1,Receive Data Register 1" group.long 0x10++0x13 line.long 0x00 "SCR,SSI Control Register" bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched" bitfld.long 0x00 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes" bitfld.long 0x00 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes" bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "0,1" newline bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal" bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected" bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled" line.long 0x04 "SISR,SSI Interrupt Status Register" bitfld.long 0x04 24. " RFRC ,Receive Frame Complete" "Not reached,Reached" bitfld.long 0x04 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached" bitfld.long 0x04 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated" bitfld.long 0x04 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated" newline bitfld.long 0x04 16. " RXT ,Receive Tag Updated" "Not updated,Updated" bitfld.long 0x04 15. " RDR1 ,Receive Data Ready 1" "No new data,New data" bitfld.long 0x04 14. " RDR0 ,Receive Data Ready 0" "No new data,New data" bitfld.long 0x04 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty" newline bitfld.long 0x04 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty" eventfld.long 0x04 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error" eventfld.long 0x04 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error" eventfld.long 0x04 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error" newline eventfld.long 0x04 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error" bitfld.long 0x04 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 5. " TLS ,Transmit Last Time Slot" "No,Yes" newline bitfld.long 0x04 4. " RLS ,Receive Last Time Slot" "No,Yes" bitfld.long 0x04 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full" bitfld.long 0x04 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full" bitfld.long 0x04 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty" newline bitfld.long 0x04 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty" line.long 0x08 "SIER,SSI Interrupt Enable Register" bitfld.long 0x08 24. " RFRCIE ,Receive Frame Complete" "Disabled,Enabled" bitfld.long 0x08 23. " TFRCIE ,Transmit Frame Complete" "Disabled,Enabled" bitfld.long 0x08 22. " RDMAE ,SSI Receiver DMA requests" "Disabled,Enabled" bitfld.long 0x08 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x08 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " CMDAUIE ,Command Address Register Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 17. " CMDDUIE ,Command Data Register Updated Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RXTIE ,Receive Tag Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 15. " RDR1IE ,Receive Data Ready 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 14. " RDR0IE ,Receive Data Ready 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 13. " TDE1IE ,Transmit Data Register Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " TDE0IE ,Transmit Data Register Empty 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 11. " ROE1IE ,Receiver Overrun Error 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ROE0IE ,Receiver Overrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 9. " TUE1IE ,Transmitter Underrun Error 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " TUE0IE ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " TFSIE ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 6. " RFSIE ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x08 5. " TLSIE ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " RLSIE ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 3. " RFF1IE ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " RFF0IE ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " TFE1IE ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled" line.long 0x0C "STCR,SSI Transmit Configuration Register" bitfld.long 0x0C 9. " TXBIT0 ,Transmit Bit 0" "MSB,LSB" bitfld.long 0x0C 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x0C 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled" bitfld.long 0x0C 6. " TFDIR ,Transmit Frame Direction" "External,Internal" newline bitfld.long 0x0C 5. " TXDIR ,Transmit Clock Direction" "External,Internal" bitfld.long 0x0C 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first" bitfld.long 0x0C 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x0C 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low" newline bitfld.long 0x0C 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x0C 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before" line.long 0x10 "SRCR,SSI Receive Configuration Register" bitfld.long 0x10 10. " RXEXT ,Receive Data Extension" "Not extended,Extended" bitfld.long 0x10 9. " RXBIT0 ,Receive Bit 0" "MSB,LSB" bitfld.long 0x10 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x10 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled" newline bitfld.long 0x10 6. " RFDIR ,Receive Frame Direction" "External,Internal" bitfld.long 0x10 5. " RXDIR ,Receive Clock Direction" "External,Internal" bitfld.long 0x10 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first" bitfld.long 0x10 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge" newline bitfld.long 0x10 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low" bitfld.long 0x10 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x10 0. " REFS ,Receive Early Frame Sync" "First bit,One before" if (((per.l(ad:0x0202C000+0x10))&0x08)==0x08) group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" else group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" endif group.long 0x2C++0x03 line.long 0x00 "SFCSR,SSI FIFO Control/Status Register" bitfld.long 0x00 28.--31. " RFCNT1 ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TFCNT1 ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RFWM1 ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 16.--19. " TFWM1 ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" newline bitfld.long 0x00 12.--15. " RFCNT0 ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFCNT0 ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RFWM0 ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 0.--3. " TFWM0 ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" group.long 0x38++0x17 line.long 0x00 "SACNT,SSI AC97 Control Register" hexmask.long.byte 0x00 5.--10. 1. " FRDIV ,Frame Rate Divider" bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached" bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached" bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0" newline bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable" bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled" line.long 0x04 "SACADD,SSI AC97 Command Address Register" hexmask.long.tbyte 0x04 0.--18. 0x01 " SACADD ,AC97 Command Address" line.long 0x08 "SACDAT,SSI AC97 Command Data Register" hexmask.long.tbyte 0x08 0.--19. 1. " SACDAT ,AC97 Command Data" line.long 0x0C "SATAG,SSI AC97 Tag Register" hexmask.long.word 0x0C 0.--15. 1. " SATAG ,AC97 Tag Value" line.long 0x10 "STMSK,SSI Transmit Time Slot Mask Register" bitfld.long 0x10 31. " STMSK ,Transmit Mask Bit 31" "0,1" bitfld.long 0x10 30. ",Transmit Mask Bit 30" "0,1" bitfld.long 0x10 29. ",Transmit Mask Bit 29" "0,1" bitfld.long 0x10 28. ",Transmit Mask Bit 28" "0,1" bitfld.long 0x10 27. ",Transmit Mask Bit 27" "0,1" bitfld.long 0x10 26. ",Transmit Mask Bit 26" "0,1" bitfld.long 0x10 25. ",Transmit Mask Bit 25" "0,1" bitfld.long 0x10 24. ",Transmit Mask Bit 24" "0,1" bitfld.long 0x10 23. ",Transmit Mask Bit 23" "0,1" bitfld.long 0x10 22. ",Transmit Mask Bit 22" "0,1" bitfld.long 0x10 21. ",Transmit Mask Bit 21" "0,1" bitfld.long 0x10 20. ",Transmit Mask Bit 20" "0,1" bitfld.long 0x10 19. ",Transmit Mask Bit 19" "0,1" bitfld.long 0x10 18. ",Transmit Mask Bit 18" "0,1" bitfld.long 0x10 17. ",Transmit Mask Bit 17" "0,1" bitfld.long 0x10 16. ",Transmit Mask Bit 16" "0,1" bitfld.long 0x10 15. ",Transmit Mask Bit 15" "0,1" bitfld.long 0x10 14. ",Transmit Mask Bit 14" "0,1" bitfld.long 0x10 13. ",Transmit Mask Bit 13" "0,1" bitfld.long 0x10 12. ",Transmit Mask Bit 12" "0,1" bitfld.long 0x10 11. ",Transmit Mask Bit 11" "0,1" bitfld.long 0x10 10. ",Transmit Mask Bit 10" "0,1" bitfld.long 0x10 9. ",Transmit Mask Bit 9" "0,1" bitfld.long 0x10 8. ",Transmit Mask Bit 8" "0,1" bitfld.long 0x10 7. ",Transmit Mask Bit 7" "0,1" bitfld.long 0x10 6. ",Transmit Mask Bit 6" "0,1" bitfld.long 0x10 5. ",Transmit Mask Bit 5" "0,1" bitfld.long 0x10 4. ",Transmit Mask Bit 4" "0,1" bitfld.long 0x10 3. ",Transmit Mask Bit 3" "0,1" bitfld.long 0x10 2. ",Transmit Mask Bit 2" "0,1" bitfld.long 0x10 1. ",Transmit Mask Bit 1" "0,1" bitfld.long 0x10 0. ",Transmit Mask Bit 0" "0,1" line.long 0x14 "SRMSK,SSI Receive Time Slot Mask Register" bitfld.long 0x14 31. " SRMSK ,Receive Mask Bit 31" "0,1" bitfld.long 0x14 30. ",Receive Mask Bit 30" "0,1" bitfld.long 0x14 29. ",Receive Mask Bit 29" "0,1" bitfld.long 0x14 28. ",Receive Mask Bit 28" "0,1" bitfld.long 0x14 27. ",Receive Mask Bit 27" "0,1" bitfld.long 0x14 26. ",Receive Mask Bit 26" "0,1" bitfld.long 0x14 25. ",Receive Mask Bit 25" "0,1" bitfld.long 0x14 24. ",Receive Mask Bit 24" "0,1" bitfld.long 0x14 23. ",Receive Mask Bit 23" "0,1" bitfld.long 0x14 22. ",Receive Mask Bit 22" "0,1" bitfld.long 0x14 21. ",Receive Mask Bit 21" "0,1" bitfld.long 0x14 20. ",Receive Mask Bit 20" "0,1" bitfld.long 0x14 19. ",Receive Mask Bit 19" "0,1" bitfld.long 0x14 18. ",Receive Mask Bit 18" "0,1" bitfld.long 0x14 17. ",Receive Mask Bit 17" "0,1" bitfld.long 0x14 16. ",Receive Mask Bit 16" "0,1" bitfld.long 0x14 15. ",Receive Mask Bit 15" "0,1" bitfld.long 0x14 14. ",Receive Mask Bit 14" "0,1" bitfld.long 0x14 13. ",Receive Mask Bit 13" "0,1" bitfld.long 0x14 12. ",Receive Mask Bit 12" "0,1" bitfld.long 0x14 11. ",Receive Mask Bit 11" "0,1" bitfld.long 0x14 10. ",Receive Mask Bit 10" "0,1" bitfld.long 0x14 9. ",Receive Mask Bit 9" "0,1" bitfld.long 0x14 8. ",Receive Mask Bit 8" "0,1" bitfld.long 0x14 7. ",Receive Mask Bit 7" "0,1" bitfld.long 0x14 6. ",Receive Mask Bit 6" "0,1" bitfld.long 0x14 5. ",Receive Mask Bit 5" "0,1" bitfld.long 0x14 4. ",Receive Mask Bit 4" "0,1" bitfld.long 0x14 3. ",Receive Mask Bit 3" "0,1" bitfld.long 0x14 2. ",Receive Mask Bit 2" "0,1" bitfld.long 0x14 1. ",Receive Mask Bit 1" "0,1" bitfld.long 0x14 0. ",Receive Mask Bit 0" "0,1" newline width 16. group.long 0x50++0x03 line.long 0x00 "SACCST_SET/CLR,SSI AC97 Channel SET/CLR Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SACCST9_SET/CLR ,AC97 Channel Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SACCST8_SET/CLR ,AC97 Channel Status 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SACCST7_SET/CLR ,AC97 Channel Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SACCST6_SET/CLR ,AC97 Channel Status 6" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SACCST5_SET/CLR ,AC97 Channel Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SACCST4_SET/CLR ,AC97 Channel Status 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SACCST3_SET/CLR ,AC97 Channel Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SACCST2_SET/CLR ,AC97 Channel Status 2" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SACCST1_SET/CLR ,AC97 Channel Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SACCST0_SET/CLR ,AC97 Channel Status 0" "Disabled,Enabled" width 0x0B else base ad:0x4202C000 width 8. group.long 0x00++0x07 line.long 0x00 "STX0,Transmit Data Register 0" line.long 0x04 "STX1,Transmit Data Register 1" rgroup.long 0x08++0x07 line.long 0x00 "SRX0,Receive Data Register 0" line.long 0x04 "SRX1,Receive Data Register 1" group.long 0x10++0x13 line.long 0x00 "SCR,SSI Control Register" bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched" bitfld.long 0x00 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes" bitfld.long 0x00 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes" bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "0,1" newline bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal" bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected" bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled" line.long 0x04 "SISR,SSI Interrupt Status Register" bitfld.long 0x04 24. " RFRC ,Receive Frame Complete" "Not reached,Reached" bitfld.long 0x04 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached" bitfld.long 0x04 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated" bitfld.long 0x04 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated" newline bitfld.long 0x04 16. " RXT ,Receive Tag Updated" "Not updated,Updated" bitfld.long 0x04 15. " RDR1 ,Receive Data Ready 1" "No new data,New data" bitfld.long 0x04 14. " RDR0 ,Receive Data Ready 0" "No new data,New data" bitfld.long 0x04 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty" newline bitfld.long 0x04 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty" eventfld.long 0x04 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error" eventfld.long 0x04 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error" eventfld.long 0x04 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error" newline eventfld.long 0x04 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error" bitfld.long 0x04 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 5. " TLS ,Transmit Last Time Slot" "No,Yes" newline bitfld.long 0x04 4. " RLS ,Receive Last Time Slot" "No,Yes" bitfld.long 0x04 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full" bitfld.long 0x04 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full" bitfld.long 0x04 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty" newline bitfld.long 0x04 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty" line.long 0x08 "SIER,SSI Interrupt Enable Register" bitfld.long 0x08 24. " RFRCIE ,Receive Frame Complete" "Disabled,Enabled" bitfld.long 0x08 23. " TFRCIE ,Transmit Frame Complete" "Disabled,Enabled" bitfld.long 0x08 22. " RDMAE ,SSI Receiver DMA requests" "Disabled,Enabled" bitfld.long 0x08 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x08 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " CMDAUIE ,Command Address Register Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 17. " CMDDUIE ,Command Data Register Updated Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RXTIE ,Receive Tag Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 15. " RDR1IE ,Receive Data Ready 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 14. " RDR0IE ,Receive Data Ready 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 13. " TDE1IE ,Transmit Data Register Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " TDE0IE ,Transmit Data Register Empty 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 11. " ROE1IE ,Receiver Overrun Error 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ROE0IE ,Receiver Overrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 9. " TUE1IE ,Transmitter Underrun Error 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " TUE0IE ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " TFSIE ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 6. " RFSIE ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x08 5. " TLSIE ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " RLSIE ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 3. " RFF1IE ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " RFF0IE ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " TFE1IE ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled" line.long 0x0C "STCR,SSI Transmit Configuration Register" bitfld.long 0x0C 9. " TXBIT0 ,Transmit Bit 0" "MSB,LSB" bitfld.long 0x0C 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x0C 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled" bitfld.long 0x0C 6. " TFDIR ,Transmit Frame Direction" "External,Internal" newline bitfld.long 0x0C 5. " TXDIR ,Transmit Clock Direction" "External,Internal" bitfld.long 0x0C 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first" bitfld.long 0x0C 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x0C 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low" newline bitfld.long 0x0C 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x0C 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before" line.long 0x10 "SRCR,SSI Receive Configuration Register" bitfld.long 0x10 10. " RXEXT ,Receive Data Extension" "Not extended,Extended" bitfld.long 0x10 9. " RXBIT0 ,Receive Bit 0" "MSB,LSB" bitfld.long 0x10 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x10 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled" newline bitfld.long 0x10 6. " RFDIR ,Receive Frame Direction" "External,Internal" bitfld.long 0x10 5. " RXDIR ,Receive Clock Direction" "External,Internal" bitfld.long 0x10 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first" bitfld.long 0x10 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge" newline bitfld.long 0x10 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low" bitfld.long 0x10 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x10 0. " REFS ,Receive Early Frame Sync" "First bit,One before" if (((per.l(ad:0x4202C000+0x10))&0x08)==0x08) group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" else group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" endif group.long 0x2C++0x03 line.long 0x00 "SFCSR,SSI FIFO Control/Status Register" bitfld.long 0x00 28.--31. " RFCNT1 ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TFCNT1 ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RFWM1 ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 16.--19. " TFWM1 ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" newline bitfld.long 0x00 12.--15. " RFCNT0 ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFCNT0 ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RFWM0 ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 0.--3. " TFWM0 ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" group.long 0x38++0x17 line.long 0x00 "SACNT,SSI AC97 Control Register" hexmask.long.byte 0x00 5.--10. 1. " FRDIV ,Frame Rate Divider" bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached" bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached" bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0" newline bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable" bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled" line.long 0x04 "SACADD,SSI AC97 Command Address Register" hexmask.long.tbyte 0x04 0.--18. 0x01 " SACADD ,AC97 Command Address" line.long 0x08 "SACDAT,SSI AC97 Command Data Register" hexmask.long.tbyte 0x08 0.--19. 1. " SACDAT ,AC97 Command Data" line.long 0x0C "SATAG,SSI AC97 Tag Register" hexmask.long.word 0x0C 0.--15. 1. " SATAG ,AC97 Tag Value" line.long 0x10 "STMSK,SSI Transmit Time Slot Mask Register" bitfld.long 0x10 31. " STMSK ,Transmit Mask Bit 31" "0,1" bitfld.long 0x10 30. ",Transmit Mask Bit 30" "0,1" bitfld.long 0x10 29. ",Transmit Mask Bit 29" "0,1" bitfld.long 0x10 28. ",Transmit Mask Bit 28" "0,1" bitfld.long 0x10 27. ",Transmit Mask Bit 27" "0,1" bitfld.long 0x10 26. ",Transmit Mask Bit 26" "0,1" bitfld.long 0x10 25. ",Transmit Mask Bit 25" "0,1" bitfld.long 0x10 24. ",Transmit Mask Bit 24" "0,1" bitfld.long 0x10 23. ",Transmit Mask Bit 23" "0,1" bitfld.long 0x10 22. ",Transmit Mask Bit 22" "0,1" bitfld.long 0x10 21. ",Transmit Mask Bit 21" "0,1" bitfld.long 0x10 20. ",Transmit Mask Bit 20" "0,1" bitfld.long 0x10 19. ",Transmit Mask Bit 19" "0,1" bitfld.long 0x10 18. ",Transmit Mask Bit 18" "0,1" bitfld.long 0x10 17. ",Transmit Mask Bit 17" "0,1" bitfld.long 0x10 16. ",Transmit Mask Bit 16" "0,1" bitfld.long 0x10 15. ",Transmit Mask Bit 15" "0,1" bitfld.long 0x10 14. ",Transmit Mask Bit 14" "0,1" bitfld.long 0x10 13. ",Transmit Mask Bit 13" "0,1" bitfld.long 0x10 12. ",Transmit Mask Bit 12" "0,1" bitfld.long 0x10 11. ",Transmit Mask Bit 11" "0,1" bitfld.long 0x10 10. ",Transmit Mask Bit 10" "0,1" bitfld.long 0x10 9. ",Transmit Mask Bit 9" "0,1" bitfld.long 0x10 8. ",Transmit Mask Bit 8" "0,1" bitfld.long 0x10 7. ",Transmit Mask Bit 7" "0,1" bitfld.long 0x10 6. ",Transmit Mask Bit 6" "0,1" bitfld.long 0x10 5. ",Transmit Mask Bit 5" "0,1" bitfld.long 0x10 4. ",Transmit Mask Bit 4" "0,1" bitfld.long 0x10 3. ",Transmit Mask Bit 3" "0,1" bitfld.long 0x10 2. ",Transmit Mask Bit 2" "0,1" bitfld.long 0x10 1. ",Transmit Mask Bit 1" "0,1" bitfld.long 0x10 0. ",Transmit Mask Bit 0" "0,1" line.long 0x14 "SRMSK,SSI Receive Time Slot Mask Register" bitfld.long 0x14 31. " SRMSK ,Receive Mask Bit 31" "0,1" bitfld.long 0x14 30. ",Receive Mask Bit 30" "0,1" bitfld.long 0x14 29. ",Receive Mask Bit 29" "0,1" bitfld.long 0x14 28. ",Receive Mask Bit 28" "0,1" bitfld.long 0x14 27. ",Receive Mask Bit 27" "0,1" bitfld.long 0x14 26. ",Receive Mask Bit 26" "0,1" bitfld.long 0x14 25. ",Receive Mask Bit 25" "0,1" bitfld.long 0x14 24. ",Receive Mask Bit 24" "0,1" bitfld.long 0x14 23. ",Receive Mask Bit 23" "0,1" bitfld.long 0x14 22. ",Receive Mask Bit 22" "0,1" bitfld.long 0x14 21. ",Receive Mask Bit 21" "0,1" bitfld.long 0x14 20. ",Receive Mask Bit 20" "0,1" bitfld.long 0x14 19. ",Receive Mask Bit 19" "0,1" bitfld.long 0x14 18. ",Receive Mask Bit 18" "0,1" bitfld.long 0x14 17. ",Receive Mask Bit 17" "0,1" bitfld.long 0x14 16. ",Receive Mask Bit 16" "0,1" bitfld.long 0x14 15. ",Receive Mask Bit 15" "0,1" bitfld.long 0x14 14. ",Receive Mask Bit 14" "0,1" bitfld.long 0x14 13. ",Receive Mask Bit 13" "0,1" bitfld.long 0x14 12. ",Receive Mask Bit 12" "0,1" bitfld.long 0x14 11. ",Receive Mask Bit 11" "0,1" bitfld.long 0x14 10. ",Receive Mask Bit 10" "0,1" bitfld.long 0x14 9. ",Receive Mask Bit 9" "0,1" bitfld.long 0x14 8. ",Receive Mask Bit 8" "0,1" bitfld.long 0x14 7. ",Receive Mask Bit 7" "0,1" bitfld.long 0x14 6. ",Receive Mask Bit 6" "0,1" bitfld.long 0x14 5. ",Receive Mask Bit 5" "0,1" bitfld.long 0x14 4. ",Receive Mask Bit 4" "0,1" bitfld.long 0x14 3. ",Receive Mask Bit 3" "0,1" bitfld.long 0x14 2. ",Receive Mask Bit 2" "0,1" bitfld.long 0x14 1. ",Receive Mask Bit 1" "0,1" bitfld.long 0x14 0. ",Receive Mask Bit 0" "0,1" newline width 16. group.long 0x50++0x03 line.long 0x00 "SACCST_SET/CLR,SSI AC97 Channel SET/CLR Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SACCST9_SET/CLR ,AC97 Channel Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SACCST8_SET/CLR ,AC97 Channel Status 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SACCST7_SET/CLR ,AC97 Channel Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SACCST6_SET/CLR ,AC97 Channel Status 6" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SACCST5_SET/CLR ,AC97 Channel Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SACCST4_SET/CLR ,AC97 Channel Status 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SACCST3_SET/CLR ,AC97 Channel Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SACCST2_SET/CLR ,AC97 Channel Status 2" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SACCST1_SET/CLR ,AC97 Channel Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SACCST0_SET/CLR ,AC97 Channel Status 0" "Disabled,Enabled" width 0x0B endif tree.end tree "SSI3" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02030000 width 8. group.long 0x00++0x07 line.long 0x00 "STX0,Transmit Data Register 0" line.long 0x04 "STX1,Transmit Data Register 1" rgroup.long 0x08++0x07 line.long 0x00 "SRX0,Receive Data Register 0" line.long 0x04 "SRX1,Receive Data Register 1" group.long 0x10++0x13 line.long 0x00 "SCR,SSI Control Register" bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched" bitfld.long 0x00 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes" bitfld.long 0x00 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes" bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "0,1" newline bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal" bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected" bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled" line.long 0x04 "SISR,SSI Interrupt Status Register" bitfld.long 0x04 24. " RFRC ,Receive Frame Complete" "Not reached,Reached" bitfld.long 0x04 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached" bitfld.long 0x04 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated" bitfld.long 0x04 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated" newline bitfld.long 0x04 16. " RXT ,Receive Tag Updated" "Not updated,Updated" bitfld.long 0x04 15. " RDR1 ,Receive Data Ready 1" "No new data,New data" bitfld.long 0x04 14. " RDR0 ,Receive Data Ready 0" "No new data,New data" bitfld.long 0x04 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty" newline bitfld.long 0x04 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty" eventfld.long 0x04 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error" eventfld.long 0x04 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error" eventfld.long 0x04 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error" newline eventfld.long 0x04 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error" bitfld.long 0x04 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 5. " TLS ,Transmit Last Time Slot" "No,Yes" newline bitfld.long 0x04 4. " RLS ,Receive Last Time Slot" "No,Yes" bitfld.long 0x04 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full" bitfld.long 0x04 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full" bitfld.long 0x04 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty" newline bitfld.long 0x04 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty" line.long 0x08 "SIER,SSI Interrupt Enable Register" bitfld.long 0x08 24. " RFRCIE ,Receive Frame Complete" "Disabled,Enabled" bitfld.long 0x08 23. " TFRCIE ,Transmit Frame Complete" "Disabled,Enabled" bitfld.long 0x08 22. " RDMAE ,SSI Receiver DMA requests" "Disabled,Enabled" bitfld.long 0x08 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x08 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " CMDAUIE ,Command Address Register Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 17. " CMDDUIE ,Command Data Register Updated Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RXTIE ,Receive Tag Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 15. " RDR1IE ,Receive Data Ready 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 14. " RDR0IE ,Receive Data Ready 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 13. " TDE1IE ,Transmit Data Register Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " TDE0IE ,Transmit Data Register Empty 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 11. " ROE1IE ,Receiver Overrun Error 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ROE0IE ,Receiver Overrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 9. " TUE1IE ,Transmitter Underrun Error 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " TUE0IE ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " TFSIE ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 6. " RFSIE ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x08 5. " TLSIE ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " RLSIE ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 3. " RFF1IE ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " RFF0IE ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " TFE1IE ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled" line.long 0x0C "STCR,SSI Transmit Configuration Register" bitfld.long 0x0C 9. " TXBIT0 ,Transmit Bit 0" "MSB,LSB" bitfld.long 0x0C 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x0C 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled" bitfld.long 0x0C 6. " TFDIR ,Transmit Frame Direction" "External,Internal" newline bitfld.long 0x0C 5. " TXDIR ,Transmit Clock Direction" "External,Internal" bitfld.long 0x0C 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first" bitfld.long 0x0C 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x0C 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low" newline bitfld.long 0x0C 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x0C 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before" line.long 0x10 "SRCR,SSI Receive Configuration Register" bitfld.long 0x10 10. " RXEXT ,Receive Data Extension" "Not extended,Extended" bitfld.long 0x10 9. " RXBIT0 ,Receive Bit 0" "MSB,LSB" bitfld.long 0x10 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x10 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled" newline bitfld.long 0x10 6. " RFDIR ,Receive Frame Direction" "External,Internal" bitfld.long 0x10 5. " RXDIR ,Receive Clock Direction" "External,Internal" bitfld.long 0x10 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first" bitfld.long 0x10 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge" newline bitfld.long 0x10 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low" bitfld.long 0x10 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x10 0. " REFS ,Receive Early Frame Sync" "First bit,One before" if (((per.l(ad:0x02030000+0x10))&0x08)==0x08) group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" else group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" endif group.long 0x2C++0x03 line.long 0x00 "SFCSR,SSI FIFO Control/Status Register" bitfld.long 0x00 28.--31. " RFCNT1 ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TFCNT1 ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RFWM1 ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 16.--19. " TFWM1 ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" newline bitfld.long 0x00 12.--15. " RFCNT0 ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFCNT0 ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RFWM0 ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 0.--3. " TFWM0 ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" group.long 0x38++0x17 line.long 0x00 "SACNT,SSI AC97 Control Register" hexmask.long.byte 0x00 5.--10. 1. " FRDIV ,Frame Rate Divider" bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached" bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached" bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0" newline bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable" bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled" line.long 0x04 "SACADD,SSI AC97 Command Address Register" hexmask.long.tbyte 0x04 0.--18. 0x01 " SACADD ,AC97 Command Address" line.long 0x08 "SACDAT,SSI AC97 Command Data Register" hexmask.long.tbyte 0x08 0.--19. 1. " SACDAT ,AC97 Command Data" line.long 0x0C "SATAG,SSI AC97 Tag Register" hexmask.long.word 0x0C 0.--15. 1. " SATAG ,AC97 Tag Value" line.long 0x10 "STMSK,SSI Transmit Time Slot Mask Register" bitfld.long 0x10 31. " STMSK ,Transmit Mask Bit 31" "0,1" bitfld.long 0x10 30. ",Transmit Mask Bit 30" "0,1" bitfld.long 0x10 29. ",Transmit Mask Bit 29" "0,1" bitfld.long 0x10 28. ",Transmit Mask Bit 28" "0,1" bitfld.long 0x10 27. ",Transmit Mask Bit 27" "0,1" bitfld.long 0x10 26. ",Transmit Mask Bit 26" "0,1" bitfld.long 0x10 25. ",Transmit Mask Bit 25" "0,1" bitfld.long 0x10 24. ",Transmit Mask Bit 24" "0,1" bitfld.long 0x10 23. ",Transmit Mask Bit 23" "0,1" bitfld.long 0x10 22. ",Transmit Mask Bit 22" "0,1" bitfld.long 0x10 21. ",Transmit Mask Bit 21" "0,1" bitfld.long 0x10 20. ",Transmit Mask Bit 20" "0,1" bitfld.long 0x10 19. ",Transmit Mask Bit 19" "0,1" bitfld.long 0x10 18. ",Transmit Mask Bit 18" "0,1" bitfld.long 0x10 17. ",Transmit Mask Bit 17" "0,1" bitfld.long 0x10 16. ",Transmit Mask Bit 16" "0,1" bitfld.long 0x10 15. ",Transmit Mask Bit 15" "0,1" bitfld.long 0x10 14. ",Transmit Mask Bit 14" "0,1" bitfld.long 0x10 13. ",Transmit Mask Bit 13" "0,1" bitfld.long 0x10 12. ",Transmit Mask Bit 12" "0,1" bitfld.long 0x10 11. ",Transmit Mask Bit 11" "0,1" bitfld.long 0x10 10. ",Transmit Mask Bit 10" "0,1" bitfld.long 0x10 9. ",Transmit Mask Bit 9" "0,1" bitfld.long 0x10 8. ",Transmit Mask Bit 8" "0,1" bitfld.long 0x10 7. ",Transmit Mask Bit 7" "0,1" bitfld.long 0x10 6. ",Transmit Mask Bit 6" "0,1" bitfld.long 0x10 5. ",Transmit Mask Bit 5" "0,1" bitfld.long 0x10 4. ",Transmit Mask Bit 4" "0,1" bitfld.long 0x10 3. ",Transmit Mask Bit 3" "0,1" bitfld.long 0x10 2. ",Transmit Mask Bit 2" "0,1" bitfld.long 0x10 1. ",Transmit Mask Bit 1" "0,1" bitfld.long 0x10 0. ",Transmit Mask Bit 0" "0,1" line.long 0x14 "SRMSK,SSI Receive Time Slot Mask Register" bitfld.long 0x14 31. " SRMSK ,Receive Mask Bit 31" "0,1" bitfld.long 0x14 30. ",Receive Mask Bit 30" "0,1" bitfld.long 0x14 29. ",Receive Mask Bit 29" "0,1" bitfld.long 0x14 28. ",Receive Mask Bit 28" "0,1" bitfld.long 0x14 27. ",Receive Mask Bit 27" "0,1" bitfld.long 0x14 26. ",Receive Mask Bit 26" "0,1" bitfld.long 0x14 25. ",Receive Mask Bit 25" "0,1" bitfld.long 0x14 24. ",Receive Mask Bit 24" "0,1" bitfld.long 0x14 23. ",Receive Mask Bit 23" "0,1" bitfld.long 0x14 22. ",Receive Mask Bit 22" "0,1" bitfld.long 0x14 21. ",Receive Mask Bit 21" "0,1" bitfld.long 0x14 20. ",Receive Mask Bit 20" "0,1" bitfld.long 0x14 19. ",Receive Mask Bit 19" "0,1" bitfld.long 0x14 18. ",Receive Mask Bit 18" "0,1" bitfld.long 0x14 17. ",Receive Mask Bit 17" "0,1" bitfld.long 0x14 16. ",Receive Mask Bit 16" "0,1" bitfld.long 0x14 15. ",Receive Mask Bit 15" "0,1" bitfld.long 0x14 14. ",Receive Mask Bit 14" "0,1" bitfld.long 0x14 13. ",Receive Mask Bit 13" "0,1" bitfld.long 0x14 12. ",Receive Mask Bit 12" "0,1" bitfld.long 0x14 11. ",Receive Mask Bit 11" "0,1" bitfld.long 0x14 10. ",Receive Mask Bit 10" "0,1" bitfld.long 0x14 9. ",Receive Mask Bit 9" "0,1" bitfld.long 0x14 8. ",Receive Mask Bit 8" "0,1" bitfld.long 0x14 7. ",Receive Mask Bit 7" "0,1" bitfld.long 0x14 6. ",Receive Mask Bit 6" "0,1" bitfld.long 0x14 5. ",Receive Mask Bit 5" "0,1" bitfld.long 0x14 4. ",Receive Mask Bit 4" "0,1" bitfld.long 0x14 3. ",Receive Mask Bit 3" "0,1" bitfld.long 0x14 2. ",Receive Mask Bit 2" "0,1" bitfld.long 0x14 1. ",Receive Mask Bit 1" "0,1" bitfld.long 0x14 0. ",Receive Mask Bit 0" "0,1" newline width 16. group.long 0x50++0x03 line.long 0x00 "SACCST_SET/CLR,SSI AC97 Channel SET/CLR Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SACCST9_SET/CLR ,AC97 Channel Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SACCST8_SET/CLR ,AC97 Channel Status 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SACCST7_SET/CLR ,AC97 Channel Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SACCST6_SET/CLR ,AC97 Channel Status 6" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SACCST5_SET/CLR ,AC97 Channel Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SACCST4_SET/CLR ,AC97 Channel Status 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SACCST3_SET/CLR ,AC97 Channel Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SACCST2_SET/CLR ,AC97 Channel Status 2" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SACCST1_SET/CLR ,AC97 Channel Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SACCST0_SET/CLR ,AC97 Channel Status 0" "Disabled,Enabled" width 0x0B else base ad:0x42030000 width 8. group.long 0x00++0x07 line.long 0x00 "STX0,Transmit Data Register 0" line.long 0x04 "STX1,Transmit Data Register 1" rgroup.long 0x08++0x07 line.long 0x00 "SRX0,Receive Data Register 0" line.long 0x04 "SRX1,Receive Data Register 1" group.long 0x10++0x13 line.long 0x00 "SCR,SSI Control Register" bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched" bitfld.long 0x00 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes" bitfld.long 0x00 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes" bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "0,1" newline bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal" bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected" bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled" line.long 0x04 "SISR,SSI Interrupt Status Register" bitfld.long 0x04 24. " RFRC ,Receive Frame Complete" "Not reached,Reached" bitfld.long 0x04 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached" bitfld.long 0x04 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated" bitfld.long 0x04 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated" newline bitfld.long 0x04 16. " RXT ,Receive Tag Updated" "Not updated,Updated" bitfld.long 0x04 15. " RDR1 ,Receive Data Ready 1" "No new data,New data" bitfld.long 0x04 14. " RDR0 ,Receive Data Ready 0" "No new data,New data" bitfld.long 0x04 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty" newline bitfld.long 0x04 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty" eventfld.long 0x04 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error" eventfld.long 0x04 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error" eventfld.long 0x04 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error" newline eventfld.long 0x04 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error" bitfld.long 0x04 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 5. " TLS ,Transmit Last Time Slot" "No,Yes" newline bitfld.long 0x04 4. " RLS ,Receive Last Time Slot" "No,Yes" bitfld.long 0x04 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full" bitfld.long 0x04 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full" bitfld.long 0x04 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty" newline bitfld.long 0x04 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty" line.long 0x08 "SIER,SSI Interrupt Enable Register" bitfld.long 0x08 24. " RFRCIE ,Receive Frame Complete" "Disabled,Enabled" bitfld.long 0x08 23. " TFRCIE ,Transmit Frame Complete" "Disabled,Enabled" bitfld.long 0x08 22. " RDMAE ,SSI Receiver DMA requests" "Disabled,Enabled" bitfld.long 0x08 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x08 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " CMDAUIE ,Command Address Register Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 17. " CMDDUIE ,Command Data Register Updated Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RXTIE ,Receive Tag Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 15. " RDR1IE ,Receive Data Ready 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 14. " RDR0IE ,Receive Data Ready 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 13. " TDE1IE ,Transmit Data Register Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " TDE0IE ,Transmit Data Register Empty 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 11. " ROE1IE ,Receiver Overrun Error 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ROE0IE ,Receiver Overrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 9. " TUE1IE ,Transmitter Underrun Error 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " TUE0IE ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " TFSIE ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 6. " RFSIE ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x08 5. " TLSIE ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " RLSIE ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 3. " RFF1IE ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " RFF0IE ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " TFE1IE ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled" line.long 0x0C "STCR,SSI Transmit Configuration Register" bitfld.long 0x0C 9. " TXBIT0 ,Transmit Bit 0" "MSB,LSB" bitfld.long 0x0C 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x0C 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled" bitfld.long 0x0C 6. " TFDIR ,Transmit Frame Direction" "External,Internal" newline bitfld.long 0x0C 5. " TXDIR ,Transmit Clock Direction" "External,Internal" bitfld.long 0x0C 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first" bitfld.long 0x0C 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x0C 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low" newline bitfld.long 0x0C 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x0C 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before" line.long 0x10 "SRCR,SSI Receive Configuration Register" bitfld.long 0x10 10. " RXEXT ,Receive Data Extension" "Not extended,Extended" bitfld.long 0x10 9. " RXBIT0 ,Receive Bit 0" "MSB,LSB" bitfld.long 0x10 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x10 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled" newline bitfld.long 0x10 6. " RFDIR ,Receive Frame Direction" "External,Internal" bitfld.long 0x10 5. " RXDIR ,Receive Clock Direction" "External,Internal" bitfld.long 0x10 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first" bitfld.long 0x10 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge" newline bitfld.long 0x10 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low" bitfld.long 0x10 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x10 0. " REFS ,Receive Early Frame Sync" "First bit,One before" if (((per.l(ad:0x42030000+0x10))&0x08)==0x08) group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" else group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" endif group.long 0x2C++0x03 line.long 0x00 "SFCSR,SSI FIFO Control/Status Register" bitfld.long 0x00 28.--31. " RFCNT1 ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TFCNT1 ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RFWM1 ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 16.--19. " TFWM1 ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" newline bitfld.long 0x00 12.--15. " RFCNT0 ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFCNT0 ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RFWM0 ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 0.--3. " TFWM0 ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" group.long 0x38++0x17 line.long 0x00 "SACNT,SSI AC97 Control Register" hexmask.long.byte 0x00 5.--10. 1. " FRDIV ,Frame Rate Divider" bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached" bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached" bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0" newline bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable" bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled" line.long 0x04 "SACADD,SSI AC97 Command Address Register" hexmask.long.tbyte 0x04 0.--18. 0x01 " SACADD ,AC97 Command Address" line.long 0x08 "SACDAT,SSI AC97 Command Data Register" hexmask.long.tbyte 0x08 0.--19. 1. " SACDAT ,AC97 Command Data" line.long 0x0C "SATAG,SSI AC97 Tag Register" hexmask.long.word 0x0C 0.--15. 1. " SATAG ,AC97 Tag Value" line.long 0x10 "STMSK,SSI Transmit Time Slot Mask Register" bitfld.long 0x10 31. " STMSK ,Transmit Mask Bit 31" "0,1" bitfld.long 0x10 30. ",Transmit Mask Bit 30" "0,1" bitfld.long 0x10 29. ",Transmit Mask Bit 29" "0,1" bitfld.long 0x10 28. ",Transmit Mask Bit 28" "0,1" bitfld.long 0x10 27. ",Transmit Mask Bit 27" "0,1" bitfld.long 0x10 26. ",Transmit Mask Bit 26" "0,1" bitfld.long 0x10 25. ",Transmit Mask Bit 25" "0,1" bitfld.long 0x10 24. ",Transmit Mask Bit 24" "0,1" bitfld.long 0x10 23. ",Transmit Mask Bit 23" "0,1" bitfld.long 0x10 22. ",Transmit Mask Bit 22" "0,1" bitfld.long 0x10 21. ",Transmit Mask Bit 21" "0,1" bitfld.long 0x10 20. ",Transmit Mask Bit 20" "0,1" bitfld.long 0x10 19. ",Transmit Mask Bit 19" "0,1" bitfld.long 0x10 18. ",Transmit Mask Bit 18" "0,1" bitfld.long 0x10 17. ",Transmit Mask Bit 17" "0,1" bitfld.long 0x10 16. ",Transmit Mask Bit 16" "0,1" bitfld.long 0x10 15. ",Transmit Mask Bit 15" "0,1" bitfld.long 0x10 14. ",Transmit Mask Bit 14" "0,1" bitfld.long 0x10 13. ",Transmit Mask Bit 13" "0,1" bitfld.long 0x10 12. ",Transmit Mask Bit 12" "0,1" bitfld.long 0x10 11. ",Transmit Mask Bit 11" "0,1" bitfld.long 0x10 10. ",Transmit Mask Bit 10" "0,1" bitfld.long 0x10 9. ",Transmit Mask Bit 9" "0,1" bitfld.long 0x10 8. ",Transmit Mask Bit 8" "0,1" bitfld.long 0x10 7. ",Transmit Mask Bit 7" "0,1" bitfld.long 0x10 6. ",Transmit Mask Bit 6" "0,1" bitfld.long 0x10 5. ",Transmit Mask Bit 5" "0,1" bitfld.long 0x10 4. ",Transmit Mask Bit 4" "0,1" bitfld.long 0x10 3. ",Transmit Mask Bit 3" "0,1" bitfld.long 0x10 2. ",Transmit Mask Bit 2" "0,1" bitfld.long 0x10 1. ",Transmit Mask Bit 1" "0,1" bitfld.long 0x10 0. ",Transmit Mask Bit 0" "0,1" line.long 0x14 "SRMSK,SSI Receive Time Slot Mask Register" bitfld.long 0x14 31. " SRMSK ,Receive Mask Bit 31" "0,1" bitfld.long 0x14 30. ",Receive Mask Bit 30" "0,1" bitfld.long 0x14 29. ",Receive Mask Bit 29" "0,1" bitfld.long 0x14 28. ",Receive Mask Bit 28" "0,1" bitfld.long 0x14 27. ",Receive Mask Bit 27" "0,1" bitfld.long 0x14 26. ",Receive Mask Bit 26" "0,1" bitfld.long 0x14 25. ",Receive Mask Bit 25" "0,1" bitfld.long 0x14 24. ",Receive Mask Bit 24" "0,1" bitfld.long 0x14 23. ",Receive Mask Bit 23" "0,1" bitfld.long 0x14 22. ",Receive Mask Bit 22" "0,1" bitfld.long 0x14 21. ",Receive Mask Bit 21" "0,1" bitfld.long 0x14 20. ",Receive Mask Bit 20" "0,1" bitfld.long 0x14 19. ",Receive Mask Bit 19" "0,1" bitfld.long 0x14 18. ",Receive Mask Bit 18" "0,1" bitfld.long 0x14 17. ",Receive Mask Bit 17" "0,1" bitfld.long 0x14 16. ",Receive Mask Bit 16" "0,1" bitfld.long 0x14 15. ",Receive Mask Bit 15" "0,1" bitfld.long 0x14 14. ",Receive Mask Bit 14" "0,1" bitfld.long 0x14 13. ",Receive Mask Bit 13" "0,1" bitfld.long 0x14 12. ",Receive Mask Bit 12" "0,1" bitfld.long 0x14 11. ",Receive Mask Bit 11" "0,1" bitfld.long 0x14 10. ",Receive Mask Bit 10" "0,1" bitfld.long 0x14 9. ",Receive Mask Bit 9" "0,1" bitfld.long 0x14 8. ",Receive Mask Bit 8" "0,1" bitfld.long 0x14 7. ",Receive Mask Bit 7" "0,1" bitfld.long 0x14 6. ",Receive Mask Bit 6" "0,1" bitfld.long 0x14 5. ",Receive Mask Bit 5" "0,1" bitfld.long 0x14 4. ",Receive Mask Bit 4" "0,1" bitfld.long 0x14 3. ",Receive Mask Bit 3" "0,1" bitfld.long 0x14 2. ",Receive Mask Bit 2" "0,1" bitfld.long 0x14 1. ",Receive Mask Bit 1" "0,1" bitfld.long 0x14 0. ",Receive Mask Bit 0" "0,1" newline width 16. group.long 0x50++0x03 line.long 0x00 "SACCST_SET/CLR,SSI AC97 Channel SET/CLR Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SACCST9_SET/CLR ,AC97 Channel Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SACCST8_SET/CLR ,AC97 Channel Status 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SACCST7_SET/CLR ,AC97 Channel Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SACCST6_SET/CLR ,AC97 Channel Status 6" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SACCST5_SET/CLR ,AC97 Channel Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SACCST4_SET/CLR ,AC97 Channel Status 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SACCST3_SET/CLR ,AC97 Channel Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SACCST2_SET/CLR ,AC97 Channel Status 2" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SACCST1_SET/CLR ,AC97 Channel Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SACCST0_SET/CLR ,AC97 Channel Status 0" "Disabled,Enabled" width 0x0B endif tree.end tree.end tree "TEMPMON (Temperature Monitor)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020C8180 else base ad:0x420C8180 endif width 16. group.long 0x00++0x1F line.long 0x00 "TEMPSENSE0,Tempsensor Control Register 0" hexmask.long.word 0x00 20.--31. 1. " ALARM_VALUE ,Temperature count" hexmask.long.word 0x00 8.--19. 1. " TEMP_CNT ,Last measured temperature" rbitfld.long 0x00 2. " FINISHED ,Latest temp valid" "Invalid,Valid" textline " " bitfld.long 0x00 1. " MEASURE_TEMP ,Starts the measurement process" "Stopped,Started" bitfld.long 0x00 0. " POWER_DOWN ,Power down the temperature sensor" "Powered up,Powered down" line.long 0x04 "TEMPSENSE0_SET, Tempsensor Control Set Register 0" hexmask.long.word 0x04 20.--31. 1. " ALARM_VALUE ,Temperature count set" hexmask.long.word 0x04 8.--19. 1. " TEMP_CNT ,Last measured temperature set" rbitfld.long 0x04 2. " FINISHED ,Latest temp valid set" "No effect,Set" textline " " bitfld.long 0x04 1. " MEASURE_TEMP ,Starts the measurement process set" "No effect,Set" bitfld.long 0x04 0. " POWER_DOWN ,Power down the temperature sensor set" "No effect,Set" line.long 0x08 "TEMPSENSE0_CLR, Tempsensor Control Clear Register 0" hexmask.long.word 0x08 20.--31. 1. " ALARM_VALUE ,Temperature count clear" hexmask.long.word 0x08 8.--19. 1. " TEMP_CNT ,Last measured temperature clear" rbitfld.long 0x08 2. " FINISHED ,Latest temp valid clear" "No effect,Cleared" textline " " bitfld.long 0x08 1. " MEASURE_TEMP ,Starts the measurement process clear" "No effect,Cleared" bitfld.long 0x08 0. " POWER_DOWN ,Power down the temperature sensor clear" "No effect,Cleared" line.long 0x0C "TEMPSENSE0_TOG, Tempsensor Control Toggle Register 0" hexmask.long.word 0x0C 20.--31. 1. " ALARM_VALUE ,Temperature count toggle" hexmask.long.word 0x0C 8.--19. 1. " TEMP_CNT ,Last measured temperature toggle" rbitfld.long 0x0C 2. " FINISHED ,Latest temp valid toggle" "Not toggled,Toggled" textline " " bitfld.long 0x0C 1. " MEASURE_TEMP ,Starts the measurement process toggle" "Not toggled,Toggled" bitfld.long 0x0C 0. " POWER_DOWN ,Power down the temperature sensor toggle" "Not toggled,Toggled" line.long 0x10 "TEMPSENSE1,Tempsensor Control Register 1" hexmask.long.word 0x10 0.--15. 1. " MEASURE_FREQ ,Numbers of RTC clocks to wait before automatically repeating" line.long 0x14 "TEMPSENSE1_SET,Tempsensor Control Register 1" hexmask.long.word 0x14 0.--15. 1. " MEASURE_FREQ ,Numbers of RTC clocks to wait before automatically repeating set" line.long 0x18 "TEMPSENSE1_CLR,Tempsensor Control Register 1" hexmask.long.word 0x18 0.--15. 1. " MEASURE_FREQ ,Numbers of RTC clocks to wait before automatically repeating clear" line.long 0x1C "TEMPSENSE1_TOG,Tempsensor Control Register 1" hexmask.long.word 0x1C 0.--15. 1. " MEASURE_FREQ ,Numbers of RTC clocks to wait before automatically repeating toggle" group.long 0x110++0x00F line.long 0x00 "TEMPSENSE2,Tempsensor Control Register 2" hexmask.long.word 0x00 16.--27. 1. " PANIC_ALARM_VALUE ,Temperature that will generate a panic interrupt when exceeded by the temperature measurement" hexmask.long.word 0x00 0.--11. 1. " LOW_ALARM_VALUE ,Temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement" line.long 0x04 "TEMPSENSE2_SET,Tempsensor Control Register 2" hexmask.long.word 0x04 16.--27. 1. " PANIC_ALARM_VALUE ,Temperature that will generate a panic interrupt when exceeded by the temperature measurement" hexmask.long.word 0x04 0.--11. 1. " LOW_ALARM_VALUE ,Temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement" line.long 0x08 "TEMPSENSE2_CLR,Tempsensor Control Register 2" hexmask.long.word 0x08 16.--27. 1. " PANIC_ALARM_VALUE ,Temperature that will generate a panic interrupt when exceeded by the temperature measurement" hexmask.long.word 0x08 0.--11. 1. " LOW_ALARM_VALUE ,Temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement" line.long 0x0C "TEMPSENSE2_TOG,Tempsensor Control Register 2" hexmask.long.word 0x0C 16.--27. 1. " PANIC_ALARM_VALUE ,Temperature that will generate a panic interrupt when exceeded by the temperature measurement" hexmask.long.word 0x0C 0.--11. 1. " LOW_ALARM_VALUE ,Temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement" width 0xb tree.end tree.open "UART (Universal Asynchronous Receiver/Transmitter)" tree "UART1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02020000 width 7. if ((((per.l(ad:0x02020000+0x80))&0x01)==0x00)||(((per.l(ad:0x02020000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x02020000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x02020000+0x80)&0x01)==0x00)||((per.l(ad:0x02020000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x02020000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x02020000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02020000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02020000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02020000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02020000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02020000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02020000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb else base ad:0x42020000 width 7. if ((((per.l(ad:0x42020000+0x80))&0x01)==0x00)||(((per.l(ad:0x42020000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x42020000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x42020000+0x80)&0x01)==0x00)||((per.l(ad:0x42020000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x42020000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x42020000+0x90))&0x40)==0x40)&&((((per.l(ad:0x42020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x42020000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x42020000+0x90))&0x40)==0x40)&&((((per.l(ad:0x42020000+0xB8))&0x01)==0x01)||((((per.l(ad:0x42020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x42020000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x42020000+0x90))&0x40)==0x00)&&((((per.l(ad:0x42020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x42020000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x42020000+0x90))&0x40)==0x00)&&((((per.l(ad:0x42020000+0xB8))&0x01)==0x01)||((((per.l(ad:0x42020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x42020000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x42020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x42020000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x42020000+0xB8))&0x01)==0x01)||((((per.l(ad:0x42020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x42020000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb endif tree.end tree "UART2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021E8000 width 7. if ((((per.l(ad:0x021E8000+0x80))&0x01)==0x00)||(((per.l(ad:0x021E8000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x021E8000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x021E8000+0x80)&0x01)==0x00)||((per.l(ad:0x021E8000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x021E8000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x021E8000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021E8000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021E8000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021E8000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021E8000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021E8000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021E8000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021E8000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021E8000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021E8000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x021E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021E8000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021E8000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021E8000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb else base ad:0x421E8000 width 7. if ((((per.l(ad:0x421E8000+0x80))&0x01)==0x00)||(((per.l(ad:0x421E8000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x421E8000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x421E8000+0x80)&0x01)==0x00)||((per.l(ad:0x421E8000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x421E8000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x421E8000+0x90))&0x40)==0x40)&&((((per.l(ad:0x421E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421E8000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421E8000+0x90))&0x40)==0x40)&&((((per.l(ad:0x421E8000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421E8000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421E8000+0x90))&0x40)==0x00)&&((((per.l(ad:0x421E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421E8000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421E8000+0x90))&0x40)==0x00)&&((((per.l(ad:0x421E8000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421E8000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x421E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421E8000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421E8000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421E8000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421E8000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb endif tree.end tree "UART3" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021EC000 width 7. if ((((per.l(ad:0x021EC000+0x80))&0x01)==0x00)||(((per.l(ad:0x021EC000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x021EC000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x021EC000+0x80)&0x01)==0x00)||((per.l(ad:0x021EC000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x021EC000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x021EC000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021EC000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021EC000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021EC000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021EC000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021EC000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021EC000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021EC000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021EC000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021EC000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x021EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021EC000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021EC000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021EC000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb else base ad:0x421EC000 width 7. if ((((per.l(ad:0x421EC000+0x80))&0x01)==0x00)||(((per.l(ad:0x421EC000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x421EC000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x421EC000+0x80)&0x01)==0x00)||((per.l(ad:0x421EC000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x421EC000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x421EC000+0x90))&0x40)==0x40)&&((((per.l(ad:0x421EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421EC000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421EC000+0x90))&0x40)==0x40)&&((((per.l(ad:0x421EC000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421EC000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421EC000+0x90))&0x40)==0x00)&&((((per.l(ad:0x421EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421EC000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421EC000+0x90))&0x40)==0x00)&&((((per.l(ad:0x421EC000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421EC000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x421EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421EC000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421EC000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421EC000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421EC000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb endif tree.end tree "UART4" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021F0000 width 7. if ((((per.l(ad:0x021F0000+0x80))&0x01)==0x00)||(((per.l(ad:0x021F0000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x021F0000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x021F0000+0x80)&0x01)==0x00)||((per.l(ad:0x021F0000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x021F0000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x021F0000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F0000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F0000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021F0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F0000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F0000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F0000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F0000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021F0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F0000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x021F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F0000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F0000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb else base ad:0x421F0000 width 7. if ((((per.l(ad:0x421F0000+0x80))&0x01)==0x00)||(((per.l(ad:0x421F0000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x421F0000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x421F0000+0x80)&0x01)==0x00)||((per.l(ad:0x421F0000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x421F0000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x421F0000+0x90))&0x40)==0x40)&&((((per.l(ad:0x421F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F0000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421F0000+0x90))&0x40)==0x40)&&((((per.l(ad:0x421F0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F0000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421F0000+0x90))&0x40)==0x00)&&((((per.l(ad:0x421F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F0000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421F0000+0x90))&0x40)==0x00)&&((((per.l(ad:0x421F0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F0000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x421F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F0000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421F0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421F0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F0000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb endif tree.end tree "UART5" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x021F4000 width 7. if ((((per.l(ad:0x021F4000+0x80))&0x01)==0x00)||(((per.l(ad:0x021F4000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x021F4000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x021F4000+0x80)&0x01)==0x00)||((per.l(ad:0x021F4000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x021F4000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x021F4000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F4000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021F4000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F4000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F4000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021F4000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F4000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb else base ad:0x421F4000 width 7. if ((((per.l(ad:0x421F4000+0x80))&0x01)==0x00)||(((per.l(ad:0x421F4000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x421F4000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x421F4000+0x80)&0x01)==0x00)||((per.l(ad:0x421F4000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x421F4000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x421F4000+0x90))&0x40)==0x40)&&((((per.l(ad:0x421F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F4000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421F4000+0x90))&0x40)==0x40)&&((((per.l(ad:0x421F4000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F4000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421F4000+0x90))&0x40)==0x00)&&((((per.l(ad:0x421F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F4000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421F4000+0x90))&0x40)==0x00)&&((((per.l(ad:0x421F4000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F4000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x421F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F4000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x421F4000+0xB8))&0x01)==0x01)||((((per.l(ad:0x421F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x421F4000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb endif tree.end tree "UART6" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x022A0000 width 7. if ((((per.l(ad:0x022A0000+0x80))&0x01)==0x00)||(((per.l(ad:0x022A0000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x022A0000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x022A0000+0x80)&0x01)==0x00)||((per.l(ad:0x022A0000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x022A0000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x022A0000+0x90))&0x40)==0x40)&&((((per.l(ad:0x022A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x022A0000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x022A0000+0x90))&0x40)==0x40)&&((((per.l(ad:0x022A0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x022A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x022A0000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x022A0000+0x90))&0x40)==0x00)&&((((per.l(ad:0x022A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x022A0000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x022A0000+0x90))&0x40)==0x00)&&((((per.l(ad:0x022A0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x022A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x022A0000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x022A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x022A0000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x022A0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x022A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x022A0000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb else base ad:0x422A0000 width 7. if ((((per.l(ad:0x422A0000+0x80))&0x01)==0x00)||(((per.l(ad:0x422A0000+0x84))&0x02)==0x00)) hgroup.long 0x00++0x3 hide.long 0x00 "URXD,UART Receiver Register" elif (((per.l(ad:0x422A0000+0xB8))&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" textline " " bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " RX_DATA[8] ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" textline " " hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif if (((per.l(ad:0x422A0000+0x80)&0x01)==0x00)||((per.l(ad:0x422A0000+0x84)&0x02)==0x00)) hgroup.long 0x40++0x3 hide.long 0x00 "UTXD,UART Transmitter Register" else wgroup.long 0x40++0x3 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif if (((per.l(ad:0x422A0000+0xB8))&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "> 4 frames,> 8 frames,> 16 frames,> 32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled," bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x3 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" textline " " bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" textline " " bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" textline " " bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x422A0000+0x90))&0x40)==0x40)&&((((per.l(ad:0x422A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x422A0000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x422A0000+0x90))&0x40)==0x40)&&((((per.l(ad:0x422A0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x422A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x422A0000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x422A0000+0x90))&0x40)==0x00)&&((((per.l(ad:0x422A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x422A0000+0x80))&0x80)==0x80))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x422A0000+0x90))&0x40)==0x00)&&((((per.l(ad:0x422A0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x422A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x422A0000+0x80))&0x80)==0x00)))) group.long 0x88++0x3 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" textline " " bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" textline " " bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x422A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x422A0000+0x80))&0x80)==0x80)) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in In IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x422A0000+0xB8))&0x01)==0x01)||((((per.l(ad:0x422A0000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x422A0000+0x80))&0x80)==0x00))) group.long 0x8c++0x3 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" textline " " bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x3 line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7," textline " " bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," group.long 0x94++0x3 line.long 0x00 "USR1,UART Status Register 1" eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low" rbitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" textline " " eventfld.long 0x00 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" group.long 0x98++0x3 line.long 0x00 "USR2,UART Status Register 2" eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" textline " " rbitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected" textline " " eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" textline " " rbitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error" textline " " rbitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready" group.long 0x9c++0x3 line.long 0x00 "UESC,UART Escape Character Register" hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character" group.long 0xa0++0x0b line.long 0x00 "UTIM,UART Escape Timer Register" hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x04 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x08 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xac++0x3 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xb0++0x3 line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" group.long 0xb4++0x7 line.long 0x00 "UTS,UART Test Register" bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented" bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x04 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x04 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" textline " " bitfld.long 0x04 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" textline " " bitfld.long 0x04 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x04 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0xb endif tree.end tree.end tree "USB Controller (Universal Serial Bus Controller)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02184000 else base ad:0x42184000 endif tree "USB Core Registers" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) tree "OTG1" width 22. rgroup.long (0x00+0x0)++0x03 line.long 0x00 "UOG1_ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION[7:0] ,Revision Number of the Core" hexmask.long.byte 0x00 8.--13. 1. " NID[5:0] ,Ones Complement Version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID[5:0] ,Configuration Number" rgroup.long (0x04+0x0)++0x03 line.long 0x00 "UOG1_HWGENERAL,General Hardware Register" bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "No engine/parallel signaling,Engine present/serial signalling,Soft programmable/Reset to parallel,Soft programmable/Reset to serial" bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Soft programmable reset to UTMI/UMTI+,Soft programmable reset to ULPI DDR,Soft programmable reset to ULPI,Soft programmable reset to Serial" textline " " bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core" "8 bit non programmable,16 bit non programmable,8 bit programmable,16 bit programmable" textline " " rgroup.long (0x08+0x0)++0x03 line.long 0x00 "UOG1_HWHOST,Host Hardware Parameters Register" bitfld.long 0x00 1.--3. " NPORT ,Number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0. " HC ,Host operation mode support for device" "Not supported,Supported" rgroup.long (0x0C+0x0)++0x03 line.long 0x00 "UOG1_HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x00 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device operation mode support" "Not supported,Supported" rgroup.long (0x10+0x0)++0x07 line.long 0x00 "UOG1_HWTXBUF,TX Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "UOG1_HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" textline " " group.long (0x80+0x0)++0xf "Device/Host Timer Registers" line.long 0x00 "UOG1_GPTIMER0LD,General Purpose Timer #0 Load Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x04 "UOG1_GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x04 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x04 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" line.long 0x08 "UOG1_GPTIMER1LD,General Purpose Timer #1 Load Register" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x0C "UOG1_GPTIMER1CTRL,General Purpose Timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x0C 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x0C 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" textline " " group.long (0x90+0x0)++0x03 line.long 0x00 "UOG1_SBUSCFG,System Bus Config" bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface Burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte (0x100+0x0)++0x00 line.byte 0x00 "UOG1_CAPLENGTH,Address offset to the Operational registers" rgroup.word (0x102+0x0)++0x01 line.word 0x00 "UOG1_HCIVERSION,EHCI revision number supported by this host controller" rgroup.long (0x104+0x0)++0x07 line.long 0x00 "UOG1_HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PI ,Port Indicators" "0,1" bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included" bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "UOG1_HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer" bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" rgroup.word (0x120+0x0)++0x1 line.word 0x00 "UOG1_DCIVERSION,Device Interface Version Number Register" rgroup.long (0x124+0x0)++0x3 line.long 0x00 "UOG1_DCCPARAMS,Device Control Capability Parameters Register" bitfld.long 0x00 8. " HC ,Host Capable" "Not supported,Supported" bitfld.long 0x00 7. " DC ,Device Capable" "Not supported,Supported" bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " width 22. group.long (0x140+0x0)++0x03 line.long 0x00 "UOG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard" bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x144+0x0)++0x03 line.long 0x00 "UOG1_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" rbitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested" textline " " bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" else group.long (0x144+0x0)++0x03 line.long 0x00 "UOG1_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" textline " " bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" endif group.long (0x148+0x0)++0x07 line.long 0x00 "UOG1_USBINTR,USB Interrupt Enable" bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host Asynchronous Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " ULPIE ,ULPI Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x04 "UOG1_FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index" if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x154+0x0)++0x03 line.long 0x00 "UOG1_PERCLISTBASE,Host Controller Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)" elif ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x154+0x0)++0x03 line.long 0x00 "UOG1_DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x02 " BASEADR ,USB device address" bitfld.long 0x00 24. " USBADRA ,Write method to USBADR" "Instantaneous,Staged/hidden register" endif if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x158+0x0)++0x03 line.long 0x00 "UOG1_ASYNCLISTADDR,Host Controller Next Asynch Address Register" hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low" elif ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x158+0x0)++0x03 line.long 0x00 "UOG1_ENDPTLISTADDR,Device Controller Endpoint List Address Register" hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address" endif group.long (0x160+0x0)++0x7 line.long 0x00 "UOG1_BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length" line.long 0x04 "UOG1_TXFILLTUNING,TX FIFO Fill Tuning Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler Health Counter" hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead" textline " " width 22. group.long (0x178+0x0)++0x07 line.long 0x00 "UOG1_ENDPTNAK,Endpoint NAK register" bitfld.long 0x00 23. " EPTN[7] ,TX Endpoint NAK 7" "Low,High" bitfld.long 0x00 22. " EPTN[6] ,TX Endpoint NAK 6" "Low,High" bitfld.long 0x00 21. " EPTN[5] ,TX Endpoint NAK 5" "Low,High" bitfld.long 0x00 20. " EPTN[4] ,TX Endpoint NAK 4" "Low,High" textline " " bitfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3" "Low,High" bitfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2" "Low,High" bitfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1" "Low,High" bitfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0" "Low,High" textline " " bitfld.long 0x00 7. " EPRN[7] ,RX Endpoint NAK 7" "Low,High" bitfld.long 0x00 6. " EPRN[6] ,RX Endpoint NAK 6" "Low,High" bitfld.long 0x00 5. " EPRN[5] ,RX Endpoint NAK 5" "Low,High" bitfld.long 0x00 4. " EPRN[4] ,RX Endpoint NAK 4" "Low,High" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3" "Low,High" bitfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2" "Low,High" bitfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1" "Low,High" bitfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0" "Low,High" line.long 0x04 "UOG1_ENDPTNAKEN,Endpoint NAK register enable" bitfld.long 0x04 23. " EPTN[7] ,TX Endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 22. " EPTN[6] ,TX Endpoint NAK 6" "Disabled,Enabled" bitfld.long 0x04 21. " EPTN[5] ,TX Endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 20. " EPTN[4] ,TX Endpoint NAK 4" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EPTN[3] ,TX Endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 18. " EPTN[2] ,TX Endpoint NAK 2" "Disabled,Enabled" bitfld.long 0x04 17. " EPTN[1] ,TX Endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 16. " EPTN[0] ,TX Endpoint NAK 0" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " EPRN[7] ,RX Endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 6. " EPRN[6] ,RX Endpoint NAK 6" "Disabled,Enabled" bitfld.long 0x04 5. " EPRN[5] ,RX Endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 4. " EPRN[4] ,RX Endpoint NAK 4" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRN[3] ,RX Endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 2. " EPRN[2] ,RX Endpoint NAK 2" "Disabled,Enabled" bitfld.long 0x04 1. " EPRN[1] ,RX Endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 0. " EPRN[0] ,RX Endpoint NAK 0" "Disabled,Enabled" rgroup.long (0x180+0x0)++0x03 line.long 0x00 "UOG1_CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Configure Flag" "Classic,This" textline " " width 17. if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x184+0x0)++0x03 line.long 0x00 "UOG1_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" else group.long (0x184+0x0)++0x03 line.long 0x00 "UOG1_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif rbitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" endif group.long (0x1a4+0x0)++0x03 line.long 0x00 "UOG1_OTGSC,OTG Status Control Register" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1MSE ,1 Milisecond Timer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " 1MSS ,1 Milisecond Timer Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "No interrupt,Interrupt" rbitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" rbitfld.long 0x00 13. " 1MST ,1 Milisecond Timer Toggle" "Not toggled,Toggled" textline " " rbitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended" rbitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid" rbitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid" rbitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid" textline " " rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Disabled,Enabled" bitfld.long 0x00 4. " DP ,Data Pulsing" "Disabled,Enabled" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" bitfld.long 0x00 0. " VD ,VBUS Discharge" "Not discharged,Discharged" group.long (0x1a8+0x0)++0x03 line.long 0x00 "UOG1_USBMODE,USB Device Mode Register" bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,,Device,Host" textline " " width 22. if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x1ac+0x0)++0x0b line.long 0x00 "UOG1_ENDPTSETUPSTAT,Endpoint Setup Status Register" bitfld.long 0x00 15. " ENDPTSETUPSTAT[15] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 14. " ENDPTSETUPSTAT[14] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 13. " ENDPTSETUPSTAT[13] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 12. " ENDPTSETUPSTAT[12] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 11. " ENDPTSETUPSTAT[11] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 10. " ENDPTSETUPSTAT[10] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 9. " ENDPTSETUPSTAT[09] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 8. " ENDPTSETUPSTAT[08] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 7. " ENDPTSETUPSTAT[07] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 6. " ENDPTSETUPSTAT[06] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 5. " ENDPTSETUPSTAT[05] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 4. " ENDPTSETUPSTAT[04] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 3. " ENDPTSETUPSTAT[03] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 2. " ENDPTSETUPSTAT[02] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 1. " ENDPTSETUPSTAT[01] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 0. " ENDPTSETUPSTAT[00] ,Setup Endpoint Status" "Not received,Received" textline " " line.long 0x04 "UOG1_ENDPTPRIME,Endpoint Initialization Register" bitfld.long 0x04 23. " PETB7 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 22. " PETB6 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 21. " PETB5 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 20. " PETB4 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 19. " PETB3 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 18. " PETB2 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 17. " PETB1 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 16. " PETB0 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 7. " PERB7 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 6. " PERB6 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 5. " PERB5 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 4. " PERB4 ,Prime Endpoint Receive Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 3. " PERB3 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 2. " PERB2 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 1. " PERB1 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 0. " PERB0 ,Prime Endpoint Receive Buffer" "Not prime,Prime" line.long 0x08 "UOG1_ENDPTFLUSH,Endpoint De-Initialize Register" bitfld.long 0x08 23. " FETB7 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 22. " FETB6 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 21. " FETB5 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 20. " FETB4 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 19. " FETB3 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 18. " FETB2 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 17. " FETB1 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 16. " FETB0 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 7. " FERB7 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 6. " FERB6 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 5. " FERB5 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 4. " FERB4 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 3. " FERB3 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 2. " FERB2 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 1. " FERB1 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 0. " FERB0 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" rgroup.long (0x1b8+0x0)++0x03 line.long 0x00 "UOG1_ENDPTSTAT,Endpoint Status Register" bitfld.long 0x00 23. " ETBR7 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 22. " ETBR6 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 21. " ETBR5 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 20. " ETBR4 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 19. " ETBR3 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR2 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 17. " ETBR1 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR0 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 7. " ERBR7 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 6. " ERBR6 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 5. " ERBR5 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 4. " ERBR4 ,Endpoint Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " ERBR3 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR2 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 1. " ERBR1 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR0 ,Endpoint Receive Buffer Ready" "Not ready,Ready" group.long 0x1bc++0x03 line.long 0x00 "UOG1_ENDPTCOMPLETE,Endpoint Compete Register" eventfld.long 0x00 23. " ETCE7 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 22. " ETCE6 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 21. " ETCE5 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 20. " ETCE4 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " ETCE3 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE2 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 17. " ETCE1 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE0 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " ERCE7 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 6. " ERCE6 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 5. " ERCE5 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 4. " ERCE4 ,Endpoint Receive Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " ERCE3 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE2 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 1. " ERCE1 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE0 ,Endpoint Receive Complete Event" "Not occurred,Occurred" else hgroup.long (0x1ac+0x0)++0x0b hide.long 0x00 "UOG1_ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "UOG1_ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "UOG1_ENDPTFLUSH,Endpoint De-Initialize Register" hgroup.long (0x1b8+0x0)++0x03 hide.long 0x00 "UOG1_ENDPTSTAT,Endpoint Status Register" hgroup.long 0x1bc++0x03 hide.long 0x00 "UOG1_ENDPTCOMPLETE,Endpoint Compete Register" endif textline " " width 22. group.long 0x1c0++0x03 line.long 0x00 "UOG1_ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,,," bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,,," bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x2) group.long 0x1c4++0x1B line.long 0x0 "UOG1_ENDPTCTRL1,Endpoint Control 1 Register" bitfld.long 0x0 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x0 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x0 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x0 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x0 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x0 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x0 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x0 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x0 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x0 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x0 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x0 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "UOG1_ENDPTCTRL2,Endpoint Control 2 Register" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x4 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "UOG1_ENDPTCTRL3,Endpoint Control 3 Register" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x8 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "UOG1_ENDPTCTRL4,Endpoint Control 4 Register" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0xC 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x10 "UOG1_ENDPTCTRL5,Endpoint Control 5 Register" bitfld.long 0x10 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x10 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x10 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x10 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x10 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x10 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x10 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x10 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x10 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x10 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x10 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x10 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x14 "UOG1_ENDPTCTRL6,Endpoint Control 6 Register" bitfld.long 0x14 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x14 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x14 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x14 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x14 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x14 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x14 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x14 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x14 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x14 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x14 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x14 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x18 "UOG1_ENDPTCTRL7,Endpoint Control 7 Register" bitfld.long 0x18 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x18 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x18 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x18 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x18 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x18 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x18 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x18 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x18 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x18 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x18 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x18 0. " RXS ,RX Endpoint Stall" "OK,Stalled" else hgroup.long 0x1c4++0x1B hide.long 0x4 "UOG1_ENDPTCTRL1,Endpoint Control 1 Register" hide.long 0x8 "UOG1_ENDPTCTRL2,Endpoint Control 2 Register" hide.long 0xC "UOG1_ENDPTCTRL3,Endpoint Control 3 Register" hide.long 0x10 "UOG1_ENDPTCTRL4,Endpoint Control 4 Register" hide.long 0x14 "UOG1_ENDPTCTRL5,Endpoint Control 5 Register" hide.long 0x18 "UOG1_ENDPTCTRL6,Endpoint Control 6 Register" hide.long 0x1C "UOG1_ENDPTCTRL7,Endpoint Control 7 Register" endif width 0xb tree.end tree "OTG2" width 22. rgroup.long (0x00+0x200)++0x03 line.long 0x00 "UOG2_ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION[7:0] ,Revision Number of the Core" hexmask.long.byte 0x00 8.--13. 1. " NID[5:0] ,Ones Complement Version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID[5:0] ,Configuration Number" rgroup.long (0x04+0x200)++0x03 line.long 0x00 "UOG2_HWGENERAL,General Hardware Register" bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "No engine/parallel signaling,Engine present/serial signalling,Soft programmable/Reset to parallel,Soft programmable/Reset to serial" bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Soft programmable reset to UTMI/UMTI+,Soft programmable reset to ULPI DDR,Soft programmable reset to ULPI,Soft programmable reset to Serial" textline " " bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core" "8 bit non programmable,16 bit non programmable,8 bit programmable,16 bit programmable" textline " " rgroup.long (0x08+0x200)++0x03 line.long 0x00 "UOG2_HWHOST,Host Hardware Parameters Register" bitfld.long 0x00 1.--3. " NPORT ,Number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0. " HC ,Host operation mode support for device" "Not supported,Supported" rgroup.long (0x0C+0x200)++0x03 line.long 0x00 "UOG2_HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x00 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device operation mode support" "Not supported,Supported" rgroup.long (0x10+0x200)++0x07 line.long 0x00 "UOG2_HWTXBUF,TX Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "UOG2_HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" textline " " group.long (0x80+0x200)++0xf "Device/Host Timer Registers" line.long 0x00 "UOG2_GPTIMER0LD,General Purpose Timer #0 Load Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x04 "UOG2_GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x04 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x04 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" line.long 0x08 "UOG2_GPTIMER1LD,General Purpose Timer #1 Load Register" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x0C "UOG2_GPTIMER1CTRL,General Purpose Timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x0C 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x0C 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" textline " " group.long (0x90+0x200)++0x03 line.long 0x00 "UOG2_SBUSCFG,System Bus Config" bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface Burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte (0x100+0x200)++0x00 line.byte 0x00 "UOG2_CAPLENGTH,Address offset to the Operational registers" rgroup.word (0x102+0x200)++0x01 line.word 0x00 "UOG2_HCIVERSION,EHCI revision number supported by this host controller" rgroup.long (0x104+0x200)++0x07 line.long 0x00 "UOG2_HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PI ,Port Indicators" "0,1" bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included" bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "UOG2_HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer" bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" rgroup.word (0x120+0x200)++0x1 line.word 0x00 "UOG2_DCIVERSION,Device Interface Version Number Register" rgroup.long (0x124+0x200)++0x3 line.long 0x00 "UOG2_DCCPARAMS,Device Control Capability Parameters Register" bitfld.long 0x00 8. " HC ,Host Capable" "Not supported,Supported" bitfld.long 0x00 7. " DC ,Device Capable" "Not supported,Supported" bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " width 22. group.long (0x140+0x200)++0x03 line.long 0x00 "UOG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard" bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x144+0x200)++0x03 line.long 0x00 "UOG2_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" rbitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested" textline " " bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" else group.long (0x144+0x200)++0x03 line.long 0x00 "UOG2_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" textline " " bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" endif group.long (0x148+0x200)++0x07 line.long 0x00 "UOG2_USBINTR,USB Interrupt Enable" bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host Asynchronous Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " ULPIE ,ULPI Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x04 "UOG2_FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index" if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x154+0x200)++0x03 line.long 0x00 "UOG2_PERCLISTBASE,Host Controller Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)" elif ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x154+0x200)++0x03 line.long 0x00 "UOG2_DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x02 " BASEADR ,USB device address" bitfld.long 0x00 24. " USBADRA ,Write method to USBADR" "Instantaneous,Staged/hidden register" endif if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x158+0x200)++0x03 line.long 0x00 "UOG2_ASYNCLISTADDR,Host Controller Next Asynch Address Register" hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low" elif ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x158+0x200)++0x03 line.long 0x00 "UOG2_ENDPTLISTADDR,Device Controller Endpoint List Address Register" hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address" endif group.long (0x160+0x200)++0x7 line.long 0x00 "UOG2_BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length" line.long 0x04 "UOG2_TXFILLTUNING,TX FIFO Fill Tuning Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler Health Counter" hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead" textline " " width 22. group.long (0x178+0x200)++0x07 line.long 0x00 "UOG2_ENDPTNAK,Endpoint NAK register" bitfld.long 0x00 23. " EPTN[7] ,TX Endpoint NAK 7" "Low,High" bitfld.long 0x00 22. " EPTN[6] ,TX Endpoint NAK 6" "Low,High" bitfld.long 0x00 21. " EPTN[5] ,TX Endpoint NAK 5" "Low,High" bitfld.long 0x00 20. " EPTN[4] ,TX Endpoint NAK 4" "Low,High" textline " " bitfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3" "Low,High" bitfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2" "Low,High" bitfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1" "Low,High" bitfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0" "Low,High" textline " " bitfld.long 0x00 7. " EPRN[7] ,RX Endpoint NAK 7" "Low,High" bitfld.long 0x00 6. " EPRN[6] ,RX Endpoint NAK 6" "Low,High" bitfld.long 0x00 5. " EPRN[5] ,RX Endpoint NAK 5" "Low,High" bitfld.long 0x00 4. " EPRN[4] ,RX Endpoint NAK 4" "Low,High" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3" "Low,High" bitfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2" "Low,High" bitfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1" "Low,High" bitfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0" "Low,High" line.long 0x04 "UOG2_ENDPTNAKEN,Endpoint NAK register enable" bitfld.long 0x04 23. " EPTN[7] ,TX Endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 22. " EPTN[6] ,TX Endpoint NAK 6" "Disabled,Enabled" bitfld.long 0x04 21. " EPTN[5] ,TX Endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 20. " EPTN[4] ,TX Endpoint NAK 4" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EPTN[3] ,TX Endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 18. " EPTN[2] ,TX Endpoint NAK 2" "Disabled,Enabled" bitfld.long 0x04 17. " EPTN[1] ,TX Endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 16. " EPTN[0] ,TX Endpoint NAK 0" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " EPRN[7] ,RX Endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 6. " EPRN[6] ,RX Endpoint NAK 6" "Disabled,Enabled" bitfld.long 0x04 5. " EPRN[5] ,RX Endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 4. " EPRN[4] ,RX Endpoint NAK 4" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRN[3] ,RX Endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 2. " EPRN[2] ,RX Endpoint NAK 2" "Disabled,Enabled" bitfld.long 0x04 1. " EPRN[1] ,RX Endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 0. " EPRN[0] ,RX Endpoint NAK 0" "Disabled,Enabled" rgroup.long (0x180+0x200)++0x03 line.long 0x00 "UOG2_CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Configure Flag" "Classic,This" textline " " width 17. if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x184+0x200)++0x03 line.long 0x00 "UOG2_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" else group.long (0x184+0x200)++0x03 line.long 0x00 "UOG2_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif rbitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" endif group.long (0x1a4+0x200)++0x03 line.long 0x00 "UOG2_OTGSC,OTG Status Control Register" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1MSE ,1 Milisecond Timer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " 1MSS ,1 Milisecond Timer Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "No interrupt,Interrupt" rbitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" rbitfld.long 0x00 13. " 1MST ,1 Milisecond Timer Toggle" "Not toggled,Toggled" textline " " rbitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended" rbitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid" rbitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid" rbitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid" textline " " rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Disabled,Enabled" bitfld.long 0x00 4. " DP ,Data Pulsing" "Disabled,Enabled" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" bitfld.long 0x00 0. " VD ,VBUS Discharge" "Not discharged,Discharged" group.long (0x1a8+0x200)++0x03 line.long 0x00 "UOG2_USBMODE,USB Device Mode Register" bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,,Device,Host" textline " " width 22. if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x1ac+0x200)++0x0b line.long 0x00 "UOG2_ENDPTSETUPSTAT,Endpoint Setup Status Register" bitfld.long 0x00 15. " ENDPTSETUPSTAT[15] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 14. " ENDPTSETUPSTAT[14] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 13. " ENDPTSETUPSTAT[13] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 12. " ENDPTSETUPSTAT[12] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 11. " ENDPTSETUPSTAT[11] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 10. " ENDPTSETUPSTAT[10] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 9. " ENDPTSETUPSTAT[09] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 8. " ENDPTSETUPSTAT[08] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 7. " ENDPTSETUPSTAT[07] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 6. " ENDPTSETUPSTAT[06] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 5. " ENDPTSETUPSTAT[05] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 4. " ENDPTSETUPSTAT[04] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 3. " ENDPTSETUPSTAT[03] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 2. " ENDPTSETUPSTAT[02] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 1. " ENDPTSETUPSTAT[01] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 0. " ENDPTSETUPSTAT[00] ,Setup Endpoint Status" "Not received,Received" textline " " line.long 0x04 "UOG2_ENDPTPRIME,Endpoint Initialization Register" bitfld.long 0x04 23. " PETB7 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 22. " PETB6 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 21. " PETB5 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 20. " PETB4 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 19. " PETB3 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 18. " PETB2 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 17. " PETB1 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 16. " PETB0 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 7. " PERB7 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 6. " PERB6 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 5. " PERB5 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 4. " PERB4 ,Prime Endpoint Receive Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 3. " PERB3 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 2. " PERB2 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 1. " PERB1 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 0. " PERB0 ,Prime Endpoint Receive Buffer" "Not prime,Prime" line.long 0x08 "UOG2_ENDPTFLUSH,Endpoint De-Initialize Register" bitfld.long 0x08 23. " FETB7 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 22. " FETB6 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 21. " FETB5 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 20. " FETB4 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 19. " FETB3 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 18. " FETB2 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 17. " FETB1 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 16. " FETB0 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 7. " FERB7 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 6. " FERB6 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 5. " FERB5 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 4. " FERB4 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 3. " FERB3 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 2. " FERB2 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 1. " FERB1 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 0. " FERB0 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" rgroup.long (0x1b8+0x200)++0x03 line.long 0x00 "UOG2_ENDPTSTAT,Endpoint Status Register" bitfld.long 0x00 23. " ETBR7 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 22. " ETBR6 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 21. " ETBR5 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 20. " ETBR4 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 19. " ETBR3 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR2 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 17. " ETBR1 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR0 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 7. " ERBR7 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 6. " ERBR6 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 5. " ERBR5 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 4. " ERBR4 ,Endpoint Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " ERBR3 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR2 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 1. " ERBR1 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR0 ,Endpoint Receive Buffer Ready" "Not ready,Ready" group.long 0x1bc++0x03 line.long 0x00 "UOG2_ENDPTCOMPLETE,Endpoint Compete Register" eventfld.long 0x00 23. " ETCE7 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 22. " ETCE6 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 21. " ETCE5 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 20. " ETCE4 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " ETCE3 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE2 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 17. " ETCE1 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE0 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " ERCE7 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 6. " ERCE6 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 5. " ERCE5 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 4. " ERCE4 ,Endpoint Receive Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " ERCE3 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE2 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 1. " ERCE1 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE0 ,Endpoint Receive Complete Event" "Not occurred,Occurred" else hgroup.long (0x1ac+0x200)++0x0b hide.long 0x00 "UOG2_ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "UOG2_ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "UOG2_ENDPTFLUSH,Endpoint De-Initialize Register" hgroup.long (0x1b8+0x200)++0x03 hide.long 0x00 "UOG2_ENDPTSTAT,Endpoint Status Register" hgroup.long 0x1bc++0x03 hide.long 0x00 "UOG2_ENDPTCOMPLETE,Endpoint Compete Register" endif textline " " width 22. group.long 0x1c0++0x03 line.long 0x00 "UOG2_ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,,," bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,,," bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x2) group.long 0x1c4++0x1B line.long 0x0 "UOG2_ENDPTCTRL1,Endpoint Control 1 Register" bitfld.long 0x0 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x0 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x0 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x0 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x0 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x0 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x0 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x0 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x0 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x0 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x0 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x0 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "UOG2_ENDPTCTRL2,Endpoint Control 2 Register" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x4 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "UOG2_ENDPTCTRL3,Endpoint Control 3 Register" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x8 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "UOG2_ENDPTCTRL4,Endpoint Control 4 Register" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0xC 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x10 "UOG2_ENDPTCTRL5,Endpoint Control 5 Register" bitfld.long 0x10 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x10 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x10 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x10 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x10 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x10 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x10 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x10 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x10 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x10 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x10 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x10 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x14 "UOG2_ENDPTCTRL6,Endpoint Control 6 Register" bitfld.long 0x14 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x14 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x14 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x14 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x14 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x14 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x14 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x14 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x14 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x14 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x14 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x14 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x18 "UOG2_ENDPTCTRL7,Endpoint Control 7 Register" bitfld.long 0x18 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x18 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x18 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x18 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x18 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x18 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x18 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x18 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x18 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x18 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x18 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x18 0. " RXS ,RX Endpoint Stall" "OK,Stalled" else hgroup.long 0x1c4++0x1B hide.long 0x4 "UOG2_ENDPTCTRL1,Endpoint Control 1 Register" hide.long 0x8 "UOG2_ENDPTCTRL2,Endpoint Control 2 Register" hide.long 0xC "UOG2_ENDPTCTRL3,Endpoint Control 3 Register" hide.long 0x10 "UOG2_ENDPTCTRL4,Endpoint Control 4 Register" hide.long 0x14 "UOG2_ENDPTCTRL5,Endpoint Control 5 Register" hide.long 0x18 "UOG2_ENDPTCTRL6,Endpoint Control 6 Register" hide.long 0x1C "UOG2_ENDPTCTRL7,Endpoint Control 7 Register" endif width 0xb tree.end else tree "OTG1" width 22. rgroup.long (0x00+0x0)++0x03 line.long 0x00 "UOG1_ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION[7:0] ,Revision Number of the Core" hexmask.long.byte 0x00 8.--13. 1. " NID[5:0] ,Ones Complement Version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID[5:0] ,Configuration Number" rgroup.long (0x04+0x0)++0x03 line.long 0x00 "UOG1_HWGENERAL,General Hardware Register" bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "No engine/parallel signaling,Engine present/serial signalling,Soft programmable/Reset to parallel,Soft programmable/Reset to serial" bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Soft programmable reset to UTMI/UMTI+,Soft programmable reset to ULPI DDR,Soft programmable reset to ULPI,Soft programmable reset to Serial" textline " " bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core" "8 bit non programmable,16 bit non programmable,8 bit programmable,16 bit programmable" textline " " rgroup.long (0x08+0x0)++0x03 line.long 0x00 "UOG1_HWHOST,Host Hardware Parameters Register" bitfld.long 0x00 1.--3. " NPORT ,Number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0. " HC ,Host operation mode support for device" "Not supported,Supported" rgroup.long (0x0C+0x0)++0x03 line.long 0x00 "UOG1_HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x00 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device operation mode support" "Not supported,Supported" rgroup.long (0x10+0x0)++0x07 line.long 0x00 "UOG1_HWTXBUF,TX Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "UOG1_HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" textline " " group.long (0x80+0x0)++0xf "Device/Host Timer Registers" line.long 0x00 "UOG1_GPTIMER0LD,General Purpose Timer #0 Load Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x04 "UOG1_GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x04 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x04 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" line.long 0x08 "UOG1_GPTIMER1LD,General Purpose Timer #1 Load Register" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x0C "UOG1_GPTIMER1CTRL,General Purpose Timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x0C 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x0C 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" textline " " group.long (0x90+0x0)++0x03 line.long 0x00 "UOG1_SBUSCFG,System Bus Config" bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface Burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte (0x100+0x0)++0x00 line.byte 0x00 "UOG1_CAPLENGTH,Address offset to the Operational registers" rgroup.word (0x102+0x0)++0x01 line.word 0x00 "UOG1_HCIVERSION,EHCI revision number supported by this host controller" rgroup.long (0x104+0x0)++0x07 line.long 0x00 "UOG1_HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PI ,Port Indicators" "0,1" bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included" bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "UOG1_HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer" bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" rgroup.word (0x120+0x0)++0x1 line.word 0x00 "UOG1_DCIVERSION,Device Interface Version Number Register" rgroup.long (0x124+0x0)++0x3 line.long 0x00 "UOG1_DCCPARAMS,Device Control Capability Parameters Register" bitfld.long 0x00 8. " HC ,Host Capable" "Not supported,Supported" bitfld.long 0x00 7. " DC ,Device Capable" "Not supported,Supported" bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " width 22. group.long (0x140+0x0)++0x03 line.long 0x00 "UOG1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard" bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x144+0x0)++0x03 line.long 0x00 "UOG1_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" rbitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested" textline " " bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" else group.long (0x144+0x0)++0x03 line.long 0x00 "UOG1_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" textline " " bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" endif group.long (0x148+0x0)++0x07 line.long 0x00 "UOG1_USBINTR,USB Interrupt Enable" bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host Asynchronous Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " ULPIE ,ULPI Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x04 "UOG1_FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index" if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x154+0x0)++0x03 line.long 0x00 "UOG1_PERCLISTBASE,Host Controller Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)" elif ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x154+0x0)++0x03 line.long 0x00 "UOG1_DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x02 " BASEADR ,USB device address" bitfld.long 0x00 24. " USBADRA ,Write method to USBADR" "Instantaneous,Staged/hidden register" endif if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x158+0x0)++0x03 line.long 0x00 "UOG1_ASYNCLISTADDR,Host Controller Next Asynch Address Register" hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low" elif ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x158+0x0)++0x03 line.long 0x00 "UOG1_ENDPTLISTADDR,Device Controller Endpoint List Address Register" hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address" endif group.long (0x160+0x0)++0x7 line.long 0x00 "UOG1_BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length" line.long 0x04 "UOG1_TXFILLTUNING,TX FIFO Fill Tuning Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler Health Counter" hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead" textline " " width 22. group.long (0x178+0x0)++0x07 line.long 0x00 "UOG1_ENDPTNAK,Endpoint NAK register" bitfld.long 0x00 23. " EPTN[7] ,TX Endpoint NAK 7" "Low,High" bitfld.long 0x00 22. " EPTN[6] ,TX Endpoint NAK 6" "Low,High" bitfld.long 0x00 21. " EPTN[5] ,TX Endpoint NAK 5" "Low,High" bitfld.long 0x00 20. " EPTN[4] ,TX Endpoint NAK 4" "Low,High" textline " " bitfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3" "Low,High" bitfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2" "Low,High" bitfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1" "Low,High" bitfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0" "Low,High" textline " " bitfld.long 0x00 7. " EPRN[7] ,RX Endpoint NAK 7" "Low,High" bitfld.long 0x00 6. " EPRN[6] ,RX Endpoint NAK 6" "Low,High" bitfld.long 0x00 5. " EPRN[5] ,RX Endpoint NAK 5" "Low,High" bitfld.long 0x00 4. " EPRN[4] ,RX Endpoint NAK 4" "Low,High" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3" "Low,High" bitfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2" "Low,High" bitfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1" "Low,High" bitfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0" "Low,High" line.long 0x04 "UOG1_ENDPTNAKEN,Endpoint NAK register enable" bitfld.long 0x04 23. " EPTN[7] ,TX Endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 22. " EPTN[6] ,TX Endpoint NAK 6" "Disabled,Enabled" bitfld.long 0x04 21. " EPTN[5] ,TX Endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 20. " EPTN[4] ,TX Endpoint NAK 4" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EPTN[3] ,TX Endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 18. " EPTN[2] ,TX Endpoint NAK 2" "Disabled,Enabled" bitfld.long 0x04 17. " EPTN[1] ,TX Endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 16. " EPTN[0] ,TX Endpoint NAK 0" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " EPRN[7] ,RX Endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 6. " EPRN[6] ,RX Endpoint NAK 6" "Disabled,Enabled" bitfld.long 0x04 5. " EPRN[5] ,RX Endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 4. " EPRN[4] ,RX Endpoint NAK 4" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRN[3] ,RX Endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 2. " EPRN[2] ,RX Endpoint NAK 2" "Disabled,Enabled" bitfld.long 0x04 1. " EPRN[1] ,RX Endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 0. " EPRN[0] ,RX Endpoint NAK 0" "Disabled,Enabled" rgroup.long (0x180+0x0)++0x03 line.long 0x00 "UOG1_CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Configure Flag" "Classic,This" textline " " width 17. if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x184+0x0)++0x03 line.long 0x00 "UOG1_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" else group.long (0x184+0x0)++0x03 line.long 0x00 "UOG1_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif rbitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" endif group.long (0x1a4+0x0)++0x03 line.long 0x00 "UOG1_OTGSC,OTG Status Control Register" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1MSE ,1 Milisecond Timer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " 1MSS ,1 Milisecond Timer Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "No interrupt,Interrupt" rbitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" rbitfld.long 0x00 13. " 1MST ,1 Milisecond Timer Toggle" "Not toggled,Toggled" textline " " rbitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended" rbitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid" rbitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid" rbitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid" textline " " rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Disabled,Enabled" bitfld.long 0x00 4. " DP ,Data Pulsing" "Disabled,Enabled" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" bitfld.long 0x00 0. " VD ,VBUS Discharge" "Not discharged,Discharged" group.long (0x1a8+0x0)++0x03 line.long 0x00 "UOG1_USBMODE,USB Device Mode Register" bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,,Device,Host" textline " " width 22. if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x1ac+0x0)++0x0b line.long 0x00 "UOG1_ENDPTSETUPSTAT,Endpoint Setup Status Register" bitfld.long 0x00 15. " ENDPTSETUPSTAT[15] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 14. " ENDPTSETUPSTAT[14] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 13. " ENDPTSETUPSTAT[13] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 12. " ENDPTSETUPSTAT[12] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 11. " ENDPTSETUPSTAT[11] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 10. " ENDPTSETUPSTAT[10] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 9. " ENDPTSETUPSTAT[09] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 8. " ENDPTSETUPSTAT[08] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 7. " ENDPTSETUPSTAT[07] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 6. " ENDPTSETUPSTAT[06] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 5. " ENDPTSETUPSTAT[05] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 4. " ENDPTSETUPSTAT[04] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 3. " ENDPTSETUPSTAT[03] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 2. " ENDPTSETUPSTAT[02] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 1. " ENDPTSETUPSTAT[01] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 0. " ENDPTSETUPSTAT[00] ,Setup Endpoint Status" "Not received,Received" textline " " line.long 0x04 "UOG1_ENDPTPRIME,Endpoint Initialization Register" bitfld.long 0x04 23. " PETB7 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 22. " PETB6 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 21. " PETB5 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 20. " PETB4 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 19. " PETB3 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 18. " PETB2 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 17. " PETB1 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 16. " PETB0 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 7. " PERB7 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 6. " PERB6 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 5. " PERB5 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 4. " PERB4 ,Prime Endpoint Receive Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 3. " PERB3 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 2. " PERB2 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 1. " PERB1 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 0. " PERB0 ,Prime Endpoint Receive Buffer" "Not prime,Prime" line.long 0x08 "UOG1_ENDPTFLUSH,Endpoint De-Initialize Register" bitfld.long 0x08 23. " FETB7 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 22. " FETB6 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 21. " FETB5 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 20. " FETB4 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 19. " FETB3 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 18. " FETB2 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 17. " FETB1 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 16. " FETB0 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 7. " FERB7 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 6. " FERB6 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 5. " FERB5 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 4. " FERB4 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 3. " FERB3 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 2. " FERB2 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 1. " FERB1 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 0. " FERB0 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" rgroup.long (0x1b8+0x0)++0x03 line.long 0x00 "UOG1_ENDPTSTAT,Endpoint Status Register" bitfld.long 0x00 23. " ETBR7 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 22. " ETBR6 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 21. " ETBR5 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 20. " ETBR4 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 19. " ETBR3 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR2 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 17. " ETBR1 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR0 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 7. " ERBR7 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 6. " ERBR6 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 5. " ERBR5 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 4. " ERBR4 ,Endpoint Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " ERBR3 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR2 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 1. " ERBR1 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR0 ,Endpoint Receive Buffer Ready" "Not ready,Ready" group.long 0x1bc++0x03 line.long 0x00 "UOG1_ENDPTCOMPLETE,Endpoint Compete Register" eventfld.long 0x00 23. " ETCE7 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 22. " ETCE6 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 21. " ETCE5 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 20. " ETCE4 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " ETCE3 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE2 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 17. " ETCE1 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE0 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " ERCE7 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 6. " ERCE6 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 5. " ERCE5 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 4. " ERCE4 ,Endpoint Receive Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " ERCE3 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE2 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 1. " ERCE1 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE0 ,Endpoint Receive Complete Event" "Not occurred,Occurred" else hgroup.long (0x1ac+0x0)++0x0b hide.long 0x00 "UOG1_ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "UOG1_ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "UOG1_ENDPTFLUSH,Endpoint De-Initialize Register" hgroup.long (0x1b8+0x0)++0x03 hide.long 0x00 "UOG1_ENDPTSTAT,Endpoint Status Register" hgroup.long 0x1bc++0x03 hide.long 0x00 "UOG1_ENDPTCOMPLETE,Endpoint Compete Register" endif textline " " width 22. group.long 0x1c0++0x03 line.long 0x00 "UOG1_ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,,," bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,,," bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" if ((per.l(0x0+ad:0x02184000+0x1a8)&0x3)==0x2) group.long 0x1c4++0x1B line.long 0x0 "UOG1_ENDPTCTRL1,Endpoint Control 1 Register" bitfld.long 0x0 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x0 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x0 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x0 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x0 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x0 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x0 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x0 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x0 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x0 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x0 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x0 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "UOG1_ENDPTCTRL2,Endpoint Control 2 Register" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x4 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "UOG1_ENDPTCTRL3,Endpoint Control 3 Register" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x8 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "UOG1_ENDPTCTRL4,Endpoint Control 4 Register" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0xC 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x10 "UOG1_ENDPTCTRL5,Endpoint Control 5 Register" bitfld.long 0x10 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x10 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x10 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x10 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x10 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x10 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x10 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x10 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x10 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x10 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x10 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x10 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x14 "UOG1_ENDPTCTRL6,Endpoint Control 6 Register" bitfld.long 0x14 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x14 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x14 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x14 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x14 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x14 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x14 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x14 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x14 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x14 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x14 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x14 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x18 "UOG1_ENDPTCTRL7,Endpoint Control 7 Register" bitfld.long 0x18 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x18 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x18 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x18 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x18 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x18 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x18 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x18 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x18 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x18 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x18 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x18 0. " RXS ,RX Endpoint Stall" "OK,Stalled" else hgroup.long 0x1c4++0x1B hide.long 0x4 "UOG1_ENDPTCTRL1,Endpoint Control 1 Register" hide.long 0x8 "UOG1_ENDPTCTRL2,Endpoint Control 2 Register" hide.long 0xC "UOG1_ENDPTCTRL3,Endpoint Control 3 Register" hide.long 0x10 "UOG1_ENDPTCTRL4,Endpoint Control 4 Register" hide.long 0x14 "UOG1_ENDPTCTRL5,Endpoint Control 5 Register" hide.long 0x18 "UOG1_ENDPTCTRL6,Endpoint Control 6 Register" hide.long 0x1C "UOG1_ENDPTCTRL7,Endpoint Control 7 Register" endif width 0xb tree.end tree "OTG2" width 22. rgroup.long (0x00+0x200)++0x03 line.long 0x00 "UOG2_ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION[7:0] ,Revision Number of the Core" hexmask.long.byte 0x00 8.--13. 1. " NID[5:0] ,Ones Complement Version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID[5:0] ,Configuration Number" rgroup.long (0x04+0x200)++0x03 line.long 0x00 "UOG2_HWGENERAL,General Hardware Register" bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "No engine/parallel signaling,Engine present/serial signalling,Soft programmable/Reset to parallel,Soft programmable/Reset to serial" bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Soft programmable reset to UTMI/UMTI+,Soft programmable reset to ULPI DDR,Soft programmable reset to ULPI,Soft programmable reset to Serial" textline " " bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core" "8 bit non programmable,16 bit non programmable,8 bit programmable,16 bit programmable" textline " " rgroup.long (0x08+0x200)++0x03 line.long 0x00 "UOG2_HWHOST,Host Hardware Parameters Register" bitfld.long 0x00 1.--3. " NPORT ,Number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0. " HC ,Host operation mode support for device" "Not supported,Supported" rgroup.long (0x0C+0x200)++0x03 line.long 0x00 "UOG2_HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x00 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device operation mode support" "Not supported,Supported" rgroup.long (0x10+0x200)++0x07 line.long 0x00 "UOG2_HWTXBUF,TX Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "UOG2_HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" textline " " group.long (0x80+0x200)++0xf "Device/Host Timer Registers" line.long 0x00 "UOG2_GPTIMER0LD,General Purpose Timer #0 Load Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x04 "UOG2_GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x04 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x04 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" line.long 0x08 "UOG2_GPTIMER1LD,General Purpose Timer #1 Load Register" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x0C "UOG2_GPTIMER1CTRL,General Purpose Timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x0C 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x0C 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" textline " " group.long (0x90+0x200)++0x03 line.long 0x00 "UOG2_SBUSCFG,System Bus Config" bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface Burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte (0x100+0x200)++0x00 line.byte 0x00 "UOG2_CAPLENGTH,Address offset to the Operational registers" rgroup.word (0x102+0x200)++0x01 line.word 0x00 "UOG2_HCIVERSION,EHCI revision number supported by this host controller" rgroup.long (0x104+0x200)++0x07 line.long 0x00 "UOG2_HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PI ,Port Indicators" "0,1" bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included" bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "UOG2_HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer" bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" rgroup.word (0x120+0x200)++0x1 line.word 0x00 "UOG2_DCIVERSION,Device Interface Version Number Register" rgroup.long (0x124+0x200)++0x3 line.long 0x00 "UOG2_DCCPARAMS,Device Control Capability Parameters Register" bitfld.long 0x00 8. " HC ,Host Capable" "Not supported,Supported" bitfld.long 0x00 7. " DC ,Device Capable" "Not supported,Supported" bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " width 22. group.long (0x140+0x200)++0x03 line.long 0x00 "UOG2_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard" bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x144+0x200)++0x03 line.long 0x00 "UOG2_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" rbitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested" textline " " bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" else group.long (0x144+0x200)++0x03 line.long 0x00 "UOG2_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" textline " " bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" endif group.long (0x148+0x200)++0x07 line.long 0x00 "UOG2_USBINTR,USB Interrupt Enable" bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host Asynchronous Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " ULPIE ,ULPI Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x04 "UOG2_FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index" if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x154+0x200)++0x03 line.long 0x00 "UOG2_PERCLISTBASE,Host Controller Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)" elif ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x154+0x200)++0x03 line.long 0x00 "UOG2_DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x02 " BASEADR ,USB device address" bitfld.long 0x00 24. " USBADRA ,Write method to USBADR" "Instantaneous,Staged/hidden register" endif if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x158+0x200)++0x03 line.long 0x00 "UOG2_ASYNCLISTADDR,Host Controller Next Asynch Address Register" hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low" elif ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x158+0x200)++0x03 line.long 0x00 "UOG2_ENDPTLISTADDR,Device Controller Endpoint List Address Register" hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address" endif group.long (0x160+0x200)++0x7 line.long 0x00 "UOG2_BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length" line.long 0x04 "UOG2_TXFILLTUNING,TX FIFO Fill Tuning Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler Health Counter" hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead" textline " " width 22. group.long (0x178+0x200)++0x07 line.long 0x00 "UOG2_ENDPTNAK,Endpoint NAK register" bitfld.long 0x00 23. " EPTN[7] ,TX Endpoint NAK 7" "Low,High" bitfld.long 0x00 22. " EPTN[6] ,TX Endpoint NAK 6" "Low,High" bitfld.long 0x00 21. " EPTN[5] ,TX Endpoint NAK 5" "Low,High" bitfld.long 0x00 20. " EPTN[4] ,TX Endpoint NAK 4" "Low,High" textline " " bitfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3" "Low,High" bitfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2" "Low,High" bitfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1" "Low,High" bitfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0" "Low,High" textline " " bitfld.long 0x00 7. " EPRN[7] ,RX Endpoint NAK 7" "Low,High" bitfld.long 0x00 6. " EPRN[6] ,RX Endpoint NAK 6" "Low,High" bitfld.long 0x00 5. " EPRN[5] ,RX Endpoint NAK 5" "Low,High" bitfld.long 0x00 4. " EPRN[4] ,RX Endpoint NAK 4" "Low,High" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3" "Low,High" bitfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2" "Low,High" bitfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1" "Low,High" bitfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0" "Low,High" line.long 0x04 "UOG2_ENDPTNAKEN,Endpoint NAK register enable" bitfld.long 0x04 23. " EPTN[7] ,TX Endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 22. " EPTN[6] ,TX Endpoint NAK 6" "Disabled,Enabled" bitfld.long 0x04 21. " EPTN[5] ,TX Endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 20. " EPTN[4] ,TX Endpoint NAK 4" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EPTN[3] ,TX Endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 18. " EPTN[2] ,TX Endpoint NAK 2" "Disabled,Enabled" bitfld.long 0x04 17. " EPTN[1] ,TX Endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 16. " EPTN[0] ,TX Endpoint NAK 0" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " EPRN[7] ,RX Endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 6. " EPRN[6] ,RX Endpoint NAK 6" "Disabled,Enabled" bitfld.long 0x04 5. " EPRN[5] ,RX Endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 4. " EPRN[4] ,RX Endpoint NAK 4" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRN[3] ,RX Endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 2. " EPRN[2] ,RX Endpoint NAK 2" "Disabled,Enabled" bitfld.long 0x04 1. " EPRN[1] ,RX Endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 0. " EPRN[0] ,RX Endpoint NAK 0" "Disabled,Enabled" rgroup.long (0x180+0x200)++0x03 line.long 0x00 "UOG2_CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Configure Flag" "Classic,This" textline " " width 17. if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x184+0x200)++0x03 line.long 0x00 "UOG2_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" else group.long (0x184+0x200)++0x03 line.long 0x00 "UOG2_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif rbitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" endif group.long (0x1a4+0x200)++0x03 line.long 0x00 "UOG2_OTGSC,OTG Status Control Register" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1MSE ,1 Milisecond Timer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " 1MSS ,1 Milisecond Timer Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "No interrupt,Interrupt" rbitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected" rbitfld.long 0x00 13. " 1MST ,1 Milisecond Timer Toggle" "Not toggled,Toggled" textline " " rbitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended" rbitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid" rbitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid" rbitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid" textline " " rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Disabled,Enabled" bitfld.long 0x00 4. " DP ,Data Pulsing" "Disabled,Enabled" bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged" bitfld.long 0x00 0. " VD ,VBUS Discharge" "Not discharged,Discharged" group.long (0x1a8+0x200)++0x03 line.long 0x00 "UOG2_USBMODE,USB Device Mode Register" bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,,Device,Host" textline " " width 22. if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x1ac+0x200)++0x0b line.long 0x00 "UOG2_ENDPTSETUPSTAT,Endpoint Setup Status Register" bitfld.long 0x00 15. " ENDPTSETUPSTAT[15] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 14. " ENDPTSETUPSTAT[14] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 13. " ENDPTSETUPSTAT[13] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 12. " ENDPTSETUPSTAT[12] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 11. " ENDPTSETUPSTAT[11] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 10. " ENDPTSETUPSTAT[10] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 9. " ENDPTSETUPSTAT[09] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 8. " ENDPTSETUPSTAT[08] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 7. " ENDPTSETUPSTAT[07] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 6. " ENDPTSETUPSTAT[06] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 5. " ENDPTSETUPSTAT[05] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 4. " ENDPTSETUPSTAT[04] ,Setup Endpoint Status" "Not received,Received" textline " " bitfld.long 0x00 3. " ENDPTSETUPSTAT[03] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 2. " ENDPTSETUPSTAT[02] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 1. " ENDPTSETUPSTAT[01] ,Setup Endpoint Status" "Not received,Received" bitfld.long 0x00 0. " ENDPTSETUPSTAT[00] ,Setup Endpoint Status" "Not received,Received" textline " " line.long 0x04 "UOG2_ENDPTPRIME,Endpoint Initialization Register" bitfld.long 0x04 23. " PETB7 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 22. " PETB6 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 21. " PETB5 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 20. " PETB4 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 19. " PETB3 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 18. " PETB2 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 17. " PETB1 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" bitfld.long 0x04 16. " PETB0 ,Prime Endpoint Transmit Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 7. " PERB7 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 6. " PERB6 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 5. " PERB5 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 4. " PERB4 ,Prime Endpoint Receive Buffer" "Not prime,Prime" textline " " bitfld.long 0x04 3. " PERB3 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 2. " PERB2 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 1. " PERB1 ,Prime Endpoint Receive Buffer" "Not prime,Prime" bitfld.long 0x04 0. " PERB0 ,Prime Endpoint Receive Buffer" "Not prime,Prime" line.long 0x08 "UOG2_ENDPTFLUSH,Endpoint De-Initialize Register" bitfld.long 0x08 23. " FETB7 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 22. " FETB6 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 21. " FETB5 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 20. " FETB4 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 19. " FETB3 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 18. " FETB2 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 17. " FETB1 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" bitfld.long 0x08 16. " FETB0 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 7. " FERB7 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 6. " FERB6 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 5. " FERB5 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 4. " FERB4 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x08 3. " FERB3 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 2. " FERB2 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 1. " FERB1 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x08 0. " FERB0 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" rgroup.long (0x1b8+0x200)++0x03 line.long 0x00 "UOG2_ENDPTSTAT,Endpoint Status Register" bitfld.long 0x00 23. " ETBR7 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 22. " ETBR6 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 21. " ETBR5 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 20. " ETBR4 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 19. " ETBR3 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR2 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 17. " ETBR1 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR0 ,Endpoint Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 7. " ERBR7 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 6. " ERBR6 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 5. " ERBR5 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 4. " ERBR4 ,Endpoint Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " ERBR3 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR2 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 1. " ERBR1 ,Endpoint Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR0 ,Endpoint Receive Buffer Ready" "Not ready,Ready" group.long 0x1bc++0x03 line.long 0x00 "UOG2_ENDPTCOMPLETE,Endpoint Compete Register" eventfld.long 0x00 23. " ETCE7 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 22. " ETCE6 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 21. " ETCE5 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 20. " ETCE4 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " ETCE3 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE2 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 17. " ETCE1 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE0 ,Endpoint Transmit Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 7. " ERCE7 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 6. " ERCE6 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 5. " ERCE5 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 4. " ERCE4 ,Endpoint Receive Complete Event" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " ERCE3 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE2 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 1. " ERCE1 ,Endpoint Receive Complete Event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE0 ,Endpoint Receive Complete Event" "Not occurred,Occurred" else hgroup.long (0x1ac+0x200)++0x0b hide.long 0x00 "UOG2_ENDPTSETUPSTAT,Endpoint Setup Status Register" hide.long 0x04 "UOG2_ENDPTPRIME,Endpoint Initialization Register" hide.long 0x08 "UOG2_ENDPTFLUSH,Endpoint De-Initialize Register" hgroup.long (0x1b8+0x200)++0x03 hide.long 0x00 "UOG2_ENDPTSTAT,Endpoint Status Register" hgroup.long 0x1bc++0x03 hide.long 0x00 "UOG2_ENDPTCOMPLETE,Endpoint Compete Register" endif textline " " width 22. group.long 0x1c0++0x03 line.long 0x00 "UOG2_ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,,," bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,,," bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" if ((per.l(0x200+ad:0x02184000+0x1a8)&0x3)==0x2) group.long 0x1c4++0x1B line.long 0x0 "UOG2_ENDPTCTRL1,Endpoint Control 1 Register" bitfld.long 0x0 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x0 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x0 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x0 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x0 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x0 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x0 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x0 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x0 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x0 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x0 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x0 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x4 "UOG2_ENDPTCTRL2,Endpoint Control 2 Register" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x4 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x4 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x8 "UOG2_ENDPTCTRL3,Endpoint Control 3 Register" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x8 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x8 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0xC "UOG2_ENDPTCTRL4,Endpoint Control 4 Register" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0xC 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0xC 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x10 "UOG2_ENDPTCTRL5,Endpoint Control 5 Register" bitfld.long 0x10 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x10 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x10 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x10 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x10 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x10 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x10 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x10 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x10 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x10 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x10 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x10 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x14 "UOG2_ENDPTCTRL6,Endpoint Control 6 Register" bitfld.long 0x14 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x14 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x14 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x14 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x14 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x14 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x14 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x14 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x14 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x14 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x14 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x14 0. " RXS ,RX Endpoint Stall" "OK,Stalled" line.long 0x18 "UOG2_ENDPTCTRL7,Endpoint Control 7 Register" bitfld.long 0x18 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x18 22. " TXR ,TX Data Toggle Reset" "No effect,Reset" bitfld.long 0x18 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x18 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x18 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine," bitfld.long 0x18 16. " TXS ,TX Endpoint Stall" "OK,Stalled" textline " " bitfld.long 0x18 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x18 6. " RXR ,RX Data Toggle Reset" "No effect,Reset" bitfld.long 0x18 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" textline " " bitfld.long 0x18 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk," bitfld.long 0x18 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine," bitfld.long 0x18 0. " RXS ,RX Endpoint Stall" "OK,Stalled" else hgroup.long 0x1c4++0x1B hide.long 0x4 "UOG2_ENDPTCTRL1,Endpoint Control 1 Register" hide.long 0x8 "UOG2_ENDPTCTRL2,Endpoint Control 2 Register" hide.long 0xC "UOG2_ENDPTCTRL3,Endpoint Control 3 Register" hide.long 0x10 "UOG2_ENDPTCTRL4,Endpoint Control 4 Register" hide.long 0x14 "UOG2_ENDPTCTRL5,Endpoint Control 5 Register" hide.long 0x18 "UOG2_ENDPTCTRL6,Endpoint Control 6 Register" hide.long 0x1C "UOG2_ENDPTCTRL7,Endpoint Control 7 Register" endif width 0xb tree.end tree "HOST" width 22. rgroup.long (0x00+0x400)++0x03 line.long 0x00 "UH1_ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION[7:0] ,Revision Number of the Core" hexmask.long.byte 0x00 8.--13. 1. " NID[5:0] ,Ones Complement Version of ID[5:0]" textline " " hexmask.long.byte 0x00 0.--5. 1. " ID[5:0] ,Configuration Number" rgroup.long (0x04+0x400)++0x03 line.long 0x00 "UH1_HWGENERAL,General Hardware Register" bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "No engine/parallel signaling,Engine present/serial signalling,Soft programmable/Reset to parallel,Soft programmable/Reset to serial" bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Soft programmable reset to UTMI/UMTI+,Soft programmable reset to ULPI DDR,Soft programmable reset to ULPI,Soft programmable reset to Serial" textline " " bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core" "8 bit non programmable,16 bit non programmable,8 bit programmable,16 bit programmable" textline " " rgroup.long (0x08+0x400)++0x03 line.long 0x00 "UH1_HWHOST,Host Hardware Parameters Register" bitfld.long 0x00 1.--3. " NPORT ,Number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0. " HC ,Host operation mode support for device" "Not supported,Supported" rgroup.long (0x10+0x400)++0x07 line.long 0x00 "UH1_HWTXBUF,TX Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "UH1_HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" textline " " group.long (0x80+0x400)++0xf "Device/Host Timer Registers" line.long 0x00 "UH1_GPTIMER0LD,General Purpose Timer #0 Load Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x04 "UH1_GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x04 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x04 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" line.long 0x08 "UH1_GPTIMER1LD,General Purpose Timer #1 Load Register" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General Purpose Timer Load Value" line.long 0x0C "UH1_GPTIMER1CTRL,General Purpose Timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General Purpose Timer Run" "Stoped,Running" bitfld.long 0x0C 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset" bitfld.long 0x0C 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General Purpose Timer Counter" textline " " group.long (0x90+0x400)++0x03 line.long 0x00 "UH1_SBUSCFG,System Bus Config" bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface Burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte (0x100+0x400)++0x00 line.byte 0x00 "UH1_CAPLENGTH,Address offset to the Operational registers" rgroup.word (0x102+0x400)++0x01 line.word 0x00 "UH1_HCIVERSION,EHCI revision number supported by this host controller" rgroup.long (0x104+0x400)++0x07 line.long 0x00 "UH1_HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PI ,Port Indicators" "0,1" bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included" bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "UH1_HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer" bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" textline " " width 22. group.long (0x140+0x400)++0x03 line.long 0x00 "UH1_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard" bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" if ((per.l(0x400+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x144+0x400)++0x03 line.long 0x00 "UH1_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" rbitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected" bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested" textline " " bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" textline " " bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" else group.long (0x144+0x400)++0x03 line.long 0x00 "UH1_USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" textline " " bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" endif group.long (0x148+0x400)++0x07 line.long 0x00 "UH1_USBINTR,USB Interrupt Enable" bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host Asynchronous Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " ULPIE ,ULPI Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x04 "UH1_FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index" if ((per.l(0x400+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x154+0x400)++0x03 line.long 0x00 "UH1_PERCLISTBASE,Host Controller Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)" elif ((per.l(0x400+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x154+0x400)++0x03 line.long 0x00 "UH1_DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x02 " BASEADR ,USB device address" bitfld.long 0x00 24. " USBADRA ,Write method to USBADR" "Instantaneous,Staged/hidden register" endif if ((per.l(0x400+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x158+0x400)++0x03 line.long 0x00 "UH1_ASYNCLISTADDR,Host Controller Next Asynch Address Register" hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low" elif ((per.l(0x400+ad:0x02184000+0x1a8)&0x3)==0x2) group.long (0x158+0x400)++0x03 line.long 0x00 "UH1_ENDPTLISTADDR,Device Controller Endpoint List Address Register" hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address" endif group.long (0x160+0x400)++0x7 line.long 0x00 "UH1_BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length" line.long 0x04 "UH1_TXFILLTUNING,TX FIFO Fill Tuning Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler Health Counter" hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead" textline " " width 22. rgroup.long (0x180+0x400)++0x03 line.long 0x00 "UH1_CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Configure Flag" "Classic,This" textline " " width 17. if ((per.l(0x400+ad:0x02184000+0x1a8)&0x3)==0x3) group.long (0x184+0x400)++0x03 line.long 0x00 "UH1_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" else group.long (0x184+0x400)++0x03 line.long 0x00 "UH1_PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected" bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High," textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,,,,,,,," bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green," bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set" textline " " bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state," sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" else bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" endif rbitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed" sif ((cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")) rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" else bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current" endif textline " " eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device" endif group.long (0x1a8+0x400)++0x03 line.long 0x00 "UH1_USBMODE,USB Device Mode Register" bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,,Device,Host" textline " " width 22. width 0xb tree.end endif tree.end width 26. tree "USB Non-core Registers" group.long 0x800++0x07 line.long 0x00 "USB_OTG1_CTRL,USB OTG1 Control Register" rbitfld.long 0x00 31. " WIR ,OTG Wake-up Interrupt Request" "Not requested,Requested" bitfld.long 0x00 17. " WKUP_VBUS_EN ,OTG wake-up on VBUS change enable" "Disabled,Enabled" bitfld.long 0x00 16. " WKUP_ID_EN ,OTG Wake-up on ID change enable" "Disabled,Enabled" bitfld.long 0x00 15. " WKUP_SW ,OTG Software Wake-up" "Inactive,Wake-up" textline " " bitfld.long 0x00 14. " WKUP_SW_EN ,OTG Software Wake-up Enable" "Disabled,Enabled" bitfld.long 0x00 10. " WIE ,OTG Wake-up Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PWR_POL ,OTG Power Polarity" "Low,High" bitfld.long 0x00 8. " OVER_CUR_POL ,OTG Polarity of Overcurrent" "High,Low" textline " " bitfld.long 0x00 7. " OVER_CUR_DIS ,Disable OTG Overcurrent Detection" "No,Yes" line.long 0x04 "USB_OTG2_CTRL,USB OTG2 Control Register" rbitfld.long 0x04 31. " WIR ,OTG Wake-up Interrupt Request" "Not requested,Requested" bitfld.long 0x04 17. " WKUP_VBUS_EN ,OTG wake-up on VBUS change enable" "Disabled,Enabled" bitfld.long 0x04 16. " WKUP_ID_EN ,OTG Wake-up on ID change enable" "Disabled,Enabled" bitfld.long 0x04 15. " WKUP_SW ,OTG Software Wake-up" "Inactive,Wake-up" textline " " bitfld.long 0x04 14. " WKUP_SW_EN ,OTG Software Wake-up Enable" "Disabled,Enabled" bitfld.long 0x04 10. " WIE ,OTG Wake-up Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 9. " PWR_POL ,OTG Power Polarity" "Low,High" bitfld.long 0x04 8. " OVER_CUR_POL ,OTG Polarity of Overcurrent" "High,Low" textline " " bitfld.long 0x04 7. " OVER_CUR_DIS ,Disable OTG Overcurrent Detection" "No,Yes" sif ((cpu()!="IMX6ULTRALITE")&&(cpu()!="IMX6ULL")) group.long 0x808++0x07 line.long 0x00 "USB_UH_CTRL,USB Host Control Register" rbitfld.long 0x00 31. " WIR ,Host 2 Wake-up Interrupt Request" "Not requested,Requested" bitfld.long 0x00 15. " WKUP_SW ,Host 2 Software Wake-up" "Inactive,Wake-up" bitfld.long 0x00 14. " WKUP_SW_EN ,Host 2 Software Wake-up Enable" "Disabled,Enabled" bitfld.long 0x00 13. " 480_CLK_ON ,Force OTG UTMI PHY 480M clock output on when Host 2 is not in suspend mode" "Inactive,Forced" textline " " bitfld.long 0x00 12. " SUSPENDM ,Host 2 UTMI PHY Suspend" "Enabled,Disabled" bitfld.long 0x00 11. " RESET ,Host 2 UTMI PHY Reset" "Inactive,Reset" bitfld.long 0x00 10. " WIE ,Host 2 Wake-up Interrupt Enable" "Disabled,Enabled" line.long 0x04 "USB_UH_HSIC_CTRL,USB Host High Speed Inter-Chip Control Register" rbitfld.long 0x04 31. " CLK_VLD ,Host2 HSIC clock valid" "Invalid,Valid" bitfld.long 0x04 12. " HSIC_EN ,Host HSIC enable" "Disabled,Enabled" bitfld.long 0x04 11. " HSIC_CLK_ON ,Force Host HSIC module 480M clock on" "Inactive,Active" endif group.long 0x818++0x07 line.long 0x00 "USB_OTG1_PHY_CTRL_0,OTG1 UTMI PHY Control 0 Register" bitfld.long 0x00 31. " UTMI_CLK_VLD ,UTMI PHY Clock Valid" "Invalid,Valid" line.long 0x04 "USB_OTG2_PHY_CTRL_0,OTG2 UTMI PHY Control 0 Register" bitfld.long 0x04 31. " UTMI_CLK_VLD ,UTMI PHY Clock Valid" "Invalid,Valid" tree.end width 11. tree.end tree.open "USB-PHY (Universal Serial Bus 2.0 Integrated PHY)" tree "PHY1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020C9000 else base ad:0x420C9000 endif width 29. group.long 0x00++0x43 line.long 0x00 "HW_USBPHY1_PWD,USB PHY Power-Down Register" bitfld.long 0x00 20. " RXPWDRX ,Receiver block power-down" "Normal,Power-down" bitfld.long 0x00 19. " RXPWDDIFF ,High-speed differential receiver power-down" "Normal,Power-down" bitfld.long 0x00 18. " RXPWD1PT1 ,Full-speed differential receiver power-down" "Normal,Power-down" textline " " bitfld.long 0x00 17. " RXPWDENV ,High-speed receiver envelope detector power-down" "Normal,Power-down" bitfld.long 0x00 12. " TXPWDV2I ,Transmit V-to-I converter and the current mirror power-down" "Normal,Power-down" bitfld.long 0x00 11. " TXPWDIBIAS ,Current bias block for the transmitter power-down" "Normal,Power-down" textline " " bitfld.long 0x00 10. " TXPWDFS ,Full-speed drivers power-down" "Normal,Power-down" line.long 0x04 "HW_USBPHY1_PWD_SET,USB PHY Power-Down Set Register" bitfld.long 0x04 20. " RXPWDRX ,Receiver block power-down set" "No effect,Set" bitfld.long 0x04 19. " RXPWDDIFF ,High-speed differential receiver power-down set" "No effect,Set" bitfld.long 0x04 18. " RXPWD1PT1 ,Full-speed differential receiver power-down set" "No effect,Set" textline " " bitfld.long 0x04 17. " RXPWDENV ,High-speed receiver envelope detector power-down set" "No effect,Set" bitfld.long 0x04 12. " TXPWDV2I ,Transmit V-to-I converter and the current mirror power-down set" "No effect,Set" bitfld.long 0x04 11. " TXPWDIBIAS ,Current bias block for the transmitter power-down set" "No effect,Set" textline " " bitfld.long 0x04 10. " TXPWDFS ,Full-speed drivers power-down" "No effect,Set" line.long 0x08 "HW_USBPHY1_PWD_CLR,USB PHY Power-Down Clear Register" bitfld.long 0x08 20. " RXPWDRX ,Receiver block power-down clear" "No effect,Clear" bitfld.long 0x08 19. " RXPWDDIFF ,High-speed differential receiver power-down clear" "No effect,Clear" bitfld.long 0x08 18. " RXPWD1PT1 ,Full-speed differential receiver power-down clear" "No effect,Clear" textline " " bitfld.long 0x08 17. " RXPWDENV ,High-speed receiver envelope detector power-down clear" "No effect,Clear" bitfld.long 0x08 12. " TXPWDV2I ,Transmit V-to-I converter and the current mirror power-down clear" "No effect,Clear" bitfld.long 0x08 11. " TXPWDIBIAS ,Current bias block for the transmitter power-down clear" "No effect,Clear" textline " " bitfld.long 0x08 10. " TXPWDFS ,Full-speed drivers power-down clear" "No effect,Clear" line.long 0x0C "HW_USBPHY1_PWD_TOG,USB PHY Power-Down Toggle Register" bitfld.long 0x0C 20. " RXPWDRX ,Receiver block power-down toggle" "No effect,Toggled" bitfld.long 0x0C 19. " RXPWDDIFF ,High-speed differential receiver power-down toggle" "No effect,Toggled" bitfld.long 0x0C 18. " RXPWD1PT1 ,Full-speed differential receiver power-down toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 17. " RXPWDENV ,High-speed receiver envelope detector power-down toggle" "No effect,Toggled" bitfld.long 0x0C 12. " TXPWDV2I ,Transmit V-to-I converter and the current mirror power-down toggle" "No effect,Toggled" bitfld.long 0x0C 11. " TXPWDIBIAS ,Current bias block for the transmitter power-down toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 10. " TXPWDFS ,Full-speed drivers power-down toggle" "No effect,Toggled" line.long 0x10 "HW_USBPHY1_TX,USB PHY Transmitter Control Register" bitfld.long 0x10 16.--19. " TXCAL45DP ,Resistance selection to the USB_DP output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x10 8.--11. " TXCAL45DN ,Resistance selection to the USB_DN output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x10 0.--3. " D_CAL ,Resistor Trimming Code" "0.16%,,,,,,,Nominal,,,,,,,,+25%" line.long 0x14 "HW_USBPHY1_TX_SET,USB PHY Transmitter Set Register" bitfld.long 0x14 16.--19. " TXCAL45DP ,Resistance selection to the USB_DP output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x14 8.--11. " TXCAL45DN ,Resistance selection to the USB_DN output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x14 0.--3. " D_CAL ,Resistor Trimming Code" "0.16%,,,,,,,Nominal,,,,,,,,+25%" line.long 0x18 "HW_USBPHY1_TX_CLR,USB PHY Transmitter Clear Register" bitfld.long 0x18 16.--19. " TXCAL45DP ,Resistance selection to the USB_DP output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x18 8.--11. " TXCAL45DN ,Resistance selection to the USB_DN output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x18 0.--3. " D_CAL ,Resistor Trimming Code" "0.16%,,,,,,,Nominal,,,,,,,,+25%" line.long 0x1C "HW_USBPHY1_TX_TOG,USB PHY Transmitter Toggle Register" bitfld.long 0x1C 16.--19. " TXCAL45DP ,Resistance selection to the USB_DP output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x1C 8.--11. " TXCAL45DN ,Resistance selection to the USB_DN output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x1C 0.--3. " D_CAL ,Resistor Trimming Code" "0.16%,,,,,,,Nominal,,,,,,,,+25%" line.long 0x20 "HW_USBPHY1_RX,USB PHY Receiver Control Register" bitfld.long 0x20 22. " RXDBYPASS ,Bypass" "Normal,Single-ended" bitfld.long 0x20 4.--6. " DISCONADJ ,Adjusts the trip point for the disconnect detector" "0.57500 V,0.56875 V,0.58125 V,0.58750 V,?..." bitfld.long 0x20 0.--2. " ENVADJ ,Adjusts the trip point for the envelope detector" "0.12500 V,0.10000 V,0.13750 V,0.15000 V,?..." line.long 0x24 "HW_USBPHY1_RX_SET,USB PHY Receiver Set Register" bitfld.long 0x24 22. " RXDBYPASS ,Bypass set" "No effect,Set" bitfld.long 0x24 4.--6. " DISCONADJ ,Adjusts the trip point for the disconnect detector" "0.57500 V,0.56875 V,0.58125 V,0.58750 V,?..." bitfld.long 0x24 0.--2. " ENVADJ ,Adjusts the trip point for the envelope detector" "0.12500 V,0.10000 V,0.13750 V,0.15000 V,?..." line.long 0x28 "HW_USBPHY1_RX_CLR,USB PHY Receiver Clear Register" bitfld.long 0x28 22. " RXDBYPASS ,Bypass clear" "No effect,Clear" bitfld.long 0x28 4.--6. " DISCONADJ ,Adjusts the trip point for the disconnect detector" "0.57500 V,0.56875 V,0.58125 V,0.58750 V,?..." bitfld.long 0x28 0.--2. " ENVADJ ,Adjusts the trip point for the envelope detector" "0.12500 V,0.10000 V,0.13750 V,0.15000 V,?..." line.long 0x2C "HW_USBPHY1_RX_TOG,USB PHY Receiver Toggle Register" bitfld.long 0x2C 22. " RXDBYPASS ,Bypass toggle" "No effect,Toggled" bitfld.long 0x2C 4.--6. " DISCONADJ ,Adjusts the trip point for the disconnect detector" "0.57500 V,0.56875 V,0.58125 V,0.58750 V,?..." bitfld.long 0x2C 0.--2. " ENVADJ ,Adjusts the trip point for the envelope detector" "0.12500 V,0.10000 V,0.13750 V,0.15000 V,?..." line.long 0x30 "HW_USBPHY1_CTRL,USB PHY General Control Register" bitfld.long 0x30 31. " SFTRST ,Soft reset" "No reset,Reset" bitfld.long 0x30 30. " CLKGATE ,Gate UTMI Clocks" "Running,Gated" rbitfld.long 0x30 29. " UTMI_SUSPENDM ,UTMI suspend mode" "Disabled,Enabled" textline " " bitfld.long 0x30 28. " HOST_FORCE_LS_SE0 ,EOP with low-speed timing" "No effect,Low-speed" rbitfld.long 0x30 27. " OTG_ID_VALUE ,ID value" "A-side,B-side" bitfld.long 0x30 24. " FSDLL_RST_EN ,FSDLL reset enable" "Disabled,Enabled" textline " " bitfld.long 0x30 23. " ENVBUSCHG_WKUP ,Wakeup USB if VBUS is toggled when USB is suspended enable" "Disabled,Enabled" bitfld.long 0x30 22. " ENIDCHG_WKUP ,Wakeup USB if ID is toggled when USB is suspended enable" "Disabled,Enabled" bitfld.long 0x30 21. " ENDPDMCHG_WKUP ,Wakeup USB if DP/DM is toggled when USB is suspended enable" "Disabled,Enabled" textline " " bitfld.long 0x30 20. " ENAUTOCLR_PHY_PWD ,Auto-clear the PWD register bits enable" "Disabled,Enabled" bitfld.long 0x30 19. " ENAUTOCLR_CLKGATE ,Auto-clear the CLKGATE bit enable" "Disabled,Enabled" bitfld.long 0x30 17. " WAKEUP_IRQ ,Wake-up event" "No interrupt,Interrupt" textline " " bitfld.long 0x30 16. " ENIRQWAKEUP ,Interrupt for the wakeup events enable" "Disabled,Enabled" bitfld.long 0x30 15. " ENUTMILEVEL3 ,UTMI+ Level3 enable" "Disabled,Enabled" bitfld.long 0x30 14. " ENUTMILEVEL2 ,UTMI+ Level2 enable" "Disabled,Enabled" textline " " bitfld.long 0x30 13. " DATA_ON_LRADC ,LRADC to monitor USB_DP and USB_DM enable" "Disabled,Enabled" bitfld.long 0x30 12. " DEVPLUGIN_IRQ ,Device connection" "No interrupt,Interrupt" bitfld.long 0x30 11. " ENIRQDEVPLUGIN ,Interrupt for the detection of connectivity to the USB line" "Disabled,Enabled" textline " " bitfld.long 0x30 10. " RESUME_IRQ ,Sending a wake-up after suspend" "Not sent,Sent" bitfld.long 0x30 9. " ENIRQRESUMEDETECT ,Interrupt for detection of a non-J state on the USB line enable" "Disabled,Enabled" bitfld.long 0x30 8. " RESUMEIRQSTICKY ,Resume_IRQ sticky bit" "During wake-up,Until software clear" textline " " bitfld.long 0x30 7. " ENOTGIDDETECT ,Circuit to detect resistance of MiniAB ID pin enable" "Disabled,Enabled" bitfld.long 0x30 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt" "No interrupt,Interrupt" bitfld.long 0x30 5. " DEVPLUGIN_POLARITY ,Devplugin polarity interrupt" "Plugged in,Unplugged" textline " " bitfld.long 0x30 4. " ENDEVPLUGINDETECT ,200-KOhm pullups enable" "Disabled,Enabled" bitfld.long 0x30 3. " HOSTDISCONDETECT_IRQ ,Disconnected in high-speed mode" "Connected,Disconnected" bitfld.long 0x30 2. " ENIRQHOSTDISCON ,Detection of disconnection to Device when in high-speed host mode interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " ENHOSTDISCONDETECT ,High-speed disconnect detector enable" "Disabled,Enabled" bitfld.long 0x30 0. " ENOTG_ID_CHG_IRQ ,OTG_ID_CHG_IRQ enable" "Disabled,Enabled" line.long 0x34 "HW_USBPHY1_CTRL_SET,USB PHY General Control Set Register" bitfld.long 0x34 31. " SFTRST ,Soft reset set" "No effect,Set" bitfld.long 0x34 30. " CLKGATE ,Gate UTMI Clocks set" "No effect,Set" rbitfld.long 0x34 29. " UTMI_SUSPENDM ,UTMI suspend mode set" "No effect,Set" textline " " bitfld.long 0x34 28. " HOST_FORCE_LS_SE0 ,EOP with low-speed timing set" "No effect,Set" rbitfld.long 0x34 27. " OTG_ID_VALUE ,ID value set" "No effect,Set" bitfld.long 0x34 24. " FSDLL_RST_EN ,FSDLL reset set" "No effect,Set" textline " " bitfld.long 0x34 23. " ENVBUSCHG_WKUP ,Wakeup USB if VBUS is toggled when USB is suspended set" "No effect,Set" bitfld.long 0x34 22. " ENIDCHG_WKUP ,Wakeup USB if ID is toggled when USB is suspended set" "No effect,Set" bitfld.long 0x34 21. " ENDPDMCHG_WKUP ,Wakeup USB if DP/DM is toggled when USB is suspended set" "No effect,Set" textline " " bitfld.long 0x34 20. " ENAUTOCLR_PHY_PWD ,Auto-clear the PWD register bits set" "No effect,Set" bitfld.long 0x34 19. " ENAUTOCLR_CLKGATE ,Auto-clear the CLKGATE bit set" "No effect,Set" bitfld.long 0x34 17. " WAKEUP_IRQ ,Wake-up event set" "No effect,Set" textline " " bitfld.long 0x34 16. " ENIRQWAKEUP ,Interrupt for the wakeup events set" "No effect,Set" bitfld.long 0x34 15. " ENUTMILEVEL3 ,UTMI+ Level3 set" "No effect,Set" bitfld.long 0x34 14. " ENUTMILEVEL2 ,UTMI+ Level2 set" "No effect,Set" textline " " bitfld.long 0x34 13. " DATA_ON_LRADC ,LRADC to monitor USB_DP and USB_DM set" "No effect,Set" bitfld.long 0x34 12. " DEVPLUGIN_IRQ ,Device connection set" "No effect,Set" bitfld.long 0x34 11. " ENIRQDEVPLUGIN ,Interrupt for the detection of connectivity to the USB line set" "No effect,Set" textline " " bitfld.long 0x34 10. " RESUME_IRQ ,Sending a wake-up after suspend set" "No effect,Set" bitfld.long 0x34 9. " ENIRQRESUMEDETECT ,Interrupt for detection of a non-J state on the USB line set" "No effect,Set" bitfld.long 0x34 8. " RESUMEIRQSTICKY ,Resume_IRQ sticky bit set" "No effect,Set" textline " " bitfld.long 0x34 7. " ENOTGIDDETECT ,Circuit to detect resistance of MiniAB ID pin set" "No effect,Set" bitfld.long 0x34 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt set" "No effect,Set" bitfld.long 0x34 5. " DEVPLUGIN_POLARITY ,Devplugin polarity interrupt set" "No effect,Set" textline " " bitfld.long 0x34 4. " ENDEVPLUGINDETECT ,200-KOhm pullups set" "No effect,Set" bitfld.long 0x34 3. " HOSTDISCONDETECT_IRQ ,Disconnected in high-speed mode set" "No effect,Set" bitfld.long 0x34 2. " ENIRQHOSTDISCON ,Detection of disconnection to Device when in high-speed host mode interrupt set" "No effect,Set" textline " " bitfld.long 0x34 1. " ENHOSTDISCONDETECT ,High-speed disconnect detector set" "No effect,Set" bitfld.long 0x34 0. " ENOTG_ID_CHG_IRQ ,OTG_ID_CHG_IRQ set" "No effect,Set" line.long 0x38 "HW_USBPHY1_CTRL_CLR,USB PHY General Control Clear Register" bitfld.long 0x38 31. " SFTRST ,Soft reset clear" "No effect,Clear" bitfld.long 0x38 30. " CLKGATE ,Gate UTMI Clocks clear" "No effect,Clear" rbitfld.long 0x38 29. " UTMI_SUSPENDM ,UTMI suspend mode clear" "No effect,Clear" textline " " bitfld.long 0x38 28. " HOST_FORCE_LS_SE0 ,EOP with low-speed timing clear" "No effect,Clear" rbitfld.long 0x38 27. " OTG_ID_VALUE ,ID value clear" "No effect,Clear" bitfld.long 0x38 24. " FSDLL_RST_EN ,FSDLL reset clear" "No effect,Clear" textline " " bitfld.long 0x38 23. " ENVBUSCHG_WKUP ,Wakeup USB f VBUS is toggled when USB is suspended clear" "No effect,Clear" bitfld.long 0x38 22. " ENIDCHG_WKUP ,Wakeup USB if ID is toggled when USB is suspended clear" "No effect,Clear" bitfld.long 0x38 21. " ENDPDMCHG_WKUP ,Wakeup USB if DP/DM is toggled when USB is suspended clear" "No effect,Clear" textline " " bitfld.long 0x38 20. " ENAUTOCLR_PHY_PWD ,Auto-clear the PWD register bits clear" "No effect,Clear" bitfld.long 0x38 19. " ENAUTOCLR_CLKGATE ,Auto-clear the CLKGATE bit clear" "No effect,Clear" bitfld.long 0x38 17. " WAKEUP_IRQ ,Wake-up event clear" "No effect,Clear" textline " " bitfld.long 0x38 16. " ENIRQWAKEUP ,Interrupt for the wakeup events clear" "No effect,Clear" bitfld.long 0x38 15. " ENUTMILEVEL3 ,UTMI+ Level3 clear" "No effect,Clear" bitfld.long 0x38 14. " ENUTMILEVEL2 ,UTMI+ Level2 clear" "No effect,Clear" textline " " bitfld.long 0x38 13. " DATA_ON_LRADC ,LRADC to monitor USB_DP and USB_DM clear" "No effect,Clear" bitfld.long 0x38 12. " DEVPLUGIN_IRQ ,Device connection clear" "No effect,Clear" bitfld.long 0x38 11. " ENIRQDEVPLUGIN ,Interrupt for the detection of connectivity to the USB line clear" "No effect,Clear" textline " " bitfld.long 0x38 10. " RESUME_IRQ ,Sending a wake-up after suspend clear" "No effect,Clear" bitfld.long 0x38 9. " ENIRQRESUMEDETECT ,Interrupt for detection of a non-J state on the USB line clear" "No effect,Clear" bitfld.long 0x38 8. " RESUMEIRQSTICKY ,Resume_IRQ sticky bit clear" "No effect,Clear" textline " " bitfld.long 0x38 7. " ENOTGIDDETECT ,Circuit to detect resistance of MiniAB ID pin clear" "No effect,Clear" bitfld.long 0x38 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt clear" "No effect,Clear" bitfld.long 0x38 5. " DEVPLUGIN_POLARITY ,Devplugin polarity interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 4. " ENDEVPLUGINDETECT ,200-KOhm pullups clear" "No effect,Clear" bitfld.long 0x38 3. " HOSTDISCONDETECT_IRQ ,Disconnected in high-speed mode clear" "No effect,Clear" bitfld.long 0x38 2. " ENIRQHOSTDISCON ,Detection of disconnection to Device when in high-speed host mode interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 1. " ENHOSTDISCONDETECT ,High-speed disconnect detector clear" "No effect,Clear" bitfld.long 0x38 0. " ENOTG_ID_CHG_IRQ ,OTG_ID_CHG_IRQ clear" "No effect,Clear" line.long 0x3C "HW_USBPHY1_CTRL_TOG,USB PHY General Control Toggle Register" bitfld.long 0x3C 31. " SFTRST ,Soft reset toggle" "No effect,Toggled" bitfld.long 0x3C 30. " CLKGATE ,Gate UTMI Clocks toggle" "No effect,Toggled" rbitfld.long 0x3C 29. " UTMI_SUSPENDM ,UTMI suspend mode toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 28. " HOST_FORCE_LS_SE0 ,EOP with low-speed timing toggle" "No effect,Toggled" rbitfld.long 0x3C 27. " OTG_ID_VALUE ,ID value toggle" "No effect,Toggled" bitfld.long 0x3C 24. " FSDLL_RST_EN ,FSDLL reset clear toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 23. " ENVBUSCHG_WKUP ,Wakeup USB f VBUS is toggled when USB is suspended toggle" "No effect,Toggled" bitfld.long 0x3C 22. " ENIDCHG_WKUP ,Wakeup USB if ID is toggled when USB is suspended toggle" "No effect,Toggled" bitfld.long 0x3C 21. " ENDPDMCHG_WKUP ,Wakeup USB if DP/DM is toggled when USB is suspended toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 20. " ENAUTOCLR_PHY_PWD ,Auto-clear the PWD register bits toggle" "No effect,Toggled" bitfld.long 0x3C 19. " ENAUTOCLR_CLKGATE ,Auto-clear the CLKGATE bit toggle" "No effect,Toggled" bitfld.long 0x3C 17. " WAKEUP_IRQ ,Wake-up event toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 16. " ENIRQWAKEUP ,Interrupt for the wakeup events toggle" "No effect,Toggled" bitfld.long 0x3C 15. " ENUTMILEVEL3 ,UTMI+ Level3 toggle" "No effect,Toggled" bitfld.long 0x3C 14. " ENUTMILEVEL2 ,UTMI+ Level2 toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 13. " DATA_ON_LRADC ,LRADC to monitor USB_DP and USB_DM toggle" "No effect,Toggled" bitfld.long 0x3C 12. " DEVPLUGIN_IRQ ,Device connection toggle" "No effect,Toggled" bitfld.long 0x3C 11. " ENIRQDEVPLUGIN ,Interrupt for the detection of connectivity to the USB line toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 10. " RESUME_IRQ ,Sending a wake-up after suspend toggle" "No effect,Toggled" bitfld.long 0x3C 9. " ENIRQRESUMEDETECT ,Interrupt for detection of a non-J state on the USB line toggle" "No effect,Toggled" bitfld.long 0x3C 8. " RESUMEIRQSTICKY ,Resume_IRQ sticky bit toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 7. " ENOTGIDDETECT ,Circuit to detect resistance of MiniAB ID pin toggle" "No effect,Toggled" bitfld.long 0x3C 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt toggle" "No effect,Toggled" bitfld.long 0x3C 5. " DEVPLUGIN_POLARITY ,Devplugin polarity interrupt toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 4. " ENDEVPLUGINDETECT ,200-KOhm pullups toggle" "No effect,Toggled" bitfld.long 0x3C 3. " HOSTDISCONDETECT_IRQ ,Disconnected in high-speed mode toggle" "No effect,Toggled" bitfld.long 0x3C 2. " ENIRQHOSTDISCON ,Detection of disconnection to Device when in high-speed host mode interrupt toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 1. " ENHOSTDISCONDETECT ,High-speed disconnect detector toggle" "No effect,Toggled" bitfld.long 0x3C 0. " ENOTG_ID_CHG_IRQ ,OTG_ID_CHG_IRQ toggle" "No effect,Toggled" line.long 0x40 "HW_USBPHY1_STATUS,USB PHY Status Register" rbitfld.long 0x40 10. " RESUME_STATUS ,Wake-up after suspend sent - interrupt" "No interrupt,Interrupt" bitfld.long 0x40 8. " OTGID_STATUS ,OTGID status" "A-side,B-side" rbitfld.long 0x40 6. " DEVPLUGIN_STATUS ,Device connection on USP_DP and USB_DM lines" "Not connected,Connected" textline " " rbitfld.long 0x40 3. " HOSTDISCONDETECT_STATUS ,Device disconnected in high-speed host mode" "Not disconnected,Disconnected" group.long 0x50++0x0F line.long 0x00 "HW_USBPHY1_DEBUG,USB PHY Debug Register" bitfld.long 0x00 30. " CLKGATE ,Gate Test Clocks" "Running,Gated" bitfld.long 0x00 29. " HOST_RESUME_DEBUG ,Host resume debug" "HOST_FORCE_LS_SE0,UTMI_SUSPEND" bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 24. " ENSQUELCHRESET ,Squelch high-speed receive reset enable" "Disabled,Enabled" bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12. " ENTX2RXCOUNT ,Countdown to transition in between TX and RX enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 5. " ENHSTPULLDOWN[1] ,ENHST pull down for USB_DP control override" "Not overrided,Overrided" bitfld.long 0x00 4. " ENHSTPULLDOWN[0] ,ENHST pull down for USB_DM control override" "Not overrided,Overrided" textline " " bitfld.long 0x00 3. " HSTPULLDOWN[1] ,HST pull down for USB_DP" "No effect,Pulled down" bitfld.long 0x00 2. " HSTPULLDOWN[0] ,HST pull down for USB_DM" "No effect,Pulled down" bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD ,Debug interface hold" "Not assisted,Assisted" textline " " bitfld.long 0x00 0. " OTGIDPIOLOCK ,OTG ID lock" "Not locked,Locked" line.long 0x04 "HW_USBPHY1_DEBUG_SET,USB PHY Debug Set Register" bitfld.long 0x04 30. " CLKGATE ,Gate Test Clocks Set" "No effect,Set" bitfld.long 0x04 29. " HOST_RESUME_DEBUG ,Host resume debug set" "No effect,Set" bitfld.long 0x04 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 24. " ENSQUELCHRESET ,Squelch high-speed receive reset set" "No effect,Set" bitfld.long 0x04 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 12. " ENTX2RXCOUNT ,Transition in between TX and RX set" "No effect,Set" textline " " bitfld.long 0x04 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x04 5. " ENHSTPULLDOWN[1] ,ENHST pull down for USB_DP control override set" "No effect,Set" bitfld.long 0x04 4. " ENHSTPULLDOWN[0] ,ENHST pull down for USB_DM control override set" "No effect,Set" textline " " bitfld.long 0x04 3. " HSTPULLDOWN[1] ,HST pull down for USB_DP set" "No effect,Set" bitfld.long 0x04 2. " HSTPULLDOWN[0] ,HST pull down for USB_DM set" "No effect,Set" bitfld.long 0x04 1. " DEBUG_INTERFACE_HOLD ,Debug interface hold set" "No effect,Set" textline " " bitfld.long 0x04 0. " OTGIDPIOLOCK ,OTG ID lock set" "No effect,Set" line.long 0x08 "HW_USBPHY1_DEBUG_CLR,USB PHY Debug Clear Register" bitfld.long 0x08 30. " CLKGATE ,Gate Test Clocks clear" "No effect,Clear" bitfld.long 0x08 29. " HOST_RESUME_DEBUG ,Host resume debug clear" "No effect,Clear" bitfld.long 0x08 25.--28. " SQUELCHRESETLENGTH ,Duration of REclear clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 24. " ENSQUELCHRESET ,Squelch high-speed receive reclear clear" "No effect,Clear" bitfld.long 0x08 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 12. " ENTX2RXCOUNT ,Transition in between TX and RX clear" "No effect,Clear" textline " " bitfld.long 0x08 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x08 5. " ENHSTPULLDOWN[1] ,ENHST pull down for USB_DP control override clear" "No effect,Clear" bitfld.long 0x08 4. " ENHSTPULLDOWN[0] ,ENHST pull down for USB_DM control override clear" "No effect,Clear" textline " " bitfld.long 0x08 3. " HSTPULLDOWN[1] ,HST pull down for USB_DP clear" "No effect,Clear" bitfld.long 0x08 2. " HSTPULLDOWN[0] ,HST pull down for USB_DM clear" "No effect,Clear" bitfld.long 0x08 1. " DEBUG_INTERFACE_HOLD ,Debug interface hold clear" "No effect,Clear" textline " " bitfld.long 0x08 0. " OTGIDPIOLOCK ,OTG ID lock clear" "No effect,Clear" line.long 0x0C "HW_USBPHY1_DEBUG_TOG,USB PHY Debug Toggle Register" bitfld.long 0x0C 30. " CLKGATE ,Gate Test Clocks toggle" "No effect,Toggled" bitfld.long 0x0C 29. " HOST_RESUME_DEBUG ,Host resume debug toggle" "No effect,Toggled" bitfld.long 0x0C 25.--28. " SQUELCHRESETLENGTH ,Duration of REtoggle toggle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0C 24. " ENSQUELCHRESET ,Squelch high-speed receive retoggle toggle" "No effect,Toggled" bitfld.long 0x0C 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX toggle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 12. " ENTX2RXCOUNT ,Transition in between TX and RX toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x0C 5. " ENHSTPULLDOWN[1] ,ENHST pull down for USB_DP control override toggle" "No effect,Toggled" bitfld.long 0x0C 4. " ENHSTPULLDOWN[0] ,ENHST pull down for USB_DM control override toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 3. " HSTPULLDOWN[1] ,HST pull down for USB_DP toggle" "No effect,Toggled" bitfld.long 0x0C 2. " HSTPULLDOWN[0] ,HST pull down for USB_DM toggle" "No effect,Toggled" bitfld.long 0x0C 1. " DEBUG_INTERFACE_HOLD ,Debug interface hold toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 0. " OTGIDPIOLOCK ,OTG ID lock toggle" "No effect,Toggled" rgroup.long 0x60++0x03 line.long 0x00 "HW_USBPHY1_DEBUG0_STATUS,UTMI Debug Status Register 0" bitfld.long 0x00 26.--31. " SQUELCH_COUNT ,Running count of the squelch reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. " UTMI_RXERROR_FAIL_COUNT ,UTMI_RXERROR running count" hexmask.long.word 0x00 0.--15. 1. " LOOP_BACK_FAIL_COUNT ,Failed pseudo-random generator loopback running count" group.long 0x70++0x0F line.long 0x00 "HW_USBPHY1_DEBUG1,UTMI Debug Status Register 1" bitfld.long 0x00 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x04 "HW_USBPHY1_DEBUG1_SET,UTMI Debug Set Register 1" bitfld.long 0x04 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x08 "HW_USBPHY1_DEBUG1_CLR,UTMI Debug Clear Register 1" bitfld.long 0x08 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x0C "HW_USBPHY1_DEBUG1_TOG,UTMI Debug Toggle Register 1" bitfld.long 0x0C 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" rgroup.long 0x80++0x03 line.long 0x00 "HW_USBPHY1_VERSION,UTMI RTL Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Stepping of the RTL version" width 0x0B tree.end tree "PHY2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020CA000 else base ad:0x420CA000 endif width 29. group.long 0x00++0x43 line.long 0x00 "HW_USBPHY2_PWD,USB PHY Power-Down Register" bitfld.long 0x00 20. " RXPWDRX ,Receiver block power-down" "Normal,Power-down" bitfld.long 0x00 19. " RXPWDDIFF ,High-speed differential receiver power-down" "Normal,Power-down" bitfld.long 0x00 18. " RXPWD1PT1 ,Full-speed differential receiver power-down" "Normal,Power-down" textline " " bitfld.long 0x00 17. " RXPWDENV ,High-speed receiver envelope detector power-down" "Normal,Power-down" bitfld.long 0x00 12. " TXPWDV2I ,Transmit V-to-I converter and the current mirror power-down" "Normal,Power-down" bitfld.long 0x00 11. " TXPWDIBIAS ,Current bias block for the transmitter power-down" "Normal,Power-down" textline " " bitfld.long 0x00 10. " TXPWDFS ,Full-speed drivers power-down" "Normal,Power-down" line.long 0x04 "HW_USBPHY2_PWD_SET,USB PHY Power-Down Set Register" bitfld.long 0x04 20. " RXPWDRX ,Receiver block power-down set" "No effect,Set" bitfld.long 0x04 19. " RXPWDDIFF ,High-speed differential receiver power-down set" "No effect,Set" bitfld.long 0x04 18. " RXPWD1PT1 ,Full-speed differential receiver power-down set" "No effect,Set" textline " " bitfld.long 0x04 17. " RXPWDENV ,High-speed receiver envelope detector power-down set" "No effect,Set" bitfld.long 0x04 12. " TXPWDV2I ,Transmit V-to-I converter and the current mirror power-down set" "No effect,Set" bitfld.long 0x04 11. " TXPWDIBIAS ,Current bias block for the transmitter power-down set" "No effect,Set" textline " " bitfld.long 0x04 10. " TXPWDFS ,Full-speed drivers power-down" "No effect,Set" line.long 0x08 "HW_USBPHY2_PWD_CLR,USB PHY Power-Down Clear Register" bitfld.long 0x08 20. " RXPWDRX ,Receiver block power-down clear" "No effect,Clear" bitfld.long 0x08 19. " RXPWDDIFF ,High-speed differential receiver power-down clear" "No effect,Clear" bitfld.long 0x08 18. " RXPWD1PT1 ,Full-speed differential receiver power-down clear" "No effect,Clear" textline " " bitfld.long 0x08 17. " RXPWDENV ,High-speed receiver envelope detector power-down clear" "No effect,Clear" bitfld.long 0x08 12. " TXPWDV2I ,Transmit V-to-I converter and the current mirror power-down clear" "No effect,Clear" bitfld.long 0x08 11. " TXPWDIBIAS ,Current bias block for the transmitter power-down clear" "No effect,Clear" textline " " bitfld.long 0x08 10. " TXPWDFS ,Full-speed drivers power-down clear" "No effect,Clear" line.long 0x0C "HW_USBPHY2_PWD_TOG,USB PHY Power-Down Toggle Register" bitfld.long 0x0C 20. " RXPWDRX ,Receiver block power-down toggle" "No effect,Toggled" bitfld.long 0x0C 19. " RXPWDDIFF ,High-speed differential receiver power-down toggle" "No effect,Toggled" bitfld.long 0x0C 18. " RXPWD1PT1 ,Full-speed differential receiver power-down toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 17. " RXPWDENV ,High-speed receiver envelope detector power-down toggle" "No effect,Toggled" bitfld.long 0x0C 12. " TXPWDV2I ,Transmit V-to-I converter and the current mirror power-down toggle" "No effect,Toggled" bitfld.long 0x0C 11. " TXPWDIBIAS ,Current bias block for the transmitter power-down toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 10. " TXPWDFS ,Full-speed drivers power-down toggle" "No effect,Toggled" line.long 0x10 "HW_USBPHY2_TX,USB PHY Transmitter Control Register" bitfld.long 0x10 16.--19. " TXCAL45DP ,Resistance selection to the USB_DP output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x10 8.--11. " TXCAL45DN ,Resistance selection to the USB_DN output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x10 0.--3. " D_CAL ,Resistor Trimming Code" "0.16%,,,,,,,Nominal,,,,,,,,+25%" line.long 0x14 "HW_USBPHY2_TX_SET,USB PHY Transmitter Set Register" bitfld.long 0x14 16.--19. " TXCAL45DP ,Resistance selection to the USB_DP output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x14 8.--11. " TXCAL45DN ,Resistance selection to the USB_DN output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x14 0.--3. " D_CAL ,Resistor Trimming Code" "0.16%,,,,,,,Nominal,,,,,,,,+25%" line.long 0x18 "HW_USBPHY2_TX_CLR,USB PHY Transmitter Clear Register" bitfld.long 0x18 16.--19. " TXCAL45DP ,Resistance selection to the USB_DP output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x18 8.--11. " TXCAL45DN ,Resistance selection to the USB_DN output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x18 0.--3. " D_CAL ,Resistor Trimming Code" "0.16%,,,,,,,Nominal,,,,,,,,+25%" line.long 0x1C "HW_USBPHY2_TX_TOG,USB PHY Transmitter Toggle Register" bitfld.long 0x1C 16.--19. " TXCAL45DP ,Resistance selection to the USB_DP output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x1C 8.--11. " TXCAL45DN ,Resistance selection to the USB_DN output pin" "0(maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(minimum)" bitfld.long 0x1C 0.--3. " D_CAL ,Resistor Trimming Code" "0.16%,,,,,,,Nominal,,,,,,,,+25%" line.long 0x20 "HW_USBPHY2_RX,USB PHY Receiver Control Register" bitfld.long 0x20 22. " RXDBYPASS ,Bypass" "Normal,Single-ended" bitfld.long 0x20 4.--6. " DISCONADJ ,Adjusts the trip point for the disconnect detector" "0.57500 V,0.56875 V,0.58125 V,0.58750 V,?..." bitfld.long 0x20 0.--2. " ENVADJ ,Adjusts the trip point for the envelope detector" "0.12500 V,0.10000 V,0.13750 V,0.15000 V,?..." line.long 0x24 "HW_USBPHY2_RX_SET,USB PHY Receiver Set Register" bitfld.long 0x24 22. " RXDBYPASS ,Bypass set" "No effect,Set" bitfld.long 0x24 4.--6. " DISCONADJ ,Adjusts the trip point for the disconnect detector" "0.57500 V,0.56875 V,0.58125 V,0.58750 V,?..." bitfld.long 0x24 0.--2. " ENVADJ ,Adjusts the trip point for the envelope detector" "0.12500 V,0.10000 V,0.13750 V,0.15000 V,?..." line.long 0x28 "HW_USBPHY2_RX_CLR,USB PHY Receiver Clear Register" bitfld.long 0x28 22. " RXDBYPASS ,Bypass clear" "No effect,Clear" bitfld.long 0x28 4.--6. " DISCONADJ ,Adjusts the trip point for the disconnect detector" "0.57500 V,0.56875 V,0.58125 V,0.58750 V,?..." bitfld.long 0x28 0.--2. " ENVADJ ,Adjusts the trip point for the envelope detector" "0.12500 V,0.10000 V,0.13750 V,0.15000 V,?..." line.long 0x2C "HW_USBPHY2_RX_TOG,USB PHY Receiver Toggle Register" bitfld.long 0x2C 22. " RXDBYPASS ,Bypass toggle" "No effect,Toggled" bitfld.long 0x2C 4.--6. " DISCONADJ ,Adjusts the trip point for the disconnect detector" "0.57500 V,0.56875 V,0.58125 V,0.58750 V,?..." bitfld.long 0x2C 0.--2. " ENVADJ ,Adjusts the trip point for the envelope detector" "0.12500 V,0.10000 V,0.13750 V,0.15000 V,?..." line.long 0x30 "HW_USBPHY2_CTRL,USB PHY General Control Register" bitfld.long 0x30 31. " SFTRST ,Soft reset" "No reset,Reset" bitfld.long 0x30 30. " CLKGATE ,Gate UTMI Clocks" "Running,Gated" rbitfld.long 0x30 29. " UTMI_SUSPENDM ,UTMI suspend mode" "Disabled,Enabled" textline " " bitfld.long 0x30 28. " HOST_FORCE_LS_SE0 ,EOP with low-speed timing" "No effect,Low-speed" rbitfld.long 0x30 27. " OTG_ID_VALUE ,ID value" "A-side,B-side" bitfld.long 0x30 24. " FSDLL_RST_EN ,FSDLL reset enable" "Disabled,Enabled" textline " " bitfld.long 0x30 23. " ENVBUSCHG_WKUP ,Wakeup USB if VBUS is toggled when USB is suspended enable" "Disabled,Enabled" bitfld.long 0x30 22. " ENIDCHG_WKUP ,Wakeup USB if ID is toggled when USB is suspended enable" "Disabled,Enabled" bitfld.long 0x30 21. " ENDPDMCHG_WKUP ,Wakeup USB if DP/DM is toggled when USB is suspended enable" "Disabled,Enabled" textline " " bitfld.long 0x30 20. " ENAUTOCLR_PHY_PWD ,Auto-clear the PWD register bits enable" "Disabled,Enabled" bitfld.long 0x30 19. " ENAUTOCLR_CLKGATE ,Auto-clear the CLKGATE bit enable" "Disabled,Enabled" bitfld.long 0x30 17. " WAKEUP_IRQ ,Wake-up event" "No interrupt,Interrupt" textline " " bitfld.long 0x30 16. " ENIRQWAKEUP ,Interrupt for the wakeup events enable" "Disabled,Enabled" bitfld.long 0x30 15. " ENUTMILEVEL3 ,UTMI+ Level3 enable" "Disabled,Enabled" bitfld.long 0x30 14. " ENUTMILEVEL2 ,UTMI+ Level2 enable" "Disabled,Enabled" textline " " bitfld.long 0x30 13. " DATA_ON_LRADC ,LRADC to monitor USB_DP and USB_DM enable" "Disabled,Enabled" bitfld.long 0x30 12. " DEVPLUGIN_IRQ ,Device connection" "No interrupt,Interrupt" bitfld.long 0x30 11. " ENIRQDEVPLUGIN ,Interrupt for the detection of connectivity to the USB line" "Disabled,Enabled" textline " " bitfld.long 0x30 10. " RESUME_IRQ ,Sending a wake-up after suspend" "Not sent,Sent" bitfld.long 0x30 9. " ENIRQRESUMEDETECT ,Interrupt for detection of a non-J state on the USB line enable" "Disabled,Enabled" bitfld.long 0x30 8. " RESUMEIRQSTICKY ,Resume_IRQ sticky bit" "During wake-up,Until software clear" textline " " bitfld.long 0x30 7. " ENOTGIDDETECT ,Circuit to detect resistance of MiniAB ID pin enable" "Disabled,Enabled" bitfld.long 0x30 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt" "No interrupt,Interrupt" bitfld.long 0x30 5. " DEVPLUGIN_POLARITY ,Devplugin polarity interrupt" "Plugged in,Unplugged" textline " " bitfld.long 0x30 4. " ENDEVPLUGINDETECT ,200-KOhm pullups enable" "Disabled,Enabled" bitfld.long 0x30 3. " HOSTDISCONDETECT_IRQ ,Disconnected in high-speed mode" "Connected,Disconnected" bitfld.long 0x30 2. " ENIRQHOSTDISCON ,Detection of disconnection to Device when in high-speed host mode interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " ENHOSTDISCONDETECT ,High-speed disconnect detector enable" "Disabled,Enabled" bitfld.long 0x30 0. " ENOTG_ID_CHG_IRQ ,OTG_ID_CHG_IRQ enable" "Disabled,Enabled" line.long 0x34 "HW_USBPHY2_CTRL_SET,USB PHY General Control Set Register" bitfld.long 0x34 31. " SFTRST ,Soft reset set" "No effect,Set" bitfld.long 0x34 30. " CLKGATE ,Gate UTMI Clocks set" "No effect,Set" rbitfld.long 0x34 29. " UTMI_SUSPENDM ,UTMI suspend mode set" "No effect,Set" textline " " bitfld.long 0x34 28. " HOST_FORCE_LS_SE0 ,EOP with low-speed timing set" "No effect,Set" rbitfld.long 0x34 27. " OTG_ID_VALUE ,ID value set" "No effect,Set" bitfld.long 0x34 24. " FSDLL_RST_EN ,FSDLL reset set" "No effect,Set" textline " " bitfld.long 0x34 23. " ENVBUSCHG_WKUP ,Wakeup USB if VBUS is toggled when USB is suspended set" "No effect,Set" bitfld.long 0x34 22. " ENIDCHG_WKUP ,Wakeup USB if ID is toggled when USB is suspended set" "No effect,Set" bitfld.long 0x34 21. " ENDPDMCHG_WKUP ,Wakeup USB if DP/DM is toggled when USB is suspended set" "No effect,Set" textline " " bitfld.long 0x34 20. " ENAUTOCLR_PHY_PWD ,Auto-clear the PWD register bits set" "No effect,Set" bitfld.long 0x34 19. " ENAUTOCLR_CLKGATE ,Auto-clear the CLKGATE bit set" "No effect,Set" bitfld.long 0x34 17. " WAKEUP_IRQ ,Wake-up event set" "No effect,Set" textline " " bitfld.long 0x34 16. " ENIRQWAKEUP ,Interrupt for the wakeup events set" "No effect,Set" bitfld.long 0x34 15. " ENUTMILEVEL3 ,UTMI+ Level3 set" "No effect,Set" bitfld.long 0x34 14. " ENUTMILEVEL2 ,UTMI+ Level2 set" "No effect,Set" textline " " bitfld.long 0x34 13. " DATA_ON_LRADC ,LRADC to monitor USB_DP and USB_DM set" "No effect,Set" bitfld.long 0x34 12. " DEVPLUGIN_IRQ ,Device connection set" "No effect,Set" bitfld.long 0x34 11. " ENIRQDEVPLUGIN ,Interrupt for the detection of connectivity to the USB line set" "No effect,Set" textline " " bitfld.long 0x34 10. " RESUME_IRQ ,Sending a wake-up after suspend set" "No effect,Set" bitfld.long 0x34 9. " ENIRQRESUMEDETECT ,Interrupt for detection of a non-J state on the USB line set" "No effect,Set" bitfld.long 0x34 8. " RESUMEIRQSTICKY ,Resume_IRQ sticky bit set" "No effect,Set" textline " " bitfld.long 0x34 7. " ENOTGIDDETECT ,Circuit to detect resistance of MiniAB ID pin set" "No effect,Set" bitfld.long 0x34 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt set" "No effect,Set" bitfld.long 0x34 5. " DEVPLUGIN_POLARITY ,Devplugin polarity interrupt set" "No effect,Set" textline " " bitfld.long 0x34 4. " ENDEVPLUGINDETECT ,200-KOhm pullups set" "No effect,Set" bitfld.long 0x34 3. " HOSTDISCONDETECT_IRQ ,Disconnected in high-speed mode set" "No effect,Set" bitfld.long 0x34 2. " ENIRQHOSTDISCON ,Detection of disconnection to Device when in high-speed host mode interrupt set" "No effect,Set" textline " " bitfld.long 0x34 1. " ENHOSTDISCONDETECT ,High-speed disconnect detector set" "No effect,Set" bitfld.long 0x34 0. " ENOTG_ID_CHG_IRQ ,OTG_ID_CHG_IRQ set" "No effect,Set" line.long 0x38 "HW_USBPHY2_CTRL_CLR,USB PHY General Control Clear Register" bitfld.long 0x38 31. " SFTRST ,Soft reset clear" "No effect,Clear" bitfld.long 0x38 30. " CLKGATE ,Gate UTMI Clocks clear" "No effect,Clear" rbitfld.long 0x38 29. " UTMI_SUSPENDM ,UTMI suspend mode clear" "No effect,Clear" textline " " bitfld.long 0x38 28. " HOST_FORCE_LS_SE0 ,EOP with low-speed timing clear" "No effect,Clear" rbitfld.long 0x38 27. " OTG_ID_VALUE ,ID value clear" "No effect,Clear" bitfld.long 0x38 24. " FSDLL_RST_EN ,FSDLL reset clear" "No effect,Clear" textline " " bitfld.long 0x38 23. " ENVBUSCHG_WKUP ,Wakeup USB f VBUS is toggled when USB is suspended clear" "No effect,Clear" bitfld.long 0x38 22. " ENIDCHG_WKUP ,Wakeup USB if ID is toggled when USB is suspended clear" "No effect,Clear" bitfld.long 0x38 21. " ENDPDMCHG_WKUP ,Wakeup USB if DP/DM is toggled when USB is suspended clear" "No effect,Clear" textline " " bitfld.long 0x38 20. " ENAUTOCLR_PHY_PWD ,Auto-clear the PWD register bits clear" "No effect,Clear" bitfld.long 0x38 19. " ENAUTOCLR_CLKGATE ,Auto-clear the CLKGATE bit clear" "No effect,Clear" bitfld.long 0x38 17. " WAKEUP_IRQ ,Wake-up event clear" "No effect,Clear" textline " " bitfld.long 0x38 16. " ENIRQWAKEUP ,Interrupt for the wakeup events clear" "No effect,Clear" bitfld.long 0x38 15. " ENUTMILEVEL3 ,UTMI+ Level3 clear" "No effect,Clear" bitfld.long 0x38 14. " ENUTMILEVEL2 ,UTMI+ Level2 clear" "No effect,Clear" textline " " bitfld.long 0x38 13. " DATA_ON_LRADC ,LRADC to monitor USB_DP and USB_DM clear" "No effect,Clear" bitfld.long 0x38 12. " DEVPLUGIN_IRQ ,Device connection clear" "No effect,Clear" bitfld.long 0x38 11. " ENIRQDEVPLUGIN ,Interrupt for the detection of connectivity to the USB line clear" "No effect,Clear" textline " " bitfld.long 0x38 10. " RESUME_IRQ ,Sending a wake-up after suspend clear" "No effect,Clear" bitfld.long 0x38 9. " ENIRQRESUMEDETECT ,Interrupt for detection of a non-J state on the USB line clear" "No effect,Clear" bitfld.long 0x38 8. " RESUMEIRQSTICKY ,Resume_IRQ sticky bit clear" "No effect,Clear" textline " " bitfld.long 0x38 7. " ENOTGIDDETECT ,Circuit to detect resistance of MiniAB ID pin clear" "No effect,Clear" bitfld.long 0x38 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt clear" "No effect,Clear" bitfld.long 0x38 5. " DEVPLUGIN_POLARITY ,Devplugin polarity interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 4. " ENDEVPLUGINDETECT ,200-KOhm pullups clear" "No effect,Clear" bitfld.long 0x38 3. " HOSTDISCONDETECT_IRQ ,Disconnected in high-speed mode clear" "No effect,Clear" bitfld.long 0x38 2. " ENIRQHOSTDISCON ,Detection of disconnection to Device when in high-speed host mode interrupt clear" "No effect,Clear" textline " " bitfld.long 0x38 1. " ENHOSTDISCONDETECT ,High-speed disconnect detector clear" "No effect,Clear" bitfld.long 0x38 0. " ENOTG_ID_CHG_IRQ ,OTG_ID_CHG_IRQ clear" "No effect,Clear" line.long 0x3C "HW_USBPHY2_CTRL_TOG,USB PHY General Control Toggle Register" bitfld.long 0x3C 31. " SFTRST ,Soft reset toggle" "No effect,Toggled" bitfld.long 0x3C 30. " CLKGATE ,Gate UTMI Clocks toggle" "No effect,Toggled" rbitfld.long 0x3C 29. " UTMI_SUSPENDM ,UTMI suspend mode toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 28. " HOST_FORCE_LS_SE0 ,EOP with low-speed timing toggle" "No effect,Toggled" rbitfld.long 0x3C 27. " OTG_ID_VALUE ,ID value toggle" "No effect,Toggled" bitfld.long 0x3C 24. " FSDLL_RST_EN ,FSDLL reset clear toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 23. " ENVBUSCHG_WKUP ,Wakeup USB f VBUS is toggled when USB is suspended toggle" "No effect,Toggled" bitfld.long 0x3C 22. " ENIDCHG_WKUP ,Wakeup USB if ID is toggled when USB is suspended toggle" "No effect,Toggled" bitfld.long 0x3C 21. " ENDPDMCHG_WKUP ,Wakeup USB if DP/DM is toggled when USB is suspended toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 20. " ENAUTOCLR_PHY_PWD ,Auto-clear the PWD register bits toggle" "No effect,Toggled" bitfld.long 0x3C 19. " ENAUTOCLR_CLKGATE ,Auto-clear the CLKGATE bit toggle" "No effect,Toggled" bitfld.long 0x3C 17. " WAKEUP_IRQ ,Wake-up event toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 16. " ENIRQWAKEUP ,Interrupt for the wakeup events toggle" "No effect,Toggled" bitfld.long 0x3C 15. " ENUTMILEVEL3 ,UTMI+ Level3 toggle" "No effect,Toggled" bitfld.long 0x3C 14. " ENUTMILEVEL2 ,UTMI+ Level2 toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 13. " DATA_ON_LRADC ,LRADC to monitor USB_DP and USB_DM toggle" "No effect,Toggled" bitfld.long 0x3C 12. " DEVPLUGIN_IRQ ,Device connection toggle" "No effect,Toggled" bitfld.long 0x3C 11. " ENIRQDEVPLUGIN ,Interrupt for the detection of connectivity to the USB line toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 10. " RESUME_IRQ ,Sending a wake-up after suspend toggle" "No effect,Toggled" bitfld.long 0x3C 9. " ENIRQRESUMEDETECT ,Interrupt for detection of a non-J state on the USB line toggle" "No effect,Toggled" bitfld.long 0x3C 8. " RESUMEIRQSTICKY ,Resume_IRQ sticky bit toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 7. " ENOTGIDDETECT ,Circuit to detect resistance of MiniAB ID pin toggle" "No effect,Toggled" bitfld.long 0x3C 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt toggle" "No effect,Toggled" bitfld.long 0x3C 5. " DEVPLUGIN_POLARITY ,Devplugin polarity interrupt toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 4. " ENDEVPLUGINDETECT ,200-KOhm pullups toggle" "No effect,Toggled" bitfld.long 0x3C 3. " HOSTDISCONDETECT_IRQ ,Disconnected in high-speed mode toggle" "No effect,Toggled" bitfld.long 0x3C 2. " ENIRQHOSTDISCON ,Detection of disconnection to Device when in high-speed host mode interrupt toggle" "No effect,Toggled" textline " " bitfld.long 0x3C 1. " ENHOSTDISCONDETECT ,High-speed disconnect detector toggle" "No effect,Toggled" bitfld.long 0x3C 0. " ENOTG_ID_CHG_IRQ ,OTG_ID_CHG_IRQ toggle" "No effect,Toggled" line.long 0x40 "HW_USBPHY2_STATUS,USB PHY Status Register" rbitfld.long 0x40 10. " RESUME_STATUS ,Wake-up after suspend sent - interrupt" "No interrupt,Interrupt" bitfld.long 0x40 8. " OTGID_STATUS ,OTGID status" "A-side,B-side" rbitfld.long 0x40 6. " DEVPLUGIN_STATUS ,Device connection on USP_DP and USB_DM lines" "Not connected,Connected" textline " " rbitfld.long 0x40 3. " HOSTDISCONDETECT_STATUS ,Device disconnected in high-speed host mode" "Not disconnected,Disconnected" group.long 0x50++0x0F line.long 0x00 "HW_USBPHY2_DEBUG,USB PHY Debug Register" bitfld.long 0x00 30. " CLKGATE ,Gate Test Clocks" "Running,Gated" bitfld.long 0x00 29. " HOST_RESUME_DEBUG ,Host resume debug" "HOST_FORCE_LS_SE0,UTMI_SUSPEND" bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 24. " ENSQUELCHRESET ,Squelch high-speed receive reset enable" "Disabled,Enabled" bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12. " ENTX2RXCOUNT ,Countdown to transition in between TX and RX enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 5. " ENHSTPULLDOWN[1] ,ENHST pull down for USB_DP control override" "Not overrided,Overrided" bitfld.long 0x00 4. " ENHSTPULLDOWN[0] ,ENHST pull down for USB_DM control override" "Not overrided,Overrided" textline " " bitfld.long 0x00 3. " HSTPULLDOWN[1] ,HST pull down for USB_DP" "No effect,Pulled down" bitfld.long 0x00 2. " HSTPULLDOWN[0] ,HST pull down for USB_DM" "No effect,Pulled down" bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD ,Debug interface hold" "Not assisted,Assisted" textline " " bitfld.long 0x00 0. " OTGIDPIOLOCK ,OTG ID lock" "Not locked,Locked" line.long 0x04 "HW_USBPHY2_DEBUG_SET,USB PHY Debug Set Register" bitfld.long 0x04 30. " CLKGATE ,Gate Test Clocks Set" "No effect,Set" bitfld.long 0x04 29. " HOST_RESUME_DEBUG ,Host resume debug set" "No effect,Set" bitfld.long 0x04 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 24. " ENSQUELCHRESET ,Squelch high-speed receive reset set" "No effect,Set" bitfld.long 0x04 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 12. " ENTX2RXCOUNT ,Transition in between TX and RX set" "No effect,Set" textline " " bitfld.long 0x04 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x04 5. " ENHSTPULLDOWN[1] ,ENHST pull down for USB_DP control override set" "No effect,Set" bitfld.long 0x04 4. " ENHSTPULLDOWN[0] ,ENHST pull down for USB_DM control override set" "No effect,Set" textline " " bitfld.long 0x04 3. " HSTPULLDOWN[1] ,HST pull down for USB_DP set" "No effect,Set" bitfld.long 0x04 2. " HSTPULLDOWN[0] ,HST pull down for USB_DM set" "No effect,Set" bitfld.long 0x04 1. " DEBUG_INTERFACE_HOLD ,Debug interface hold set" "No effect,Set" textline " " bitfld.long 0x04 0. " OTGIDPIOLOCK ,OTG ID lock set" "No effect,Set" line.long 0x08 "HW_USBPHY2_DEBUG_CLR,USB PHY Debug Clear Register" bitfld.long 0x08 30. " CLKGATE ,Gate Test Clocks clear" "No effect,Clear" bitfld.long 0x08 29. " HOST_RESUME_DEBUG ,Host resume debug clear" "No effect,Clear" bitfld.long 0x08 25.--28. " SQUELCHRESETLENGTH ,Duration of REclear clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 24. " ENSQUELCHRESET ,Squelch high-speed receive reclear clear" "No effect,Clear" bitfld.long 0x08 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 12. " ENTX2RXCOUNT ,Transition in between TX and RX clear" "No effect,Clear" textline " " bitfld.long 0x08 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x08 5. " ENHSTPULLDOWN[1] ,ENHST pull down for USB_DP control override clear" "No effect,Clear" bitfld.long 0x08 4. " ENHSTPULLDOWN[0] ,ENHST pull down for USB_DM control override clear" "No effect,Clear" textline " " bitfld.long 0x08 3. " HSTPULLDOWN[1] ,HST pull down for USB_DP clear" "No effect,Clear" bitfld.long 0x08 2. " HSTPULLDOWN[0] ,HST pull down for USB_DM clear" "No effect,Clear" bitfld.long 0x08 1. " DEBUG_INTERFACE_HOLD ,Debug interface hold clear" "No effect,Clear" textline " " bitfld.long 0x08 0. " OTGIDPIOLOCK ,OTG ID lock clear" "No effect,Clear" line.long 0x0C "HW_USBPHY2_DEBUG_TOG,USB PHY Debug Toggle Register" bitfld.long 0x0C 30. " CLKGATE ,Gate Test Clocks toggle" "No effect,Toggled" bitfld.long 0x0C 29. " HOST_RESUME_DEBUG ,Host resume debug toggle" "No effect,Toggled" bitfld.long 0x0C 25.--28. " SQUELCHRESETLENGTH ,Duration of REtoggle toggle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0C 24. " ENSQUELCHRESET ,Squelch high-speed receive retoggle toggle" "No effect,Toggled" bitfld.long 0x0C 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX toggle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 12. " ENTX2RXCOUNT ,Transition in between TX and RX toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x0C 5. " ENHSTPULLDOWN[1] ,ENHST pull down for USB_DP control override toggle" "No effect,Toggled" bitfld.long 0x0C 4. " ENHSTPULLDOWN[0] ,ENHST pull down for USB_DM control override toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 3. " HSTPULLDOWN[1] ,HST pull down for USB_DP toggle" "No effect,Toggled" bitfld.long 0x0C 2. " HSTPULLDOWN[0] ,HST pull down for USB_DM toggle" "No effect,Toggled" bitfld.long 0x0C 1. " DEBUG_INTERFACE_HOLD ,Debug interface hold toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 0. " OTGIDPIOLOCK ,OTG ID lock toggle" "No effect,Toggled" rgroup.long 0x60++0x03 line.long 0x00 "HW_USBPHY2_DEBUG0_STATUS,UTMI Debug Status Register 0" bitfld.long 0x00 26.--31. " SQUELCH_COUNT ,Running count of the squelch reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. " UTMI_RXERROR_FAIL_COUNT ,UTMI_RXERROR running count" hexmask.long.word 0x00 0.--15. 1. " LOOP_BACK_FAIL_COUNT ,Failed pseudo-random generator loopback running count" group.long 0x70++0x0F line.long 0x00 "HW_USBPHY2_DEBUG1,UTMI Debug Status Register 1" bitfld.long 0x00 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x04 "HW_USBPHY2_DEBUG1_SET,UTMI Debug Set Register 1" bitfld.long 0x04 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x08 "HW_USBPHY2_DEBUG1_CLR,UTMI Debug Clear Register 1" bitfld.long 0x08 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x0C "HW_USBPHY2_DEBUG1_TOG,UTMI Debug Toggle Register 1" bitfld.long 0x0C 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" rgroup.long 0x80++0x03 line.long 0x00 "HW_USBPHY2_VERSION,UTMI RTL Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Stepping of the RTL version" width 0x0B tree.end tree "Analog 1 (USB1 Analog)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020C81A0 else base ad:0x420C81A0 endif width 18. group.long 0x00++0x1F line.long 0x00 "VBUS_DETECT,USB VBUS Detect Register" bitfld.long 0x00 27. " CHARGE_VBUS ,USB OTG charge VBUS" "Not detected,Detected" bitfld.long 0x00 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS" "Not detected,Detected" textline " " bitfld.long 0x00 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector" "Not detected,Detected" bitfld.long 0x00 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x04 "VBUS_DETECT_SET,USB VBUS Detect Set Register" bitfld.long 0x04 27. " CHARGE_VBUS ,USB OTG charge VBUS set" "No effect,Set" bitfld.long 0x04 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS set" "No effect,Set" textline " " bitfld.long 0x04 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector set" "No effect,Set" bitfld.long 0x04 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x08 "VBUS_DETECT_CLR,USB VBUS Detect Clear Register" bitfld.long 0x08 27. " CHARGE_VBUS ,USB OTG charge VBUS clear" "No effect,Clear" bitfld.long 0x08 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS clear" "No effect,Clear" textline " " bitfld.long 0x08 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector clear" "No effect,Clear" bitfld.long 0x08 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x0C "VBUS_DETECT_TOG,USB VBUS Detect Toggle Register" bitfld.long 0x0C 27. " CHARGE_VBUS ,USB OTG charge VBUS toggle" "No effect,Toggled" bitfld.long 0x0C 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector toggle" "No effect,Toggled" bitfld.long 0x0C 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x10 "CHRG_DETECT,USB Charger Detect Register" bitfld.long 0x10 20. " EN_B ,Control the charger detector" "Enabled,Disabled" bitfld.long 0x10 19. " CHK_CHRG_B ,Check charger connection to USB port" "Check,No check" bitfld.long 0x10 18. " CHK_CONTACT ,Contact of USB plug" "No check,Check" line.long 0x14 "CHRG_DETECT_SET,USB Charger Detect Set Register" bitfld.long 0x14 20. " EN_B ,Control the charger detector set" "No effect,Set" bitfld.long 0x14 19. " CHK_CHRG_B ,Check charger connection to USB port set" "No effect,Set" bitfld.long 0x14 18. " CHK_CONTACT ,Contact of USB plug set" "No effect,Set" line.long 0x18 "CHRG_DETECT_CLR,USB Charger Detect Clear Register" bitfld.long 0x18 20. " EN_B ,Control the charger detector clear" "No effect,Clear" bitfld.long 0x18 19. " CHK_CHRG_B ,Check charger connection to USB port clear" "No effect,Clear" bitfld.long 0x18 18. " CHK_CONTACT ,Contact of USB plug clear" "No effect,Clear" line.long 0x1C "CHRG_DETECT_TOG,USB Charger Detect Toggle Register" bitfld.long 0x1C 20. " EN_B ,Control the charger detector toggle" "No effect,Toggled" bitfld.long 0x1C 19. " CHK_CHRG_B ,Check charger connection to USB port toggle" "No effect,Toggled" bitfld.long 0x1C 18. " CHK_CONTACT ,Contact of USB plug toggle" "No effect,Toggled" rgroup.long 0x20++0x03 line.long 0x00 "VBUS_DETECT_STAT,USB VBUS Detect Status Register" bitfld.long 0x00 3. " VBUS_VALID ,VBus valid for USB OTG" "Not valid,Valid" bitfld.long 0x00 2. " AVALID ,VBus valid for A-peripheral" "Not valid,Valid" bitfld.long 0x00 1. " BVALID ,VBus valid for B-peripheral" "Not valid,Valid" textline " " bitfld.long 0x00 0. " SESSEND ,Session end for USB OTG" "Not end,End" rgroup.long 0x30++0x03 line.long 0x00 "CHRG_DETECT_STAT,USB Charger Detect Status Register" bitfld.long 0x00 3. " DP_STATE ,DP line state output of the charger detector" "Not detected,Detected" bitfld.long 0x00 2. " DM_STATE ,DM line state output of the charger detector" "Not detected,Detected" bitfld.long 0x00 1. " CHRG_DETECTED ,State of charger detection" "Not connected,Connected" textline " " bitfld.long 0x00 0. " PLUG_CONTACT ,State of the USB plug contact detector" "Not contact,Good contact" group.long 0x50++0x0F line.long 0x00 "MISC,USB Misc Register" bitfld.long 0x00 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block" "Disabled,Enabled" bitfld.long 0x00 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output" "Disabled,Enabled" bitfld.long 0x00 0. " HS_USE_EXTERNAL_R ,External resistor to generate the current bias for the high speed transmitter" "Not used,Used" line.long 0x04 "MISC_SET,USB Misc Set Register" bitfld.long 0x04 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block set" "No effect,Set" bitfld.long 0x04 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output set" "No effect,Set" bitfld.long 0x04 0. " HS_USE_EXTERNAL_R ,External resistor to generate the current bias for the high speed transmitter set" "No effect,Set" line.long 0x08 "MISC_CLEAR,USB Misc Clear Register" bitfld.long 0x08 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block clear" "No effect,Clear" bitfld.long 0x08 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output clear" "No effect,Clear" bitfld.long 0x08 0. " HS_USE_EXTERNAL_R ,External resistor to generate the current bias for the high speed transmitter clear" "No effect,Clear" line.long 0x0C "MISC_TOG,USB Misc Toggle Register" bitfld.long 0x0C 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block toggle" "No effect,Toggled" bitfld.long 0x0C 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output toggle" "No effect,Toggled" bitfld.long 0x0C 0. " HS_USE_EXTERNAL_R ,External resistor to generate the current bias for the high speed transmitter toggle" "No effect,Toggled" width 0x0B tree.end tree "Analog 2 (USB2 Analog)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020C8200 else base ad:0x420C8200 endif width 18. group.long 0x00++0x1F line.long 0x00 "VBUS_DETECT,USB VBUS Detect Register" bitfld.long 0x00 27. " CHARGE_VBUS ,USB OTG charge VBUS" "Not detected,Detected" bitfld.long 0x00 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS" "Not detected,Detected" textline " " bitfld.long 0x00 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector" "Not detected,Detected" bitfld.long 0x00 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x04 "VBUS_DETECT_SET,USB VBUS Detect Set Register" bitfld.long 0x04 27. " CHARGE_VBUS ,USB OTG charge VBUS set" "No effect,Set" bitfld.long 0x04 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS set" "No effect,Set" textline " " bitfld.long 0x04 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector set" "No effect,Set" bitfld.long 0x04 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x08 "VBUS_DETECT_CLR,USB VBUS Detect Clear Register" bitfld.long 0x08 27. " CHARGE_VBUS ,USB OTG charge VBUS clear" "No effect,Clear" bitfld.long 0x08 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS clear" "No effect,Clear" textline " " bitfld.long 0x08 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector clear" "No effect,Clear" bitfld.long 0x08 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x0C "VBUS_DETECT_TOG,USB VBUS Detect Toggle Register" bitfld.long 0x0C 27. " CHARGE_VBUS ,USB OTG charge VBUS toggle" "No effect,Toggled" bitfld.long 0x0C 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS toggle" "No effect,Toggled" textline " " bitfld.long 0x0C 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector toggle" "No effect,Toggled" bitfld.long 0x0C 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x10 "CHRG_DETECT,USB Charger Detect Register" bitfld.long 0x10 20. " EN_B ,Control the charger detector" "Enabled,Disabled" bitfld.long 0x10 19. " CHK_CHRG_B ,Check charger connection to USB port" "Check,No check" bitfld.long 0x10 18. " CHK_CONTACT ,Contact of USB plug" "No check,Check" line.long 0x14 "CHRG_DETECT_SET,USB Charger Detect Set Register" bitfld.long 0x14 20. " EN_B ,Control the charger detector set" "No effect,Set" bitfld.long 0x14 19. " CHK_CHRG_B ,Check charger connection to USB port set" "No effect,Set" bitfld.long 0x14 18. " CHK_CONTACT ,Contact of USB plug set" "No effect,Set" line.long 0x18 "CHRG_DETECT_CLR,USB Charger Detect Clear Register" bitfld.long 0x18 20. " EN_B ,Control the charger detector clear" "No effect,Clear" bitfld.long 0x18 19. " CHK_CHRG_B ,Check charger connection to USB port clear" "No effect,Clear" bitfld.long 0x18 18. " CHK_CONTACT ,Contact of USB plug clear" "No effect,Clear" line.long 0x1C "CHRG_DETECT_TOG,USB Charger Detect Toggle Register" bitfld.long 0x1C 20. " EN_B ,Control the charger detector toggle" "No effect,Toggled" bitfld.long 0x1C 19. " CHK_CHRG_B ,Check charger connection to USB port toggle" "No effect,Toggled" bitfld.long 0x1C 18. " CHK_CONTACT ,Contact of USB plug toggle" "No effect,Toggled" rgroup.long 0x20++0x03 line.long 0x00 "VBUS_DETECT_STAT,USB VBUS Detect Status Register" bitfld.long 0x00 3. " VBUS_VALID ,VBus valid for USB OTG" "Not valid,Valid" bitfld.long 0x00 2. " AVALID ,VBus valid for A-peripheral" "Not valid,Valid" bitfld.long 0x00 1. " BVALID ,VBus valid for B-peripheral" "Not valid,Valid" textline " " bitfld.long 0x00 0. " SESSEND ,Session end for USB OTG" "Not end,End" rgroup.long 0x30++0x03 line.long 0x00 "CHRG_DETECT_STAT,USB Charger Detect Status Register" bitfld.long 0x00 3. " DP_STATE ,DP line state output of the charger detector" "Not detected,Detected" bitfld.long 0x00 2. " DM_STATE ,DM line state output of the charger detector" "Not detected,Detected" bitfld.long 0x00 1. " CHRG_DETECTED ,State of charger detection" "Not connected,Connected" textline " " bitfld.long 0x00 0. " PLUG_CONTACT ,State of the USB plug contact detector" "Not contact,Good contact" group.long 0x50++0x0F line.long 0x00 "MISC,USB Misc Register" bitfld.long 0x00 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block" "Disabled,Enabled" bitfld.long 0x00 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output" "Disabled,Enabled" bitfld.long 0x00 0. " HS_USE_EXTERNAL_R ,External resistor to generate the current bias for the high speed transmitter" "Not used,Used" line.long 0x04 "MISC_SET,USB Misc Set Register" bitfld.long 0x04 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block set" "No effect,Set" bitfld.long 0x04 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output set" "No effect,Set" bitfld.long 0x04 0. " HS_USE_EXTERNAL_R ,External resistor to generate the current bias for the high speed transmitter set" "No effect,Set" line.long 0x08 "MISC_CLEAR,USB Misc Clear Register" bitfld.long 0x08 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block clear" "No effect,Clear" bitfld.long 0x08 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output clear" "No effect,Clear" bitfld.long 0x08 0. " HS_USE_EXTERNAL_R ,External resistor to generate the current bias for the high speed transmitter clear" "No effect,Clear" line.long 0x0C "MISC_TOG,USB Misc Toggle Register" bitfld.long 0x0C 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block toggle" "No effect,Toggled" bitfld.long 0x0C 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output toggle" "No effect,Toggled" bitfld.long 0x0C 0. " HS_USE_EXTERNAL_R ,External resistor to generate the current bias for the high speed transmitter toggle" "No effect,Toggled" sif (cpu()=="IMX6SOLOLITE") rgroup.long 0x60++0x03 "Version Register" line.long 0x00 "DIGPROG,Chip Silicon Version Register" hexmask.long.byte 0x00 16.--23. 1. " MAJOR_UPPER ,MAJOR field of the RTL version" hexmask.long.byte 0x00 8.--15. 1. " MAJOR_LOWER ,MAJOR field of the RTL version" hexmask.long.byte 0x00 0.--7. 1. " MINOR ,MINOR field of the RTL version" else rgroup.long 0x60++0x03 "Version Register" line.long 0x00 "DIGPROG,Chip Silicon Version Register" hexmask.long.word 0x00 8.--23. 1. " MAJOR ,MAJOR field of the RTL version" hexmask.long.byte 0x00 0.--7. 1. " MINOR ,MINOR field of the RTL version" endif width 0x0B tree.end tree.end tree.open "USDHC (Ultra Secured Digital Host Controller)" tree "USDHC1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02190000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " DS_ADDR[31:2] ,DMA System Address" line.long 0x04 "BLKATT,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "CMDXFRTYP,Command Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX[5:0] ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP[1:0] ,Command Type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present" textline " " bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No response,Length 136,Length 48,Length 48/busy check" rgroup.long 0x10++0x0F line.long 0x0 "CMDRSP0,Command Response Register 0" line.long 0x4 "CMDRSP1,Command Response Register 1" line.long 0x8 "CMDRSP2,Command Response Register 2" line.long 0xC "CMDRSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "BUFFACCPORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7:0] Line 7 Signal Level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT[7:0] Line 6 Signal Level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT[7:0] Line 5 Signal Level" "Low,High" textline " " bitfld.long 0x00 28. " DLSL[4] ,DAT[7:0] Line 4 Signal Level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT[7:0] Line 3 Signal Level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT[7:0] Line 2 Signal Level" "Low,High" textline " " bitfld.long 0x00 25. " DLSL[1] ,DAT[7:0] Line 1 Signal Level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT[7:0] Line 0 Signal Level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Low,High" textline " " bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card Inserted" "Reset/Not inserted,Inserted" textline " " bitfld.long 0x00 12. " RTR ,Re-Tuning Request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RTA ,Read Transfer Active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write Transfer Active" "Inactive,Active" bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active" bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Not inhibited,Inhibited" textline " " bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Not inhibited,Inhibited" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" textline " " bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" textline " " bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restarted" textline " " bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA Select" "Not selected,ADMA1,ADMA2," bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Normal,Test" textline " " bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian," bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "No,Yes" textline " " bitfld.long 0x00 1.--2. " DTW[1:0] ,Data Transfer Width" "1-bit,4-bit,8-bit," bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 28. " RSTT ,Reset Tuning" "No reset,Reset" bitfld.long 0x04 27. " INITA ,Initialization Active" "Inactive,Active" bitfld.long 0x04 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset" textline " " bitfld.long 0x04 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset" bitfld.long 0x04 24. " RSTA ,Software Reset For ALL" "No reset,Reset" bitfld.long 0x04 23. " IPP_RST_N ,Value Output to CARD for hardware reset" "0,1" textline " " bitfld.long 0x04 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select" bitfld.long 0x04 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA Error" "No error,Error" eventfld.long 0x08 26. " TNE ,Tuning Error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 Error" "No error,Error" textline " " eventfld.long 0x08 22. " DEBE ,Data End Bit Error" "No error,Error" eventfld.long 0x08 21. " DCE ,Data CRC Error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data Timeout Error" "No error,Error" textline " " eventfld.long 0x08 19. " CIE ,Command Index Error" "No error,Error" eventfld.long 0x08 18. " CEBE ,Command End Bit Error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC Error" "No error,Error" textline " " eventfld.long 0x08 16. " CTOE ,Command Timeout Error" "No error,Error" eventfld.long 0x08 14. " TP ,Tuning Pass" "Not transferred,Transferred" eventfld.long 0x08 12. " RTE ,Re-Tuning Event" "Not requested,Requested" textline " " eventfld.long 0x08 8. " CINT ,Card Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card Removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card Insertion" "Not inserted,Inserted" textline " " eventfld.long 0x08 5. " BRR ,Buffer Read Ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer Write Ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 2. " BGE ,Block Gap Event" "No event,Stopped" eventfld.long 0x08 1. " TC ,Transfer Complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command Complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 26. " TNESEN ,Tuning Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 14. " TPSEN ,Tuning Pass Status Enable" "Masked,Enabled" bitfld.long 0x0C 12. " RTESEN ,Re-Tuning Event Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled" bitfld.long 0x0C 6. " CINSSEN ,Card Insertion Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 26. " TNEIEN ,Tuning Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 14. " TPIEN ,Tuning Pass Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 12. " RTEIEN ,Re-Tuning Event Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 8. " CINTIEN ,Card Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card Insertion Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled" textline "" if (((per.l(ad:0x02190000+0xCC))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample Clock Select" "Fixed,Tuned" bitfld.long 0x00 22. " EXECTUTE_TUNING ,Execute Tuning" "Not executed,Executed" textline " " rbitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" endif textline "" group.long 0x40++0x03 line.long 0x00 "HOSTCAPBLT,Host Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported" rbitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported" textline " " rbitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported" rbitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL[2:0] ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." textline " " rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3," bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use Tuning for SDR50" "No,Yes" textline " " bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time Counter for Retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" textline " " rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" textline "" group.long 0x44++0x07 line.long 0x00 "WML,Watermark Level Register" bitfld.long 0x00 24.--28. " WR_BRST_LEN[4:0] ,Write Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 16.--23. 1. " WR_WML[7:0] ,Write Watermark Level" textline " " bitfld.long 0x00 8.--12. " RD_BRST_LEN[4:0] ,Read Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 0.--7. 1. " RD_WML[7:0] ,Read Watermark Level" textline "" line.long 0x04 "MIXERCTRL,Mixer control Regiseter" bitfld.long 0x04 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x04 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x04 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" textline " " bitfld.long 0x04 22. " EXE_TUNE ,Execute Tuning" "Not executed,Executed" bitfld.long 0x04 7. " AC23EN ,Auto CMD23 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" textline " " bitfld.long 0x04 5. " MSBSEL ,Multi/Single Block Select" "Single,Multiple" bitfld.long 0x04 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read" bitfld.long 0x04 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " BCEN ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x04 0. " DMAEN ,DMA Enable" "Disabled,Enabled" textline "" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "Not forced,Forced" bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "Not forced,Forced" bitfld.long 0x00 26. " FEVTTNE ,Force Tuning Error" "Not forced,Forced" textline " " bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "Not forced,Forced" bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "Not forced,Forced" bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "Not forced,Forced" bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "Not forced,Forced" bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "Not forced,Forced" textline " " bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "Not forced,Forced" bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "Not forced,Forced" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "Not forced,Forced" textline " " bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "Not forced,Forced" bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "Not forced,Forced" bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "Not forced,Forced" bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "Not forced,Forced" textline "" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State " "Stop DMA,Fetch Descriptor,Change Address,Transfer Data" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR[31:0] ,ADMA System Address" group.long 0x60++0x03 line.long 0x00 "DLLCTRL,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT ,Slave delay line update interval" textline " " bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET ,Slave delay target" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Slave override value" textline " " bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatically,No update" textline " " bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET ,The delay target for the uSDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,DLL slave update" "No update,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLLSTS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if (((per.l(ad:0x02190000+0x48))&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline "" ;section group.long 0xC0++0x0F line.long 0x00 "VENDOR,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Controlled by hardware,Active" textline " " bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending Abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of Dat3 pin when its used as card detection" "High,Low" textline " " bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage Selection (around: 3.0V,1.8V)" "High,Low" bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled" line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" textline " " bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ack mode select" "No ACK,ACK" bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACKTimeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VENDOR2,Vendor Specific 2 Register" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the the Card interrupt status bit" "No,Yes" bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0]," bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" textline " " bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Drive CMD_OE/DAT_OE for one more clock cycle after the end bit" "Yes,No" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for Ncr changes/Ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0c 24. " STD_TUN_EN ,Standard tuning circuit and procedure" "Disabled,Enabled" bitfld.long 0x0c 20.--22. " TUN_WIND ,Data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--18. " TUN_STEP ,The increasing delay cell step in tuning procedure" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,Tuning procedure counter value" textline " " hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 11. else base ad:0x42190000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " DS_ADDR[31:2] ,DMA System Address" line.long 0x04 "BLKATT,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "CMDXFRTYP,Command Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX[5:0] ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP[1:0] ,Command Type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present" textline " " bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No response,Length 136,Length 48,Length 48/busy check" rgroup.long 0x10++0x0F line.long 0x0 "CMDRSP0,Command Response Register 0" line.long 0x4 "CMDRSP1,Command Response Register 1" line.long 0x8 "CMDRSP2,Command Response Register 2" line.long 0xC "CMDRSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "BUFFACCPORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7:0] Line 7 Signal Level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT[7:0] Line 6 Signal Level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT[7:0] Line 5 Signal Level" "Low,High" textline " " bitfld.long 0x00 28. " DLSL[4] ,DAT[7:0] Line 4 Signal Level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT[7:0] Line 3 Signal Level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT[7:0] Line 2 Signal Level" "Low,High" textline " " bitfld.long 0x00 25. " DLSL[1] ,DAT[7:0] Line 1 Signal Level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT[7:0] Line 0 Signal Level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Low,High" textline " " bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card Inserted" "Reset/Not inserted,Inserted" textline " " bitfld.long 0x00 12. " RTR ,Re-Tuning Request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RTA ,Read Transfer Active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write Transfer Active" "Inactive,Active" bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active" bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Not inhibited,Inhibited" textline " " bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Not inhibited,Inhibited" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" textline " " bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" textline " " bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restarted" textline " " bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA Select" "Not selected,ADMA1,ADMA2," bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Normal,Test" textline " " bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian," bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "No,Yes" textline " " bitfld.long 0x00 1.--2. " DTW[1:0] ,Data Transfer Width" "1-bit,4-bit,8-bit," bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 28. " RSTT ,Reset Tuning" "No reset,Reset" bitfld.long 0x04 27. " INITA ,Initialization Active" "Inactive,Active" bitfld.long 0x04 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset" textline " " bitfld.long 0x04 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset" bitfld.long 0x04 24. " RSTA ,Software Reset For ALL" "No reset,Reset" bitfld.long 0x04 23. " IPP_RST_N ,Value Output to CARD for hardware reset" "0,1" textline " " bitfld.long 0x04 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select" bitfld.long 0x04 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA Error" "No error,Error" eventfld.long 0x08 26. " TNE ,Tuning Error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 Error" "No error,Error" textline " " eventfld.long 0x08 22. " DEBE ,Data End Bit Error" "No error,Error" eventfld.long 0x08 21. " DCE ,Data CRC Error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data Timeout Error" "No error,Error" textline " " eventfld.long 0x08 19. " CIE ,Command Index Error" "No error,Error" eventfld.long 0x08 18. " CEBE ,Command End Bit Error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC Error" "No error,Error" textline " " eventfld.long 0x08 16. " CTOE ,Command Timeout Error" "No error,Error" eventfld.long 0x08 14. " TP ,Tuning Pass" "Not transferred,Transferred" eventfld.long 0x08 12. " RTE ,Re-Tuning Event" "Not requested,Requested" textline " " eventfld.long 0x08 8. " CINT ,Card Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card Removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card Insertion" "Not inserted,Inserted" textline " " eventfld.long 0x08 5. " BRR ,Buffer Read Ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer Write Ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 2. " BGE ,Block Gap Event" "No event,Stopped" eventfld.long 0x08 1. " TC ,Transfer Complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command Complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 26. " TNESEN ,Tuning Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 14. " TPSEN ,Tuning Pass Status Enable" "Masked,Enabled" bitfld.long 0x0C 12. " RTESEN ,Re-Tuning Event Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled" bitfld.long 0x0C 6. " CINSSEN ,Card Insertion Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 26. " TNEIEN ,Tuning Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 14. " TPIEN ,Tuning Pass Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 12. " RTEIEN ,Re-Tuning Event Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 8. " CINTIEN ,Card Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card Insertion Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled" textline "" if (((per.l(ad:0x42190000+0xCC))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample Clock Select" "Fixed,Tuned" bitfld.long 0x00 22. " EXECTUTE_TUNING ,Execute Tuning" "Not executed,Executed" textline " " rbitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" endif textline "" group.long 0x40++0x03 line.long 0x00 "HOSTCAPBLT,Host Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported" rbitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported" textline " " rbitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported" rbitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL[2:0] ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." textline " " rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3," bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use Tuning for SDR50" "No,Yes" textline " " bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time Counter for Retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" textline " " rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" textline "" group.long 0x44++0x07 line.long 0x00 "WML,Watermark Level Register" bitfld.long 0x00 24.--28. " WR_BRST_LEN[4:0] ,Write Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 16.--23. 1. " WR_WML[7:0] ,Write Watermark Level" textline " " bitfld.long 0x00 8.--12. " RD_BRST_LEN[4:0] ,Read Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 0.--7. 1. " RD_WML[7:0] ,Read Watermark Level" textline "" line.long 0x04 "MIXERCTRL,Mixer control Regiseter" bitfld.long 0x04 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x04 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x04 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" textline " " bitfld.long 0x04 22. " EXE_TUNE ,Execute Tuning" "Not executed,Executed" bitfld.long 0x04 7. " AC23EN ,Auto CMD23 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" textline " " bitfld.long 0x04 5. " MSBSEL ,Multi/Single Block Select" "Single,Multiple" bitfld.long 0x04 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read" bitfld.long 0x04 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " BCEN ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x04 0. " DMAEN ,DMA Enable" "Disabled,Enabled" textline "" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "Not forced,Forced" bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "Not forced,Forced" bitfld.long 0x00 26. " FEVTTNE ,Force Tuning Error" "Not forced,Forced" textline " " bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "Not forced,Forced" bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "Not forced,Forced" bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "Not forced,Forced" bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "Not forced,Forced" bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "Not forced,Forced" textline " " bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "Not forced,Forced" bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "Not forced,Forced" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "Not forced,Forced" textline " " bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "Not forced,Forced" bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "Not forced,Forced" bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "Not forced,Forced" bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "Not forced,Forced" textline "" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State " "Stop DMA,Fetch Descriptor,Change Address,Transfer Data" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR[31:0] ,ADMA System Address" group.long 0x60++0x03 line.long 0x00 "DLLCTRL,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT ,Slave delay line update interval" textline " " bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET ,Slave delay target" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Slave override value" textline " " bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatically,No update" textline " " bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET ,The delay target for the uSDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,DLL slave update" "No update,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLLSTS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if (((per.l(ad:0x42190000+0x48))&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline "" ;section group.long 0xC0++0x0F line.long 0x00 "VENDOR,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Controlled by hardware,Active" textline " " bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending Abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of Dat3 pin when its used as card detection" "High,Low" textline " " bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage Selection (around: 3.0V,1.8V)" "High,Low" bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled" line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" textline " " bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ack mode select" "No ACK,ACK" bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACKTimeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VENDOR2,Vendor Specific 2 Register" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the the Card interrupt status bit" "No,Yes" bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0]," bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" textline " " bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Drive CMD_OE/DAT_OE for one more clock cycle after the end bit" "Yes,No" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for Ncr changes/Ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0c 24. " STD_TUN_EN ,Standard tuning circuit and procedure" "Disabled,Enabled" bitfld.long 0x0c 20.--22. " TUN_WIND ,Data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--18. " TUN_STEP ,The increasing delay cell step in tuning procedure" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,Tuning procedure counter value" textline " " hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 11. endif tree.end tree "USDHC2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02194000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " DS_ADDR[31:2] ,DMA System Address" line.long 0x04 "BLKATT,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "CMDXFRTYP,Command Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX[5:0] ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP[1:0] ,Command Type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present" textline " " bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No response,Length 136,Length 48,Length 48/busy check" rgroup.long 0x10++0x0F line.long 0x0 "CMDRSP0,Command Response Register 0" line.long 0x4 "CMDRSP1,Command Response Register 1" line.long 0x8 "CMDRSP2,Command Response Register 2" line.long 0xC "CMDRSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "BUFFACCPORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7:0] Line 7 Signal Level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT[7:0] Line 6 Signal Level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT[7:0] Line 5 Signal Level" "Low,High" textline " " bitfld.long 0x00 28. " DLSL[4] ,DAT[7:0] Line 4 Signal Level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT[7:0] Line 3 Signal Level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT[7:0] Line 2 Signal Level" "Low,High" textline " " bitfld.long 0x00 25. " DLSL[1] ,DAT[7:0] Line 1 Signal Level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT[7:0] Line 0 Signal Level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Low,High" textline " " bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card Inserted" "Reset/Not inserted,Inserted" textline " " bitfld.long 0x00 12. " RTR ,Re-Tuning Request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RTA ,Read Transfer Active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write Transfer Active" "Inactive,Active" bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active" bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Not inhibited,Inhibited" textline " " bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Not inhibited,Inhibited" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" textline " " bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" textline " " bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restarted" textline " " bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA Select" "Not selected,ADMA1,ADMA2," bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Normal,Test" textline " " bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian," bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "No,Yes" textline " " bitfld.long 0x00 1.--2. " DTW[1:0] ,Data Transfer Width" "1-bit,4-bit,8-bit," bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 28. " RSTT ,Reset Tuning" "No reset,Reset" bitfld.long 0x04 27. " INITA ,Initialization Active" "Inactive,Active" bitfld.long 0x04 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset" textline " " bitfld.long 0x04 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset" bitfld.long 0x04 24. " RSTA ,Software Reset For ALL" "No reset,Reset" bitfld.long 0x04 23. " IPP_RST_N ,Value Output to CARD for hardware reset" "0,1" textline " " bitfld.long 0x04 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select" bitfld.long 0x04 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA Error" "No error,Error" eventfld.long 0x08 26. " TNE ,Tuning Error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 Error" "No error,Error" textline " " eventfld.long 0x08 22. " DEBE ,Data End Bit Error" "No error,Error" eventfld.long 0x08 21. " DCE ,Data CRC Error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data Timeout Error" "No error,Error" textline " " eventfld.long 0x08 19. " CIE ,Command Index Error" "No error,Error" eventfld.long 0x08 18. " CEBE ,Command End Bit Error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC Error" "No error,Error" textline " " eventfld.long 0x08 16. " CTOE ,Command Timeout Error" "No error,Error" eventfld.long 0x08 14. " TP ,Tuning Pass" "Not transferred,Transferred" eventfld.long 0x08 12. " RTE ,Re-Tuning Event" "Not requested,Requested" textline " " eventfld.long 0x08 8. " CINT ,Card Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card Removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card Insertion" "Not inserted,Inserted" textline " " eventfld.long 0x08 5. " BRR ,Buffer Read Ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer Write Ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 2. " BGE ,Block Gap Event" "No event,Stopped" eventfld.long 0x08 1. " TC ,Transfer Complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command Complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 26. " TNESEN ,Tuning Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 14. " TPSEN ,Tuning Pass Status Enable" "Masked,Enabled" bitfld.long 0x0C 12. " RTESEN ,Re-Tuning Event Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled" bitfld.long 0x0C 6. " CINSSEN ,Card Insertion Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 26. " TNEIEN ,Tuning Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 14. " TPIEN ,Tuning Pass Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 12. " RTEIEN ,Re-Tuning Event Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 8. " CINTIEN ,Card Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card Insertion Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled" textline "" if (((per.l(ad:0x02194000+0xCC))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample Clock Select" "Fixed,Tuned" bitfld.long 0x00 22. " EXECTUTE_TUNING ,Execute Tuning" "Not executed,Executed" textline " " rbitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" endif textline "" group.long 0x40++0x03 line.long 0x00 "HOSTCAPBLT,Host Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported" rbitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported" textline " " rbitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported" rbitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL[2:0] ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." textline " " rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3," bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use Tuning for SDR50" "No,Yes" textline " " bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time Counter for Retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" textline " " rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" textline "" group.long 0x44++0x07 line.long 0x00 "WML,Watermark Level Register" bitfld.long 0x00 24.--28. " WR_BRST_LEN[4:0] ,Write Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 16.--23. 1. " WR_WML[7:0] ,Write Watermark Level" textline " " bitfld.long 0x00 8.--12. " RD_BRST_LEN[4:0] ,Read Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 0.--7. 1. " RD_WML[7:0] ,Read Watermark Level" textline "" line.long 0x04 "MIXERCTRL,Mixer control Regiseter" bitfld.long 0x04 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x04 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x04 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" textline " " bitfld.long 0x04 22. " EXE_TUNE ,Execute Tuning" "Not executed,Executed" bitfld.long 0x04 7. " AC23EN ,Auto CMD23 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" textline " " bitfld.long 0x04 5. " MSBSEL ,Multi/Single Block Select" "Single,Multiple" bitfld.long 0x04 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read" bitfld.long 0x04 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " BCEN ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x04 0. " DMAEN ,DMA Enable" "Disabled,Enabled" textline "" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "Not forced,Forced" bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "Not forced,Forced" bitfld.long 0x00 26. " FEVTTNE ,Force Tuning Error" "Not forced,Forced" textline " " bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "Not forced,Forced" bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "Not forced,Forced" bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "Not forced,Forced" bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "Not forced,Forced" bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "Not forced,Forced" textline " " bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "Not forced,Forced" bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "Not forced,Forced" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "Not forced,Forced" textline " " bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "Not forced,Forced" bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "Not forced,Forced" bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "Not forced,Forced" bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "Not forced,Forced" textline "" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State " "Stop DMA,Fetch Descriptor,Change Address,Transfer Data" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR[31:0] ,ADMA System Address" group.long 0x60++0x03 line.long 0x00 "DLLCTRL,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT ,Slave delay line update interval" textline " " bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET ,Slave delay target" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Slave override value" textline " " bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatically,No update" textline " " bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET ,The delay target for the uSDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,DLL slave update" "No update,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLLSTS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if (((per.l(ad:0x02194000+0x48))&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline "" ;section group.long 0xC0++0x0F line.long 0x00 "VENDOR,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Controlled by hardware,Active" textline " " bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending Abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of Dat3 pin when its used as card detection" "High,Low" textline " " bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage Selection (around: 3.0V,1.8V)" "High,Low" bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled" line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" textline " " bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ack mode select" "No ACK,ACK" bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACKTimeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VENDOR2,Vendor Specific 2 Register" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the the Card interrupt status bit" "No,Yes" bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0]," bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" textline " " bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Drive CMD_OE/DAT_OE for one more clock cycle after the end bit" "Yes,No" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for Ncr changes/Ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0c 24. " STD_TUN_EN ,Standard tuning circuit and procedure" "Disabled,Enabled" bitfld.long 0x0c 20.--22. " TUN_WIND ,Data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--18. " TUN_STEP ,The increasing delay cell step in tuning procedure" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,Tuning procedure counter value" textline " " hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 11. else base ad:0x42194000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " DS_ADDR[31:2] ,DMA System Address" line.long 0x04 "BLKATT,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "CMDXFRTYP,Command Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX[5:0] ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP[1:0] ,Command Type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present" textline " " bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No response,Length 136,Length 48,Length 48/busy check" rgroup.long 0x10++0x0F line.long 0x0 "CMDRSP0,Command Response Register 0" line.long 0x4 "CMDRSP1,Command Response Register 1" line.long 0x8 "CMDRSP2,Command Response Register 2" line.long 0xC "CMDRSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "BUFFACCPORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7:0] Line 7 Signal Level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT[7:0] Line 6 Signal Level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT[7:0] Line 5 Signal Level" "Low,High" textline " " bitfld.long 0x00 28. " DLSL[4] ,DAT[7:0] Line 4 Signal Level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT[7:0] Line 3 Signal Level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT[7:0] Line 2 Signal Level" "Low,High" textline " " bitfld.long 0x00 25. " DLSL[1] ,DAT[7:0] Line 1 Signal Level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT[7:0] Line 0 Signal Level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Low,High" textline " " bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card Inserted" "Reset/Not inserted,Inserted" textline " " bitfld.long 0x00 12. " RTR ,Re-Tuning Request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RTA ,Read Transfer Active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write Transfer Active" "Inactive,Active" bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active" bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Not inhibited,Inhibited" textline " " bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Not inhibited,Inhibited" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" textline " " bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" textline " " bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restarted" textline " " bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA Select" "Not selected,ADMA1,ADMA2," bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Normal,Test" textline " " bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian," bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "No,Yes" textline " " bitfld.long 0x00 1.--2. " DTW[1:0] ,Data Transfer Width" "1-bit,4-bit,8-bit," bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 28. " RSTT ,Reset Tuning" "No reset,Reset" bitfld.long 0x04 27. " INITA ,Initialization Active" "Inactive,Active" bitfld.long 0x04 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset" textline " " bitfld.long 0x04 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset" bitfld.long 0x04 24. " RSTA ,Software Reset For ALL" "No reset,Reset" bitfld.long 0x04 23. " IPP_RST_N ,Value Output to CARD for hardware reset" "0,1" textline " " bitfld.long 0x04 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select" bitfld.long 0x04 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA Error" "No error,Error" eventfld.long 0x08 26. " TNE ,Tuning Error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 Error" "No error,Error" textline " " eventfld.long 0x08 22. " DEBE ,Data End Bit Error" "No error,Error" eventfld.long 0x08 21. " DCE ,Data CRC Error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data Timeout Error" "No error,Error" textline " " eventfld.long 0x08 19. " CIE ,Command Index Error" "No error,Error" eventfld.long 0x08 18. " CEBE ,Command End Bit Error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC Error" "No error,Error" textline " " eventfld.long 0x08 16. " CTOE ,Command Timeout Error" "No error,Error" eventfld.long 0x08 14. " TP ,Tuning Pass" "Not transferred,Transferred" eventfld.long 0x08 12. " RTE ,Re-Tuning Event" "Not requested,Requested" textline " " eventfld.long 0x08 8. " CINT ,Card Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card Removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card Insertion" "Not inserted,Inserted" textline " " eventfld.long 0x08 5. " BRR ,Buffer Read Ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer Write Ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 2. " BGE ,Block Gap Event" "No event,Stopped" eventfld.long 0x08 1. " TC ,Transfer Complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command Complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 26. " TNESEN ,Tuning Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 14. " TPSEN ,Tuning Pass Status Enable" "Masked,Enabled" bitfld.long 0x0C 12. " RTESEN ,Re-Tuning Event Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled" bitfld.long 0x0C 6. " CINSSEN ,Card Insertion Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 26. " TNEIEN ,Tuning Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 14. " TPIEN ,Tuning Pass Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 12. " RTEIEN ,Re-Tuning Event Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 8. " CINTIEN ,Card Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card Insertion Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled" textline "" if (((per.l(ad:0x42194000+0xCC))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample Clock Select" "Fixed,Tuned" bitfld.long 0x00 22. " EXECTUTE_TUNING ,Execute Tuning" "Not executed,Executed" textline " " rbitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" endif textline "" group.long 0x40++0x03 line.long 0x00 "HOSTCAPBLT,Host Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported" rbitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported" textline " " rbitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported" rbitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL[2:0] ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." textline " " rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3," bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use Tuning for SDR50" "No,Yes" textline " " bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time Counter for Retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" textline " " rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" textline "" group.long 0x44++0x07 line.long 0x00 "WML,Watermark Level Register" bitfld.long 0x00 24.--28. " WR_BRST_LEN[4:0] ,Write Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 16.--23. 1. " WR_WML[7:0] ,Write Watermark Level" textline " " bitfld.long 0x00 8.--12. " RD_BRST_LEN[4:0] ,Read Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 0.--7. 1. " RD_WML[7:0] ,Read Watermark Level" textline "" line.long 0x04 "MIXERCTRL,Mixer control Regiseter" bitfld.long 0x04 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x04 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x04 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" textline " " bitfld.long 0x04 22. " EXE_TUNE ,Execute Tuning" "Not executed,Executed" bitfld.long 0x04 7. " AC23EN ,Auto CMD23 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" textline " " bitfld.long 0x04 5. " MSBSEL ,Multi/Single Block Select" "Single,Multiple" bitfld.long 0x04 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read" bitfld.long 0x04 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " BCEN ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x04 0. " DMAEN ,DMA Enable" "Disabled,Enabled" textline "" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "Not forced,Forced" bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "Not forced,Forced" bitfld.long 0x00 26. " FEVTTNE ,Force Tuning Error" "Not forced,Forced" textline " " bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "Not forced,Forced" bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "Not forced,Forced" bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "Not forced,Forced" bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "Not forced,Forced" bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "Not forced,Forced" textline " " bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "Not forced,Forced" bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "Not forced,Forced" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "Not forced,Forced" textline " " bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "Not forced,Forced" bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "Not forced,Forced" bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "Not forced,Forced" bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "Not forced,Forced" textline "" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State " "Stop DMA,Fetch Descriptor,Change Address,Transfer Data" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR[31:0] ,ADMA System Address" group.long 0x60++0x03 line.long 0x00 "DLLCTRL,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT ,Slave delay line update interval" textline " " bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET ,Slave delay target" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Slave override value" textline " " bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatically,No update" textline " " bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET ,The delay target for the uSDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,DLL slave update" "No update,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLLSTS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if (((per.l(ad:0x42194000+0x48))&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline "" ;section group.long 0xC0++0x0F line.long 0x00 "VENDOR,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Controlled by hardware,Active" textline " " bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending Abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of Dat3 pin when its used as card detection" "High,Low" textline " " bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage Selection (around: 3.0V,1.8V)" "High,Low" bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled" line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" textline " " bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ack mode select" "No ACK,ACK" bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACKTimeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VENDOR2,Vendor Specific 2 Register" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the the Card interrupt status bit" "No,Yes" bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0]," bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" textline " " bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Drive CMD_OE/DAT_OE for one more clock cycle after the end bit" "Yes,No" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for Ncr changes/Ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0c 24. " STD_TUN_EN ,Standard tuning circuit and procedure" "Disabled,Enabled" bitfld.long 0x0c 20.--22. " TUN_WIND ,Data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--18. " TUN_STEP ,The increasing delay cell step in tuning procedure" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,Tuning procedure counter value" textline " " hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 11. endif tree.end tree "USDHC3" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02198000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " DS_ADDR[31:2] ,DMA System Address" line.long 0x04 "BLKATT,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "CMDXFRTYP,Command Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX[5:0] ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP[1:0] ,Command Type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present" textline " " bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No response,Length 136,Length 48,Length 48/busy check" rgroup.long 0x10++0x0F line.long 0x0 "CMDRSP0,Command Response Register 0" line.long 0x4 "CMDRSP1,Command Response Register 1" line.long 0x8 "CMDRSP2,Command Response Register 2" line.long 0xC "CMDRSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "BUFFACCPORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7:0] Line 7 Signal Level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT[7:0] Line 6 Signal Level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT[7:0] Line 5 Signal Level" "Low,High" textline " " bitfld.long 0x00 28. " DLSL[4] ,DAT[7:0] Line 4 Signal Level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT[7:0] Line 3 Signal Level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT[7:0] Line 2 Signal Level" "Low,High" textline " " bitfld.long 0x00 25. " DLSL[1] ,DAT[7:0] Line 1 Signal Level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT[7:0] Line 0 Signal Level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Low,High" textline " " bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card Inserted" "Reset/Not inserted,Inserted" textline " " bitfld.long 0x00 12. " RTR ,Re-Tuning Request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RTA ,Read Transfer Active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write Transfer Active" "Inactive,Active" bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active" bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Not inhibited,Inhibited" textline " " bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Not inhibited,Inhibited" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" textline " " bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" textline " " bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restarted" textline " " bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA Select" "Not selected,ADMA1,ADMA2," bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Normal,Test" textline " " bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian," bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "No,Yes" textline " " bitfld.long 0x00 1.--2. " DTW[1:0] ,Data Transfer Width" "1-bit,4-bit,8-bit," bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 28. " RSTT ,Reset Tuning" "No reset,Reset" bitfld.long 0x04 27. " INITA ,Initialization Active" "Inactive,Active" bitfld.long 0x04 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset" textline " " bitfld.long 0x04 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset" bitfld.long 0x04 24. " RSTA ,Software Reset For ALL" "No reset,Reset" bitfld.long 0x04 23. " IPP_RST_N ,Value Output to CARD for hardware reset" "0,1" textline " " bitfld.long 0x04 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select" bitfld.long 0x04 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA Error" "No error,Error" eventfld.long 0x08 26. " TNE ,Tuning Error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 Error" "No error,Error" textline " " eventfld.long 0x08 22. " DEBE ,Data End Bit Error" "No error,Error" eventfld.long 0x08 21. " DCE ,Data CRC Error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data Timeout Error" "No error,Error" textline " " eventfld.long 0x08 19. " CIE ,Command Index Error" "No error,Error" eventfld.long 0x08 18. " CEBE ,Command End Bit Error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC Error" "No error,Error" textline " " eventfld.long 0x08 16. " CTOE ,Command Timeout Error" "No error,Error" eventfld.long 0x08 14. " TP ,Tuning Pass" "Not transferred,Transferred" eventfld.long 0x08 12. " RTE ,Re-Tuning Event" "Not requested,Requested" textline " " eventfld.long 0x08 8. " CINT ,Card Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card Removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card Insertion" "Not inserted,Inserted" textline " " eventfld.long 0x08 5. " BRR ,Buffer Read Ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer Write Ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 2. " BGE ,Block Gap Event" "No event,Stopped" eventfld.long 0x08 1. " TC ,Transfer Complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command Complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 26. " TNESEN ,Tuning Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 14. " TPSEN ,Tuning Pass Status Enable" "Masked,Enabled" bitfld.long 0x0C 12. " RTESEN ,Re-Tuning Event Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled" bitfld.long 0x0C 6. " CINSSEN ,Card Insertion Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 26. " TNEIEN ,Tuning Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 14. " TPIEN ,Tuning Pass Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 12. " RTEIEN ,Re-Tuning Event Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 8. " CINTIEN ,Card Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card Insertion Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled" textline "" if (((per.l(ad:0x02198000+0xCC))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample Clock Select" "Fixed,Tuned" bitfld.long 0x00 22. " EXECTUTE_TUNING ,Execute Tuning" "Not executed,Executed" textline " " rbitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" endif textline "" group.long 0x40++0x03 line.long 0x00 "HOSTCAPBLT,Host Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported" rbitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported" textline " " rbitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported" rbitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL[2:0] ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." textline " " rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3," bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use Tuning for SDR50" "No,Yes" textline " " bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time Counter for Retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" textline " " rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" textline "" group.long 0x44++0x07 line.long 0x00 "WML,Watermark Level Register" bitfld.long 0x00 24.--28. " WR_BRST_LEN[4:0] ,Write Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 16.--23. 1. " WR_WML[7:0] ,Write Watermark Level" textline " " bitfld.long 0x00 8.--12. " RD_BRST_LEN[4:0] ,Read Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 0.--7. 1. " RD_WML[7:0] ,Read Watermark Level" textline "" line.long 0x04 "MIXERCTRL,Mixer control Regiseter" bitfld.long 0x04 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x04 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x04 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" textline " " bitfld.long 0x04 22. " EXE_TUNE ,Execute Tuning" "Not executed,Executed" bitfld.long 0x04 7. " AC23EN ,Auto CMD23 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" textline " " bitfld.long 0x04 5. " MSBSEL ,Multi/Single Block Select" "Single,Multiple" bitfld.long 0x04 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read" bitfld.long 0x04 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " BCEN ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x04 0. " DMAEN ,DMA Enable" "Disabled,Enabled" textline "" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "Not forced,Forced" bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "Not forced,Forced" bitfld.long 0x00 26. " FEVTTNE ,Force Tuning Error" "Not forced,Forced" textline " " bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "Not forced,Forced" bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "Not forced,Forced" bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "Not forced,Forced" bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "Not forced,Forced" bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "Not forced,Forced" textline " " bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "Not forced,Forced" bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "Not forced,Forced" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "Not forced,Forced" textline " " bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "Not forced,Forced" bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "Not forced,Forced" bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "Not forced,Forced" bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "Not forced,Forced" textline "" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State " "Stop DMA,Fetch Descriptor,Change Address,Transfer Data" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR[31:0] ,ADMA System Address" group.long 0x60++0x03 line.long 0x00 "DLLCTRL,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT ,Slave delay line update interval" textline " " bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET ,Slave delay target" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Slave override value" textline " " bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatically,No update" textline " " bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET ,The delay target for the uSDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,DLL slave update" "No update,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLLSTS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if (((per.l(ad:0x02198000+0x48))&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline "" ;section group.long 0xC0++0x0F line.long 0x00 "VENDOR,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Controlled by hardware,Active" textline " " bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending Abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of Dat3 pin when its used as card detection" "High,Low" textline " " bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage Selection (around: 3.0V,1.8V)" "High,Low" bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled" line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" textline " " bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ack mode select" "No ACK,ACK" bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACKTimeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VENDOR2,Vendor Specific 2 Register" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the the Card interrupt status bit" "No,Yes" bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0]," bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" textline " " bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Drive CMD_OE/DAT_OE for one more clock cycle after the end bit" "Yes,No" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for Ncr changes/Ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0c 24. " STD_TUN_EN ,Standard tuning circuit and procedure" "Disabled,Enabled" bitfld.long 0x0c 20.--22. " TUN_WIND ,Data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--18. " TUN_STEP ,The increasing delay cell step in tuning procedure" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,Tuning procedure counter value" textline " " hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 11. else base ad:0x42198000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " DS_ADDR[31:2] ,DMA System Address" line.long 0x04 "BLKATT,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "CMDXFRTYP,Command Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX[5:0] ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP[1:0] ,Command Type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present" textline " " bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No response,Length 136,Length 48,Length 48/busy check" rgroup.long 0x10++0x0F line.long 0x0 "CMDRSP0,Command Response Register 0" line.long 0x4 "CMDRSP1,Command Response Register 1" line.long 0x8 "CMDRSP2,Command Response Register 2" line.long 0xC "CMDRSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "BUFFACCPORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7:0] Line 7 Signal Level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT[7:0] Line 6 Signal Level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT[7:0] Line 5 Signal Level" "Low,High" textline " " bitfld.long 0x00 28. " DLSL[4] ,DAT[7:0] Line 4 Signal Level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT[7:0] Line 3 Signal Level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT[7:0] Line 2 Signal Level" "Low,High" textline " " bitfld.long 0x00 25. " DLSL[1] ,DAT[7:0] Line 1 Signal Level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT[7:0] Line 0 Signal Level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Low,High" textline " " bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card Inserted" "Reset/Not inserted,Inserted" textline " " bitfld.long 0x00 12. " RTR ,Re-Tuning Request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RTA ,Read Transfer Active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write Transfer Active" "Inactive,Active" bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active" bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Not inhibited,Inhibited" textline " " bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Not inhibited,Inhibited" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" textline " " bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" textline " " bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restarted" textline " " bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA Select" "Not selected,ADMA1,ADMA2," bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Normal,Test" textline " " bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian," bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "No,Yes" textline " " bitfld.long 0x00 1.--2. " DTW[1:0] ,Data Transfer Width" "1-bit,4-bit,8-bit," bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 28. " RSTT ,Reset Tuning" "No reset,Reset" bitfld.long 0x04 27. " INITA ,Initialization Active" "Inactive,Active" bitfld.long 0x04 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset" textline " " bitfld.long 0x04 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset" bitfld.long 0x04 24. " RSTA ,Software Reset For ALL" "No reset,Reset" bitfld.long 0x04 23. " IPP_RST_N ,Value Output to CARD for hardware reset" "0,1" textline " " bitfld.long 0x04 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select" bitfld.long 0x04 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA Error" "No error,Error" eventfld.long 0x08 26. " TNE ,Tuning Error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 Error" "No error,Error" textline " " eventfld.long 0x08 22. " DEBE ,Data End Bit Error" "No error,Error" eventfld.long 0x08 21. " DCE ,Data CRC Error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data Timeout Error" "No error,Error" textline " " eventfld.long 0x08 19. " CIE ,Command Index Error" "No error,Error" eventfld.long 0x08 18. " CEBE ,Command End Bit Error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC Error" "No error,Error" textline " " eventfld.long 0x08 16. " CTOE ,Command Timeout Error" "No error,Error" eventfld.long 0x08 14. " TP ,Tuning Pass" "Not transferred,Transferred" eventfld.long 0x08 12. " RTE ,Re-Tuning Event" "Not requested,Requested" textline " " eventfld.long 0x08 8. " CINT ,Card Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card Removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card Insertion" "Not inserted,Inserted" textline " " eventfld.long 0x08 5. " BRR ,Buffer Read Ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer Write Ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 2. " BGE ,Block Gap Event" "No event,Stopped" eventfld.long 0x08 1. " TC ,Transfer Complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command Complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 26. " TNESEN ,Tuning Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 14. " TPSEN ,Tuning Pass Status Enable" "Masked,Enabled" bitfld.long 0x0C 12. " RTESEN ,Re-Tuning Event Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled" bitfld.long 0x0C 6. " CINSSEN ,Card Insertion Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 26. " TNEIEN ,Tuning Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 14. " TPIEN ,Tuning Pass Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 12. " RTEIEN ,Re-Tuning Event Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 8. " CINTIEN ,Card Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card Insertion Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled" textline "" if (((per.l(ad:0x42198000+0xCC))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample Clock Select" "Fixed,Tuned" bitfld.long 0x00 22. " EXECTUTE_TUNING ,Execute Tuning" "Not executed,Executed" textline " " rbitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" endif textline "" group.long 0x40++0x03 line.long 0x00 "HOSTCAPBLT,Host Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported" rbitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported" textline " " rbitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported" rbitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL[2:0] ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." textline " " rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3," bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use Tuning for SDR50" "No,Yes" textline " " bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time Counter for Retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" textline " " rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" textline "" group.long 0x44++0x07 line.long 0x00 "WML,Watermark Level Register" bitfld.long 0x00 24.--28. " WR_BRST_LEN[4:0] ,Write Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 16.--23. 1. " WR_WML[7:0] ,Write Watermark Level" textline " " bitfld.long 0x00 8.--12. " RD_BRST_LEN[4:0] ,Read Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 0.--7. 1. " RD_WML[7:0] ,Read Watermark Level" textline "" line.long 0x04 "MIXERCTRL,Mixer control Regiseter" bitfld.long 0x04 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x04 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x04 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" textline " " bitfld.long 0x04 22. " EXE_TUNE ,Execute Tuning" "Not executed,Executed" bitfld.long 0x04 7. " AC23EN ,Auto CMD23 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" textline " " bitfld.long 0x04 5. " MSBSEL ,Multi/Single Block Select" "Single,Multiple" bitfld.long 0x04 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read" bitfld.long 0x04 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " BCEN ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x04 0. " DMAEN ,DMA Enable" "Disabled,Enabled" textline "" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "Not forced,Forced" bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "Not forced,Forced" bitfld.long 0x00 26. " FEVTTNE ,Force Tuning Error" "Not forced,Forced" textline " " bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "Not forced,Forced" bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "Not forced,Forced" bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "Not forced,Forced" bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "Not forced,Forced" bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "Not forced,Forced" textline " " bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "Not forced,Forced" bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "Not forced,Forced" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "Not forced,Forced" textline " " bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "Not forced,Forced" bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "Not forced,Forced" bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "Not forced,Forced" bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "Not forced,Forced" textline "" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State " "Stop DMA,Fetch Descriptor,Change Address,Transfer Data" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR[31:0] ,ADMA System Address" group.long 0x60++0x03 line.long 0x00 "DLLCTRL,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT ,Slave delay line update interval" textline " " bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET ,Slave delay target" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Slave override value" textline " " bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatically,No update" textline " " bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET ,The delay target for the uSDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,DLL slave update" "No update,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLLSTS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if (((per.l(ad:0x42198000+0x48))&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline "" ;section group.long 0xC0++0x0F line.long 0x00 "VENDOR,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Controlled by hardware,Active" textline " " bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending Abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of Dat3 pin when its used as card detection" "High,Low" textline " " bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage Selection (around: 3.0V,1.8V)" "High,Low" bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled" line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" textline " " bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ack mode select" "No ACK,ACK" bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACKTimeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VENDOR2,Vendor Specific 2 Register" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the the Card interrupt status bit" "No,Yes" bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0]," bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" textline " " bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Drive CMD_OE/DAT_OE for one more clock cycle after the end bit" "Yes,No" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for Ncr changes/Ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0c 24. " STD_TUN_EN ,Standard tuning circuit and procedure" "Disabled,Enabled" bitfld.long 0x0c 20.--22. " TUN_WIND ,Data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--18. " TUN_STEP ,The increasing delay cell step in tuning procedure" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,Tuning procedure counter value" textline " " hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 11. endif tree.end tree "USDHC4" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0219C000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " DS_ADDR[31:2] ,DMA System Address" line.long 0x04 "BLKATT,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "CMDXFRTYP,Command Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX[5:0] ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP[1:0] ,Command Type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present" textline " " bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No response,Length 136,Length 48,Length 48/busy check" rgroup.long 0x10++0x0F line.long 0x0 "CMDRSP0,Command Response Register 0" line.long 0x4 "CMDRSP1,Command Response Register 1" line.long 0x8 "CMDRSP2,Command Response Register 2" line.long 0xC "CMDRSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "BUFFACCPORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7:0] Line 7 Signal Level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT[7:0] Line 6 Signal Level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT[7:0] Line 5 Signal Level" "Low,High" textline " " bitfld.long 0x00 28. " DLSL[4] ,DAT[7:0] Line 4 Signal Level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT[7:0] Line 3 Signal Level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT[7:0] Line 2 Signal Level" "Low,High" textline " " bitfld.long 0x00 25. " DLSL[1] ,DAT[7:0] Line 1 Signal Level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT[7:0] Line 0 Signal Level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Low,High" textline " " bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card Inserted" "Reset/Not inserted,Inserted" textline " " bitfld.long 0x00 12. " RTR ,Re-Tuning Request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RTA ,Read Transfer Active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write Transfer Active" "Inactive,Active" bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active" bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Not inhibited,Inhibited" textline " " bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Not inhibited,Inhibited" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" textline " " bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" textline " " bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restarted" textline " " bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA Select" "Not selected,ADMA1,ADMA2," bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Normal,Test" textline " " bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian," bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "No,Yes" textline " " bitfld.long 0x00 1.--2. " DTW[1:0] ,Data Transfer Width" "1-bit,4-bit,8-bit," bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 28. " RSTT ,Reset Tuning" "No reset,Reset" bitfld.long 0x04 27. " INITA ,Initialization Active" "Inactive,Active" bitfld.long 0x04 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset" textline " " bitfld.long 0x04 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset" bitfld.long 0x04 24. " RSTA ,Software Reset For ALL" "No reset,Reset" bitfld.long 0x04 23. " IPP_RST_N ,Value Output to CARD for hardware reset" "0,1" textline " " bitfld.long 0x04 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select" bitfld.long 0x04 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA Error" "No error,Error" eventfld.long 0x08 26. " TNE ,Tuning Error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 Error" "No error,Error" textline " " eventfld.long 0x08 22. " DEBE ,Data End Bit Error" "No error,Error" eventfld.long 0x08 21. " DCE ,Data CRC Error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data Timeout Error" "No error,Error" textline " " eventfld.long 0x08 19. " CIE ,Command Index Error" "No error,Error" eventfld.long 0x08 18. " CEBE ,Command End Bit Error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC Error" "No error,Error" textline " " eventfld.long 0x08 16. " CTOE ,Command Timeout Error" "No error,Error" eventfld.long 0x08 14. " TP ,Tuning Pass" "Not transferred,Transferred" eventfld.long 0x08 12. " RTE ,Re-Tuning Event" "Not requested,Requested" textline " " eventfld.long 0x08 8. " CINT ,Card Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card Removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card Insertion" "Not inserted,Inserted" textline " " eventfld.long 0x08 5. " BRR ,Buffer Read Ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer Write Ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 2. " BGE ,Block Gap Event" "No event,Stopped" eventfld.long 0x08 1. " TC ,Transfer Complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command Complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 26. " TNESEN ,Tuning Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 14. " TPSEN ,Tuning Pass Status Enable" "Masked,Enabled" bitfld.long 0x0C 12. " RTESEN ,Re-Tuning Event Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled" bitfld.long 0x0C 6. " CINSSEN ,Card Insertion Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 26. " TNEIEN ,Tuning Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 14. " TPIEN ,Tuning Pass Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 12. " RTEIEN ,Re-Tuning Event Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 8. " CINTIEN ,Card Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card Insertion Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled" textline "" if (((per.l(ad:0x0219C000+0xCC))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample Clock Select" "Fixed,Tuned" bitfld.long 0x00 22. " EXECTUTE_TUNING ,Execute Tuning" "Not executed,Executed" textline " " rbitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" endif textline "" group.long 0x40++0x03 line.long 0x00 "HOSTCAPBLT,Host Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported" rbitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported" textline " " rbitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported" rbitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL[2:0] ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." textline " " rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3," bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use Tuning for SDR50" "No,Yes" textline " " bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time Counter for Retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" textline " " rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" textline "" group.long 0x44++0x07 line.long 0x00 "WML,Watermark Level Register" bitfld.long 0x00 24.--28. " WR_BRST_LEN[4:0] ,Write Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 16.--23. 1. " WR_WML[7:0] ,Write Watermark Level" textline " " bitfld.long 0x00 8.--12. " RD_BRST_LEN[4:0] ,Read Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 0.--7. 1. " RD_WML[7:0] ,Read Watermark Level" textline "" line.long 0x04 "MIXERCTRL,Mixer control Regiseter" bitfld.long 0x04 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x04 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x04 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" textline " " bitfld.long 0x04 22. " EXE_TUNE ,Execute Tuning" "Not executed,Executed" bitfld.long 0x04 7. " AC23EN ,Auto CMD23 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" textline " " bitfld.long 0x04 5. " MSBSEL ,Multi/Single Block Select" "Single,Multiple" bitfld.long 0x04 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read" bitfld.long 0x04 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " BCEN ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x04 0. " DMAEN ,DMA Enable" "Disabled,Enabled" textline "" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "Not forced,Forced" bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "Not forced,Forced" bitfld.long 0x00 26. " FEVTTNE ,Force Tuning Error" "Not forced,Forced" textline " " bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "Not forced,Forced" bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "Not forced,Forced" bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "Not forced,Forced" bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "Not forced,Forced" bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "Not forced,Forced" textline " " bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "Not forced,Forced" bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "Not forced,Forced" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "Not forced,Forced" textline " " bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "Not forced,Forced" bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "Not forced,Forced" bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "Not forced,Forced" bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "Not forced,Forced" textline "" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State " "Stop DMA,Fetch Descriptor,Change Address,Transfer Data" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR[31:0] ,ADMA System Address" group.long 0x60++0x03 line.long 0x00 "DLLCTRL,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT ,Slave delay line update interval" textline " " bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET ,Slave delay target" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Slave override value" textline " " bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatically,No update" textline " " bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET ,The delay target for the uSDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,DLL slave update" "No update,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLLSTS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if (((per.l(ad:0x0219C000+0x48))&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline "" ;section group.long 0xC0++0x0F line.long 0x00 "VENDOR,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Controlled by hardware,Active" textline " " bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending Abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of Dat3 pin when its used as card detection" "High,Low" textline " " bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage Selection (around: 3.0V,1.8V)" "High,Low" bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled" line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" textline " " bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ack mode select" "No ACK,ACK" bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACKTimeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VENDOR2,Vendor Specific 2 Register" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the the Card interrupt status bit" "No,Yes" bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0]," bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" textline " " bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Drive CMD_OE/DAT_OE for one more clock cycle after the end bit" "Yes,No" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for Ncr changes/Ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0c 24. " STD_TUN_EN ,Standard tuning circuit and procedure" "Disabled,Enabled" bitfld.long 0x0c 20.--22. " TUN_WIND ,Data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--18. " TUN_STEP ,The increasing delay cell step in tuning procedure" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,Tuning procedure counter value" textline " " hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 11. else base ad:0x4219C000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " DS_ADDR[31:2] ,DMA System Address" line.long 0x04 "BLKATT,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "CMDXFRTYP,Command Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX[5:0] ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP[1:0] ,Command Type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present" textline " " bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No response,Length 136,Length 48,Length 48/busy check" rgroup.long 0x10++0x0F line.long 0x0 "CMDRSP0,Command Response Register 0" line.long 0x4 "CMDRSP1,Command Response Register 1" line.long 0x8 "CMDRSP2,Command Response Register 2" line.long 0xC "CMDRSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "BUFFACCPORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT[7:0] Line 7 Signal Level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT[7:0] Line 6 Signal Level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT[7:0] Line 5 Signal Level" "Low,High" textline " " bitfld.long 0x00 28. " DLSL[4] ,DAT[7:0] Line 4 Signal Level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT[7:0] Line 3 Signal Level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT[7:0] Line 2 Signal Level" "Low,High" textline " " bitfld.long 0x00 25. " DLSL[1] ,DAT[7:0] Line 1 Signal Level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT[7:0] Line 0 Signal Level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Low,High" textline " " bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card Inserted" "Reset/Not inserted,Inserted" textline " " bitfld.long 0x00 12. " RTR ,Re-Tuning Request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RTA ,Read Transfer Active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write Transfer Active" "Inactive,Active" bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off" textline " " bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active" bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Not inhibited,Inhibited" textline " " bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Not inhibited,Inhibited" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" textline " " bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" textline " " bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restarted" textline " " bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA Select" "Not selected,ADMA1,ADMA2," bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Normal,Test" textline " " bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian," bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "No,Yes" textline " " bitfld.long 0x00 1.--2. " DTW[1:0] ,Data Transfer Width" "1-bit,4-bit,8-bit," bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 28. " RSTT ,Reset Tuning" "No reset,Reset" bitfld.long 0x04 27. " INITA ,Initialization Active" "Inactive,Active" bitfld.long 0x04 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset" textline " " bitfld.long 0x04 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset" bitfld.long 0x04 24. " RSTA ,Software Reset For ALL" "No reset,Reset" bitfld.long 0x04 23. " IPP_RST_N ,Value Output to CARD for hardware reset" "0,1" textline " " bitfld.long 0x04 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select" bitfld.long 0x04 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA Error" "No error,Error" eventfld.long 0x08 26. " TNE ,Tuning Error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 Error" "No error,Error" textline " " eventfld.long 0x08 22. " DEBE ,Data End Bit Error" "No error,Error" eventfld.long 0x08 21. " DCE ,Data CRC Error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data Timeout Error" "No error,Error" textline " " eventfld.long 0x08 19. " CIE ,Command Index Error" "No error,Error" eventfld.long 0x08 18. " CEBE ,Command End Bit Error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC Error" "No error,Error" textline " " eventfld.long 0x08 16. " CTOE ,Command Timeout Error" "No error,Error" eventfld.long 0x08 14. " TP ,Tuning Pass" "Not transferred,Transferred" eventfld.long 0x08 12. " RTE ,Re-Tuning Event" "Not requested,Requested" textline " " eventfld.long 0x08 8. " CINT ,Card Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card Removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card Insertion" "Not inserted,Inserted" textline " " eventfld.long 0x08 5. " BRR ,Buffer Read Ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer Write Ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 2. " BGE ,Block Gap Event" "No event,Stopped" eventfld.long 0x08 1. " TC ,Transfer Complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command Complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 26. " TNESEN ,Tuning Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled" bitfld.long 0x0C 14. " TPSEN ,Tuning Pass Status Enable" "Masked,Enabled" bitfld.long 0x0C 12. " RTESEN ,Re-Tuning Event Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled" bitfld.long 0x0C 6. " CINSSEN ,Card Insertion Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled" textline " " bitfld.long 0x0C 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 26. " TNEIEN ,Tuning Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 14. " TPIEN ,Tuning Pass Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 12. " RTEIEN ,Re-Tuning Event Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 8. " CINTIEN ,Card Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card Insertion Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled" textline " " bitfld.long 0x10 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled" bitfld.long 0x10 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled" textline "" if (((per.l(ad:0x4219C000+0xCC))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample Clock Select" "Fixed,Tuned" bitfld.long 0x00 22. " EXECTUTE_TUNING ,Execute Tuning" "Not executed,Executed" textline " " rbitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error" textline " " bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed" endif textline "" group.long 0x40++0x03 line.long 0x00 "HOSTCAPBLT,Host Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported" rbitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported" textline " " rbitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported" rbitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL[2:0] ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." textline " " rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3," bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use Tuning for SDR50" "No,Yes" textline " " bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time Counter for Retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" textline " " rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" textline "" group.long 0x44++0x07 line.long 0x00 "WML,Watermark Level Register" bitfld.long 0x00 24.--28. " WR_BRST_LEN[4:0] ,Write Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 16.--23. 1. " WR_WML[7:0] ,Write Watermark Level" textline " " bitfld.long 0x00 8.--12. " RD_BRST_LEN[4:0] ,Read Burst Length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x00 0.--7. 1. " RD_WML[7:0] ,Read Watermark Level" textline "" line.long 0x04 "MIXERCTRL,Mixer control Regiseter" bitfld.long 0x04 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x04 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" bitfld.long 0x04 23. " SMP_CLK_SEL ,Sample clock selection" "Fixed,Tuned" textline " " bitfld.long 0x04 22. " EXE_TUNE ,Execute Tuning" "Not executed,Executed" bitfld.long 0x04 7. " AC23EN ,Auto CMD23 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " NIBBLE_POS ,Nibble position" "Odd high->even high->odd low->even low,Odd high->odd low->even high->even low" textline " " bitfld.long 0x04 5. " MSBSEL ,Multi/Single Block Select" "Single,Multiple" bitfld.long 0x04 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read" bitfld.long 0x04 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled" bitfld.long 0x04 1. " BCEN ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x04 0. " DMAEN ,DMA Enable" "Disabled,Enabled" textline "" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "Not forced,Forced" bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "Not forced,Forced" bitfld.long 0x00 26. " FEVTTNE ,Force Tuning Error" "Not forced,Forced" textline " " bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "Not forced,Forced" bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "Not forced,Forced" bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "Not forced,Forced" bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "Not forced,Forced" bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "Not forced,Forced" textline " " bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "Not forced,Forced" bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "Not forced,Forced" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "Not forced,Forced" textline " " bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "Not forced,Forced" bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "Not forced,Forced" bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "Not forced,Forced" textline " " bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "Not forced,Forced" bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "Not forced,Forced" textline "" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State " "Stop DMA,Fetch Descriptor,Change Address,Transfer Data" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR[31:0] ,ADMA System Address" group.long 0x60++0x03 line.long 0x00 "DLLCTRL,DLL Control Register" bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT ,Slave delay line update interval" textline " " bitfld.long 0x00 16.--18. " DLL_CTRL_SLV_DLY_TARGET ,Slave delay target" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Slave override value" textline " " bitfld.long 0x00 8. " DLL_CTRL_SLV_OVERRIDE ,Manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL update" "Automatically,No update" textline " " bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET ,The delay target for the uSDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,DLL slave update" "No update,Updated" textline " " bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset" bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLLSTS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if (((per.l(ad:0x4219C000+0x48))&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLKTUNE,Clock Tuning Control and Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" textline " " rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" textline " " bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline "" ;section group.long 0xC0++0x0F line.long 0x00 "VENDOR,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Controlled by hardware,Active" textline " " bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending Abort command" "Active,Inactive" bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of Dat3 pin when its used as card detection" "High,Low" textline " " bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage Selection (around: 3.0V,1.8V)" "High,Low" bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled" line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" textline " " bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ack mode select" "No ACK,ACK" bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACKTimeout Counter Value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VENDOR2,Vendor Specific 2 Register" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the the Card interrupt status bit" "No,Yes" bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0]," bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" textline " " bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Drive CMD_OE/DAT_OE for one more clock cycle after the end bit" "Yes,No" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for Ncr changes/Ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0c 24. " STD_TUN_EN ,Standard tuning circuit and procedure" "Disabled,Enabled" bitfld.long 0x0c 20.--22. " TUN_WIND ,Data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--18. " TUN_STEP ,The increasing delay cell step in tuning procedure" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,Tuning procedure counter value" textline " " hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 11. endif tree.end tree.end tree.open "VADC (Video Analog-to-Digital Converter)" tree "AFE (Analog Front End)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02228000 width 17. rgroup.long 0x00++0x03 line.long 0x00 "AFE_BLOCK_ID,Block ID Register" hexmask.long.byte 0x00 0.--7. 1. " BLOCK_ID ,Block ID and revision number" group.long 0x04++0x07 line.long 0x00 "AFE_PDBUF,Power Down Buffers Register" bitfld.long 0x00 3.--4. " TESTBUFFERS_PD_N ,Active-low power down of test buffers" "Power down both,Power down test buffer 1,Power down test buffer 0,Both enabled" bitfld.long 0x00 2. " BGR_PD_N ,Active-low power down of band gap" "Powered down,Normal" textline " " bitfld.long 0x00 1. " BGR_BGR_PD_N ,Active-low power down of band gap core" "Powered down,Normal" bitfld.long 0x00 0. " ACAFE_PD_N ,Active-low power down of IP" "Powered down,Normal" line.long 0x04 "AFE_SWRST,Software Reset" bitfld.long 0x04 2. " ACAFE_SW_RST_N ,Software reset of all clocks" "Reset,Normal" bitfld.long 0x04 1. " ADC_PROC_CLK_SW_RST_N ,Software reset of adc_clk" "Reset,Normal" bitfld.long 0x04 0. " SYSCLK_SW_RST_N ,Software reset of sysclk" "Reset,Normal" group.long 0x18++0x03 line.long 0x00 "AFE_BGREG,Band Gap Register" bitfld.long 0x00 4. " BGR_EN_EXT_CURRENT ,External current reference enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " BGR_TRIMLEVEL ,Bandgap trim" "V054,V05475,V0555,V05625,V057,V05775,V0585,V05925,V06,V06075,V0615,V06225,V063,V06375,V0645,V06525" rgroup.long 0x400++0x03 line.long 0x00 "AFE_ACCESSAR_ID,Accessar ID Register" hexmask.long.byte 0x00 0.--7. 1. " ACCESSAR_ID ,Accessar ID" group.long 0x404++0x13 line.long 0x00 "AFE_PDADC,Power Down ADC Register" bitfld.long 0x00 3. " CLAMP_PD_N ,Active-low power down of clamp circuitry" "Powered down,Normal" bitfld.long 0x00 2. " ADC_IREF_PD_N ,Active-low power down of ADC iref" "Powered down,Normal" textline " " bitfld.long 0x00 1. " DLYLOOP_PD_N ,Active-low power down of ADC delay loop reference" "Powered down,Normal" bitfld.long 0x00 0. " ACCESSAR_PD_N ,Accessar master power down control" "Powered down,Normal" line.long 0x04 "AFE_PDSARH,Power Down SAR High Register" bitfld.long 0x04 0. " ADC_PD_N ,Active-low power down of ADC" "Powered down,Normal" line.long 0x08 "AFE_PDSARL,Power Down SAR Low Register" bitfld.long 0x08 7. " ADC_PD_N[7] ,Active-low power down of ADC bit 7" "Powered down,Normal" bitfld.long 0x08 6. " [6] ,Active-low power down of ADC bit 6" "Powered down,Normal" bitfld.long 0x08 5. " [5] ,Active-low power down of ADC bit 5" "Powered down,Normal" textline " " bitfld.long 0x08 4. " [4] ,Active-low power down of ADC bit 4" "Powered down,Normal" bitfld.long 0x08 3. " [3] ,Active-low power down of ADC bit 3" "Powered down,Normal" bitfld.long 0x08 2. " [2] ,Active-low power down of ADC bit 2" "Powered down,Normal" textline " " bitfld.long 0x08 1. " [1] ,Active-low power down of ADC bit 1" "Powered down,Normal" bitfld.long 0x08 0. " [0] ,Active-low power down of ADC bit 0" "Powered down,Normal" line.long 0x0C "AFE_PDADCRFH,Power Down ADC Ref. High Register" bitfld.long 0x0C 0. " ADCREF_REFBUFSLICE_PD_N ,Active-low power down of ADC reference" "Powered down,Normal" line.long 0x10 "AFE_PDADCRFL,Power Down ADC Ref. Low Register" bitfld.long 0x10 7. " ADCREF_REFBUFSLICE_PD_N[7] ,Active-low power down of ADC reference bit 7" "Powered down,Normal" bitfld.long 0x10 6. " [6] ,Active-low power down of ADC reference bit 6" "Powered down,Normal" bitfld.long 0x10 5. " [5] ,Active-low power down of ADC reference bit 5" "Powered down,Normal" textline " " bitfld.long 0x10 4. " [4] ,Active-low power down of ADC reference bit 4" "Powered down,Normal" bitfld.long 0x10 3. " [3] ,Active-low power down of ADC reference bit 3" "Powered down,Normal" bitfld.long 0x10 2. " [2] ,Active-low power down of ADC reference bit 2" "Powered down,Normal" textline " " bitfld.long 0x10 1. " [1] ,Active-low power down of ADC reference bit 1" "Powered down,Normal" bitfld.long 0x10 0. " [0] ,Active-low power down of ADC reference bit 0" "Powered down,Normal" group.long 0x41C++0x03 line.long 0x00 "AFE_ADCGN,ADC Gain Register" bitfld.long 0x00 0.--3. " ADC_GAIN ,ADC gain setting" "No signal,1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16" group.long 0x434++0x07 line.long 0x00 "AFE_REFTRIML,ADC Ref Trim Low Register" bitfld.long 0x00 6.--7. " ADCREF_REFTRIMOP ,ADC reference" "X1,X2,X2,X3" bitfld.long 0x00 4.--5. " ADCREF_REFTRIM02 ,ADC reference" "Low,Mid,Mid,High" textline " " bitfld.long 0x00 2.--3. " ADCREF_REFTRIM04 ,ADC reference" "Low,Mid,Mid,High" bitfld.long 0x00 0.--1. " ADCREF_REFTRIM08 ,ADC reference" "Low,Mid,Mid,High" line.long 0x04 "AFE_REFTRIMH,ADC Ref Trim High Register" bitfld.long 0x04 0.--3. " ADCREF_REFTRIM ,ADC reference" "REF_0_86,REF_0_88,REF_0_89,REF_0_91,REF_0_93,REF_0_95,REF_0_96,REF_0_98,REF_1_00,REF_1_018,REF_1_04,REF_1_05,REF_1_07,REF_1_09,REF_1_11,REF_1_13" group.long 0x44C++0x03 line.long 0x00 "AFE_DACAMP,Clamp DAC Trim Register" bitfld.long 0x00 0.--3. " CLAMPDAC_TRIM ,Trim of DAC current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x454++0x7 line.long 0x00 "AFE_CLMPDAT,Clamp DAC Data Register" hexmask.long.byte 0x00 0.--7. 1. " CLAMPDAC_DATA ,Clamp DAC data" line.long 0x04 "AFE_CLMPAMP,Clamp DAC Control Register" bitfld.long 0x04 6. " CLAMP_CURRENT_REG_OVERRIDE ,Override clamp current ports and control through registers" "Ports,Register" bitfld.long 0x04 5. " CLAMP_UPDN_REG_OVERRIDE ,Override clamp up down ports and control through registers" "Ports,Register" textline " " bitfld.long 0x04 3.--4. " CLAMP_DACDATA_WEIGHT ,Maps clamp_current input to clampdac_data port in mixed-signal block" "No shift,Shift by 1,Shift by 2,Shift by 3" bitfld.long 0x04 0.--2. " CLAMP_DACDATA_EXTRA ,Clamp DAC extra data" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x02228000+0x458))&0x20)==0x20) group.long 0x45C++0x03 line.long 0x00 "AFE_CLAMP,Clamp Control Register" bitfld.long 0x00 7. " CLAMP_PWM_MODE ,Enable PWM mode" "Constant,PWM" bitfld.long 0x00 6. " CLAMP_UP_DOWN_POLARITY ,Defines polarity of MSB in clamp_current port" "Non-inverted,Inverted" bitfld.long 0x00 5. " DIV_PROC_CLK ,Divides proc_clock by 4 or 8" "/4,/8" textline " " bitfld.long 0x00 4. " CLAMP_LOWCURRMODE ,Enable low current mode" "Normal,Low current" bitfld.long 0x00 3. " CLAMP_INEN_REG ,Clamp down Remove charge" "No pump down,Pump down" bitfld.long 0x00 2. " CLAMP_IPEN_REG ,Clamp up Add charge" "No pump up,Pump up" textline " " bitfld.long 0x00 1. " CLAMP_VN ,Enable voltage clamp select" "iClamp,vClamp" bitfld.long 0x00 0. " NCLAMP_POWERSAVE ,Active-low power save" "Power save,Normal" else group.long 0x45C++0x03 line.long 0x00 "AFE_CLAMP,Clamp Control Register" bitfld.long 0x00 7. " CLAMP_PWM_MODE ,Enable PWM mode" "Constant,PWM" bitfld.long 0x00 6. " CLAMP_UP_DOWN_POLARITY ,Defines polarity of MSB in clamp_current port" "Non-inverted,Inverted" bitfld.long 0x00 5. " DIV_PROC_CLK ,Divides proc_clock by 4 or 8" "/4,/8" textline " " bitfld.long 0x00 4. " CLAMP_LOWCURRMODE ,Enable low current mode" "Normal,Low current" textline " " bitfld.long 0x00 1. " CLAMP_VN ,Enable voltage clamp select" "iClamp,vClamp" bitfld.long 0x00 0. " NCLAMP_POWERSAVE ,Active-low power save" "Power save,Normal" endif group.long 0x460++0x1B line.long 0x00 "AFE_INPBUF,Input Buffer Register" bitfld.long 0x00 5. " MUX_CLAMPEN ,Connect clamp node to analog input" "Disabled,Enabled" bitfld.long 0x00 4. " MUX_BUFFER_15M_EN ,15MHz buffer enable" "Disabled,Enabled" bitfld.long 0x00 3. " MUX_BUFFER_BP_EN ,Buffer bypass enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BUFF_EN_CM ,Common mode input buffer enable" "Disabled,Enabled" bitfld.long 0x00 0. " BUFF_EN_RI ,Differential output buffer enable" "Disabled,Enabled" line.long 0x04 "AFE_INPFLT,Analog Input Filter Register" bitfld.long 0x04 2. " MUX_FILTERBYPASS ,Fiter bypass" "Disabled,Enabled" bitfld.long 0x04 1. " MUX_FILTER_15M_EN ,15 MHz filter enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " MUX_PDCURRENTMIRROR ,Power down current mirror" "Powered down,Normal" line.long 0x08 "AFE_ADCDGN,ADC Digital Gain Register" bitfld.long 0x08 6. " ADC_DIGITAL_GAIN_BYPASS ,Bypass digital gain" "Normal,Bypass" bitfld.long 0x08 0.--5. " ADC_DIGITAL_GAIN ,ADC digital gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "AFE_OFFDRV,Off-Chip Drive Register" bitfld.long 0x0C 2. " SH_TRIM ,Enables test mode for ADC reference" "Disabled,Enabled" bitfld.long 0x0C 0.--1. " ENOFFCHIPDRIVE ,Connect input VIN3 directly to ADC P-input and input VIN2 directly to ADC N-input" "Non connected,Not allowed,Not allowed,Direct connect" line.long 0x10 "AFE_INPCONFIG,VADC Input Config Register" bitfld.long 0x10 4.--7. " MUX_ENLF ,Select analog input" "All inputs disabled,VIN0,VIN1,,VIN2,,,,VIN3,?..." bitfld.long 0x10 3. " INPUT_PULLDOWN_EN[3] ,Enable input pull-down bit 3" "Disabled,Enabled" bitfld.long 0x10 2. " [2] ,Enable input pull-down bit 2" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " [1] ,Enable input pull-down bit 1" "Disabled,Enabled" bitfld.long 0x10 0. " [0] ,Enable input pull-down bit 0" "Disabled,Enabled" line.long 0x14 "AFE_PROGDELAY,VADC Programmed Delay Register" hexmask.long.byte 0x14 0.--7. 1. " PROG_DELAY ,ADC comparator timing" line.long 0x18 "AFE_ADCOMT,ADC Comparator Timing Register" bitfld.long 0x18 6.--7. " MEASURE_TIMING ,Defines when to measure" "Not applicable,Not applicable,Used,Not applicable" bitfld.long 0x18 1.--5. " WAIT_TIME ,Defines algorithm update frequency" "Eight times,Quad,Double,Slow,?..." bitfld.long 0x18 0. " OVERRIDE ,Selects programmed value instead of value found by algorithm" "Not overriden,Overriden" rgroup.long 0x47C++0x03 line.long 0x00 "AFE_ALGDELAY,Algorithm Delay Register" hexmask.long.byte 0x00 0.--7. 1. " ALGORITHM_DELAY ,ADC comparator timing" rgroup.long 0x800++0x07 line.long 0x00 "AFE_ACC_ID,ACC ID Register" hexmask.long.byte 0x00 0.--7. 1. " ACC_ID ,Block ID and revision number" line.long 0x04 "AFE_ACCSTA,ACC Status Register" bitfld.long 0x04 4. " STATUS[4] ,Indicate selected bit calibrated" "Not calibrated,Cailibrated" bitfld.long 0x04 3. " [3] ,Indicate invalid data for selected bit" "Valid,Invalid" bitfld.long 0x04 0.--2. " [2:0] , Indicate current function state of the ACC" "Compensation mode,,Acquisition mode,,Idel mode,?..." group.long 0x808++0x17 line.long 0x00 "AFE_ACCNOSLI,ACC Number Of Slice Register" bitfld.long 0x00 0.--5. " NO_OF_SLICES ,Selects number of slices" "0,1,3,,5,,,,9,,,,,,,17,,,,,,,,,,,,,,,,,12,?..." line.long 0x04 "AFE_ACCCALCON,ACC Calibrate Control Register" bitfld.long 0x04 4. " ANA_OFFSET_COMP_EN ,Controls analog offset measurements" "Disabled,Enabled" bitfld.long 0x04 3. " OFFSET_COMP_EN ,Controls offset compensation" "Disabled,Enabled" bitfld.long 0x04 2. " BYPASS_CALIB ,Allow the user to bypass the calibration sequence for the coefficients and instead use the default values" "Run,Skipped" textline " " bitfld.long 0x04 1. " BYPASS ,Bypass ACC" "Normal,Bypass" bitfld.long 0x04 0. " CALIBRATE_START ,Initiates acquisition when set from 0 to 1" "Normal,Initiate acquisition" line.long 0x08 "AFE_ASCREG,ADC Sample Compensation Register" bitfld.long 0x08 2. " BWE_WRITE_CTRL ,Select programming of new weights can be completed on individual slices or all slices minimize the number of writes at once" "Individual slice,All slices" bitfld.long 0x08 0.--1. " BWE_CTRL ,ADC Bit Weight Estimation" "Algorithm,Write,Read,Acquire" line.long 0x0C "AFE_BLCREG,Block Level Control Register" bitfld.long 0x0C 1. " START_CAL ,Start calibration" "Normal,Start" bitfld.long 0x0C 0. " EN_BYPASS ,Enable bypass" "Normal,Bypass" line.long 0x10 "AFE_SELSLI,ACC Select Slice Register" hexmask.long.byte 0x10 0.--7. 1. " SELECT_SLICE , ADC Bit Weight Estimation lsb" line.long 0x14 "AFE_SELBYT,ACC Select Byte Register" hexmask.long.byte 0x14 0.--7. 1. " SELECT_BYTE , ADC Bit Weight Estimation msb" rgroup.long 0x820++0x03 line.long 0x00 "AFE_REDVAL,ACC Read Value Register" hexmask.long.byte 0x00 0.--7. 1. " READ_VALUE ,ADC Bit Weight Estimation Read lsb" group.long 0x824++0x03 line.long 0x00 "AFE_WRIBYT,ACC Write Byte Register" hexmask.long.byte 0x00 0.--7. 1. " WRITE_BYTE ,ADC Bit Weight Estimation Write lsb" width 0x0B else base ad:0x42228000 width 17. rgroup.long 0x00++0x03 line.long 0x00 "AFE_BLOCK_ID,Block ID Register" hexmask.long.byte 0x00 0.--7. 1. " BLOCK_ID ,Block ID and revision number" group.long 0x04++0x07 line.long 0x00 "AFE_PDBUF,Power Down Buffers Register" bitfld.long 0x00 3.--4. " TESTBUFFERS_PD_N ,Active-low power down of test buffers" "Power down both,Power down test buffer 1,Power down test buffer 0,Both enabled" bitfld.long 0x00 2. " BGR_PD_N ,Active-low power down of band gap" "Powered down,Normal" textline " " bitfld.long 0x00 1. " BGR_BGR_PD_N ,Active-low power down of band gap core" "Powered down,Normal" bitfld.long 0x00 0. " ACAFE_PD_N ,Active-low power down of IP" "Powered down,Normal" line.long 0x04 "AFE_SWRST,Software Reset" bitfld.long 0x04 2. " ACAFE_SW_RST_N ,Software reset of all clocks" "Reset,Normal" bitfld.long 0x04 1. " ADC_PROC_CLK_SW_RST_N ,Software reset of adc_clk" "Reset,Normal" bitfld.long 0x04 0. " SYSCLK_SW_RST_N ,Software reset of sysclk" "Reset,Normal" group.long 0x18++0x03 line.long 0x00 "AFE_BGREG,Band Gap Register" bitfld.long 0x00 4. " BGR_EN_EXT_CURRENT ,External current reference enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " BGR_TRIMLEVEL ,Bandgap trim" "V054,V05475,V0555,V05625,V057,V05775,V0585,V05925,V06,V06075,V0615,V06225,V063,V06375,V0645,V06525" rgroup.long 0x400++0x03 line.long 0x00 "AFE_ACCESSAR_ID,Accessar ID Register" hexmask.long.byte 0x00 0.--7. 1. " ACCESSAR_ID ,Accessar ID" group.long 0x404++0x13 line.long 0x00 "AFE_PDADC,Power Down ADC Register" bitfld.long 0x00 3. " CLAMP_PD_N ,Active-low power down of clamp circuitry" "Powered down,Normal" bitfld.long 0x00 2. " ADC_IREF_PD_N ,Active-low power down of ADC iref" "Powered down,Normal" textline " " bitfld.long 0x00 1. " DLYLOOP_PD_N ,Active-low power down of ADC delay loop reference" "Powered down,Normal" bitfld.long 0x00 0. " ACCESSAR_PD_N ,Accessar master power down control" "Powered down,Normal" line.long 0x04 "AFE_PDSARH,Power Down SAR High Register" bitfld.long 0x04 0. " ADC_PD_N ,Active-low power down of ADC" "Powered down,Normal" line.long 0x08 "AFE_PDSARL,Power Down SAR Low Register" bitfld.long 0x08 7. " ADC_PD_N[7] ,Active-low power down of ADC bit 7" "Powered down,Normal" bitfld.long 0x08 6. " [6] ,Active-low power down of ADC bit 6" "Powered down,Normal" bitfld.long 0x08 5. " [5] ,Active-low power down of ADC bit 5" "Powered down,Normal" textline " " bitfld.long 0x08 4. " [4] ,Active-low power down of ADC bit 4" "Powered down,Normal" bitfld.long 0x08 3. " [3] ,Active-low power down of ADC bit 3" "Powered down,Normal" bitfld.long 0x08 2. " [2] ,Active-low power down of ADC bit 2" "Powered down,Normal" textline " " bitfld.long 0x08 1. " [1] ,Active-low power down of ADC bit 1" "Powered down,Normal" bitfld.long 0x08 0. " [0] ,Active-low power down of ADC bit 0" "Powered down,Normal" line.long 0x0C "AFE_PDADCRFH,Power Down ADC Ref. High Register" bitfld.long 0x0C 0. " ADCREF_REFBUFSLICE_PD_N ,Active-low power down of ADC reference" "Powered down,Normal" line.long 0x10 "AFE_PDADCRFL,Power Down ADC Ref. Low Register" bitfld.long 0x10 7. " ADCREF_REFBUFSLICE_PD_N[7] ,Active-low power down of ADC reference bit 7" "Powered down,Normal" bitfld.long 0x10 6. " [6] ,Active-low power down of ADC reference bit 6" "Powered down,Normal" bitfld.long 0x10 5. " [5] ,Active-low power down of ADC reference bit 5" "Powered down,Normal" textline " " bitfld.long 0x10 4. " [4] ,Active-low power down of ADC reference bit 4" "Powered down,Normal" bitfld.long 0x10 3. " [3] ,Active-low power down of ADC reference bit 3" "Powered down,Normal" bitfld.long 0x10 2. " [2] ,Active-low power down of ADC reference bit 2" "Powered down,Normal" textline " " bitfld.long 0x10 1. " [1] ,Active-low power down of ADC reference bit 1" "Powered down,Normal" bitfld.long 0x10 0. " [0] ,Active-low power down of ADC reference bit 0" "Powered down,Normal" group.long 0x41C++0x03 line.long 0x00 "AFE_ADCGN,ADC Gain Register" bitfld.long 0x00 0.--3. " ADC_GAIN ,ADC gain setting" "No signal,1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16" group.long 0x434++0x07 line.long 0x00 "AFE_REFTRIML,ADC Ref Trim Low Register" bitfld.long 0x00 6.--7. " ADCREF_REFTRIMOP ,ADC reference" "X1,X2,X2,X3" bitfld.long 0x00 4.--5. " ADCREF_REFTRIM02 ,ADC reference" "Low,Mid,Mid,High" textline " " bitfld.long 0x00 2.--3. " ADCREF_REFTRIM04 ,ADC reference" "Low,Mid,Mid,High" bitfld.long 0x00 0.--1. " ADCREF_REFTRIM08 ,ADC reference" "Low,Mid,Mid,High" line.long 0x04 "AFE_REFTRIMH,ADC Ref Trim High Register" bitfld.long 0x04 0.--3. " ADCREF_REFTRIM ,ADC reference" "REF_0_86,REF_0_88,REF_0_89,REF_0_91,REF_0_93,REF_0_95,REF_0_96,REF_0_98,REF_1_00,REF_1_018,REF_1_04,REF_1_05,REF_1_07,REF_1_09,REF_1_11,REF_1_13" group.long 0x44C++0x03 line.long 0x00 "AFE_DACAMP,Clamp DAC Trim Register" bitfld.long 0x00 0.--3. " CLAMPDAC_TRIM ,Trim of DAC current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x454++0x7 line.long 0x00 "AFE_CLMPDAT,Clamp DAC Data Register" hexmask.long.byte 0x00 0.--7. 1. " CLAMPDAC_DATA ,Clamp DAC data" line.long 0x04 "AFE_CLMPAMP,Clamp DAC Control Register" bitfld.long 0x04 6. " CLAMP_CURRENT_REG_OVERRIDE ,Override clamp current ports and control through registers" "Ports,Register" bitfld.long 0x04 5. " CLAMP_UPDN_REG_OVERRIDE ,Override clamp up down ports and control through registers" "Ports,Register" textline " " bitfld.long 0x04 3.--4. " CLAMP_DACDATA_WEIGHT ,Maps clamp_current input to clampdac_data port in mixed-signal block" "No shift,Shift by 1,Shift by 2,Shift by 3" bitfld.long 0x04 0.--2. " CLAMP_DACDATA_EXTRA ,Clamp DAC extra data" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x42228000+0x458))&0x20)==0x20) group.long 0x45C++0x03 line.long 0x00 "AFE_CLAMP,Clamp Control Register" bitfld.long 0x00 7. " CLAMP_PWM_MODE ,Enable PWM mode" "Constant,PWM" bitfld.long 0x00 6. " CLAMP_UP_DOWN_POLARITY ,Defines polarity of MSB in clamp_current port" "Non-inverted,Inverted" bitfld.long 0x00 5. " DIV_PROC_CLK ,Divides proc_clock by 4 or 8" "/4,/8" textline " " bitfld.long 0x00 4. " CLAMP_LOWCURRMODE ,Enable low current mode" "Normal,Low current" bitfld.long 0x00 3. " CLAMP_INEN_REG ,Clamp down Remove charge" "No pump down,Pump down" bitfld.long 0x00 2. " CLAMP_IPEN_REG ,Clamp up Add charge" "No pump up,Pump up" textline " " bitfld.long 0x00 1. " CLAMP_VN ,Enable voltage clamp select" "iClamp,vClamp" bitfld.long 0x00 0. " NCLAMP_POWERSAVE ,Active-low power save" "Power save,Normal" else group.long 0x45C++0x03 line.long 0x00 "AFE_CLAMP,Clamp Control Register" bitfld.long 0x00 7. " CLAMP_PWM_MODE ,Enable PWM mode" "Constant,PWM" bitfld.long 0x00 6. " CLAMP_UP_DOWN_POLARITY ,Defines polarity of MSB in clamp_current port" "Non-inverted,Inverted" bitfld.long 0x00 5. " DIV_PROC_CLK ,Divides proc_clock by 4 or 8" "/4,/8" textline " " bitfld.long 0x00 4. " CLAMP_LOWCURRMODE ,Enable low current mode" "Normal,Low current" textline " " bitfld.long 0x00 1. " CLAMP_VN ,Enable voltage clamp select" "iClamp,vClamp" bitfld.long 0x00 0. " NCLAMP_POWERSAVE ,Active-low power save" "Power save,Normal" endif group.long 0x460++0x1B line.long 0x00 "AFE_INPBUF,Input Buffer Register" bitfld.long 0x00 5. " MUX_CLAMPEN ,Connect clamp node to analog input" "Disabled,Enabled" bitfld.long 0x00 4. " MUX_BUFFER_15M_EN ,15MHz buffer enable" "Disabled,Enabled" bitfld.long 0x00 3. " MUX_BUFFER_BP_EN ,Buffer bypass enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BUFF_EN_CM ,Common mode input buffer enable" "Disabled,Enabled" bitfld.long 0x00 0. " BUFF_EN_RI ,Differential output buffer enable" "Disabled,Enabled" line.long 0x04 "AFE_INPFLT,Analog Input Filter Register" bitfld.long 0x04 2. " MUX_FILTERBYPASS ,Fiter bypass" "Disabled,Enabled" bitfld.long 0x04 1. " MUX_FILTER_15M_EN ,15 MHz filter enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " MUX_PDCURRENTMIRROR ,Power down current mirror" "Powered down,Normal" line.long 0x08 "AFE_ADCDGN,ADC Digital Gain Register" bitfld.long 0x08 6. " ADC_DIGITAL_GAIN_BYPASS ,Bypass digital gain" "Normal,Bypass" bitfld.long 0x08 0.--5. " ADC_DIGITAL_GAIN ,ADC digital gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "AFE_OFFDRV,Off-Chip Drive Register" bitfld.long 0x0C 2. " SH_TRIM ,Enables test mode for ADC reference" "Disabled,Enabled" bitfld.long 0x0C 0.--1. " ENOFFCHIPDRIVE ,Connect input VIN3 directly to ADC P-input and input VIN2 directly to ADC N-input" "Non connected,Not allowed,Not allowed,Direct connect" line.long 0x10 "AFE_INPCONFIG,VADC Input Config Register" bitfld.long 0x10 4.--7. " MUX_ENLF ,Select analog input" "All inputs disabled,VIN0,VIN1,,VIN2,,,,VIN3,?..." bitfld.long 0x10 3. " INPUT_PULLDOWN_EN[3] ,Enable input pull-down bit 3" "Disabled,Enabled" bitfld.long 0x10 2. " [2] ,Enable input pull-down bit 2" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " [1] ,Enable input pull-down bit 1" "Disabled,Enabled" bitfld.long 0x10 0. " [0] ,Enable input pull-down bit 0" "Disabled,Enabled" line.long 0x14 "AFE_PROGDELAY,VADC Programmed Delay Register" hexmask.long.byte 0x14 0.--7. 1. " PROG_DELAY ,ADC comparator timing" line.long 0x18 "AFE_ADCOMT,ADC Comparator Timing Register" bitfld.long 0x18 6.--7. " MEASURE_TIMING ,Defines when to measure" "Not applicable,Not applicable,Used,Not applicable" bitfld.long 0x18 1.--5. " WAIT_TIME ,Defines algorithm update frequency" "Eight times,Quad,Double,Slow,?..." bitfld.long 0x18 0. " OVERRIDE ,Selects programmed value instead of value found by algorithm" "Not overriden,Overriden" rgroup.long 0x47C++0x03 line.long 0x00 "AFE_ALGDELAY,Algorithm Delay Register" hexmask.long.byte 0x00 0.--7. 1. " ALGORITHM_DELAY ,ADC comparator timing" rgroup.long 0x800++0x07 line.long 0x00 "AFE_ACC_ID,ACC ID Register" hexmask.long.byte 0x00 0.--7. 1. " ACC_ID ,Block ID and revision number" line.long 0x04 "AFE_ACCSTA,ACC Status Register" bitfld.long 0x04 4. " STATUS[4] ,Indicate selected bit calibrated" "Not calibrated,Cailibrated" bitfld.long 0x04 3. " [3] ,Indicate invalid data for selected bit" "Valid,Invalid" bitfld.long 0x04 0.--2. " [2:0] , Indicate current function state of the ACC" "Compensation mode,,Acquisition mode,,Idel mode,?..." group.long 0x808++0x17 line.long 0x00 "AFE_ACCNOSLI,ACC Number Of Slice Register" bitfld.long 0x00 0.--5. " NO_OF_SLICES ,Selects number of slices" "0,1,3,,5,,,,9,,,,,,,17,,,,,,,,,,,,,,,,,12,?..." line.long 0x04 "AFE_ACCCALCON,ACC Calibrate Control Register" bitfld.long 0x04 4. " ANA_OFFSET_COMP_EN ,Controls analog offset measurements" "Disabled,Enabled" bitfld.long 0x04 3. " OFFSET_COMP_EN ,Controls offset compensation" "Disabled,Enabled" bitfld.long 0x04 2. " BYPASS_CALIB ,Allow the user to bypass the calibration sequence for the coefficients and instead use the default values" "Run,Skipped" textline " " bitfld.long 0x04 1. " BYPASS ,Bypass ACC" "Normal,Bypass" bitfld.long 0x04 0. " CALIBRATE_START ,Initiates acquisition when set from 0 to 1" "Normal,Initiate acquisition" line.long 0x08 "AFE_ASCREG,ADC Sample Compensation Register" bitfld.long 0x08 2. " BWE_WRITE_CTRL ,Select programming of new weights can be completed on individual slices or all slices minimize the number of writes at once" "Individual slice,All slices" bitfld.long 0x08 0.--1. " BWE_CTRL ,ADC Bit Weight Estimation" "Algorithm,Write,Read,Acquire" line.long 0x0C "AFE_BLCREG,Block Level Control Register" bitfld.long 0x0C 1. " START_CAL ,Start calibration" "Normal,Start" bitfld.long 0x0C 0. " EN_BYPASS ,Enable bypass" "Normal,Bypass" line.long 0x10 "AFE_SELSLI,ACC Select Slice Register" hexmask.long.byte 0x10 0.--7. 1. " SELECT_SLICE , ADC Bit Weight Estimation lsb" line.long 0x14 "AFE_SELBYT,ACC Select Byte Register" hexmask.long.byte 0x14 0.--7. 1. " SELECT_BYTE , ADC Bit Weight Estimation msb" rgroup.long 0x820++0x03 line.long 0x00 "AFE_REDVAL,ACC Read Value Register" hexmask.long.byte 0x00 0.--7. 1. " READ_VALUE ,ADC Bit Weight Estimation Read lsb" group.long 0x824++0x03 line.long 0x00 "AFE_WRIBYT,ACC Write Byte Register" hexmask.long.byte 0x00 0.--7. 1. " WRITE_BYTE ,ADC Bit Weight Estimation Write lsb" width 0x0B endif tree.end tree "VDEC (Video decoder)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x0222C000 width 19. group.long 0x00++0x03 line.long 0x00 "VDEC_CFC1,2D Comb Filter Control 1 Register" bitfld.long 0x00 4.--7. " RC_DEBUGOUT ,Debug mode" "Full 2D comb filter,Vertical adaptive comb only,Fixed 3 line vertical comb only,Fixed notch filter only,?..." bitfld.long 0x00 3. " RC_COMBMODE_OVERRIDE[3] ,Comb mode override bit Force PAL 2D comb mode" "Not forced,Forced" textline " " bitfld.long 0x00 2. " [2] ,Comb mode override bit Force 4.43 MHz comb filters" "Not forced,Forced" bitfld.long 0x00 0. " [0] ,Comb mode override bit Enable override" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "VDEC_BRSTGT,Burst Gate Register" hexmask.long.byte 0x00 0.--7. 1. " RC_CBURSTSTART ,Burst start position" group.long 0x40++0x07 line.long 0x00 "VDEC_HZPOS,Horizontal Position Register" hexmask.long.byte 0x00 0.--7. 1. " RO_HPRAMP_CMP ,Horizontal Position" line.long 0x04 "VDEC_VRTPOS,Vertical Position Register" hexmask.long.byte 0x04 0.--7. 1. " RO_VLINE_CMP ,Vertical Position" group.long 0x54++0x13 line.long 0x00 "VDEC_HVSHFT,Output Conditioning and HV Shift Register" bitfld.long 0x00 6. " ANTIALIAS_DIS ,Anti-alias disable" "No,Yes" bitfld.long 0x00 5. " RO_USEACTIVE ,Use active" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " RO_VZERO_SEL ,Vertical shift" "No effect,Shifted" bitfld.long 0x00 1. " RO_INVFIELD ,Invert field" "No effect,Inverted" textline " " bitfld.long 0x00 0. " RO_HZERO_SEL ,Horizontal shift" "No effect,Shifted" line.long 0x04 "VDEC_HSIGS,HSync Ignore Start Register" hexmask.long.byte 0x04 0.--7. 1. " RV_IGNORESTART ,Ignore start" line.long 0x08 "VDEC_HSIGE,HSync Ignore End Register" hexmask.long.byte 0x08 0.--7. 1. " RV_IGNOREEND ,Ignore end" line.long 0x0C "VSCON1,VSync Control 1 Register" bitfld.long 0x0C 7. " RH_8OR16 ,Vsync detector" "New (16 long),Old (shorter)" bitfld.long 0x0C 6. " RH_MODADD_DIS ,Debug" "0,1" textline " " bitfld.long 0x0C 5. " RH_VSYNCHALFMODE ,Vsync half mode" "Disabled,Enabled" bitfld.long 0x0C 4. " RH_DIS_VSYNCDETECT ,Vsync detection disable" "No,Yes" textline " " bitfld.long 0x0C 3. " RH_ROBUST625DET ,Robust 625 detection" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " RH_VDET_DBG ,Vsync debug mode" "Predicted location of Vsync,High when a new Vphase is set in the IP,Very simple Vsync detector,High when several valid Vsyncs in a row are detected,High when this field's possible Vsync phases are looked at,The many detected Vsyncs,High when twice as many Vsync phases are matching,Low-pass filtered luma falling edge detector" line.long 0x10 "VDEC_VSCON2,VSync Control 2 Register" bitfld.long 0x10 7. " RH_DISABLE_HSW ,Head switch detection disable" "No,Yes" bitfld.long 0x10 6. " RH_SMOOTH_HSW ,Headswitch smoothing" "One new line,Average of 4 lines" textline " " bitfld.long 0x10 4.--5. " RH_HSW_CORING ,Headswitch coring value" "0,1,2,3" bitfld.long 0x10 2.--3. " RH_VCR_FORCE_DIS ,Override VCR detect mode" "Automatic detection,Disable VCR detection,Force VCR mode,?..." textline " " bitfld.long 0x10 0.--1. " RH_VCR_PHASETHR ,VCR detection threshold" "0,1,2,3" group.long 0x6C++0x07 line.long 0x00 "VDEC_YCDEL,Y/C Delay and Chroma Debug Register" bitfld.long 0x00 4.--7. " RD_LUMADEL ,Luma delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " RD_WIDE ,Wide mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RD_NARROW ,Narrow mode" "Disabled,Enabled" bitfld.long 0x00 0. " RD_NOPALAVE ,No PAL averaging" "PAL averaging,No PAL averaging" line.long 0x04 "VDEC_AFTCLP,After Clamp Register" bitfld.long 0x04 6. " RC_AOUTOAFTERCLAMP_DIS ,Auto after clamp disable" "No,Yes" bitfld.long 0x04 5. " RC_MIDFIELD_DIS ,Midfield update disable" "No,Yes" textline " " bitfld.long 0x04 4. " RC_AFTERCLAMP_UPDATE_EN ,After clamp update enable" "Disabled,Enabled" bitfld.long 0x04 2. " RL_RESETOFFSET ,Reset offset" "No reset,Reset" textline " " bitfld.long 0x04 1. " RL_DISOFFSET ,Disable offset" "No,Yes" bitfld.long 0x04 0. " RH_SHORTFRAME ,Short frame" "0,1" group.long 0x78++0x03 line.long 0x00 "VDEC_DCOFF,DC Offset Register" bitfld.long 0x00 4.--6. " RL_DCOFFSETP ,DC offset proportional gain" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " RL_LINEMEASURE_DIS ,Line measure disable" "No,Yes" textline " " bitfld.long 0x00 0.--1. " RL_DCOFFSETI ,DC offset integrator gain" "0,1,2,3" group.long 0x84++0x1B line.long 0x00 "VDEC_CSID,Chroma Swap Invert and Debug Register" bitfld.long 0x00 7. " RD_BYPASSHILBERT ,Bypass hilbert" "Disabled,Enabled" bitfld.long 0x00 3. " RD_NOPALHUE ,PAL hue disable" "No,Yes" textline " " bitfld.long 0x00 2. " RD_INVCB ,Invert Cb" "Not inverted,Inverted" bitfld.long 0x00 1. " RD_INVCR ,Invert Cr" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " RD_SWAPCRCB ,Swap Cr CB" "Not swapped,Swapped" line.long 0x04 "VDEC_CBGN,Cb Gain Register" hexmask.long.byte 0x04 0.--7. 1. " RD_CBGAIN ,Cb gain" line.long 0x08 "VDEC_CRGN,Cr Gain Register" hexmask.long.byte 0x08 0.--7. 1. " RD_CRGAIN ,Cr gain" line.long 0x0C "CNTR,Contrast Register" hexmask.long.byte 0x0C 0.--7. 1. " RD_LUMAGAIN ,Contrast" line.long 0x10 "VDEC_BRT,Brightness Register" hexmask.long.byte 0x10 0.--7. 1. " RC_BLACKLEVEL ,Brightness" line.long 0x14 "VDEC_HUE,Hue Register" hexmask.long.byte 0x14 0.--7. 1. " RD_CH_THRESH ,Hue" line.long 0x18 "VDEC_CHBTH,Chroma Burst Threshold Register" hexmask.long.byte 0x18 0.--7. 1. " RD_CH_THRESH ,Chroma burst threshold" group.long 0xA4++0x07 line.long 0x00 "VDEC_SHPIMP,Sharpness Improvement Register" bitfld.long 0x00 4.--7. " RD_SLOPE ,Slope" "No effect,Positive slope compensation,Positive slope compensation,Positive slope compensation,Positive slope compensation,Positive slope compensation,Positive slope compensation,Positive slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation" bitfld.long 0x00 0.--3. " RD_PEAK ,Peak" "0(No sharpness),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Maximum sharpness)" line.long 0x04 "VDEC_CHPLLIM,Chroma PLL and Input Mode Register" bitfld.long 0x04 4.--6. " RD_CHLOCK_ATTEN ,Chroma lock attenuation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " RD_LOCKED_FORCE ,Locked force" "Not forced,Forced" textline " " bitfld.long 0x04 0.--2. " RD_INPUTCABLES ,Input cables" "CVBS,,2,,4,,6,?..." rgroup.long 0xAC++0x0B line.long 0x00 "VDEC_VIDMOD,Video Mode Register" bitfld.long 0x00 7. " PAL ,PAL detected" "Not detected,Detected" bitfld.long 0x00 6. " F443 ,4.43MHz chroma detected" "Not detected,Detected" textline " " bitfld.long 0x00 4. " M625 ,625 mode" "Disabled,Enabled" bitfld.long 0x00 3. " CH_LOCKED ,Chroma locked" "Not locked,Locked" textline " " bitfld.long 0x00 2. " CHROMA ,Chroma carrier detected" "Not detected,Detected" bitfld.long 0x00 1. " HLOCKED ,Hsync locked" "Not locked,Locked" textline " " bitfld.long 0x00 0. " HAVESIGNAL ,Have signal" "Not detected,Detected" line.long 0x04 "VDEC_VIDSTS,Video Status Register" bitfld.long 0x04 2. " VCRDETECT ,VCR detected" "Not detected,Detected" bitfld.long 0x04 1. " NONARITH3D ,Nonarithmetic 3D ratio" "Not detected,Detected" textline " " bitfld.long 0x04 0. " NONARITH ,Invalid nonarithmetic ratio" "Not detected,Detected" line.long 0x08 "VDEC_NOISE,Noise Detector Register" hexmask.long.byte 0x08 0.--7. 1. " NOISE ,Noise detector" group.long 0xB8++0x07 line.long 0x00 "VDEC_STDDBG,Standards and Debug Register" bitfld.long 0x00 7. " RD_FC_MAUAL ,Manual carrier frequency" "Disabled,Enabled" bitfld.long 0x00 6. " NTSCJ ,NTSC keep pedestal" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " FORCE_2DNTSC443 ,Force 2D NTSC 443" "Not forced,Forced" bitfld.long 0x00 3. " FORCE_HAVESIGNAL ,Force have signal" "Not forced,Forced" textline " " bitfld.long 0x00 0.--1. " STANDARD_FILTER ,Standard filter" "0,1,2,3" line.long 0x04 "VDEC_MANOVR,Manual Override Register" bitfld.long 0x04 7. " PAL_OVERRIDE ,PAL override" "No override,Override" bitfld.long 0x04 6. " F443_OVERRIDE ,443 override" "No override,Override" textline " " bitfld.long 0x04 4. " LINE625_OVERRIDE ,Line 625 override" "No override,Override" bitfld.long 0x04 3. " PAL_MANUAL ,PAL manual override" "No override,Override" textline " " bitfld.long 0x04 2. " FOUR43_MANUAL ,443 manual override" "No override,Override" bitfld.long 0x04 0. " MANUAL_625 ,Manual 625" "No override,Override" group.long 0xC8++0x03 line.long 0x00 "VDEC_VSSGTH,VSync and Signal Thresholds Register" bitfld.long 0x00 4.--7. " RH_VSYNCLENGTH ,Vsync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " NOSIGTHRESH ,No signal threshold" "0,1,2,3,4,5,6,7" group.long 0xD0++0x17 line.long 0x00 "VDEC_DBGFBH,Debug Framebuffer Register" bitfld.long 0x00 0.--1. " CLAMP_DELAYH ,Clamp delay high" "0,1,2,3" line.long 0x04 "VDEC_DBGFBL,Debug Framebuffer 2 Register" hexmask.long.byte 0x04 0.--7. 1. " CLAMP_DELAYL ,Clamp delay low" line.long 0x08 "VDEC_HACTS,H Active Start Register" hexmask.long.byte 0x08 0.--7. 1. " RO_HACTIVESTART ,H active start" line.long 0x0C "HACTE,H Active End Register" hexmask.long.byte 0x0C 0.--7. 1. " RO_HACTIVEEND ,H active end" line.long 0x10 "VDEC_VACTS,V Active Start Register" hexmask.long.byte 0x10 0.--7. 1. " RO_VACTIVESTART ,V active start" line.long 0x14 "VDEC_VACTE,V Active End Register" hexmask.long.byte 0x14 0.--7. 1. " RO_VACTIVEEND ,V active end" group.long 0xEC++0x03 line.long 0x00 "VDEC_HSTIP,HSync Tip Register" hexmask.long.byte 0x00 0.--7. 1. " RH_TIPGATE_START ,Tip gate start" group.long 0xF8++0x07 line.long 0x00 "VDEC_BLSCRCR,Bluescreen Cr Register" hexmask.long.byte 0x00 0.--7. 1. " BLUESCREEN_CR ,Bluescreen Cr" line.long 0x04 "VDEC_BLSCRCB,Bluescreen Cb Register" hexmask.long.byte 0x04 0.--7. 1. " BLUESCREEN_CB ,Bluescreen Cb" group.long 0x104++0x03 line.long 0x00 "VDEC_LMAGC2,Luma AGC Control 2 Register" hexmask.long.byte 0x00 0.--7. 1. " RAGC_TARGET ,AGC target" group.long 0x10C++0x03 line.long 0x00 "VDEC_CHAGC2,Chroma AGC Control 2 Register" hexmask.long.byte 0x00 0.--7. 1. " RD_CHAGC_TARGET ,Chroma AGC target" group.long 0x114++0x03 line.long 0x00 "VDEC_MINTH,Minimum Threshold Register" hexmask.long.byte 0x00 0.--7. 1. " MINTHRESH ,Minimum threshold" rgroup.long 0x11C++0x07 line.long 0x00 "VDEC_VFRQOH,Vertical Lines High Register" bitfld.long 0x00 0.--3. " VFREQO ,Vertical frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VDEC_VFRQOL,Vertical Lines Low Register" hexmask.long.byte 0x04 0.--7. 1. " VFREQO ,Vertical frequency" group.long 0x320++0x03 line.long 0x00 "VDEC_ASYNCLKFREQ1,Asynchronous Clock Frequency 1 Register" hexmask.long.byte 0x00 0.--7. 1. " ASYNCHCLK_FREQUENCY ,Constantly set the master asynchronous clock frequency" group.long 0x324++0x03 line.long 0x00 "VDEC_ASYNCLKFREQ2,Asynchronous Clock Frequency 2 Register" hexmask.long.byte 0x00 0.--7. 1. " ASYNCHCLK_FREQUENCY ,Constantly set the master asynchronous clock frequency" group.long 0x328++0x03 line.long 0x00 "VDEC_ASYNCLKFREQ3,Asynchronous Clock Frequency 3 Register" hexmask.long.byte 0x00 0.--7. 1. " ASYNCHCLK_FREQUENCY ,Constantly set the master asynchronous clock frequency" group.long 0x32C++0x03 line.long 0x00 "VDEC_ASYNCLKFREQ4,Asynchronous Clock Frequency 4 Register" hexmask.long.byte 0x00 0.--7. 1. " ASYNCHCLK_FREQUENCY ,Constantly set the master asynchronous clock frequency" width 0x0B else base ad:0x4222C000 width 19. group.long 0x00++0x03 line.long 0x00 "VDEC_CFC1,2D Comb Filter Control 1 Register" bitfld.long 0x00 4.--7. " RC_DEBUGOUT ,Debug mode" "Full 2D comb filter,Vertical adaptive comb only,Fixed 3 line vertical comb only,Fixed notch filter only,?..." bitfld.long 0x00 3. " RC_COMBMODE_OVERRIDE[3] ,Comb mode override bit Force PAL 2D comb mode" "Not forced,Forced" textline " " bitfld.long 0x00 2. " [2] ,Comb mode override bit Force 4.43 MHz comb filters" "Not forced,Forced" bitfld.long 0x00 0. " [0] ,Comb mode override bit Enable override" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "VDEC_BRSTGT,Burst Gate Register" hexmask.long.byte 0x00 0.--7. 1. " RC_CBURSTSTART ,Burst start position" group.long 0x40++0x07 line.long 0x00 "VDEC_HZPOS,Horizontal Position Register" hexmask.long.byte 0x00 0.--7. 1. " RO_HPRAMP_CMP ,Horizontal Position" line.long 0x04 "VDEC_VRTPOS,Vertical Position Register" hexmask.long.byte 0x04 0.--7. 1. " RO_VLINE_CMP ,Vertical Position" group.long 0x54++0x13 line.long 0x00 "VDEC_HVSHFT,Output Conditioning and HV Shift Register" bitfld.long 0x00 6. " ANTIALIAS_DIS ,Anti-alias disable" "No,Yes" bitfld.long 0x00 5. " RO_USEACTIVE ,Use active" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " RO_VZERO_SEL ,Vertical shift" "No effect,Shifted" bitfld.long 0x00 1. " RO_INVFIELD ,Invert field" "No effect,Inverted" textline " " bitfld.long 0x00 0. " RO_HZERO_SEL ,Horizontal shift" "No effect,Shifted" line.long 0x04 "VDEC_HSIGS,HSync Ignore Start Register" hexmask.long.byte 0x04 0.--7. 1. " RV_IGNORESTART ,Ignore start" line.long 0x08 "VDEC_HSIGE,HSync Ignore End Register" hexmask.long.byte 0x08 0.--7. 1. " RV_IGNOREEND ,Ignore end" line.long 0x0C "VSCON1,VSync Control 1 Register" bitfld.long 0x0C 7. " RH_8OR16 ,Vsync detector" "New (16 long),Old (shorter)" bitfld.long 0x0C 6. " RH_MODADD_DIS ,Debug" "0,1" textline " " bitfld.long 0x0C 5. " RH_VSYNCHALFMODE ,Vsync half mode" "Disabled,Enabled" bitfld.long 0x0C 4. " RH_DIS_VSYNCDETECT ,Vsync detection disable" "No,Yes" textline " " bitfld.long 0x0C 3. " RH_ROBUST625DET ,Robust 625 detection" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " RH_VDET_DBG ,Vsync debug mode" "Predicted location of Vsync,High when a new Vphase is set in the IP,Very simple Vsync detector,High when several valid Vsyncs in a row are detected,High when this field's possible Vsync phases are looked at,The many detected Vsyncs,High when twice as many Vsync phases are matching,Low-pass filtered luma falling edge detector" line.long 0x10 "VDEC_VSCON2,VSync Control 2 Register" bitfld.long 0x10 7. " RH_DISABLE_HSW ,Head switch detection disable" "No,Yes" bitfld.long 0x10 6. " RH_SMOOTH_HSW ,Headswitch smoothing" "One new line,Average of 4 lines" textline " " bitfld.long 0x10 4.--5. " RH_HSW_CORING ,Headswitch coring value" "0,1,2,3" bitfld.long 0x10 2.--3. " RH_VCR_FORCE_DIS ,Override VCR detect mode" "Automatic detection,Disable VCR detection,Force VCR mode,?..." textline " " bitfld.long 0x10 0.--1. " RH_VCR_PHASETHR ,VCR detection threshold" "0,1,2,3" group.long 0x6C++0x07 line.long 0x00 "VDEC_YCDEL,Y/C Delay and Chroma Debug Register" bitfld.long 0x00 4.--7. " RD_LUMADEL ,Luma delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " RD_WIDE ,Wide mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RD_NARROW ,Narrow mode" "Disabled,Enabled" bitfld.long 0x00 0. " RD_NOPALAVE ,No PAL averaging" "PAL averaging,No PAL averaging" line.long 0x04 "VDEC_AFTCLP,After Clamp Register" bitfld.long 0x04 6. " RC_AOUTOAFTERCLAMP_DIS ,Auto after clamp disable" "No,Yes" bitfld.long 0x04 5. " RC_MIDFIELD_DIS ,Midfield update disable" "No,Yes" textline " " bitfld.long 0x04 4. " RC_AFTERCLAMP_UPDATE_EN ,After clamp update enable" "Disabled,Enabled" bitfld.long 0x04 2. " RL_RESETOFFSET ,Reset offset" "No reset,Reset" textline " " bitfld.long 0x04 1. " RL_DISOFFSET ,Disable offset" "No,Yes" bitfld.long 0x04 0. " RH_SHORTFRAME ,Short frame" "0,1" group.long 0x78++0x03 line.long 0x00 "VDEC_DCOFF,DC Offset Register" bitfld.long 0x00 4.--6. " RL_DCOFFSETP ,DC offset proportional gain" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " RL_LINEMEASURE_DIS ,Line measure disable" "No,Yes" textline " " bitfld.long 0x00 0.--1. " RL_DCOFFSETI ,DC offset integrator gain" "0,1,2,3" group.long 0x84++0x1B line.long 0x00 "VDEC_CSID,Chroma Swap Invert and Debug Register" bitfld.long 0x00 7. " RD_BYPASSHILBERT ,Bypass hilbert" "Disabled,Enabled" bitfld.long 0x00 3. " RD_NOPALHUE ,PAL hue disable" "No,Yes" textline " " bitfld.long 0x00 2. " RD_INVCB ,Invert Cb" "Not inverted,Inverted" bitfld.long 0x00 1. " RD_INVCR ,Invert Cr" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " RD_SWAPCRCB ,Swap Cr CB" "Not swapped,Swapped" line.long 0x04 "VDEC_CBGN,Cb Gain Register" hexmask.long.byte 0x04 0.--7. 1. " RD_CBGAIN ,Cb gain" line.long 0x08 "VDEC_CRGN,Cr Gain Register" hexmask.long.byte 0x08 0.--7. 1. " RD_CRGAIN ,Cr gain" line.long 0x0C "CNTR,Contrast Register" hexmask.long.byte 0x0C 0.--7. 1. " RD_LUMAGAIN ,Contrast" line.long 0x10 "VDEC_BRT,Brightness Register" hexmask.long.byte 0x10 0.--7. 1. " RC_BLACKLEVEL ,Brightness" line.long 0x14 "VDEC_HUE,Hue Register" hexmask.long.byte 0x14 0.--7. 1. " RD_CH_THRESH ,Hue" line.long 0x18 "VDEC_CHBTH,Chroma Burst Threshold Register" hexmask.long.byte 0x18 0.--7. 1. " RD_CH_THRESH ,Chroma burst threshold" group.long 0xA4++0x07 line.long 0x00 "VDEC_SHPIMP,Sharpness Improvement Register" bitfld.long 0x00 4.--7. " RD_SLOPE ,Slope" "No effect,Positive slope compensation,Positive slope compensation,Positive slope compensation,Positive slope compensation,Positive slope compensation,Positive slope compensation,Positive slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation,Negative slope compensation" bitfld.long 0x00 0.--3. " RD_PEAK ,Peak" "0(No sharpness),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Maximum sharpness)" line.long 0x04 "VDEC_CHPLLIM,Chroma PLL and Input Mode Register" bitfld.long 0x04 4.--6. " RD_CHLOCK_ATTEN ,Chroma lock attenuation" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " RD_LOCKED_FORCE ,Locked force" "Not forced,Forced" textline " " bitfld.long 0x04 0.--2. " RD_INPUTCABLES ,Input cables" "CVBS,,2,,4,,6,?..." rgroup.long 0xAC++0x0B line.long 0x00 "VDEC_VIDMOD,Video Mode Register" bitfld.long 0x00 7. " PAL ,PAL detected" "Not detected,Detected" bitfld.long 0x00 6. " F443 ,4.43MHz chroma detected" "Not detected,Detected" textline " " bitfld.long 0x00 4. " M625 ,625 mode" "Disabled,Enabled" bitfld.long 0x00 3. " CH_LOCKED ,Chroma locked" "Not locked,Locked" textline " " bitfld.long 0x00 2. " CHROMA ,Chroma carrier detected" "Not detected,Detected" bitfld.long 0x00 1. " HLOCKED ,Hsync locked" "Not locked,Locked" textline " " bitfld.long 0x00 0. " HAVESIGNAL ,Have signal" "Not detected,Detected" line.long 0x04 "VDEC_VIDSTS,Video Status Register" bitfld.long 0x04 2. " VCRDETECT ,VCR detected" "Not detected,Detected" bitfld.long 0x04 1. " NONARITH3D ,Nonarithmetic 3D ratio" "Not detected,Detected" textline " " bitfld.long 0x04 0. " NONARITH ,Invalid nonarithmetic ratio" "Not detected,Detected" line.long 0x08 "VDEC_NOISE,Noise Detector Register" hexmask.long.byte 0x08 0.--7. 1. " NOISE ,Noise detector" group.long 0xB8++0x07 line.long 0x00 "VDEC_STDDBG,Standards and Debug Register" bitfld.long 0x00 7. " RD_FC_MAUAL ,Manual carrier frequency" "Disabled,Enabled" bitfld.long 0x00 6. " NTSCJ ,NTSC keep pedestal" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " FORCE_2DNTSC443 ,Force 2D NTSC 443" "Not forced,Forced" bitfld.long 0x00 3. " FORCE_HAVESIGNAL ,Force have signal" "Not forced,Forced" textline " " bitfld.long 0x00 0.--1. " STANDARD_FILTER ,Standard filter" "0,1,2,3" line.long 0x04 "VDEC_MANOVR,Manual Override Register" bitfld.long 0x04 7. " PAL_OVERRIDE ,PAL override" "No override,Override" bitfld.long 0x04 6. " F443_OVERRIDE ,443 override" "No override,Override" textline " " bitfld.long 0x04 4. " LINE625_OVERRIDE ,Line 625 override" "No override,Override" bitfld.long 0x04 3. " PAL_MANUAL ,PAL manual override" "No override,Override" textline " " bitfld.long 0x04 2. " FOUR43_MANUAL ,443 manual override" "No override,Override" bitfld.long 0x04 0. " MANUAL_625 ,Manual 625" "No override,Override" group.long 0xC8++0x03 line.long 0x00 "VDEC_VSSGTH,VSync and Signal Thresholds Register" bitfld.long 0x00 4.--7. " RH_VSYNCLENGTH ,Vsync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " NOSIGTHRESH ,No signal threshold" "0,1,2,3,4,5,6,7" group.long 0xD0++0x17 line.long 0x00 "VDEC_DBGFBH,Debug Framebuffer Register" bitfld.long 0x00 0.--1. " CLAMP_DELAYH ,Clamp delay high" "0,1,2,3" line.long 0x04 "VDEC_DBGFBL,Debug Framebuffer 2 Register" hexmask.long.byte 0x04 0.--7. 1. " CLAMP_DELAYL ,Clamp delay low" line.long 0x08 "VDEC_HACTS,H Active Start Register" hexmask.long.byte 0x08 0.--7. 1. " RO_HACTIVESTART ,H active start" line.long 0x0C "HACTE,H Active End Register" hexmask.long.byte 0x0C 0.--7. 1. " RO_HACTIVEEND ,H active end" line.long 0x10 "VDEC_VACTS,V Active Start Register" hexmask.long.byte 0x10 0.--7. 1. " RO_VACTIVESTART ,V active start" line.long 0x14 "VDEC_VACTE,V Active End Register" hexmask.long.byte 0x14 0.--7. 1. " RO_VACTIVEEND ,V active end" group.long 0xEC++0x03 line.long 0x00 "VDEC_HSTIP,HSync Tip Register" hexmask.long.byte 0x00 0.--7. 1. " RH_TIPGATE_START ,Tip gate start" group.long 0xF8++0x07 line.long 0x00 "VDEC_BLSCRCR,Bluescreen Cr Register" hexmask.long.byte 0x00 0.--7. 1. " BLUESCREEN_CR ,Bluescreen Cr" line.long 0x04 "VDEC_BLSCRCB,Bluescreen Cb Register" hexmask.long.byte 0x04 0.--7. 1. " BLUESCREEN_CB ,Bluescreen Cb" group.long 0x104++0x03 line.long 0x00 "VDEC_LMAGC2,Luma AGC Control 2 Register" hexmask.long.byte 0x00 0.--7. 1. " RAGC_TARGET ,AGC target" group.long 0x10C++0x03 line.long 0x00 "VDEC_CHAGC2,Chroma AGC Control 2 Register" hexmask.long.byte 0x00 0.--7. 1. " RD_CHAGC_TARGET ,Chroma AGC target" group.long 0x114++0x03 line.long 0x00 "VDEC_MINTH,Minimum Threshold Register" hexmask.long.byte 0x00 0.--7. 1. " MINTHRESH ,Minimum threshold" rgroup.long 0x11C++0x07 line.long 0x00 "VDEC_VFRQOH,Vertical Lines High Register" bitfld.long 0x00 0.--3. " VFREQO ,Vertical frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VDEC_VFRQOL,Vertical Lines Low Register" hexmask.long.byte 0x04 0.--7. 1. " VFREQO ,Vertical frequency" group.long 0x320++0x03 line.long 0x00 "VDEC_ASYNCLKFREQ1,Asynchronous Clock Frequency 1 Register" hexmask.long.byte 0x00 0.--7. 1. " ASYNCHCLK_FREQUENCY ,Constantly set the master asynchronous clock frequency" group.long 0x324++0x03 line.long 0x00 "VDEC_ASYNCLKFREQ2,Asynchronous Clock Frequency 2 Register" hexmask.long.byte 0x00 0.--7. 1. " ASYNCHCLK_FREQUENCY ,Constantly set the master asynchronous clock frequency" group.long 0x328++0x03 line.long 0x00 "VDEC_ASYNCLKFREQ3,Asynchronous Clock Frequency 3 Register" hexmask.long.byte 0x00 0.--7. 1. " ASYNCHCLK_FREQUENCY ,Constantly set the master asynchronous clock frequency" group.long 0x32C++0x03 line.long 0x00 "VDEC_ASYNCLKFREQ4,Asynchronous Clock Frequency 4 Register" hexmask.long.byte 0x00 0.--7. 1. " ASYNCHCLK_FREQUENCY ,Constantly set the master asynchronous clock frequency" width 0x0B endif tree.end tree.end tree.open "WDOG (Watchdog)" tree "WDOG-1" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020BC000 else base ad:0x420BC000 endif width 6. group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog 1 Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Time-out Field" bitfld.word 0x00 7. " WDW ,Watchdog Disable for Wait" "Continues,Suspended" textline " " sif (cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpuis("IMX6SLX*"))||(cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")||(cpu()=="IMX6SOLOLITE") bitfld.word 0x00 6. " SRE ,Software reset extension" "Original,Extended" textline " " endif bitfld.word 0x00 5. " WDA ,WDOG assertion" "Asserted,No effect" bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect" bitfld.word 0x00 3. " WDT ,WDOG Time-out assertion" "No effect,Asserted" textline " " bitfld.word 0x00 2. " WDE ,Watchdog Enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG Enable" "Continues,Suspended" bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Continues,Suspended" line.word 0x02 "WSR,Watchdog 1 Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog 1 Reset Status Register" bitfld.word 0x00 4. " POR ,Power On Reset" "No reset,Reset" bitfld.word 0x00 1. " TOUT ,Time-out" "No reset,Reset" bitfld.word 0x00 0. " SFTW ,Software Reset" "No reset,Reset" group.word 0x06++0x03 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog Timer Interrupt Enable" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog Timer Interrupt Status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog Interrupt Count Time-out " line.word 0x02 "WMCR,Watchdog 1 Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power Down Enable" "Disabled,Enabled" width 0x0B tree.end tree "WDOG-2" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020C0000 else base ad:0x420C0000 endif width 6. group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog 2 Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Time-out Field" bitfld.word 0x00 7. " WDW ,Watchdog Disable for Wait" "Continues,Suspended" textline " " sif (cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpuis("IMX6SLX*"))||(cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")||(cpu()=="IMX6SOLOLITE") bitfld.word 0x00 6. " SRE ,Software reset extension" "Original,Extended" textline " " endif bitfld.word 0x00 5. " WDA ,WDOG assertion" "Asserted,No effect" bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect" bitfld.word 0x00 3. " WDT ,WDOG Time-out assertion" "No effect,Asserted" textline " " bitfld.word 0x00 2. " WDE ,Watchdog Enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG Enable" "Continues,Suspended" bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Continues,Suspended" line.word 0x02 "WSR,Watchdog 2 Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog 2 Reset Status Register" bitfld.word 0x00 4. " POR ,Power On Reset" "No reset,Reset" bitfld.word 0x00 1. " TOUT ,Time-out" "No reset,Reset" bitfld.word 0x00 0. " SFTW ,Software Reset" "No reset,Reset" group.word 0x06++0x03 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog Timer Interrupt Enable" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog Timer Interrupt Status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog Interrupt Count Time-out " line.word 0x02 "WMCR,Watchdog 2 Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power Down Enable" "Disabled,Enabled" width 0x0B tree.end tree "WDOG-3" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x02288000 else base ad:0x42288000 endif width 6. group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog 3 Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Time-out Field" bitfld.word 0x00 7. " WDW ,Watchdog Disable for Wait" "Continues,Suspended" textline " " sif (cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpuis("IMX6SLX*"))||(cpu()=="IMX6ULTRALITE")||(cpu()=="IMX6ULL")||(cpu()=="IMX6SOLOLITE") bitfld.word 0x00 6. " SRE ,Software reset extension" "Original,Extended" textline " " endif bitfld.word 0x00 5. " WDA ,WDOG assertion" "Asserted,No effect" bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect" bitfld.word 0x00 3. " WDT ,WDOG Time-out assertion" "No effect,Asserted" textline " " bitfld.word 0x00 2. " WDE ,Watchdog Enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG Enable" "Continues,Suspended" bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Continues,Suspended" line.word 0x02 "WSR,Watchdog 3 Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog 3 Reset Status Register" bitfld.word 0x00 4. " POR ,Power On Reset" "No reset,Reset" bitfld.word 0x00 1. " TOUT ,Time-out" "No reset,Reset" bitfld.word 0x00 0. " SFTW ,Software Reset" "No reset,Reset" group.word 0x06++0x03 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog Timer Interrupt Enable" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog Timer Interrupt Status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog Interrupt Count Time-out " line.word 0x02 "WMCR,Watchdog 3 Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power Down Enable" "Disabled,Enabled" width 0x0B tree.end tree.end tree "XTALOSC (Crystal Oscillator)" sif (cpu()=="IMX6SOLOX-CA9") base ad:0x020C8150 else base ad:0x420C8150 endif width 19. group.long 0x00++0x03 line.long 0x00 "MISC0,Miscellaneous Register 0" bitfld.long 0x00 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "Div by 1,Div by 2" bitfld.long 0x00 30. " XTAL_24M_PWD ,24M crystal oscillator power down" "No,Yes" bitfld.long 0x00 29. " RTC_XTAL_SOURCE ,This field indicates which chip source is being used for the rtc clock" "Internal,RTX_XTAL" textline " " bitfld.long 0x00 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and release the clock to the digital logic inside the analog block" "0.5ms,1.0ms,2.0ms,3.0ms,4.0ms,5.0ms,6.0ms,7.0ms" bitfld.long 0x00 25. " CLKGATE_CTRL ,Disabling the clock gate" "No,Yes" bitfld.long 0x00 18.--19. " WBCP_VPW_THRESH ,Alters the voltage that the pwell is charged pumped to" "Nominal voltage,Increase by 25mV,Decrease by 25mV,Decrease by 50mV" textline " " bitfld.long 0x00 17. " OSC_XTALOK_EN ,Enable bit for the xtal_ok module (24 MHz)" "Disabled,Enabled" rbitfld.long 0x00 16. " OSC_XTALOK ,Status of output of the 24MHz crystal oscillator" "Not stable,Stable" bitfld.long 0x00 14.--15. " OSC_I ,Determines the bias current in the 24MHz oscillator" "Nominal,-12.5%,-25.0%,-37.5%" textline " " bitfld.long 0x00 12. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode" "All powered down (except RTC),Certain powered-up" textline " " bitfld.long 0x00 7. " REFTOP_VBGUP ,Status of the analog bandgap voltage" "Not stable,Stable" bitfld.long 0x00 4.--6. " REFTOP_VBGADJ ,Analog bandgap voltage adjustment" "Nominal,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" textline " " bitfld.long 0x00 3. " REFTOP_SELFBIASOFF ,Disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x00 0. " REFTOP_PWD ,Power-down the analog bandgap reference circuitry" "Not set,Set" textline " " group.long 0x120++0x0F line.long 0x00 "LOWPWR_CTRL,LP Control Register" bitfld.long 0x00 18. " GPU_PWRGATE ,GPU power gate control" "Not gated,Gated" bitfld.long 0x00 17. " MIX_PWRGATE ,Display power gate control" "Not gated,Gated" rbitfld.long 0x00 16. " XTALOSC_PWRUP_STAT ,Display power gate control" "Not stable,Stable" bitfld.long 0x00 11. " DISPLAY_PWRGATE ,Display logic power gate control" "Not gated,Gated" textline " " bitfld.long 0x00 10. " CPU_PWRGATE ,CPU power gate control" "Not gated,Gated" bitfld.long 0x00 9. " L2_PWRGATE ,L2 power gate control" "Not gated,Gated" bitfld.long 0x00 8. " L1_PWRGATE ,L1 power gate control" "Not gated,Gated" bitfld.long 0x00 7. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No,Yes" textline " " bitfld.long 0x00 6. " LPBG_TEST ,Low power bandgap test bit" "0,1" bitfld.long 0x00 5. " LPBG_SEL ,Bandgap select" "Normal,Low power" bitfld.long 0x00 4. " OSC_SEL ,Select the source for the 24MHz clock" "XTAL,RC" bitfld.long 0x00 1.--3. " RC_OSC_PROG ,RC osc. tuning values" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " RC_OSC_EN ,RC Osc. enable control" "Disabled,Enabled" line.long 0x04 "LOWPWR_CTRL_SET,LP Control Register Set" bitfld.long 0x04 18. " GPU_PWRGATE ,GPU power gate control" "No effect,Set" bitfld.long 0x04 17. " MIX_PWRGATE ,Display power gate control" "No effect,Set" rbitfld.long 0x04 16. " XTALOSC_PWRUP_STAT ,Display power gate control" "No effect,Set" bitfld.long 0x04 11. " DISPLAY_PWRGATE ,Display logic power gate control" "No effect,Set" textline " " bitfld.long 0x04 10. " CPU_PWRGATE ,CPU power gate control" "No effect,Set" bitfld.long 0x04 9. " L2_PWRGATE ,L2 power gate control" "No effect,Set" bitfld.long 0x04 8. " L1_PWRGATE ,L1 power gate control" "No effect,Set" bitfld.long 0x04 7. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No effect,Set" textline " " bitfld.long 0x04 6. " LPBG_TEST ,Low power bandgap test bit" "No effect,Set" bitfld.long 0x04 5. " LPBG_SEL ,Bandgap select" "Normal,Low power" bitfld.long 0x04 4. " OSC_SEL ,Select the source for the 24MHz clock" "No effect,Set" bitfld.long 0x04 1.--3. " RC_OSC_PROG ,RC osc. tuning values" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 0. " RC_OSC_EN ,RC Osc. enable control" "No effect,Set" line.long 0x08 "LOWPWR_CTRL_CLR,LP Control Register Clear" bitfld.long 0x08 18. " GPU_PWRGATE ,GPU power gate control" "No effect,Cleared" bitfld.long 0x08 17. " MIX_PWRGATE ,Display power gate control" "No effect,Cleared" rbitfld.long 0x08 16. " XTALOSC_PWRUP_STAT ,Display power gate control" "No effect,Cleared" bitfld.long 0x08 11. " DISPLAY_PWRGATE ,Display logic power gate control" "No effect,Cleared" textline " " bitfld.long 0x08 10. " CPU_PWRGATE ,CPU power gate control" "No effect,Cleared" bitfld.long 0x08 9. " L2_PWRGATE ,L2 power gate control" "No effect,Cleared" bitfld.long 0x08 8. " L1_PWRGATE ,L1 power gate control" "No effect,Cleared" bitfld.long 0x08 7. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No effect,Cleared" textline " " bitfld.long 0x08 6. " LPBG_TEST ,Low power bandgap test bit" "No effect,Cleared" bitfld.long 0x08 5. " LPBG_SEL ,Bandgap select" "Normal,Low power" bitfld.long 0x08 4. " OSC_SEL ,Select the source for the 24MHz clock" "No effect,Cleared" bitfld.long 0x08 1.--3. " RC_OSC_PROG ,RC osc. tuning values" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 0. " RC_OSC_EN ,RC Osc. enable control" "No effect,Cleared" line.long 0x0C "LOWPWR_CTRL_TOG,LP Control Register Toggle" bitfld.long 0x0C 18. " GPU_PWRGATE ,GPU power gate control" "No effect,Toggled" bitfld.long 0x0C 17. " MIX_PWRGATE ,Display power gate control" "No effect,Toggled" rbitfld.long 0x0C 16. " XTALOSC_PWRUP_STAT ,Display power gate control" "No effect,Toggled" bitfld.long 0x0C 11. " DISPLAY_PWRGATE ,Display logic power gate control" "No effect,Toggled" textline " " bitfld.long 0x0C 10. " CPU_PWRGATE ,CPU power gate control" "No effect,Toggled" bitfld.long 0x0C 9. " L2_PWRGATE ,L2 power gate control" "No effect,Toggled" bitfld.long 0x0C 8. " L1_PWRGATE ,L1 power gate control" "No effect,Toggled" bitfld.long 0x0C 7. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No effect,Toggled" textline " " bitfld.long 0x0C 6. " LPBG_TEST ,Low power bandgap test bit" "No effect,Toggled" bitfld.long 0x0C 5. " LPBG_SEL ,Bandgap select" "Normal,Low power" bitfld.long 0x0C 4. " OSC_SEL ,Select the source for the 24MHz clock" "No effect,Toggled" bitfld.long 0x0C 1.--3. " RC_OSC_PROG ,RC osc. tuning values" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 0. " RC_OSC_EN ,RC Osc. enable control" "No effect,Toggled" group.long 0x150++0x3F line.long 0x00 "CONFIG0,Configuration 0 Register" hexmask.long.byte 0x00 25.--31. 1. " RC_OSC_PROG_CUR ,The current tuning value in use" bitfld.long 0x00 16.--19. " HYST_MINUS ,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " HYST_PLUS ,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 4.--11. 1. " RC_OSC_PROG ,RC osc. tuning values" textline " " bitfld.long 0x00 3. " INVERT ,Invert the stepping of the calculated RC tuning value" "0,1" bitfld.long 0x00 2. " BYPASS ,Bypasses any calculated RC tuning value and uses the programmed register value" "0,1" bitfld.long 0x00 1. " ENABLE ,Enables the tuning logic to calculate new RC tuning values" "0,1" bitfld.long 0x00 0. " START ,Start/stop bit for the RC tuning calculation logic" "0,1" line.long 0x04 "CONFIG0_SET,Configuration 0 Register Set" hexmask.long.byte 0x04 25.--31. 1. " RC_OSC_PROG_CUR ,The current tuning value in use" bitfld.long 0x04 16.--19. " HYST_MINUS ,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " HYST_PLUS ,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 4.--11. 1. " RC_OSC_PROG ,RC osc. tuning values" textline " " bitfld.long 0x04 3. " INVERT ,Invert the stepping of the calculated RC tuning value" "No effect,Set" bitfld.long 0x04 2. " BYPASS ,Bypasses any calculated RC tuning value and uses the programmed register value" "No effect,Set" bitfld.long 0x04 1. " ENABLE ,Enables the tuning logic to calculate new RC tuning values" "No effect,Set" bitfld.long 0x04 0. " START ,Start/stop bit for the RC tuning calculation logic" "No effect,Set" line.long 0x08 "CONFIG0_CLR,Configuration 0 Register Clear" hexmask.long.byte 0x08 25.--31. 1. " RC_OSC_PROG_CUR ,The current tuning value in use" bitfld.long 0x08 16.--19. " HYST_MINUS ,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 12.--15. " HYST_PLUS ,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 4.--11. 1. " RC_OSC_PROG ,RC osc. tuning values" textline " " bitfld.long 0x08 3. " INVERT ,Invert the stepping of the calculated RC tuning value" "No effect,Cleared" bitfld.long 0x08 2. " BYPASS ,Bypasses any calculated RC tuning value and uses the programmed register value" "No effect,Cleared" bitfld.long 0x08 1. " ENABLE ,Enables the tuning logic to calculate new RC tuning values" "No effect,Cleared" bitfld.long 0x08 0. " START ,Start/stop bit for the RC tuning calculation logic" "No effect,Cleared" line.long 0x0C "CONFIG0_CLR,Configuration 0 Register Toggle" hexmask.long.byte 0x0C 25.--31. 1. " RC_OSC_PROG_CUR ,The current tuning value in use" bitfld.long 0x0C 16.--19. " HYST_MINUS ,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 12.--15. " HYST_PLUS ,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 4.--11. 1. " RC_OSC_PROG ,RC osc. tuning values" textline " " bitfld.long 0x0C 3. " INVERT ,Invert the stepping of the calculated RC tuning value" "No effect,Toggled" bitfld.long 0x0C 2. " BYPASS ,Bypasses any calculated RC tuning value and uses the programmed register value" "No effect,Toggled" bitfld.long 0x0C 1. " ENABLE ,Enables the tuning logic to calculate new RC tuning values" "No effect,Toggled" bitfld.long 0x0C 0. " START ,Start/stop bit for the RC tuning calculation logic" "No effect,Toggled" line.long 0x10 "CONFIG1,Configuration 1 Register" hexmask.long.word 0x10 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x10 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x14 "CONFIG1_SET,Configuration 1 Register Set" hexmask.long.word 0x14 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x14 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x18 "CONFIG1_CLR,Configuration 1 Register Clear" hexmask.long.word 0x18 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x18 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x1C "CONFIG1_TOG,Configuration 1 Register Toggle" hexmask.long.word 0x1C 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x1C 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x20 "CONFIG2,Configuration 2 Register" bitfld.long 0x20 31. " CLK_1M_ERR_FL ,Flag indicates that the count_1m count wasn't reached within 1 32KHz period" "0,1" bitfld.long 0x20 17. " MUX_1M ,Mux the corrected or uncorrected 1MHz clock to the output" "0,1" bitfld.long 0x20 16. " ENABLE_1M ,Enable the 1MHz clock output" "Disabled,Enabled" hexmask.long.word 0x20 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" line.long 0x24 "CONFIG2_SET,Configuration 2 Register Set" bitfld.long 0x24 31. " CLK_1M_ERR_FL ,Flag indicates that the count_1m count wasn't reached within 1 32KHz period" "No effect,Set" bitfld.long 0x24 17. " MUX_1M ,Mux the corrected or uncorrected 1MHz clock to the output" "No effect,Set" bitfld.long 0x24 16. " ENABLE_1M ,Enable the 1MHz clock output" "No effect,Set" hexmask.long.word 0x24 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" line.long 0x28 "CONFIG2_CLR,Configuration 2 Register Clear" bitfld.long 0x28 31. " CLK_1M_ERR_FL ,Flag indicates that the count_1m count wasn't reached within 1 32KHz period" "No effect,Cleared" bitfld.long 0x28 17. " MUX_1M ,Mux the corrected or uncorrected 1MHz clock to the output" "No effect,Cleared" bitfld.long 0x28 16. " ENABLE_1M ,Enable the 1MHz clock output" "No effect,Cleared" hexmask.long.word 0x28 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" line.long 0x2C "CONFIG2_CLR,Configuration 2 Register Toggle" bitfld.long 0x2C 31. " CLK_1M_ERR_FL ,Flag indicates that the count_1m count wasn't reached within 1 32KHz period" "No effect,Toggled" bitfld.long 0x2C 17. " MUX_1M ,Mux the corrected or uncorrected 1MHz clock to the output" "No effect,Toggled" bitfld.long 0x2C 16. " ENABLE_1M ,Enable the 1MHz clock output" "No effect,Toggled" hexmask.long.word 0x2C 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" width 0xB tree.end textline ""