; -------------------------------------------------------------------------------- ; @Title: iMX6SLL On-Chip Peripherals ; @Props: Released ; @Author: MSU, KOF ; @Changelog: 2019-01-16 KOF ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: IMX6SLL_RM_Rev0.pdf (Rev. 0, 2017-06) ; DDI0431C_tzasc_tzc380_r0p1_trm.pdf (Rev. r0p1, 2010-07) ; @Core: Cortex-A9 ; @Chip: IMX6SLL ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perimx6sll.per 15964 2023-04-13 11:46:29Z bschroefel $ config 16. 8. tree "Core Registers (Cortex-A9MPCore)" width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x0++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" textline " " bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x200++0x0 line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register" rgroup.long c15:0x300++0x0 line.long 0x0 "TLBTR,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries" bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128" textline " " bitfld.long 0x0 0. " nU ,Unified or Separate TLBs" "Unified,Separate" rgroup.long c15:0x500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 8.--11. " ClusterID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "0,1,2,3" rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..." bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported" bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Not supported,Supported,?..." rgroup.long c15:0x0020++0x00 line.long 0x00 "ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..." tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " PARON ,Parity On" "Disabled,Enabled" bitfld.long 0x00 8. " ALIOW ,Enable allocation in one cache way only" "Disabled,Enabled" bitfld.long 0x00 7. " EXCL ,Exclusive cache Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SMP ,Signals if the Cortex-A9 processor is taking part in coherency or not" "0,1" bitfld.long 0x00 3. " FOZ ,Full Of Zero mode Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DP1 ,L1 Dside prefetch Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PH2 ,L2 prefetch hint Enable" "Disabled,Enabled" bitfld.long 0x00 0. " FW ,Cache and TLB maintenance broadcast" "Disabled,Enabled" group.long c15:0x201++0x0 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x11++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 6. " nET ,Not early termination" "Not early,Early" bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" textline " " bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group.long c15:0x111++0x0 line.long 0x0 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted" bitfld.long 0x00 16. " PLE ,NS accesses to the Preload Engine resources control" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register" "No,Yes" bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted" group.long c15:0x0311++0x00 line.long 0x00 "VCR,Virtualization Control Register" bitfld.long 0x00 8. " AMO ,Abort Mask Override" "0,1" bitfld.long 0x00 7. " IMO ,IRQ Mask Override" "0,1" bitfld.long 0x00 6. " IFO ,FIQ Mask Override" "0,1" group.long c15:0xf++0x0 line.long 0x00 "PCR,Power Control Register" bitfld.long 0x00 8.--10. " MCL ,Max Clock Latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EDCG ,Enable Dynamic Clock Gating" "Disabled,Enabled" textline " " group.long c15:0x000c++0x00 line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address" group.long c15:0x10c++0x00 line.long 0x0 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address" rgroup.long c15:0x1C++0x0 line.long 0x0 "ISR,Interrupt status Register" bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending" bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending" bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending" group.long c15:0x11c++0x0 line.long 0x00 "VIR,Virtualization Interrupt Register" bitfld.long 0x00 8. " VA ,Virtual Abort" "0,1" bitfld.long 0x00 7. " VI ,Virtual IRQ" "0,1" bitfld.long 0x00 6. " VF ,Virtual FIQ" "0,1" tree.end width 0x0d tree "Memory Management Unit" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" textline " " group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address" bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" textline " " bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address" bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" textline " " bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable" bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable" bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000" textline " " group.long c15:0x3--0x3 line.long 0x0 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" hexmask.long 0x00 0.--31. 1. " DFA ,Data Fault Address" group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " SD ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" hexmask.long 0x00 0.--31. 1. " IFA ,Instruction Fault Address" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" hexmask.long 0x00 0.--31. 1. " DAFS ,Data Auxiliary Fault Status" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,AuxiliaryInstruction Fault Status Register" hexmask.long 0x00 0.--31. 1. " IAFS ,Instruction Auxiliary Fault Status" textline " " group.long c15:0xa++0x0 line.long 0x0 "TLBLR,TLB Lockdown Register" bitfld.long 0x0 28.--29. " VICTIM ,Victim Value Increments after Each Tabel Walk" "0,1,2,3" bitfld.long 0x0 0. " P ,Lockdown by Victim or Set Associative Region of TLB" "Associative,Lockdown" group.long c15:0x0047++0x00 line.long 0x00 "PAR,PA Register" hexmask.long 0x00 12.--31. 0x1000 " PA ,Physical Adress" bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable" textline " " bitfld.long 0x00 9. " NS ,Non-secure" "Not secured,Secured" bitfld.long 0x00 7. " SH ,Shareable attribute" "Non-shareable,Shareable" textline " " bitfld.long 0x00 4.--6. " Inner ,Signals region inner attributes" "Noncacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back allocate,Write-through,Write-back" bitfld.long 0x00 2.--3. " Outer ,Signals region outer attributes for normal memory type" "Noncacheable,Write-back allocate,Write-through,Write-back" textline " " bitfld.long 0x00 1. " SS ,Supersection Enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " F ,Translation Successful" "Successful,No successful" textline " " group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attribute 7" "Outer,Inner" bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attribute 6" "Outer,Inner" textline " " bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attribute 5" "Outer,Inner" bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attribute 4" "Outer,Inner" textline " " bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attribute 3" "Outer,Inner" bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attribute 2" "Outer,Inner" textline " " bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attribute 1" "Outer,Inner" bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attribute 0" "Outer,Inner" textline " " bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " group.long c15:0x400f++0x0 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long 0x00 0.--31. 1. " CBA ,Configuration Base Address" textline " " rgroup.long c15:0x000d++0x00 line.long 0x00 "FCSEIDR,FCSE PID Register" hexmask.long.byte 0x00 25.--31. 0x02 " PID ,Process for Fast Context Switch Identification and Specification" group.long c15:0x10d++0x0 line.long 0x0 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID" hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID" group.long c15:0x020d++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRURW ,User Read/Write Thread ID" group.long c15:0x030d++0x00 line.long 0x00 "TPIDRURO,User Read-only Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRURO ,User Read-only Thread ID" group.long c15:0x040d++0x00 line.long 0x00 "TPIDRPRW,Privileged Only Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRPRW ,Privileged Only Thread ID" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 18.--20. " CType7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 15.--17. " CType6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 12.--14. " CType5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 9.--11. " CType4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 6.--8. " CType3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 3.--5. " CType2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 0.--2. " CType1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words" group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction" tree.end width 12. tree "System Performance Monitor" group.long c15:0xC9++0x0 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled" group.long c15:0x1C9++0x0 line.long 0x0 "PMCNTENSET,Count Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x2C9++0x0 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x3C9++0x0 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. " P4 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4C9++0x0 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 5. " P5 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 4. " P4 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" textline " " eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x5C9++0x0 line.long 0x0 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--5. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,CNT4,CNT5,?..." group.long c15:0xD9++0x0 line.long 0x00 "PMCCNTR,Cycle Count Register" hexmask.long 0x00 0.--31. 1. " CCNT ,Cycle Count" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Select Register" hexmask.long.byte 0x00 0.--7. 1. " EVCNT ,Event to count" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" hexmask.long 0x00 0.--31. 1. " PMNX ,Event Count" group.long c15:0xE9++0x0 line.long 0x0 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled" group.long c15:0x1E9++0x0 line.long 0x0 "PMINTENSET,Interrupt Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2E9++0x0 line.long 0x0 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" tree.end width 8. tree "Preload Engine" rgroup.long c15:0x000b++0x00 line.long 0x00 "PLEIDR,PLE ID Register" bitfld.long 0x00 16.--20. " FIFOS ,PLE FIFO size" "Not present,Reserved,Reserved,Reserved,4,Reserved,Reserved,Reserved,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,?..." bitfld.long 0x00 0. " PEP ,Preload Engine presence" "Not present,Present" rgroup.long c15:0x020b++0x00 line.long 0x00 "PLEASR,PLE Activity Status Register" bitfld.long 0x00 0. " R ,PLE Channel running" "Not running,Running" rgroup.long c15:0x040b++0x00 line.long 0x00 "PLEFSR,PLE FIFO Status Register" bitfld.long 0x00 0.--4. " AE ,Number of available entries in the PLE FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x001b++0x00 line.long 0x00 "PLEUAR,Preload Engine User Accessibility Register" bitfld.long 0x00 0. " U ,User accessibility" "Not permited,Permited" group.long c15:0x011b++0x00 line.long 0x00 "PLEPCR,Preload Engine Parameters Control Register" hexmask.long.word 0x00 16.--29. 1. " BSM ,Block size mask" hexmask.long.byte 0x00 8.--15. 1. " BNM ,Block number mask" hexmask.long.byte 0x00 0.--7. 1. " WS ,PLE wait states" tree.end tree "NEON" rgroup.long c15:0x000f++0x00 line.long 0x00 "NEON,NEON busy Register" bitfld.long 0x00 0. " Busy ,NEON busy" "Not busy,Busy" tree.end width 0xb width 9. tree "Debug Registers" tree "Jazelle Register" group.long c14:0x7000++0x0 line.long 0x00 "JIDR,Jazelle ID Register" bitfld.long 0x00 28.--31. " ARCH ,Architecture code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DESIGN ,Implementor code of the designer of the subarchitecture" textline " " hexmask.long.byte 0x00 12.--19. 1. " SAMAJ ,The subarchitecture code" bitfld.long 0x00 8.--11. " SAMIN ,The subarchitecture minor code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6. " TRTBFR ,Format of the Jazelle Configurable Opcode Translation Table Register" "0,1" bitfld.long 0x00 0.--5. " TRTBSZ ,Size of the Jazelle Configurable Opcode Translation Table Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long c14:0x7001++0x0 line.long 0x00 "JOSCR,Jazelle OS Control Register" bitfld.long 0x00 1. " CV ,Configuration Valid" "Not valid,Valid" bitfld.long 0x00 0. " CD ,Configuration Disabled" "No,Yes" group.long c14:0x7002++0x0 line.long 0x00 "JMCR,Jazelle Main Configuration Register" bitfld.long 0x00 31. " nAR ,Not Array Operations" "Disabled,Enabled" bitfld.long 0x00 30. " FP ,Floating-point opcodes handler" "VM implementation,VFP instructions" bitfld.long 0x00 29. " AP ,Array Pointer" "Handler,Pointer" textline " " bitfld.long 0x00 28. " OP ,Object Pointer" "Handler,Pointer" bitfld.long 0x00 27. " IS ,Index Size" "8 bits,16 bits" bitfld.long 0x00 26. " SP ,Static Pointer" "Handler,Pointer" textline " " bitfld.long 0x00 0. " JE ,Jazelle Enable" "Disabled,Enabled" group.long c14:0x7003++0x0 line.long 0x00 "JPR,Jazelle Parameters Register" bitfld.long 0x00 17.--21. " BSH ,Bounds SHift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " sADO ,Signed Array Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " ARO ,Array Reference Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " STO ,STatic Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ODO ,Object Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long c14:0x7004++0x0 line.long 0x00 "JCOTTRR,Jazelle Configurable Opcode Translation Table Register" bitfld.long 0x00 10.--15. " OPCODE ,Bottom bits of the configurable opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " OPERATION ,Code for the operation" "0,1,2,3,4,5,6,7,8,9,?..." tree.end width 11. tree "Processor Identifier Registers" rgroup c14:0x340--0x340 line.long 0x00 "CPUID,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup c14:0x341--0x341 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DMinLine ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." textline " " bitfld.long 0x00 14.--15. " L1_Ipolicy ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " IMinLine ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup c14:0x343--0x343 line.long 0x00 "TLBTYPE,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILsize ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLsize ,Specifies the number of unified or data TLB lockable entries" textline " " bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128" bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate" rgroup c14:0x348--0x348 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..." rgroup c14:0x349--0x349 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..." rgroup c14:0x34a--0x34a line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..." rgroup c14:0x34c--0x34c line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..." textline " " bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..." rgroup c14:0x34d--0x34d line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup c14:0x34e--0x34e line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." rgroup c14:0x34f--0x34f line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup c14:0x350--0x350 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..." rgroup c14:0x351--0x351 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..." rgroup c14:0x352--0x352 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..." rgroup c14:0x353--0x353 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..." rgroup c14:0x354--0x354 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..." tree.end tree "Coresight Management Registers" width 0xC textline " " group c14:0x3c0--0x3c0 line.long 0x0 "ITCTRL,Integration Mode Control Register" bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group c14:0x3e8--0x3e8 line.long 0x0 "CLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set" group c14:0x3e9--0x3e9 line.long 0x0 "CLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared" wgroup c14:0x3ec--0x3ec line.long 0x0 "LAR,Lock Access Register" hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key" rgroup c14:0x3ed--0x3ed line.long 0x0 "LSR,Lock Status Register" bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed" bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored" textline " " bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required" width 0xc rgroup c14:0x3ee--0x3ee line.long 0x0 "AUTHSTATUS,Authentication Status Register" bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented" bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented" bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented" bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented" bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled" width 0xc rgroup c14:0x3f2--0x3f2 line.long 0x0 "DEVID,Device Identifier" bitfld.long 0x00 0.--3. " PCSAMPLE ,Level of Program Counter sampling support (DBGPCSR and DBGCIDSR)" "Not implemented,DBGPCSR,Both,?..." rgroup c14:0x3f3--0x3f3 line.long 0x0 "DEVTYPE,Device Type" hexmask.long.byte 0x0 4.--7. 1. " STPC ,Sub Type: Processor Core" hexmask.long.byte 0x0 0.--3. 1. " MCDL ,Main Class: Debug Logic" rgroup c14:0x3f8--0x3f8 line.long 0x0 "PID0,Peripherial ID0" hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]" rgroup c14:0x3f9--0x3f9 line.long 0x0 "PID1,Peripherial ID1" hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]" hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]" rgroup c14:0x3fa--0x3fa line.long 0x0 "PID2,Peripherial ID2" hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " JEPCD ,JEP 106 ID code" "Not used,Used" textline " " hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]" rgroup c14:0x3fb--0x3fb line.long 0x0 "PID3,Peripherial ID3" hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd" hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified" rgroup c14:0x3f4--0x3f4 line.long 0x0 "PID4,Peripherial ID4" bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" rgroup c14:0x3fc--0x3fc line.long 0x0 "COMPONENTID0,Component ID0" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3fd--0x3fd line.long 0x0 "COMPONENTID1,Component ID1" hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)" hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble" rgroup c14:0x3fe--0x3fe line.long 0x0 "COMPONENTID2,Component ID2" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3ff--0x3ff line.long 0x0 "COMPONENTID3,Component ID3" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" tree.end textline " " width 0x7 rgroup c14:0x000--0x000 line.long 0x0 "DIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x0 16.--19. " Version ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,ARMv7 no ext.,?..." textline " " bitfld.long 0x0 15. " DEVID_IMP ,Debug Device ID Register DBGDEVID implemented" "Not implemented,Implemented" bitfld.long 0x0 14. " NSUHD_IMP ,Secure User halting debug implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 13. " PCSR_IMP ,Program Counter Sampling Register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " SE_IMP ,Security Extensions implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 4.--7. " Variant ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " Revision ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x7 group c14:0x22--0x22 line.long 0x0 "DSCR,Debug Status and Control Register" bitfld.long 0x0 30. " DTRRXfull ,The DTRRX Full Flag" "Empty,Full" bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full" textline " " bitfld.long 0x00 27. " DTRRXfull_l ,The DTRRX Full Flag 1" "Empty,Full" bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full" textline " " bitfld.long 0x0 25. " PIPEADV ,Sticky Pipeline Advance" "No effect,Instruction retired" bitfld.long 0x0 24. " INSTRCOMPL_L ,Latched Instruction Complete" "Executing,Not executing" textline " " bitfld.long 0x0 20.--21. " EXTDCCMODE ,External DCC access mode" "Non-blocking,Stall,Fast,?..." bitfld.long 0x0 19. " ADADISCARD ,Asynchronous Data Aborts Discarded" "Not discarded,Discarded" textline " " bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured" bitfld.long 0x0 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disabled" "No,Yes" textline " " bitfld.long 0x0 16. " SPIDDIS ,Secure Privileged Invasive Debug Disabled" "No,Yes" bitfld.long 0x0 15. " MDBGEN ,Monitor Debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled" bitfld.long 0x0 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " UDCCDIS ,User mode access to Comms Channel disable" "No,Yes" bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "No,Yes" textline " " bitfld.long 0x0 10. " DbgAck ,Force Debug Acknowledge" "Not forced,Forced" bitfld.long 0x0 8. " UND_l ,Sticky Undefined Instruction" "No exception,Exception" textline " " bitfld.long 0x0 7. " ADABORT_l ,Sticky Asynchronous Data Abort" "Not aborted,Aborted" bitfld.long 0x0 6. " SDABORT_l ,Sticky Synchronous Data Abort" "Not aborted,Aborted" textline " " bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Halt request,Breakpoint,Asynchronous Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited" textline " " bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state" width 0x7 if (((data.long(c14:0x00))&0x01000)==0x00000) group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled" bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" else group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled" bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled" bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" endif ;rgroup c14:0x1++0x1 ; line.long 0x0 "DRAR,Debug ROM Address Register" ; hexmask.long 0x0 12.--31. 0x1000 " DBROMPA ,Debug bus ROM physical address" ; bitfld.long 0x0 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid" ; line.long 0x4 "DSAR,Debug Self Address Offset Register" ; hexmask.long 0x4 12.--31. 0x1000 " DBSAOV ,Debug bus self-address offset value" ; bitfld.long 0x4 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid" ;hgroup c14:0x50++0x0 ; hide.long 0x0 "DTR,Data Transfer Register" ; in width 0x7 hgroup c14:0x020--0x020 hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register" in group c14:0x023--0x023 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" wgroup c14:0x21++0x00 line.long 0x00 "ITR,Instruction Transfer Register" hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute" wgroup c14:0x24++0x00 line.long 0x00 "DRCR,Debug Run Control Register" bitfld.long 0x00 4. " CBIUR , Cancel Bus Interface Unit Requests" "Not canceled,Canceled" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared" bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested" rgroup c14:0xc4++0x00 line.long 0x00 "PRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 2. " HNDLR ,Hold non-debug logic reset" "No reset,Reset" bitfld.long 0x00 1. " WRR ,Warm reset request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high" hgroup c14:0xc5++0x00 hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register" in tree.end width 6. tree "Breakpoint Registers" group c14:0x40++0x00 line.long 0x00 "BVR0,Breakpoint Value Register 0" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group c14:0x50++0x00 line.long 0x00 "BCR0,Breakpoint Control Register 0" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x41++0x00 line.long 0x00 "BVR1,Breakpoint Value Register 1" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group c14:0x51++0x00 line.long 0x00 "BCR1,Breakpoint Control Register 1" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x42++0x00 line.long 0x00 "BVR2,Breakpoint Value Register 2" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group c14:0x52++0x00 line.long 0x00 "BCR2,Breakpoint Control Register 2" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x43++0x00 line.long 0x00 "BVR3,Breakpoint Value Register 3" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group c14:0x53++0x00 line.long 0x00 "BCR3,Breakpoint Control Register 3" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x44++0x00 line.long 0x00 "BVR4,Breakpoint Value Register 4" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group c14:0x54++0x00 line.long 0x00 "BCR4,Breakpoint Control Register 4" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x45++0x00 line.long 0x00 "BVR5,Breakpoint Value Register 5" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group c14:0x55++0x00 line.long 0x00 "BCR5,Breakpoint Control Register 5" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end width 6. tree "Watchpoint Control Registers" group c14:0x60++0x00 line.long 0x00 "WVR0,Watchpoint Value Register 0" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group c14:0x70--0x70 line.long 0x0 "WCR0,Watchpoint Control Register 0" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x61++0x00 line.long 0x00 "WVR1,Watchpoint Value Register 1" hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1" group c14:0x71--0x71 line.long 0x0 "WCR1,Watchpoint Control Register 1" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x62++0x00 line.long 0x00 "WVR2,Watchpoint Value Register 2" hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2" group c14:0x72--0x72 line.long 0x0 "WCR2,Watchpoint Control Register 2" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x63++0x00 line.long 0x00 "WVR3,Watchpoint Value Register 3" hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3" group c14:0x73--0x73 line.long 0x0 "WCR3,Watchpoint Control Register 3" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x006--0x006 line.long 0x0 "WFAR,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction" tree.end width 0xb width 9. base ad:(d.l(c15:0x400f)) tree "Snoop Control Unit (SCU)" group.long 0x00++0x03 line.long 0x00 "SCUCR,SCU Control Register" bitfld.long 0x00 6. " ICSE ,IC standby enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCUSE ,SCU standby enable" "Disabled,Enabled" bitfld.long 0x00 4. " FADTP0E ,Force all Device to port0 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SCUSLE ,SCU Speculative linefills enable" "Disabled,Enabled" bitfld.long 0x00 2. " SCURPE ,SCU RAMs Parity enable" "Disabled,Enabled" bitfld.long 0x00 1. " AFE ,Address filtering enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SCUE ,SCU enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SCUCON,SCU Configuration Register" bitfld.long 0x00 14.--15. " RAM3 ,Cortex-A9 CPU3 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 12.--13. " RAM2 ,Cortex-A9 CPU2 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 10.--11. " RAM1 ,Cortex-A9 CPU1 Tag RAM Size" "16KB,32KB,64KB,?..." textline " " bitfld.long 0x00 8.--9. " RAM0 ,Cortex-A9 CPU0 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 7. " MOD3 ,CPU3 Mode" "AMP,SMP" bitfld.long 0x00 6. " MOD2 ,CPU2 Mode" "AMP,SMP" textline " " bitfld.long 0x00 5. " MOD1 ,CPU1 Mode" "AMP,SMP" bitfld.long 0x00 4. " MOD0 ,CPU0 Mode" "AMP,SMP" bitfld.long 0x00 0.--1. " NUM ,CPU Number" "CPU0,CPU0-CPU1,CPU0-CPU2,CPU0-CPU3" group.long 0x08++0x03 line.long 0x00 "SCUSTAT,SCU CPU Power Status Register" bitfld.long 0x00 24.--25. " STAT3 ,CPU3 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 16.--17. " STAT2 ,CPU2 Status" "Normal,Reserved,Dormant,Powered-off" textline " " bitfld.long 0x00 8.--9. " STAT1 ,CPU1 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 0.--1. " STAT0 ,CPU0 Status" "Normal,Reserved,Dormant,Powered-off" wgroup.long 0x0c++0x03 line.long 0x00 "INV,SCU Invalidate All Register" bitfld.long 0x00 12.--15. " WAY3 ,Cortex-A9 CPU3 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " WAY2 ,Cortex-A9 CPU2 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " WAY1 ,Cortex-A9 CPU1 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " WAY0 ,Cortex-A9 CPU0 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x03 line.long 0x00 "FSAR,Filtering Start Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FSA ,Filtering start address" group.long 0x44++0x03 line.long 0x00 "FEAR,Filtering End Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FEA ,Filtering end address" group.long 0x50++0x03 line.long 0x00 "SAC,SCU Access Control Register" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" group.long 0x54++0x03 line.long 0x00 "SSAC,SCU Secure Access Control Register" bitfld.long 0x00 11. " GCPU3 ,Global timer for CPU3" "Secure only,Secure/Non-secure" bitfld.long 0x00 10. " GCPU2 ,Global timer for CPU2" "Secure only,Secure/Non-secure" bitfld.long 0x00 9. " GCPU1 ,Global timer for CPU1" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 8. " GCPU0 ,Global timer for CPU0" "Secure only,Secure/Non-secure" bitfld.long 0x00 7. " TCPU3 ,Private timer for CPU3 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 6. " TCPU2 ,Private timer for CPU2 Access" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 5. " TCPU1 ,Private timer for CPU1 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 4. " TCPU0 ,Private timer for CPU0 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" tree.end width 0xb width 8. tree "Timer and Watchdog Blocks" base ad:(d.l(c15:0x400f))+0x600 group.long 0x00++0xb "Timer" line.long 0x00 "TLR,Timer Load Register" line.long 0x04 "TCR,Timer Counter Register" line.long 0x08 "TCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " AREL ,Auto reload" "Single shot,Auto-reload" bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "TISR,Timer Interrupt Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x20++0x13 "Watchdog" line.long 0x00 "WLR,Watchdog Load Register" line.long 0x04 "WCR,Watchdog Counter Register" line.long 0x08 "WCONR,Watchdog Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " WDM ,WD Mode" "Timer,Watchdog" bitfld.long 0x08 2. " ITEN ,IT Enable" "Disabled,Enabled" bitfld.long 0x08 1. " AREL ,Auto-Reload" "Single shot,Auto-reload" textline " " bitfld.long 0x08 0. " WEN ,Watchdog Enable" "Disabled,Enabled" line.long 0x0c "WISR,Watchdog Interrupt Status Register" eventfld.long 0x0C 0. " EFLAG ,Event Flag" "0,1" line.long 0x10 "WRSR,Watchdog Reset Sent Register" eventfld.long 0x10 0. " RFLAG ,Reset Flag" "No effect,Reset" wgroup.long 0x34++0x3 line.long 0x00 "WDR,Watchdog Disable Register" base ad:(d.l(c15:0x400f))+0x200 group.long 0x00++0xb "Global Timer" line.long 0x00 "GTLCR,Lower 32-bit Timer Counter Register" line.long 0x04 "GTUCR,Upper 32-bit Timer Counter Register" line.long 0x08 "GTCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "GTSR,Timer Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x10++0xb line.long 0x00 "GTLCOMR,Lower 32-bit Comparator Register" line.long 0x04 "GTUCOMR,Upper 32-bit Comparator Register" line.long 0x08 "GTINCR,Auto-increment Register for Comparator" tree.end width 11. tree.open "Interrupt Controller (GIC-400)" width 17. base AD:(data.long(c15:0x400F)&0xffff8000)+0x1000 tree "Distributor Interface" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400) rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" else rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" endif rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure) width 17. tree "Group/Security Registers" group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x0E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x0F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)==0x1F) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1" else hgroup.long 0x00FC++0x03 hide.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end endif width 24. tree "Set/Clear Enable Registers" group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)==0x1F) group.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled" else hgroup.long 0x017C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 22. tree "Set/Clear Pending Registers" group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Disabled,Enabled" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Disabled,Enabled" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Disabled,Enabled" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Disabled,Enabled" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Disabled,Enabled" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Disabled,Enabled" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Disabled,Enabled" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Disabled,Enabled" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Disabled,Enabled" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Disabled,Enabled" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Disabled,Enabled" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Disabled,Enabled" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Disabled,Enabled" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Disabled,Enabled" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Disabled,Enabled" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Disabled,Enabled" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Disabled,Enabled" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Disabled,Enabled" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Disabled,Enabled" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Disabled,Enabled" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Disabled,Enabled" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Disabled,Enabled" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Disabled,Enabled" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Disabled,Enabled" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Disabled,Enabled" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Disabled,Enabled" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Disabled,Enabled" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Disabled,Enabled" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Disabled,Enabled" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Disabled,Enabled" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Disabled,Enabled" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)==0x1F) group.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Disabled,Enabled" else hgroup.long 0x027C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 24. tree "Set/Clear Active Registers" group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " hgroup.long 0x037C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER31,Interrupt Set/Clear Active Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " tree.end width 20. tree "Priority Registers" group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1F) group.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 " group.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 " group.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000" group.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004" group.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008" group.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012" group.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016" else hgroup.long 0x7E0++0x03 hide.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hgroup.long 0x7E4++0x03 hide.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hgroup.long 0x7E8++0x03 hide.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hgroup.long 0x7EC++0x03 hide.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hgroup.long 0x7F0++0x03 hide.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hgroup.long 0x7F4++0x03 hide.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hgroup.long 0x7F8++0x03 hide.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" endif tree.end width 19. tree "Processor Targets Registers" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x000000E0)>0x1) rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 " if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1F) group.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 " group.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 " group.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000" group.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004" group.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008" group.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012" group.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016" else hgroup.long 0xBE0++0x03 hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hgroup.long 0xBE4++0x03 hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hgroup.long 0xBE8++0x03 hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hgroup.long 0xBEC++0x03 hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hgroup.long 0xBF0++0x03 hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hgroup.long 0xBF4++0x03 hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hgroup.long 0xBF8++0x03 hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hgroup.long 0xBE0++0x03 hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hgroup.long 0xBE4++0x03 hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hgroup.long 0xBE8++0x03 hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hgroup.long 0xBEC++0x03 hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hgroup.long 0xBF0++0x03 hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hgroup.long 0xBF4++0x03 hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hgroup.long 0xBF8++0x03 hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif tree.end width 14. tree "Configuration Registers" hgroup.long 0xC00++0x03 hide.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" textline " " rgroup.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1F) group.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCF8++0x03 hide.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" hgroup.long 0xCFC++0x03 hide.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" endif tree.end width 12. tree "Peripheral Interrupt Status Registers" rgroup.long 0x0D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt" bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt" textline " " width 22. if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High" bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High" bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High" textline " " bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High" bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High" bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High" textline " " bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High" bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High" bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High" textline " " bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High" bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High" bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High" textline " " bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High" bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High" bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High" textline " " bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High" bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High" bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High" textline " " bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High" bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High" bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High" textline " " bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High" bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High" bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High" textline " " bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High" bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High" bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High" textline " " bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High" bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High" bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High" textline " " bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High" bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High" bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High" bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High" bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High" bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High" bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High" bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High" bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High" bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High" bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High" bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High" bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High" bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High" bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High" bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High" bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High" bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High" bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High" bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High" bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High" bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High" bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x03) rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High" bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High" bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High" bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High" bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High" bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High" bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High" bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High" bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High" bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High" bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High" bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High" bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High" bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High" bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High" bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High" bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High" bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High" bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High" bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High" bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High" bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High" bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High" bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High" bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High" bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High" bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High" bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High" bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High" bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High" bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High" bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High" bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High" bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High" bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High" bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High" bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High" bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High" bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High" bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High" bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High" bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High" bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High" bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High" bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High" bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High" bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High" bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High" bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High" bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High" bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High" bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High" bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High" bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High" bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High" bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High" bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High" bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High" bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High" bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High" bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High" bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High" bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High" bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High" bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High" bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High" bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High" bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High" bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High" bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High" bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High" bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High" bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High" bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High" bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High" bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High" bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High" bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High" bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High" bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High" bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High" bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High" bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High" bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High" bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x07) rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High" bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High" bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High" bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High" bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High" bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High" bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High" bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High" bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High" bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High" bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High" bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High" bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High" bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High" bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High" bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High" bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High" bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High" bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High" bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High" bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High" bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High" bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High" bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High" bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High" bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High" bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High" bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High" bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High" bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High" bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High" bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High" bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High" bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High" bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High" bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High" bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High" bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High" bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High" bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High" bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High" bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High" bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High" bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High" bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High" bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High" bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High" bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High" bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High" bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High" bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High" bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High" bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High" bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High" bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High" bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High" bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High" bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High" bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High" bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High" bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High" bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High" bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High" bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High" bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High" bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High" bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High" bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High" bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High" bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High" bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High" bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High" bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High" bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High" bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High" bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High" bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High" bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High" bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High" bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High" bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High" bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High" bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High" bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High" bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High" bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High" bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High" bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High" bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High" bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High" bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High" bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High" bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High" bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High" bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High" bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High" bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High" bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High" bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High" bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High" bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High" bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High" bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High" bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High" bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High" bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High" bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High" bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High" bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High" bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High" bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High" bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High" bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High" bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High" bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High" bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High" bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High" bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High" bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High" bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High" bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High" bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High" bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High" bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High" bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High" bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High" bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High" bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High" bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High" bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High" bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High" bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High" bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High" bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High" bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High" bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High" bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High" bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High" bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High" bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High" bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High" bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High" bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High" bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High" bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High" bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High" bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High" bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High" bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High" bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High" bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High" bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High" bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High" bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High" bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High" bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High" bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High" bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High" bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High" bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High" bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High" bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High" bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High" bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High" bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High" bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High" bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High" bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High" bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High" bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High" bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High" bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High" bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High" bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High" bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High" bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High" bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High" bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High" bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High" bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High" bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High" bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High" bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High" bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High" bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High" bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High" bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High" bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High" bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High" bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High" bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High" bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High" bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High" bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High" bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High" bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High" bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High" bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High" bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High" bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High" bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High" bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High" bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High" bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High" bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High" bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High" bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High" bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High" bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High" bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High" bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High" bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High" bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High" bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High" bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High" bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High" bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High" bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High" bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High" bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High" bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High" bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High" bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High" bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High" bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High" bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High" bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High" bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High" bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High" bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High" bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High" bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High" bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High" bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High" bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High" bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High" bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High" bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High" bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High" bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High" bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High" bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High" bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High" bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High" bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High" bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High" bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High" bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High" bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High" bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High" bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High" bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High" bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x13) rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High" bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High" bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High" bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High" bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High" bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High" bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High" bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High" bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High" bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High" bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High" bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High" bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High" bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High" bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High" bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High" bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High" bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High" bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High" bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High" bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High" bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High" bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High" bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High" bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High" bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High" bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High" bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High" bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High" bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High" bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High" bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High" bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High" bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High" bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High" bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High" bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High" bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High" bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High" bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High" bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High" bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High" bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High" bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High" bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High" bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High" bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High" bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High" bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High" bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High" bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High" bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High" bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High" bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High" bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High" bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High" bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High" bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High" bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High" bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High" bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High" bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High" bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High" bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High" bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High" bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High" bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High" bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High" bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High" bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High" bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High" bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High" bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High" bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High" bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High" bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High" bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High" bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High" bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High" bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High" bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High" bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High" bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High" bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High" bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x17) rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High" bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High" bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High" bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High" bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High" bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High" bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High" bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High" bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High" bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High" bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High" bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High" bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High" bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High" bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High" bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High" bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High" bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High" bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High" bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High" bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High" bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x18) rgroup.long 0x060++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High" bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High" bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High" bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High" bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High" bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High" bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High" bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High" bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High" bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High" bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High" bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High" bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High" bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High" bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High" bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High" bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High" bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High" bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High" bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High" bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High" bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High" bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High" bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High" bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High" bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High" bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High" bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High" bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High" bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High" bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High" bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High" bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High" bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High" bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High" bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High" bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High" bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High" bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High" bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High" bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High" bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High" bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High" bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High" bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High" bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High" bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High" bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High" bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High" bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High" bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High" bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High" bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High" bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High" bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High" bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High" bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High" bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High" bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High" bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High" bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High" bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High" bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High" bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High" bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High" bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High" bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High" bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High" bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High" bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High" bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High" bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High" bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High" bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High" bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High" bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High" bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High" bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High" bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High" bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High" bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High" bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High" bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High" bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High" bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High" bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High" bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High" bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High" bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High" bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High" bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High" bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High" bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High" bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High" bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High" bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High" bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High" bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High" bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High" bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High" bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High" bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High" bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High" bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High" bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High" bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High" bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High" bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High" bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High" bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High" bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High" bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High" bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High" bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High" bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High" bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High" bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High" bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High" bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High" bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High" bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High" bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High" bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High" bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High" bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High" bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High" bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High" bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High" bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High" bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High" bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High" bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High" bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High" bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High" bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High" bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High" bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High" bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High" bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High" bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High" bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High" bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High" bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High" bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High" bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High" bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High" bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High" bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x0000001F)>=0x1F) rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High" bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High" bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High" bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High" bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High" bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High" bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High" bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High" bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High" bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High" bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High" bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High" bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High" bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High" bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High" bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High" bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High" bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High" bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High" else hgroup.long 0x0D7C++0x03 hide.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400) wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x0F20++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR0,SGI Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F24++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR1,SGI Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F28++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F2C++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.byte 0x0FE0++0x00 line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.byte 0x00 0.--7. 1. " DEVID ,DevID field" rgroup.byte 0x0FE4++0x00 line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.byte 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FE8++0x00 line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.byte 0x00 4.--7. " ARCHREV ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High" bitfld.byte 0x00 0.--2. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7" rgroup.byte 0x0FEC++0x00 line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.byte 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD0++0x00 line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.byte 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.byte 0xFD4++0x00 hide.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.byte 0xFD8++0x00 hide.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.byte 0xFDC++0x00 hide.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register" textline " " rgroup.byte 0xFF0++0x00 line.byte 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF4++0x00 line.byte 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF8++0x00 line.byte 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFFC++0x00 line.byte 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " tree.end tree.end base AD:(data.long(c15:0x400F)&0xffff8000)+0x100 width 17. tree "CPU Interface" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x0) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " else group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " endif group.long 0x0004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400) group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif hgroup.long 0x000C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400) group.long 0x001C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else hgroup.long 0x001C++0x03 hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register" endif hgroup.long 0x0020++0x003 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400) wgroup.long 0x0024++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" else hgroup.long 0x0024++0x03 hide.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hgroup.long 0x0028++0x03 hide.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" endif group.long 0x00D0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register" if (((per.l(AD:(data.long(c15:0x400F)&0xffff8000)+0x1000+0x04))&0x400)==0x400) group.long 0x00E0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" else hgroup.long 0x00E0++0x03 hide.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" endif rgroup.long 0x00FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end sif CPU.FEATURE(hypervisor) base AD:0x0 width 12. tree "Virtual CPU Control Interface" group.long 0x0000++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Disable Group 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Enable Group 1 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " VGRP0DIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " VGRP0EIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" rgroup.long 0x0004++0x03 line.long 0x00 "GICH_VTR,VGIC Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..." textline " " bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..." textline " " bitfld.long 0x00 0.--5. " LISTREGS ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..." group.long 0x008++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" bitfld.long 0x00 27.--31. " VMPRIMASK ,Alias of GICV_PMR.Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--23. " VMBP ,Alias of GICV_BPR.Binary point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VMABP ,Alias of GICV_ABPR.Binary point" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9. " VEM ,Alias of GICV_CTLR.EOImode" "0,1" bitfld.long 0x00 4. " VMCBPR ,Alias of GICV_CTLR.CBPR" "0,1" bitfld.long 0x00 3. " VMFIQEN ,Alias of GICV_CTLR.FIQEn" "0,1" textline " " bitfld.long 0x00 2. " VMACKCTL ,Alias of GICV_CTLR.AckCtl" "0,1" bitfld.long 0x00 1. " VMGRP1EN ,Alias of GICV_CTLR.EnableGrp1" "0,1" bitfld.long 0x00 0. " VMGRP0EN ,Alias of GICV_CTLR.EnableGrp0" "0,1" rgroup.long 0x0010++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,Disabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " VGRP1E ,Enabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. " VGRP0D ,Disabled Group 0 maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " VGRP0E ,Enabled Group 0 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " U ,Underflow maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " EOI ,EOI maintenance interrupt" "No interrupt,Interrupt" rgroup.long 0x020++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x0030++0x03 line.long 0x00 "GICH_ELSR0,Empty List register Status Register" bitfld.long 0x00 3. " STATUS3 ,Emptiness status bit for List register 3" "Not empty,Empty" bitfld.long 0x00 2. " STATUS2 ,Emptiness status bit for List register 2" "Not empty,Empty" bitfld.long 0x00 1. " STATUS1 ,Emptiness status bit for List register 1" "Not empty,Empty" textline " " bitfld.long 0x00 0. " STATUS0 ,Emptiness status bit for List register 0" "Not empty,Empty" group.long 0x00F0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" if (((per.l(AD:0x0+0x100))&0x80000000)==0x80000000) group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(AD:0x0+0x104))&0x80000000)==0x80000000) group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(AD:0x0+0x108))&0x80000000)==0x80000000) group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(AD:0x0+0x10C))&0x80000000)==0x80000000) group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif tree.end base AD:0x0 width 12. tree "Virtual CPU Interface" group.long 0x0000++0x03 line.long 0x00 "GICV_CTLR,Virtual Machine Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior associated with the GICV_EOIR GICV_AEOIR and GICV_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 4. " CBPR ,Controls whether the GICV_BPR controls both Group 0 and Group 1 virtual interrupts" "BPR/ABPR split,BPR common" bitfld.long 0x00 3. " FIQEN ,Controls whether interrupts marked as Group 0 are presented as virtual FIQs" "IRQs,FIQs" textline " " bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x0004++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" bitfld.long 0x00 3.--7. " PRIORITY ,Priority mask level for CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x0008++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x000C++0x03 hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICV_EOIR,VM End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the Virtual CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x001C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x0020++0x03 hide.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" in wgroup.long 0x0024++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x00D0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" rgroup.long 0x00FC++0x03 line.long 0x00 "GICV_IIDR,VM CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end endif width 0x0B tree.end tree.end tree "AIPSTZ (AHB to IP Bridge Trust Zone)" tree "AIPSTZ 1" base ad:0x0207C000 width 19. group.long 0x00++0x03 line.long 0x00 "AIPSTZ1_MPR,Master Privilege Registers" bitfld.long 0x00 31. " MPROT0_MBW ,Master 0 buffer control" "Disabled,Enabled" bitfld.long 0x00 30. " MPROT0_MTR ,Master 0 read control" "Not trusted,Trusted" bitfld.long 0x00 29. " MPROT0_MTW ,Master 0 write control" "Not trusted,Trusted" bitfld.long 0x00 28. " MPROT0_MPL ,Master 0 privilege control" "Forced,Not forced" newline bitfld.long 0x00 27. " MPROT1_MBW ,Master 1 buffer control" "Disabled,Enabled" bitfld.long 0x00 26. " MPROT1_MTR ,Master 1 read control" "Not trusted,Trusted" bitfld.long 0x00 25. " MPROT1_MTW ,Master 1 write control" "Not trusted,Trusted" bitfld.long 0x00 24. " MPROT1_MPL ,Master 1 privilege control" "Forced,Not forced" newline bitfld.long 0x00 19. " MPROT3_MBW ,Master 3 buffer control" "Disabled,Enabled" bitfld.long 0x00 18. " MPROT3_MTR ,Master 3 read control" "Not trusted,Trusted" bitfld.long 0x00 17. " MPROT3_MTW ,Master 3 write control" "Not trusted,Trusted" bitfld.long 0x00 16. " MPROT3_MPL ,Master 3 privilege control" "Forced,Not forced" group.long 0x40++0x13 line.long 0x00 "AIPSTZ1_OPACR,Off-Platform Peripheral Access Control Registers" bitfld.long 0x00 31. " OPAC0_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 30. " OPAC0_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 29. " OPAC0_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 28. " OPAC0_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 27. " OPAC1_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 26. " OPAC1_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 25. " OPAC1_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 24. " OPAC1_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 23. " OPAC2_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 22. " OPAC2_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 21. " OPAC2_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 20. " OPAC2_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 19. " OPAC3_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 18. " OPAC3_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 17. " OPAC3_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 16. " OPAC3_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 15. " OPAC4_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 14. " OPAC4_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 13. " OPAC4_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 12. " OPAC4_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 11. " OPAC5_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 10. " OPAC5_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 9. " OPAC5_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 8. " OPAC5_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 7. " OPAC6_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 6. " OPAC6_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 5. " OPAC6_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 4. " OPAC6_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 3. " OPAC7_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 2. " OPAC7_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 1. " OPAC7_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 0. " OPAC7_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x04 "AIPSTZ1_OPACR1,Off-Platform Peripheral Access Control Registers" bitfld.long 0x04 31. " OPAC8_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 30. " OPAC8_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 29. " OPAC8_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 28. " OPAC8_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 27. " OPAC9_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 26. " OPAC9_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 25. " OPAC9_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 24. " OPAC9_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 23. " OPAC10_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 22. " OPAC10_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 21. " OPAC10_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 20. " OPAC10_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 19. " OPAC11_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 18. " OPAC11_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 17. " OPAC11_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 16. " OPAC11_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 15. " OPAC12_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 14. " OPAC12_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 13. " OPAC12_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 12. " OPAC12_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 11. " OPAC13_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 10. " OPAC13_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 9. " OPAC13_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 8. " OPAC13_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 7. " OPAC14_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 6. " OPAC14_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 5. " OPAC14_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 4. " OPAC14_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 3. " OPAC15_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 2. " OPAC15_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 1. " OPAC15_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 0. " OPAC15_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x08 "AIPSTZ1_OPACR2,Off-Platform Peripheral Access Control Registers" bitfld.long 0x08 31. " OPAC16_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 30. " OPAC16_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 29. " OPAC16_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 28. " OPAC16_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 27. " OPAC17_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 26. " OPAC17_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 25. " OPAC17_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 24. " OPAC17_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 23. " OPAC18_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 22. " OPAC18_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 21. " OPAC18_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 20. " OPAC18_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 19. " OPAC19_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 18. " OPAC19_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 17. " OPAC19_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 16. " OPAC19_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 15. " OPAC20_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 14. " OPAC20_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 13. " OPAC20_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 12. " OPAC20_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 11. " OPAC21_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 10. " OPAC21_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 9. " OPAC21_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 8. " OPAC21_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 7. " OPAC22_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 6. " OPAC22_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 5. " OPAC22_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 4. " OPAC22_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 3. " OPAC23_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 2. " OPAC23_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 1. " OPAC23_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 0. " OPAC23_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x0C "AIPSTZ1_OPACR3,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0C 31. " OPAC24_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 30. " OPAC24_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 29. " OPAC24_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 28. " OPAC24_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 27. " OPAC25_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 26. " OPAC25_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 25. " OPAC25_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 24. " OPAC25_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 23. " OPAC26_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 22. " OPAC26_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 21. " OPAC26_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 20. " OPAC26_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 19. " OPAC27_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 18. " OPAC27_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 17. " OPAC27_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 16. " OPAC27_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 15. " OPAC28_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 14. " OPAC28_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 13. " OPAC28_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 12. " OPAC28_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 11. " OPAC29_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 10. " OPAC29_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 9. " OPAC29_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 8. " OPAC29_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 7. " OPAC30_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 6. " OPAC30_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 5. " OPAC30_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 4. " OPAC30_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 3. " OPAC15_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 2. " OPAC31_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 1. " OPAC31_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 0. " OPAC31_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x10 "AIPSTZ1_OPACR4,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 31. " OPAC32_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x10 30. " OPAC32_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 29. " OPAC32_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 28. " OPAC32_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x10 27. " OPAC33_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x10 26. " OPAC33_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 25. " OPAC33_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 24. " OPAC33_TP ,Untrusted master" "Allowed,Not allowed" width 0x0B tree.end tree "AIPSTZ 2" base ad:0x0217C000 width 19. group.long 0x00++0x03 line.long 0x00 "AIPSTZ2_MPR,Master Privilege Registers" bitfld.long 0x00 31. " MPROT0_MBW ,Master 0 buffer control" "Disabled,Enabled" bitfld.long 0x00 30. " MPROT0_MTR ,Master 0 read control" "Not trusted,Trusted" bitfld.long 0x00 29. " MPROT0_MTW ,Master 0 write control" "Not trusted,Trusted" bitfld.long 0x00 28. " MPROT0_MPL ,Master 0 privilege control" "Forced,Not forced" newline bitfld.long 0x00 27. " MPROT1_MBW ,Master 1 buffer control" "Disabled,Enabled" bitfld.long 0x00 26. " MPROT1_MTR ,Master 1 read control" "Not trusted,Trusted" bitfld.long 0x00 25. " MPROT1_MTW ,Master 1 write control" "Not trusted,Trusted" bitfld.long 0x00 24. " MPROT1_MPL ,Master 1 privilege control" "Forced,Not forced" newline bitfld.long 0x00 19. " MPROT3_MBW ,Master 3 buffer control" "Disabled,Enabled" bitfld.long 0x00 18. " MPROT3_MTR ,Master 3 read control" "Not trusted,Trusted" bitfld.long 0x00 17. " MPROT3_MTW ,Master 3 write control" "Not trusted,Trusted" bitfld.long 0x00 16. " MPROT3_MPL ,Master 3 privilege control" "Forced,Not forced" group.long 0x40++0x13 line.long 0x00 "AIPSTZ2_OPACR,Off-Platform Peripheral Access Control Registers" bitfld.long 0x00 31. " OPAC0_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 30. " OPAC0_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 29. " OPAC0_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 28. " OPAC0_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 27. " OPAC1_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 26. " OPAC1_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 25. " OPAC1_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 24. " OPAC1_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 23. " OPAC2_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 22. " OPAC2_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 21. " OPAC2_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 20. " OPAC2_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 19. " OPAC3_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 18. " OPAC3_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 17. " OPAC3_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 16. " OPAC3_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 15. " OPAC4_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 14. " OPAC4_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 13. " OPAC4_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 12. " OPAC4_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 11. " OPAC5_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 10. " OPAC5_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 9. " OPAC5_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 8. " OPAC5_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 7. " OPAC6_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 6. " OPAC6_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 5. " OPAC6_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 4. " OPAC6_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x00 3. " OPAC7_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x00 2. " OPAC7_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x00 1. " OPAC7_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x00 0. " OPAC7_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x04 "AIPSTZ2_OPACR1,Off-Platform Peripheral Access Control Registers" bitfld.long 0x04 31. " OPAC8_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 30. " OPAC8_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 29. " OPAC8_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 28. " OPAC8_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 27. " OPAC9_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 26. " OPAC9_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 25. " OPAC9_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 24. " OPAC9_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 23. " OPAC10_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 22. " OPAC10_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 21. " OPAC10_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 20. " OPAC10_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 19. " OPAC11_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 18. " OPAC11_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 17. " OPAC11_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 16. " OPAC11_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 15. " OPAC12_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 14. " OPAC12_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 13. " OPAC12_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 12. " OPAC12_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 11. " OPAC13_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 10. " OPAC13_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 9. " OPAC13_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 8. " OPAC13_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 7. " OPAC14_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 6. " OPAC14_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 5. " OPAC14_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 4. " OPAC14_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x04 3. " OPAC15_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x04 2. " OPAC15_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x04 1. " OPAC15_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x04 0. " OPAC15_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x08 "AIPSTZ2_OPACR2,Off-Platform Peripheral Access Control Registers" bitfld.long 0x08 31. " OPAC16_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 30. " OPAC16_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 29. " OPAC16_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 28. " OPAC16_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 27. " OPAC17_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 26. " OPAC17_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 25. " OPAC17_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 24. " OPAC17_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 23. " OPAC18_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 22. " OPAC18_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 21. " OPAC18_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 20. " OPAC18_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 19. " OPAC19_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 18. " OPAC19_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 17. " OPAC19_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 16. " OPAC19_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 15. " OPAC20_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 14. " OPAC20_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 13. " OPAC20_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 12. " OPAC20_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 11. " OPAC21_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 10. " OPAC21_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 9. " OPAC21_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 8. " OPAC21_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 7. " OPAC22_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 6. " OPAC22_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 5. " OPAC22_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 4. " OPAC22_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x08 3. " OPAC23_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x08 2. " OPAC23_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x08 1. " OPAC23_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x08 0. " OPAC23_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x0C "AIPSTZ2_OPACR3,Off-Platform Peripheral Access Control Registers" bitfld.long 0x0C 31. " OPAC24_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 30. " OPAC24_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 29. " OPAC24_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 28. " OPAC24_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 27. " OPAC25_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 26. " OPAC25_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 25. " OPAC25_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 24. " OPAC25_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 23. " OPAC26_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 22. " OPAC26_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 21. " OPAC26_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 20. " OPAC26_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 19. " OPAC27_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 18. " OPAC27_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 17. " OPAC27_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 16. " OPAC27_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 15. " OPAC28_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 14. " OPAC28_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 13. " OPAC28_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 12. " OPAC28_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 11. " OPAC29_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 10. " OPAC29_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 9. " OPAC29_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 8. " OPAC29_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 7. " OPAC30_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 6. " OPAC30_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 5. " OPAC30_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 4. " OPAC30_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x0C 3. " OPAC15_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x0C 2. " OPAC31_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x0C 1. " OPAC31_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x0C 0. " OPAC31_TP ,Untrusted master" "Allowed,Not allowed" line.long 0x10 "AIPSTZ2_OPACR4,Off-Platform Peripheral Access Control Registers" bitfld.long 0x10 31. " OPAC32_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x10 30. " OPAC32_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 29. " OPAC32_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 28. " OPAC32_TP ,Untrusted master" "Allowed,Not allowed" newline bitfld.long 0x10 27. " OPAC33_BW ,Off-platform peripheral access control" "Not required,Required" bitfld.long 0x10 26. " OPAC33_SP ,Supervisor privilege" "Not required,Required" bitfld.long 0x10 25. " OPAC33_WP ,Write allowed" "Not protected,Protected" bitfld.long 0x10 24. " OPAC33_TP ,Untrusted master" "Allowed,Not allowed" width 0x0B tree.end tree.end tree "AUDMUX (Digital Audio Multiplexer)" base ad:0x021D8000 width 14. group.long 0x00++0x37 line.long 0x00 "AUDMUX_PTCR1,Port Timing Control Register 1" bitfld.long 0x00 31. " TFS_DIR ,Transmit frame sync direction control" "Input,Output" bitfld.long 0x00 30. " TFSEL[3] ,Transmit frame sync select [3]" "TXFS,RXFS" bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x00 26. " TCLKDIR ,Transmit clock direction control" "Input,Output" bitfld.long 0x00 25. " TCSEL[3] ,Transmit clock select" "TXC,RXC" bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x00 21. " RFS_DIR ,Receive frame sync direction control" "Input,Output" bitfld.long 0x00 20. " RFSEL[3] ,Receive frame sync select" "TXFS,RXFS" bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x00 16. " RCLKDIR ,Receive clock direction control" "Input,Output" bitfld.long 0x00 15. " RCSEL[3] ,Receive clock select" "TXC,RXC" bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x00 11. " SYN ,Synchronous/asynchronous select" "Asynchronous,Synchronous" line.long 0x04 "AUDMUX_PDCR1,Port Data Control Register 1" bitfld.long 0x04 13.--15. " RXDSEL ,Receive data select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." bitfld.long 0x04 12. " TXRXEN ,Transmit/receive switch enable" "Disabled,Enabled" bitfld.long 0x04 8. " MODE ,Mode select" "Normal,Internal Network" newline bitfld.long 0x04 7. " INMMASK7 ,Internal network mode mask 7" "Included,Excluded" bitfld.long 0x04 6. " INMMASK6 ,Internal network mode mask 6" "Included,Excluded" bitfld.long 0x04 5. " INMMASK5 ,Internal network mode mask 5" "Included,Excluded" bitfld.long 0x04 4. " INMMASK4 ,Internal network mode mask 4" "Included,Excluded" newline bitfld.long 0x04 3. " INMMASK3 ,Internal network mode mask 3" "Included,Excluded" bitfld.long 0x04 2. " INMMASK2 ,Internal network mode mask 2" "Included,Excluded" bitfld.long 0x04 1. " INMMASK1 ,Internal network mode mask 1" "Included,Excluded" bitfld.long 0x04 0. " INMMASK0 ,Internal network mode mask 0" "Included,Excluded" line.long 0x08 "AUDMUX_PTCR2,Port Timing Control Register 2" bitfld.long 0x08 31. " TFS_DIR ,Transmit frame sync direction control" "Input,Output" bitfld.long 0x08 30. " TFSEL[3] ,Transmit frame sync select [3]" "TXFS,RXFS" bitfld.long 0x08 27.--29. " TFSEL[2:0] ,Transmit frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x08 26. " TCLKDIR ,Transmit clock direction control" "Input,Output" bitfld.long 0x08 25. " TCSEL[3] ,Transmit clock select" "TXC,RXC" bitfld.long 0x08 22.--24. " TCSEL[2:0] ,Transmit clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x08 21. " RFS_DIR ,Receive frame sync direction control" "Input,Output" bitfld.long 0x08 20. " RFSEL[3] ,Receive frame sync select" "TXFS,RXFS" bitfld.long 0x08 17.--19. " RFSEL[2:0] ,Receive frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x08 16. " RCLKDIR ,Receive clock direction control" "Input,Output" bitfld.long 0x08 15. " RCSEL[3] ,Receive clock select" "TXC,RXC" bitfld.long 0x08 12.--14. " RCSEL[2:0] ,Receive clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x08 11. " SYN ,Synchronous/asynchronous select" "Asynchronous,Synchronous" line.long 0x0C "AUDMUX_PDCR2,Port Data Control Register 2" bitfld.long 0x0C 13.--15. " RXDSEL ,Receive data select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." bitfld.long 0x0C 12. " TXRXEN ,Transmit/receive switch enable" "Disabled,Enabled" bitfld.long 0x0C 8. " MODE ,Mode select" "Normal,Internal Network" newline bitfld.long 0x0C 7. " INMMASK7 ,Internal network Mode mask 7" "Included,Excluded" bitfld.long 0x0C 6. " INMMASK6 ,Internal network mode mask 6" "Included,Excluded" bitfld.long 0x0C 5. " INMMASK5 ,Internal network mode mask 5" "Included,Excluded" bitfld.long 0x0C 4. " INMMASK4 ,Internal network mode mask 4" "Included,Excluded" newline bitfld.long 0x0C 3. " INMMASK3 ,Internal network mode mask 3" "Included,Excluded" bitfld.long 0x0C 2. " INMMASK2 ,Internal network Mode mask 2" "Included,Excluded" bitfld.long 0x0C 1. " INMMASK1 ,Internal network Mode mask 1" "Included,Excluded" bitfld.long 0x0C 0. " INMMASK0 ,Internal network mode mask 0" "Included,Excluded" line.long 0x10 "AUDMUX_PTCR3,Port Timing Control Register 3" bitfld.long 0x10 31. " TFS_DIR ,Transmit frame sync direction control" "Input,Output" bitfld.long 0x10 30. " TFSEL[3] ,Transmit frame sync select [3]" "TXFS,RXFS" bitfld.long 0x10 27.--29. " TFSEL[2:0] ,Transmit frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x10 26. " TCLKDIR ,Transmit clock direction control" "Input,Output" bitfld.long 0x10 25. " TCSEL[3] ,Transmit clock select" "TXC,RXC" bitfld.long 0x10 22.--24. " TCSEL[2:0] ,Transmit clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x10 21. " RFS_DIR ,Receive frame sync direction control" "Input,Output" bitfld.long 0x10 20. " RFSEL[3] ,Receive frame sync select" "TXFS,RXFS" bitfld.long 0x10 17.--19. " RFSEL[2:0] ,Receive frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x10 16. " RCLKDIR ,Receive clock direction control" "Input,Output" bitfld.long 0x10 15. " RCSEL[3] ,Receive clock select" "TXC,RXC" bitfld.long 0x10 12.--14. " RCSEL[2:0] ,Receive clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x10 11. " SYN ,Synchronous/asynchronous select" "Asynchronous,Synchronous" line.long 0x14 "AUDMUX_PDCR3,Port Data Control Register 3" bitfld.long 0x14 13.--15. " RXDSEL ,Receive data select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." bitfld.long 0x14 12. " TXRXEN ,Transmit/receive switch enable" "Disabled,Enabled" bitfld.long 0x14 8. " MODE ,Mode select" "Normal,Internal Network" newline bitfld.long 0x14 7. " INMMASK7 ,Internal network mode mask 7" "Included,Excluded" bitfld.long 0x14 6. " INMMASK6 ,Internal network mode mask 6" "Included,Excluded" bitfld.long 0x14 5. " INMMASK5 ,Internal network mode mask 5" "Included,Excluded" bitfld.long 0x14 4. " INMMASK4 ,Internal network mode mask 4" "Included,Excluded" newline bitfld.long 0x14 3. " INMMASK3 ,Internal network mode mask 3" "Included,Excluded" bitfld.long 0x14 2. " INMMASK2 ,Internal network mode mask 2" "Included,Excluded" bitfld.long 0x14 1. " INMMASK1 ,Internal network mode mask 1" "Included,Excluded" bitfld.long 0x14 0. " INMMASK0 ,Internal network mode mask 0" "Included,Excluded" newline line.long 0x18 "AUDMUX_PTCR4,Port Timing Control Register 4" bitfld.long 0x18 31. " TFS_DIR ,Transmit frame sync direction control" "Input,Output" bitfld.long 0x18 30. " TFSEL[3] ,Transmit frame sync select [3]" "TXFS,RXFS" bitfld.long 0x18 27.--29. " TFSEL[2:0] ,Transmit frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x18 26. " TCLKDIR ,Transmit clock direction control" "Input,Output" bitfld.long 0x18 25. " TCSEL[3] ,Transmit clock select" "TXC,RXC" bitfld.long 0x18 22.--24. " TCSEL[2:0] ,Transmit clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x18 21. " RFS_DIR ,Receive frame sync direction control" "Input,Output" bitfld.long 0x18 20. " RFSEL[3] ,Receive frame sync select" "TXFS,RXFS" bitfld.long 0x18 17.--19. " RFSEL[2:0] ,Receive frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x18 16. " RCLKDIR ,Receive clock direction control" "Input,Output" bitfld.long 0x18 15. " RCSEL[3] ,Receive clock select" "TXC,RXC" bitfld.long 0x18 12.--14. " RCSEL[2:0] ,Receive clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x18 11. " SYN ,Synchronous/asynchronous select" "Asynchronous,Synchronous" line.long 0x1C "AUDMUX_PDCR4,Port Data Control Register 4" bitfld.long 0x1C 13.--15. " RXDSEL ,Receive data select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." bitfld.long 0x1C 12. " TXRXEN ,Transmit/receive switch enable" "Disabled,Enabled" bitfld.long 0x1C 8. " MODE ,Mode select" "Normal,Internal Network" newline bitfld.long 0x1C 7. " INMMASK7 ,Internal network mode mask 7" "Included,Excluded" bitfld.long 0x1C 6. " INMMASK6 ,Internal network mode mask 6" "Included,Excluded" bitfld.long 0x1C 5. " INMMASK5 ,Internal network mode mask 5" "Included,Excluded" bitfld.long 0x1C 4. " INMMASK4 ,Internal network mode mask 4" "Included,Excluded" newline bitfld.long 0x1C 3. " INMMASK3 ,Internal network mode mask 3" "Included,Excluded" bitfld.long 0x1C 2. " INMMASK2 ,Internal network mode mask 2" "Included,Excluded" bitfld.long 0x1C 1. " INMMASK1 ,Internal network mode mask 1" "Included,Excluded" bitfld.long 0x1C 0. " INMMASK0 ,Internal network mode mask 0" "Included,Excluded" line.long 0x20 "AUDMUX_PTCR5,Port Timing Control Register 5" bitfld.long 0x20 31. " TFS_DIR ,Transmit frame sync direction control" "Input,Output" bitfld.long 0x20 30. " TFSEL[3] ,Transmit frame sync select [3]" "TXFS,RXFS" bitfld.long 0x20 27.--29. " TFSEL[2:0] ,Transmit frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x20 26. " TCLKDIR ,Transmit clock direction control" "Input,Output" bitfld.long 0x20 25. " TCSEL[3] ,Transmit clock select" "TXC,RXC" bitfld.long 0x20 22.--24. " TCSEL[2:0] ,Transmit clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x20 21. " RFS_DIR ,Receive frame sync direction control" "Input,Output" bitfld.long 0x20 20. " RFSEL[3] ,Receive frame sync select" "TXFS,RXFS" bitfld.long 0x20 17.--19. " RFSEL[2:0] ,Receive frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x20 16. " RCLKDIR ,Receive clock direction control" "Input,Output" bitfld.long 0x20 15. " RCSEL[3] ,Receive clock select" "TXC,RXC" bitfld.long 0x20 12.--14. " RCSEL[2:0] ,Receive clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x20 11. " SYN ,Synchronous/asynchronous select" "Asynchronous,Synchronous" line.long 0x24 "AUDMUX_PDCR5,Port Data Control Register 5" bitfld.long 0x24 13.--15. " RXDSEL ,Receive data select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." bitfld.long 0x24 12. " TXRXEN ,Transmit/receive switch enable" "Disabled,Enabled" bitfld.long 0x24 8. " MODE ,Mode select" "Normal,Internal Network" newline bitfld.long 0x24 7. " INMMASK7 ,Internal network mode mask 7" "Included,Excluded" bitfld.long 0x24 6. " INMMASK6 ,Internal network mode mask 6" "Included,Excluded" bitfld.long 0x24 5. " INMMASK5 ,Internal network mode mask 5" "Included,Excluded" bitfld.long 0x24 4. " INMMASK4 ,Internal network mode mask 4" "Included,Excluded" newline bitfld.long 0x24 3. " INMMASK3 ,Internal network mode mask 3" "Included,Excluded" bitfld.long 0x24 2. " INMMASK2 ,Internal network mode mask 2" "Included,Excluded" bitfld.long 0x24 1. " INMMASK1 ,Internal network mode mask 1" "Included,Excluded" bitfld.long 0x24 0. " INMMASK0 ,Internal network mode mask 0" "Included,Excluded" line.long 0x28 "AUDMUX_PTCR6,Port Timing Control Register 6" bitfld.long 0x28 31. " TFS_DIR ,Transmit frame sync direction control" "Input,Output" bitfld.long 0x28 30. " TFSEL[3] ,Transmit frame sync select [3]" "TXFS,RXFS" bitfld.long 0x28 27.--29. " TFSEL[2:0] ,Transmit frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x28 26. " TCLKDIR ,Transmit clock direction control" "Input,Output" bitfld.long 0x28 25. " TCSEL[3] ,Transmit clock select" "TXC,RXC" bitfld.long 0x28 22.--24. " TCSEL[2:0] ,Transmit clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x28 21. " RFS_DIR ,Receive frame sync direction control" "Input,Output" bitfld.long 0x28 20. " RFSEL[3] ,Receive frame sync select" "TXFS,RXFS" bitfld.long 0x28 17.--19. " RFSEL[2:0] ,Receive frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x28 16. " RCLKDIR ,Receive clock direction control" "Input,Output" bitfld.long 0x28 15. " RCSEL[3] ,Receive clock select" "TXC,RXC" bitfld.long 0x28 12.--14. " RCSEL[2:0] ,Receive clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x28 11. " SYN ,Synchronous/asynchronous select" "Asynchronous,Synchronous" line.long 0x2C "AUDMUX_PDCR6,Port Data Control Register 6" bitfld.long 0x2C 13.--15. " RXDSEL ,Receive data select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." bitfld.long 0x2C 12. " TXRXEN ,Transmit/receive switch enable" "Disabled,Enabled" bitfld.long 0x2C 8. " MODE ,Mode select" "Normal,Internal Network" newline bitfld.long 0x2C 7. " INMMASK7 ,Internal network mode mask 7" "Included,Excluded" bitfld.long 0x2C 6. " INMMASK6 ,Internal network mode mask 6" "Included,Excluded" bitfld.long 0x2C 5. " INMMASK5 ,Internal network mode mask 5" "Included,Excluded" bitfld.long 0x2C 4. " INMMASK4 ,Internal network mode mask 4" "Included,Excluded" newline bitfld.long 0x2C 3. " INMMASK3 ,Internal network mode mask 3" "Included,Excluded" bitfld.long 0x2C 2. " INMMASK2 ,Internal network mode mask 2" "Included,Excluded" bitfld.long 0x2C 1. " INMMASK1 ,Internal network mode mask 1" "Included,Excluded" bitfld.long 0x2C 0. " INMMASK0 ,Internal network mode mask 0" "Included,Excluded" line.long 0x30 "AUDMUX_PTCR7,Port Timing Control Register 7" bitfld.long 0x30 31. " TFS_DIR ,Transmit frame sync direction control" "Input,Output" bitfld.long 0x30 30. " TFSEL[3] ,Transmit frame sync select [3]" "TXFS,RXFS" bitfld.long 0x30 27.--29. " TFSEL[2:0] ,Transmit frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x30 26. " TCLKDIR ,Transmit clock direction control" "Input,Output" bitfld.long 0x30 25. " TCSEL[3] ,Transmit clock select" "TXC,RXC" bitfld.long 0x30 22.--24. " TCSEL[2:0] ,Transmit clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x30 21. " RFS_DIR ,Receive frame sync direction control" "Input,Output" bitfld.long 0x30 20. " RFSEL[3] ,Receive frame sync select" "TXFS,RXFS" bitfld.long 0x30 17.--19. " RFSEL[2:0] ,Receive frame sync select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x30 16. " RCLKDIR ,Receive clock direction control" "Input,Output" bitfld.long 0x30 15. " RCSEL[3] ,Receive clock select" "TXC,RXC" bitfld.long 0x30 12.--14. " RCSEL[2:0] ,Receive clock select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." newline bitfld.long 0x30 11. " SYN ,Synchronous/asynchronous select" "Asynchronous,Synchronous" line.long 0x34 "AUDMUX_PDCR7,Port Data Control Register 7" bitfld.long 0x34 13.--15. " RXDSEL ,Receive data select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..." bitfld.long 0x34 12. " TXRXEN ,Transmit/receive switch enable" "Disabled,Enabled" bitfld.long 0x34 8. " MODE ,Mode select" "Normal,Internal Network" newline bitfld.long 0x34 7. " INMMASK7 ,Internal network mode mask 7" "Included,Excluded" bitfld.long 0x34 6. " INMMASK6 ,Internal network mode mask 6" "Included,Excluded" bitfld.long 0x34 5. " INMMASK5 ,Internal network mode mask 5" "Included,Excluded" bitfld.long 0x34 4. " INMMASK4 ,Internal network mode mask 4" "Included,Excluded" newline bitfld.long 0x34 3. " INMMASK3 ,Internal network mode mask 3" "Included,Excluded" bitfld.long 0x34 2. " INMMASK2 ,Internal network mode mask 2" "Included,Excluded" bitfld.long 0x34 1. " INMMASK1 ,Internal network mode mask 1" "Included,Excluded" bitfld.long 0x34 0. " INMMASK0 ,Internal network mode mask 0" "Included,Excluded" width 0x0B tree.end tree "CCM (Clock Control Module)" tree "CCM" base ad:0x020C4000 width 13. group.long 0x00++0x07 line.long 0x00 "CCM_CCR,CCM Control Register" bitfld.long 0x00 27. " RBC_EN ,Enable for REG_BYPASS_COUNTER" "Enabled,Disabled" bitfld.long 0x00 21.--26. " REG_BYPASS_COUNT ,Register bypass counter" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 12. " COSC_EN ,On chip oscillator enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " OSCNT ,Oscillator ready counter value" line.long 0x04 "CCM_CCDR,CCM Control Divider Register" bitfld.long 0x04 16. " MMDC_CH1_MASK ,Mask handshake with MMDC_CH1 module" "Not masked,Masked" rgroup.long 0x08++0x03 line.long 0x00 "CCM_CSR,CCM Status Register" bitfld.long 0x00 5. " COSC_READY ,Status indication of on board oscillator" "Not ready,Ready" bitfld.long 0x00 0. " REF_EN_B ,Status of the value of REF_EN_B output of CCM" "0,1" group.long 0x0C++0x33 line.long 0x00 "CCM_CCSR,CCM Clock Switcher Register" bitfld.long 0x00 8. " STEP_SEL ,Step frequency when shifting ARM frequency" "Source 4,PLL2 PDF clock" bitfld.long 0x00 3. " SECONDARY_CLK_SEL ,Select source to generate secondary_clk" "PLL2 PFD2,PLL2" bitfld.long 0x00 2. " PLL1_SW_CLK_SEL ,Selects source to generate PLL1_SW_CLK" "PLL1_MAIN_CLK,STEP_CLK" newline bitfld.long 0x00 0. " PLL3_SW_CLK_SEL ,Source to generate pll3_sw_clk" "PLL3_MAIN_CLK,Pll3 bypass" line.long 0x04 "CCM_CACRR,CCM Arm Clock Root Register" bitfld.long 0x04 0.--2. " ARM_PODF ,Divider for ARM clock root" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x08 "CCM_CBCDR,CCM Bus Clock Divider Register" bitfld.long 0x08 27.--29. " PERIPH_CLK2_PODF ,Divider for periph2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 26. " PERIPH2_CLK_SEL ,Selector for peripheral2 main clock" "PLL2_SW_CLK,PERIPH_CLK2_CLK" bitfld.long 0x08 25. " PERIPH_CLK_SEL ,Selector for peripheral main clock" "PLL2_SW_CLK,PERIPH_CLK2_CLK" newline bitfld.long 0x08 16.--18. " AXI_PODF ,Divider for axi podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 10.--12. " AHB_PODF ,Divider for ahb podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 8.--9. " IPG_PODF ,Divider for ipg podf" "/1,/2,/3,/4" newline bitfld.long 0x08 7. " AXI_ALT_SEL ,AXI alternative clock select" "pll2 396MHz,pll3 540MHz" bitfld.long 0x08 6. " AXI_SEL ,AXI clock source select" "Periph_clk output,AXI alternative clock" bitfld.long 0x08 3.--5. " MMDC_CH1/CB_AXI_PODF ,Divider for MMDC_CH1_AXI podf" "/1,/2,/3,/4,/5,/6,/7,/8" newline bitfld.long 0x08 0.--2. " PERIPH2_PODF2_PODF ,Divider for PERIPH2_CLK2 podf" "/1,/2,/3,/4,/5,/6,/7,/8" line.long 0x0C "CCM_CBCMR,CCM Bus Clock Multiplexer Register" bitfld.long 0x0C 23.--25. " LCDIF1_PODF ,Post-divider for lcdif1 clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 21.--22. " PRE_PERIPH2_CLK_SEL ,Selector for PRE_PERIPH2 clock multiplexer" "PLL2,PLL2 PFD2,PLL2 PFD0,PLL2 PFD2 (/2)" bitfld.long 0x0C 20. " PERIPH2_CLK2_SEL ,Selector for PERIPH2_CLK2 clock multiplexer" "PLL3_SW_CLK,PLL2_MAIN" newline bitfld.long 0x0C 18.--19. " PRE_PERIPH_CLK_SEL ,Selector for PRE_PERIPH clock multiplexer" "PLL2,PLL2 PFD2,PLL2 PFD0,PLL2 PFD2 (/2)" bitfld.long 0x0C 12.--13. " PERIPH_CLK2_SEL ,Selector for peripheral CLK2 clock multiplexer" "PLL3_SW_CLK,PLL1_REF_CLK,PLL2_BURN_IN_CLK,?..." line.long 0x10 "CCM_CSCMR1,CCM Serial Clock Multiplexer Register 1" bitfld.long 0x10 18. " USDHC3_CLK_SEL ,Selector for USDHC3 clock multiplexer" "PLL2 PFD2,PLL PFD0" bitfld.long 0x10 17. " USDHC2_CLK_SEL ,Selector for USDHC2 clock multiplexer" "PLL2 PFD2,PLL PFD0" newline bitfld.long 0x10 16. " USDHC1_CLK_SEL ,Selector for USDHC1 clock multiplexer" "PLL2 PFD2,PLL PFD0" bitfld.long 0x10 14.--15. " SSI3_CLK_SEL ,Selector for ssi3 clock multiplexer" "PLL3 PFD2,PLL3 PFD3,PLL4,?..." bitfld.long 0x10 12.--13. " SSI2_CLK_SEL ,Selector for ssi2 clock multiplexer" "PLL3 PFD2,PLL3 PFD3,PLL4,?..." newline bitfld.long 0x10 10.--11. " SSI1_CLK_SEL ,Selector for SSI1 clock multiplexer" "PLL3 PFD2,PLL3 PFD3,PLL4,?..." bitfld.long 0x10 6. " PERCLK_CLK_SEL ,Selector for the perclk clock multiplexor" "ipg clk root,osc_clk" line.long 0x14 "CCM_CSCMR2,CCM Serial Clock Multiplexer Register 2" bitfld.long 0x14 11. " LDB_DI1_IPU_DIV ,Control for divider of LDB clock for IPU di1" "/3.5,/7" bitfld.long 0x14 10. " LDB_DI0_IPU_DIV ,Control for divider of LDB clock for IPU di0" "/3.5,/7" line.long 0x18 "CCM_CSCDR1,CCM Serial Clock Divider Register 1" bitfld.long 0x18 19.--21. " USDHC3_PODF ,Divider for USDHC3 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 16.--18. " USDHC2_PODF ,Divider for USDHC2 clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 11.--13. " USDHC1_PODF ,Divider for ESDHC1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8" newline bitfld.long 0x18 6. " UART_CLK_SEL ,Selector for the UART clock multiplexor" "pll3_80m,osc_clk" bitfld.long 0x18 0.--5. " UART_CLK_PODF ,Divider for UART clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x1C "CCM_CS1CDR,CCM SSI1 Clock Divider Register" bitfld.long 0x1C 22.--24. " SSI3_CLK_PRED ,Divider for SSI3 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x1C 16.--21. " SSI3_CLK_PODF ,Divider for SSI3 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" bitfld.long 0x1C 6.--8. " SSI1_CLK_PRED ,Divider for SSI1 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" newline bitfld.long 0x1C 0.--5. " SSI1_CLK_PODF ,Divider for SSI1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x20 "CCM_CS2CDR,CCM SSI2 Clock Divider Register" bitfld.long 0x20 12.--14. " LDB_DI1_CLK_SEL ,Selector for LDB_DI1 clock multiplexer" "PLL5 clock,PLL2 PDF0,PLL2 PFD2,MMDC_CH1 clock,PLL3_SW_CLK,?..." bitfld.long 0x20 9.--11. " LDB_DI0_CLK_SEL ,Selector for LDB_DI1 clock multiplexer" "PLL5 clock,PLL2 PDF0,PLL2 PFD2,MMDC_CH1 clock,PLL3_SW_CLK,?..." bitfld.long 0x20 6.--8. " SSI2_CLK_PRED ,Divider for SSI2 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" newline bitfld.long 0x20 0.--5. " SSI2_CLK_PODF ,Divider for SSI2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x24 "CCM_CDCDR,CCM DI Clock Divider Register" bitfld.long 0x24 25.--27. " SPDIF0_CLK_PRED ,Divider for SPDIF0 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x24 22.--24. " SPDIF0_CLK_PODF ,Divider for SPDIF0 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x24 20.--21. " SPDIF0_CLK_SEL ,Selector for SPDIF0 clock multiplexer" "Divided PLL4,PLL3 PFD2,PLL3 PFD3,pll3_sw_clk" newline bitfld.long 0x24 12.--14. " SPDIF1_CLK_PRED ,Divider for SPDIF1 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x24 9.--11. " SPDIF1_CLK_PODF ,Divider for SPDIF1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x24 7.--8. " SPDIF1_CLK_SEL ,Selector for SPDIF1 clock multiplexer" "Divided PLL4,PLL3 PFD2,PLL3 PFD3,pll3_sw_clk" line.long 0x28 "CCM_CHSCCDR,CCM HSC Clock Divider Register" bitfld.long 0x28 15.--17. " EPDC_AXI_CLK_SEL ,Selector for epdc_axi root clock multiplexer" "mmdc_ch0,pll3_sw_clk,PLL2 PFD0,PLL2 PFD2,PLL3 PFD1,?..." bitfld.long 0x28 12.--14. " EPDC_PODF ,Divider for EPDC clock divider" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x28 9.--11. " EPDC_CLK_SEL ,Selector for EPDC root clock multiplexer" "ipp_di0_clk,ipp_di1_clk,ldb_di0_clk,ldb_di1_clk,?..." line.long 0x2C "CCM_CSCDR2,CCM Serial Clock Divider Register 2" bitfld.long 0x2C 19.--24. " ECSPI_CLK_PODF ,Divider for ECSPI clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" newline bitfld.long 0x2C 18. " ECSPI_CLK_SEL ,Selector for the ECSPI clock multiplexor" "pll3_60m,osc_clk" bitfld.long 0x2C 15.--17. " LCDIF1_PRE_CLK_SEL ,Selector for lcdif1 root clock pre-multiplexer" "PLL2,PLL3 PFD3,PLL5,PLL2 PFD0,PLL2 PFD1,PLL3 PFD1,?..." newline bitfld.long 0x2C 12.--14. " LCDIF1_PRED ,Pre-divider for lcdif1 clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x2C 9.--11. " LCDIF1_CLK_SEL ,Selector for lcdif1 root clock multiplexer" "ipp_di0_clk,ipp_di1_clk,ldb_di0_clk,ldb_di1_clk,?..." rgroup.long 0x48++0x03 line.long 0x00 "CCM_CDHIPR,CCM Divider Handshake In-Process Register" bitfld.long 0x00 16. " ARM_PODF_BUSY ,Busy indicator for CCM_CACRR[ARM_PODF]" "Not busy,Busy" bitfld.long 0x00 5. " PERIPH_CLK_SEL_BUSY ,Busy indicator for PERIPH_CLK_SEL mux control" "Not busy,Busy" bitfld.long 0x00 3. " PERIPH2_CLK_SEL_BUSY ,Busy indicator PERIPH2_CLK_SEL mux control" "Not busy,Busy" newline bitfld.long 0x00 2. " MMDC_CH1_PODF_BUSY ,Busy indicator for MMDC_CH1_AXI_PODF" "Not busy,Busy" bitfld.long 0x00 1. " AHB_PODF_BUSY ,Busy indicator for AHB_PODF" "Not busy,Busy" bitfld.long 0x00 0. " AXI_PODF_BUSY ,Busy indicator for AXI_PODF" "Not busy,Busy" group.long 0x54++0x2F line.long 0x00 "CCM_CLPCR,CCM Low Power Control Register" bitfld.long 0x00 27. " MASK_L2CC_IDLE ,Mask L2CC IDLE for entering low power mode" "Not masked,Masked" bitfld.long 0x00 26. " MASK_SCU_IDLE ,Mask SCU IDLE for entering low power mode" "Not masked,Masked" bitfld.long 0x00 22. " MASK_CORE0_WFI ,Mask WFI of core0 for entering low power mode" "Not masked,Masked" newline bitfld.long 0x00 21. " BYPASS_MMDC_CH1_LPM_HS ,Bypass handshake with mmdc_ch1 on next entrance to low power mode" "Not bypassed,Bypassed" bitfld.long 0x00 11. " COSC_PWRDOWN ,Oscillator power down" "Not powered down,Powered down" bitfld.long 0x00 9.--10. " STBY_COUNT ,Standby counter definition" "2 ckil clocks,4 ckil clocks,8 ckil clocks,16 ckil clocks" newline bitfld.long 0x00 8. " VSTBY ,Voltage standby request" "Not requested,Requested" bitfld.long 0x00 7. " DIS_REF_OSC ,External reference oscillator clock disable" "No,Yes" bitfld.long 0x00 6. " SBYOS ,Standby clock oscillator" "Enabled,Disabled" newline bitfld.long 0x00 5. " ARM_CLK_DIS_ON_LPM ,ARM clock disabled in WAIT mode" "No,Yes" bitfld.long 0x00 0.--1. " LPM ,Low power mode" "Remain in RUN mode,Transfer to WAIT mode,Transfer to STOP mode,?..." line.long 0x04 "CCM_CISR,CCM Interrupt Status Register" eventfld.long 0x04 26. " ARM_PODF_LOADED ,Interrupt IPI_INT_1 generated due to frequency change of ARM_PODF" "No interrupt,Interrupt" eventfld.long 0x04 22. " PERIPH_CLK_SEL_LOADED ,Interrupt IPI_INT_1 generated due to update of PERIPH_CLK_SEL" "No interrupt,Interrupt" eventfld.long 0x04 21. " MMDC_CH1_PODF_LOADED ,Interrupt IPI_INT_1 generated due to frequency change of MMDC_CH0_PODF_LOADED" "No interrupt,Interrupt" newline eventfld.long 0x04 20. " AHB_PODF_LOADED ,Interrupt IPI_INT_1 generated due to frequency change of AHB_PODF" "No interrupt,Interrupt" eventfld.long 0x04 19. " PERIPH2_CLK_SEL_LOADED ,Interrupt IPI_INT_1 generated due to frequency change of PERIPH2_CLK_SEL" "No interrupt,Interrupt" eventfld.long 0x04 6. " COSC_READY ,Interrupt IPI_INT_2 generated when on board oscillator ready" "No interrupt,Interrupt" newline eventfld.long 0x04 0. " LRF_PLL ,Interrupt IPI_INT_2 generated due to lock of all enabled and not bypaseed plls" "No interrupt,Interrupt" line.long 0x08 "CCM_CIMR,CCM Interrupt Mask Register" bitfld.long 0x08 26. " ARM_PODF_LOADED ,Mask interrupt generation due to frequency change of ARM_PODF" "Not masked,Masked" bitfld.long 0x08 22. " MASK_PERIPH_CLK_SEL_LOADED ,Mask interrupt generation due to update of PERIPH_CLK_SEL" "Not masked,Masked" bitfld.long 0x08 21. " MASK_MMDC_CH1_PODF_LOADED ,Mask interrupt generation due to frequency change of MASK_MMDC_CH1_PODF" "Not masked,Masked" newline bitfld.long 0x08 20. " MASK_AHB_PODF_LOADED ,Mask interrupt generation due to frequency change of AHB_PODF" "Not masked,Masked" bitfld.long 0x08 19. " MASK_PERIPH2_CLK_SEL_LOADED ,Mask interrupt generation due to frequency change of PERIPH2_CLK_SEL" "Not masked,Masked" bitfld.long 0x08 17. " MASK_AXI_PODF_LOADED ,Mask interrupt generation due to frequency change of AXI_PODF" "Not masked,Masked" newline bitfld.long 0x08 6. " MASK_COSC_READY ,Mask interrupt generation due to on board oscillator ready" "Not masked,Masked" bitfld.long 0x08 0. " MASK_LRF_PLL1 ,Mask interrupt generation due to lrf of plls" "Not masked,Masked" line.long 0x0C "CCM_CCOSR,CCM Clock Output Source Register" bitfld.long 0x0C 24. " CKO2_EN ,Enable of CKO2 clock" "Disabled,Enabled" bitfld.long 0x0C 21.--23. " CKO2_DIV ,Setting the divider of CKO2" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 16.--20. " CLKO2_SEL ,Selection of the clock to be generated on clko2" "mmdc_clk_root,,usdhc1_clk_root,wrck_clk_root,ecspi_clk_root,usdhc3_clk_root,arm_clk_root,,osc_clk,usdhc2_clk_root,ssi1_clk_root,ssi2_clk_root,ssi3_clk_root,extern_audio_clk_root,,uart_clk_root,spdif0_clk_root,?..." newline bitfld.long 0x0C 8. " CLK_OUT_SEL ,CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks" "CCM_CLKO1,CCM_CLKO2" bitfld.long 0x0C 7. " CKO1_EN ,Enable of CKO1 clock" "Disabled,Enabled" bitfld.long 0x0C 4.--6. " CKO1_DIV ,Setting the divider of CKO1" "/1,/2,/3,/4,/5,/6,/7,/8" newline bitfld.long 0x0C 0.--3. " CKO1_SEL ,Selection of the clock to be generated on cko1" "pll3_sw_clk,pll2_main_clk,pll1_main_clk,pll5_main_clk,axi_clk_root,epdc_axi_clk_root,lcdif_pix_clk_root,epdc_pix_clk_root,ahb_clk_root,ipg_clk_root,perclk_root,ckil_sync_clk_root,pll4_main_clk,?..." line.long 0x10 "CCM_CGPR,CCM General Purpose Register" bitfld.long 0x10 17. " INT_MEM_CLK_LPM ,Clock to the ARM platform memories" "Disabled,Enabled" bitfld.long 0x10 16. " FPL ,Engage PLL" "Default,3 CKIL" bitfld.long 0x10 14.--15. " SYS_MEM_DS_CTRL ,System memory DS control" "Disabled,STOP and PLL are Disabled,STOP,?..." newline bitfld.long 0x10 4. " EFUSE_PROG_SUPPLY_GATE ,Fuse programming supply voltage is gated" "Disabled,Enabled" bitfld.long 0x10 2. " MMDC_EXT_CLK_DIS ,Disable external clock driver of MMDC during STOP mode" "No,Yes" bitfld.long 0x10 0. " PMIC_DELAY_SCALER ,Defines clock division of clock for stby_count" "Not divided,/8" line.long 0x14 "CCM_CCGR0,CCM Clock Gating Register 0" bitfld.long 0x14 28.--29. " CG14 ,gpio2_clocks (gpio2_clk_enable)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x14 22.--23. " CG11 ,Clock gating for power reduction of CPU debug clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x14 10.--11. " CG5 ,Clock gating for power reduction of CAAM_WRAPPER_ACLK clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x14 2.--3. " CG1 ,Clock gating for power reduction of AIPS_TZ2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x14 0.--1. " CG0 ,Clock gating for power reduction of AIPS_TZ1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" line.long 0x18 "CCM_CCGR1,CCM Clock Gating Register 1" bitfld.long 0x18 26.--27. " CG13 ,Clock gating for power reduction of GPU3D clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x18 24.--25. " CG12 ,Clock gating for power reduction of GPU2D clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x18 22.--23. " CG11 ,Clock gating for power reduction of GPT serial clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x18 20.--21. " CG10 ,Clock gating for power reduction of GPT bus clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x18 16.--17. " CG8 ,Clock gating for power reduction of ESAI clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x18 14.--15. " CG7 ,Clock gating for power reduction of EPIT2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x18 12.--13. " CG6 ,Clock gating for power reduction of EPIT1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x18 10.--11. " CG5 ,Clock gating for power reduction of ENET clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x18 8.--9. " CG4 ,Clock gating for power reduction of ECSPI5 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x18 6.--7. " CG3 ,Clock gating for power reduction of ECSPI4 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x18 4.--5. " CG2 ,Clock gating for power reduction of ECSPI3 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x18 2.--3. " CG1 ,Clock gating for power reduction of ECSPI2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x18 0.--1. " CG0 ,Clock gating for power reduction of ECSPI1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" line.long 0x1C "CCM_CCGR2,CCM Clock Gating Register 2" bitfld.long 0x1C 26.--27. " CG13 ,Clock gating for power reduction of IPSYNC_VDOA_IPG clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x1C 24.--25. " CG12 ,Clock gating for power reduction of IPSYNC_IP2APB_TZASC2_IPG clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x1C 22.--23. " CG11 ,Clock gating for power reduction of IPSYNC_IP2APB_TZASC1_IPG clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x1C 20.--21. " CG10 ,Clock gating for power reduction of IPMUX3 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x1C 18.--19. " CG9 ,Clock gating for power reduction of IPMUX2 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x1C 16.--17. " CG8 ,Clock gating for power reduction of IPMUX1 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x1C 14.--15. " CG7 ,Clock gating for power reduction of IOMUX_IPT_CLK_IO clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x1C 12.--13. " CG6 ,Clock gating for power reduction of IIM clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x1C 10.--11. " CG5 ,Clock gating for power reduction of I2C3_SERIAL clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x1C 8.--9. " CG4 ,Clock gating for power reduction of I2C2_SERIAL clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x1C 6.--7. " CG3 ,Clock gating for power reduction of EI2C1_SERIAL clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x1C 4.--5. " CG2 ,Clock gating for power reduction of HDMI_TX_ISFRCLK clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x1C 0.--1. " CG0 ,Clock gating for power reduction of HDMI_TX_IAHBCLK/HDMI_TX_IHCLK clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" line.long 0x20 "CCM_CCGR3,CCM Clock Gating Register 3" bitfld.long 0x20 30.--31. " CG15 ,Clock gating for power reduction of OPENVGAXICLK clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x20 28.--29. " CG14 ,Clock gating for power reduction of OCRAM clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x20 24.--25. " CG12 ,Clock gating for power reduction of MMDC_CORE_IPG_CLK_P0 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x20 20.--21. " CG10 ,Clock gating for power reduction of MMDC_CORE_ACLK_FAST_CORE_P0 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x20 18.--19. " CG9 ,Clock gating for power reduction of MLB clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x20 16.--17. " CG8 ,Clock gating for power reduction of MIPI_CORE_CFG clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x20 14.--15. " CG7 ,Clock gating for power reduction of LDB_DI1 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x20 12.--13. " CG6 ,Clock gating for power reduction of LDB_DI0 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x20 10.--11. " CG5 ,Clock gating for power reduction of IPU2_IPU_DI1 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x20 8.--9. " CG4 ,Clock gating for power reduction of IPU2_IPU_DI0 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x20 4.--5. " CG2 ,Clock gating for power reduction of IPU1_IPU_DI1 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x20 2.--3. " CG1 ,Clock gating for power reduction of IPU1_IPU_DI0 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x20 0.--1. " CG0 ,Clock gating for power reduction of IPU1_IPU clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" line.long 0x24 "CCM_CCGR4,CCM Clock Gating Register 4" bitfld.long 0x24 30.--31. " CG15 ,Clock gating for power reduction of RAWNAND_U_GPMI_INPUT_APB clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x24 28.--29. " CG14 ,Clock gating for power reduction of RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x24 26.--27. " CG13 ,Clock gating for power reduction of RAWNAND_U_GPMI_BCH_INPUT_BCH clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x24 24.--25. " CG12 ,Clock gating for power reduction of RAWNAND_U_BCH_INPUT_APB clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x24 22.--23. " CG11 ,Clock gating for power reduction of PWM4 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x24 20.--21. " CG10 ,Clock gating for power reduction of PWM3 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x24 18.--19. " CG9 ,Clock gating for power reduction of PWM2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x24 16.--17. " CG8 ,Clock gating for power reduction of PWM1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x24 14.--15. " CG7 ,Clock gating for power reduction of PL301_MX63PER2_MAINCLK_ENABLE (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x24 12.--13. " CG6 ,Clock gating for power reduction of PL301_MX63PER1_BCH clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x24 8.--9. " CG4 ,Clock gating for power reduction of PL301_MX63FAST1_S133 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x24 0.--1. " CG0 ,Clock gating for power reduction of PCIE clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" line.long 0x28 "CCM_CCGR5,CCM Clock Gating Register 5" bitfld.long 0x28 26.--27. " CG13 ,Clock gating for power reduction of UART_SERIAL clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x28 24.--25. " CG12 ,Clock gating for power reduction of UART clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x28 22.--23. " CG11 ,Clock gating for power reduction of SSI3 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x28 20.--21. " CG10 ,Clock gating for power reduction of SSI2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x28 18.--19. " CG9 ,Clock gating for power reduction of SSI1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x28 14.--15. " CG7 ,Clock gating for power reduction of SPDIF clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x28 12.--13. " CG6 ,Clock gating for power reduction of SPBA clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x28 6.--7. " CG3 ,Clock gating for power reduction of SDMA clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x28 4.--5. " CG2 ,Clock gating for power reduction of SATA clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x28 0.--1. " CG0 ,Clock gating for power reduction of ROM clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" line.long 0x2C "CCM_CCGR6,CCM Clock Gating Register 6" bitfld.long 0x2C 14.--15. " CG7 ,Clock gating for power reduction of VPU clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x2C 12.--13. " CG6 ,Clock gating for power reduction of VDOAXICLK root clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x2C 10.--11. " CG5 ,Clock gating for power reduction of EMI_SLOW clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x2C 8.--9. " CG4 ,Clock gating for power reduction of USDHC4 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x2C 6.--7. " CG3 ,Clock gating for power reduction of USDHC3 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x2C 4.--5. " CG2 ,Clock gating for power reduction of USDHC2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" newline bitfld.long 0x2C 2.--3. " CG1 ,Clock gating for power reduction of USDHC1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" bitfld.long 0x2C 0.--1. " CG0 ,Clock gating for power reduction of USBOH3 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,,On/On/Off" group.long 0x88++0x03 line.long 0x00 "CCM_CMEOR,CCM Module Enable Override Register" bitfld.long 0x00 7. " MOD_EN_USDHC ,Override clock enable signal from USDHC" "Not overridden,Overridden" bitfld.long 0x00 6. " MOD_EN_OV_EPIT ,Override clock enable signal from EPIT (not gated based on IPG_ENABLE_CLK)" "Not overridden,Overridden" bitfld.long 0x00 5. " MOD_EN_OV_GPT ,Override clock enable signal from GPT clock (not gated based on IPG_ENABLE_CLK)" "Not overridden,Overridden" width 0x0B tree.end tree "CCM_ANALOG" base ad:0x020C8000 width 28. group.long 0x00++0x0F line.long 0x00 "CCM_ANALOG_PLL_ARM,Analog ARM PLL control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x00 18. " LVDS_24MHZ_SEL ,Analog Debug Bit" "Low,High" bitfld.long 0x00 17. " LVDS_SEL ,Analog Debug Bit" "Low,High" newline bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK1,?..." bitfld.long 0x00 13. " ENABLE ,Enable the clock output" "Disabled,Enabled" newline bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the pll loop divider" line.long 0x04 "CCM_ANALOG_PLL_ARM_SET,Analog ARM PLL control set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x04 18. " LVDS_24MHZ_SEL ,Analog Debug Bit" "Low,High" bitfld.long 0x04 17. " LVDS_SEL ,Analog Debug Bit" "Low,High" newline bitfld.long 0x04 16. " BYPASS ,Bypass the pll" "Low,High" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK1,?..." bitfld.long 0x04 13. " ENABLE ,Enable the clock output" "Disabled,Enabled" newline bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the pll loop divider" line.long 0x08 "CCM_ANALOG_PLL_ARM_CLR,Analog ARM PLL control clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x08 18. " LVDS_24MHZ_SEL ,Analog Debug Bit" "Low,High" bitfld.long 0x08 17. " LVDS_SEL ,Analog Debug Bit" "Low,High" newline bitfld.long 0x08 16. " BYPASS ,Bypass the pll" "Low,High" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK1,?..." bitfld.long 0x08 13. " ENABLE ,Enable the clock output" "Disabled,Enabled" newline bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the pll loop divider" line.long 0x0C "CCM_ANALOG_PLL_ARM_TOG,Analog ARM PLL control toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x0C 18. " LVDS_24MHZ_SEL ,Analog Debug Bit" "Low,High" bitfld.long 0x0C 17. " LVDS_SEL ,Analog Debug Bit" "Low,High" newline bitfld.long 0x0C 16. " BYPASS ,Bypass the pll" "Low,High" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK1,?..." bitfld.long 0x0C 13. " ENABLE ,Enable the clock output" "Disabled,Enabled" newline bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the pll loop divider" group.long 0x10++0x0F line.long 0x00 "CCM_ANALOG_PLL_USB0,Analog USBPHY0 480MHz PLL Control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" newline bitfld.long 0x00 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x00 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x00 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY0" "Off,On" newline bitfld.long 0x00 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,?..." line.long 0x04 "CCM_ANALOG_PLL_USB0_SET,Analog USB0 480MHz PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" newline bitfld.long 0x04 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x04 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x04 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY0" "Off,On" newline bitfld.long 0x04 0.--1. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22,?..." line.long 0x08 "CCM_ANALOG_PLL_USB0_CLR,Analog USB0 480MHz PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" newline bitfld.long 0x08 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x08 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x08 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY0" "Off,On" newline bitfld.long 0x08 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,?..." line.long 0x0C "CCM_ANALOG_PLL_USB0_TOG,Analog USB0 480MHz PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" newline bitfld.long 0x0C 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x0C 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x0C 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY0" "Off,On" newline bitfld.long 0x0C 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,?..." group.long 0x20++0x0F line.long 0x00 "CCM_ANALOG_PLL_USB1,Analog USBPHY1 480MHz PLL Control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" newline bitfld.long 0x00 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x00 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x00 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY1" "Off,On" newline bitfld.long 0x00 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,?..." line.long 0x04 "CCM_ANALOG_PLL_USB1_SET,Analog USB1 480MHz PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" newline bitfld.long 0x04 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x04 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x04 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY1" "Off,On" newline bitfld.long 0x04 0.--1. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22,?..." line.long 0x08 "CCM_ANALOG_PLL_USB1_CLR,Analog USB1 480MHz PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" newline bitfld.long 0x08 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x08 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x08 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY1" "Off,On" newline bitfld.long 0x08 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,?..." line.long 0x0C "CCM_ANALOG_PLL_USB1_TOG,Analog USB1 480MHz PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Opened,Locked" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" newline bitfld.long 0x0C 13. " ENABLE ,Enable the PLL clock output" "Disabled,Enabled" bitfld.long 0x0C 12. " POWER ,Powers up the PLL" "Off,On" bitfld.long 0x0C 6. " EN_USB_CLKS ,Powers the 9-phase PLL outputs for USBPHY1" "Off,On" newline bitfld.long 0x0C 0.--1. " DIV_SELECT ,This field controls the pll loop divider" "Fref*20,Fref*22,?..." group.long 0x30++0x13 line.long 0x00 "CCM_ANALOG_PLL_SYS,Analog System PLL Control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x00 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Low,High" newline bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" bitfld.long 0x00 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "Low,High" newline bitfld.long 0x00 0. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22" line.long 0x04 "CCM_ANALOG_PLL_SYS_SET,Analog System PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x04 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Low,High" newline bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" bitfld.long 0x04 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "Low,High" newline bitfld.long 0x04 0. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22" line.long 0x08 "CCM_ANALOG_PLL_SYS_CLR,Analog System PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x08 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Low,High" newline bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" bitfld.long 0x08 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "Low,High" newline bitfld.long 0x08 0. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22" line.long 0x0C "CCM_ANALOG_PLL_SYS_TOG,Analog System PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Low,High" newline bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,GPANAIO,CHRG_DET_B" bitfld.long 0x0C 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "Low,High" newline bitfld.long 0x0C 0. " DIV_SELECT ,This field controls the PLL loop divider" "Fref*20,Fref*22" group.long 0x40++0x03 line.long 0x00 "CCM_ANALOG_PLL_SYS_SS,528MHz System PLL Spread Spectrum Register" hexmask.long.word 0x00 16.--31. 1. " STOP ,Frequency change = STOP/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz" bitfld.long 0x00 15. " ENABLE ,Spread spectrum modulation enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--14. 1. " STEP ,Frequency change step = STEP/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz" group.long 0x70++0x0F line.long 0x00 "CCM_ANALOG_PLL_AUDIO,Analog Audio PLL control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x00 19.--20. " POST_DIV_SELECT ,Analog Debug bit" "/4,/2,/1,?..." bitfld.long 0x00 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." bitfld.long 0x00 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" newline bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x04 "CCM_ANALOG_PLL_AUDIO_SET,Analog Audio PLL control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x04 19.--20. " POST_DIV_SELECT ,Analog Debug bit" "/4,/2,/1,?..." bitfld.long 0x04 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." bitfld.long 0x04 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" newline bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x08 "CCM_ANALOG_PLL_AUDIO_CLR,Analog Audio PLL control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x08 19.--20. " POST_DIV_SELECT ,Analog Debug bit" "/4,/2,/1,?..." bitfld.long 0x08 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." bitfld.long 0x08 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" newline bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x0C "CCM_ANALOG_PLL_AUDIO_TOG,Analog Audio PLL control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x0C 19.--20. " POST_DIV_SELECT ,Analog Debug bit" "/4,/2,/1,?..." bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." bitfld.long 0x0C 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" newline bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" group.long 0x80++0x03 line.long 0x00 "CCM_ANALOG_PLL_AUDIO_NUM,Numerator of Audio PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " A ,30 bit numerator (A) of fractional loop divider" group.long 0x90++0x03 line.long 0x00 "CCM_ANALOG_PLL_AUDIO_DENOM,Denominator of Audio PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " B ,30 bit Denominator (B) of fractional loop divider" group.long 0xA0++0x0F line.long 0x00 "CCM_ANALOG_PLL_VIDEO,Analog Video PLL control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x00 19.--20. " POST_DIV_SELECT ,These bits implement a divider after the PLL Debug bit" "/4,/2,/1,?..." bitfld.long 0x00 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." bitfld.long 0x00 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" newline bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x00 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x04 "CCM_ANALOG_PLL_VIDEO_SET,Analog Video PLL control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x04 19.--20. " POST_DIV_SELECT ,These bits implement a divider after the PLL Debug bit" "/4,/2,/1,?..." bitfld.long 0x04 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." bitfld.long 0x04 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" newline bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x04 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x08 "CCM_ANALOG_PLL_VIDEO_CLR,Analog Video PLL control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x08 19.--20. " POST_DIV_SELECT ,These bits implement a divider after the PLL Debug bit" "/4,/2,/1,?..." bitfld.long 0x08 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." bitfld.long 0x08 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" newline bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x08 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" line.long 0x0C "CCM_ANALOG_PLL_VIDEO_TOG,Analog Video PLL control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not locked,Locked" bitfld.long 0x0C 19.--20. " POST_DIV_SELECT ,These bits implement a divider after the PLL Debug bit" "/4,/2,/1,?..." bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." bitfld.long 0x0C 13. " ENABLE ,Enable PLL output" "Disabled,Enabled" newline bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "Low,High" hexmask.long.byte 0x0C 0.--6. 1. " DIV_SELECT ,This field controls the PLL loop divider" group.long 0xB0++0x03 line.long 0x00 "CCM_ANALOG_PLL_VIDEO_NUM,Numerator of Video PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " A ,30 bit numerator (A) of fractional loop divider" group.long 0xC0++0x03 line.long 0x00 "CCM_ANALOG_PLL_VIDEO_DENOM,Denominator of Video PLL Fractional Loop Divider Register" hexmask.long 0x00 0.--29. 1. " B ,30 bit Denominator (B) of fractional loop divider" group.long 0xE0++0x002F line.long 0x00 "CCM_ANALOG_PLL_ENET,Analog ENET PLL Control Register" rbitfld.long 0x00 31. " LOCK ,PLL is currently locked" "Not Locked,Locked" newline bitfld.long 0x00 21. " ENET_25M_REF_EN ,Enable the PLL providing ENET 25 MHz reference clock" "Disabled,Enabled" bitfld.long 0x00 20. " ENET2_125M_EN ,Enable the PLL providing the ENET2 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x00 19. " ENABLE_125M ,Enables an offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x00 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x00 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x00 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." newline bitfld.long 0x00 13. " ENET1_125M_EN ,Enable the PLL providing the ENET1 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x00 12. " POWERDOWN ,Powers down the PLL" "Low,High" newline bitfld.long 0x00 2.--3. " ENET1_DIV_SELECT ,Controls the frequency of the ethernet1 reference clock" "25MHz,50MHz,100MHz,125MHz" bitfld.long 0x00 0.--1. " ENET0_DIV_SELECT ,Controls the frequency of the ethernet0 reference clock" "25MHz,50MHz,100MHz,125MHz" line.long 0x04 "CCM_ANALOG_PLL_ENET_SET,Analog ENET PLL Control Set Register" rbitfld.long 0x04 31. " LOCK ,PLL is currently locked" "Not Locked,Locked" newline bitfld.long 0x04 21. " ENET_25M_REF_EN ,Enable the PLL providing ENET 25 MHz reference clock" "Disabled,Enabled" bitfld.long 0x04 20. " ENET2_125M_EN ,Enable the PLL providing the ENET2 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x04 19. " ENABLE_125M ,Enables an offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x04 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x04 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x04 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." newline bitfld.long 0x04 13. " ENET1_125M_EN ,Enable the PLL providing the ENET1 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x04 12. " POWERDOWN ,Powers down the PLL" "Low,High" newline bitfld.long 0x04 2.--3. " ENET1_DIV_SELECT ,Controls the frequency of the ethernet1 reference clock" "25MHz,50MHz,100MHz,125MHz" bitfld.long 0x04 0.--1. " ENET0_DIV_SELECT ,Controls the frequency of the ethernet0 reference clock" "25MHz,50MHz,100MHz,125MHz" line.long 0x08 "CCM_ANALOG_PLL_ENET_CLR,Analog ENET PLL Control Clear Register" rbitfld.long 0x08 31. " LOCK ,PLL is currently locked" "Not Locked,Locked" newline bitfld.long 0x08 21. " ENET_25M_REF_EN ,Enable the PLL providing ENET 25 MHz reference clock" "Disabled,Enabled" bitfld.long 0x08 20. " ENET2_125M_EN ,Enable the PLL providing the ENET2 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x08 19. " ENABLE_125M ,Enables an offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x08 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x08 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x08 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." newline bitfld.long 0x08 13. " ENET1_125M_EN ,Enable the PLL providing the ENET1 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x08 12. " POWERDOWN ,Powers down the PLL" "Low,High" newline bitfld.long 0x08 2.--3. " ENET1_DIV_SELECT ,Controls the frequency of the ethernet1 reference clock" "25MHz,50MHz,100MHz,125MHz" bitfld.long 0x08 0.--1. " ENET0_DIV_SELECT ,Controls the frequency of the ethernet0 reference clock" "25MHz,50MHz,100MHz,125MHz" line.long 0x0C "CCM_ANALOG_PLL_ENET_TOG,Analog ENET PLL Control Toggle Register" rbitfld.long 0x0C 31. " LOCK ,PLL is currently locked" "Not Locked,Locked" newline bitfld.long 0x0C 21. " ENET_25M_REF_EN ,Enable the PLL providing ENET 25 MHz reference clock" "Disabled,Enabled" bitfld.long 0x0C 20. " ENET2_125M_EN ,Enable the PLL providing the ENET2 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x0C 19. " ENABLE_125M ,Enables an offset in the phase frequency detector" "Disabled,Enabled" newline bitfld.long 0x0C 18. " PFD_OFFSET_EN ,Enables an offset in the phase frequency detector" "Disabled,Enabled" bitfld.long 0x0C 16. " BYPASS ,Bypass the PLL" "Low,High" bitfld.long 0x0C 14.--15. " BYPASS_CLK_SRC ,Determines the bypass source" "REF_CLK_24M,CLK_1,?..." newline bitfld.long 0x0C 13. " ENET1_125M_EN ,Enable the PLL providing the ENET1 125 MHz reference clock" "Disabled,Enabled" bitfld.long 0x0C 12. " POWERDOWN ,Powers down the PLL" "Low,High" newline bitfld.long 0x0C 2.--3. " ENET1_DIV_SELECT ,Controls the frequency of the ethernet1 reference clock" "25MHz,50MHz,100MHz,125MHz" bitfld.long 0x0C 0.--1. " ENET0_DIV_SELECT ,Controls the frequency of the ethernet0 reference clock" "25MHz,50MHz,100MHz,125MHz" line.long 0x10 "CCM_ANALOG_PFD_480,480MHz Clock Phase Fractional Divider Control Register" bitfld.long 0x10 31. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x10 30. " PFD3_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x10 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x10 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x10 22. " PFD2_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x10 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x10 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x10 14. " PFD1_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x10 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x10 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x10 6. " PFD0_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x10 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x14 "CCM_ANALOG_PFD_480_SET,480MHz Clock Phase Fractional Divider Control Set Register" bitfld.long 0x14 31. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x14 30. " PFD3_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x14 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x14 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x14 22. " PFD2_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x14 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x14 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x14 14. " PFD1_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x14 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x14 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x14 6. " PFD0_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x14 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x18 "CCM_ANALOG_PFD_480_CLR,480MHz Clock Phase Fractional Divider Control Clear Register" bitfld.long 0x18 31. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x18 30. " PFD3_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x18 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x18 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x18 22. " PFD2_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x18 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x18 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x18 14. " PFD1_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x18 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x18 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x18 6. " PFD0_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x18 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x1C "CCM_ANALOG_PFD_480_TOG,480MHz Clock Phase Fractional Divider Control Toggle Register" bitfld.long 0x1C 31. " PFD3_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x1C 30. " PFD3_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x1C 24.--29. " PFD3_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x1C 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x1C 22. " PFD2_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x1C 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x1C 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x1C 14. " PFD1_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x1C 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x1C 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x1C 6. " PFD0_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x1C 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x20 "CCM_ANALOG_PFD_528,528MHz Clock Phase Fractional Divider Control Register" bitfld.long 0x20 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x20 22. " PFD2_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x20 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x20 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x20 14. " PFD1_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x20 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x20 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x20 6. " PFD0_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x20 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x24 "CCM_ANALOG_PFD_528_SET,528MHz Clock Phase Fractional Divider Control Set Register" bitfld.long 0x24 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x24 22. " PFD2_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x24 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x24 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x24 14. " PFD1_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x24 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x24 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x24 6. " PFD0_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x24 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x28 "CCM_ANALOG_PFD_528_CLR,528MHz Clock Phase Fractional Divider Control Clear Register" bitfld.long 0x28 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x28 22. " PFD2_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x28 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x28 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x28 14. " PFD1_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x28 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x28 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x28 6. " PFD0_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x28 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x2C "CCM_ANALOG_PFD_528_TOG,528MHz Clock Phase Fractional Divider Control Toggle Register" bitfld.long 0x2C 23. " PFD2_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x2C 22. " PFD2_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x2C 16.--21. " PFD2_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x2C 15. " PFD1_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x2C 14. " PFD1_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x2C 8.--13. " PFD1_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." newline bitfld.long 0x2C 7. " PFD0_CLKGATE ,IO Clock Gate" "Disabled,Enabled" rbitfld.long 0x2C 6. " PFD0_STABLE ,The phase divider clock output" "Low,High" bitfld.long 0x2C 0.--5. " PFD0_FRAC ,This field controls the fractional divide value" ",,,,,,,,,,,,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." group.long 0x150++0x2F line.long 0x00 "CCM_ANALOG_MISC0,Miscellaneous Control Register" bitfld.long 0x00 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x00 30. " XTAL_24M_PWD ,24M crystal oscillator supply" "Powered up,Powered down" bitfld.long 0x00 29. " RTC_XTAL_SOURCE ,Chip source for the RTC clock" "Internal,RTC_XTAL" newline bitfld.long 0x00 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x00 25. " CLKGATE_CTRL ,Disabling the clock gate for the xtal 24MHz clock that clocks the digital logic in the analog block" "ALLOW_AUTO_GATE,NO_AUTO_GATE" bitfld.long 0x00 16. " OSC_XTALOK_EN ,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "Disabled,Enabled" newline rbitfld.long 0x00 15. " OSC_XTALOK ,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "Low,High" bitfld.long 0x00 13.--14. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,-12.5%,-25%,-37.5%" bitfld.long 0x00 12. " RTC_RINGOSC_EN ,Internal ring oscillator that can be used in lieu of an external 32k crystal" "Disabled,Enabled" newline bitfld.long 0x00 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode [XtalOsc/RCOsc/Old BG/New BG]" "All down exc RTC,Certain regulators up,Off/On/On/Off,Off/On/Off/On" bitfld.long 0x00 7. " REFTOP_VBGUP ,Analog bandgap voltage is up and stable" "Unstable,Stable" bitfld.long 0x00 4.--6. " REFTOP_VBGADJ ,Configure the analog behavior in stop mode" "VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" newline bitfld.long 0x00 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "Coarse,Bandgap-based" bitfld.long 0x00 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "Low,High" line.long 0x04 "CCM_ANALOG_MISC0_SET,Miscellaneous Control Set Register" bitfld.long 0x04 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x04 30. " XTAL_24M_PWD ,24M crystal oscillator supply" "Powered up,Powered down" bitfld.long 0x04 29. " RTC_XTAL_SOURCE ,Chip source for the RTC clock" "Internal ring oscillator,RTC_XTAL" newline bitfld.long 0x04 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x04 25. " CLKGATE_CTRL ,Disabling the clock gate for the xtal 24MHz clock that clocks the digital logic in the analog block" "ALLOW_AUTO_GATE,NO_AUTO_GATE" bitfld.long 0x04 16. " OSC_XTALOK_EN ,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "Disabled,Enabled" newline rbitfld.long 0x04 15. " OSC_XTALOK ,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "Low,High" bitfld.long 0x04 13.--14. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,-12.5%,-25%,-37.5%" bitfld.long 0x04 12. " RTC_RINGOSC_EN ,Internal ring oscillator that can be used in lieu of an external 32k crystal" "Disabled,Enabled" newline bitfld.long 0x04 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode [XtalOsc/RCOsc/Old BG/New BG]" "All down exc RTC,Certain regulators up,Off/On/On/Off,Off/On/Off/On" bitfld.long 0x04 7. " REFTOP_VBGUP ,Analog bandgap voltage is up and stable" "Unstable,Stable" bitfld.long 0x04 4.--6. " REFTOP_VBGADJ ,Configure the analog behavior in stop mode" "VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" newline bitfld.long 0x04 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "Coarse,Bandgap-based" bitfld.long 0x04 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "Low,High" line.long 0x08 "CCM_ANALOG_MISC0_CLR,Miscellaneous Control Clear Register" bitfld.long 0x08 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x08 30. " XTAL_24M_PWD ,24M crystal oscillator supply" "Powered up,Powered down" bitfld.long 0x08 29. " RTC_XTAL_SOURCE ,Chip source for the RTC clock" "Internal ring oscillator,RTC_XTAL" newline bitfld.long 0x08 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x08 25. " CLKGATE_CTRL ,Disabling the clock gate for the xtal 24MHz clock that clocks the digital logic in the analog block" "ALLOW_AUTO_GATE,NO_AUTO_GATE" bitfld.long 0x08 16. " OSC_XTALOK_EN ,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "Disabled,Enabled" newline rbitfld.long 0x08 15. " OSC_XTALOK ,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "Low,High" bitfld.long 0x08 13.--14. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,-12.5%,-25%,-37.5%" bitfld.long 0x08 12. " RTC_RINGOSC_EN ,Internal ring oscillator that can be used in lieu of an external 32k crystal" "Disabled,Enabled" newline bitfld.long 0x08 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode [XtalOsc/RCOsc/Old BG/New BG]" "All down exc RTC,Certain regulators up,Off/On/On/Off,Off/On/Off/On" bitfld.long 0x08 7. " REFTOP_VBGUP ,Analog bandgap voltage is up and stable" "Unstable,Stable" bitfld.long 0x08 4.--6. " REFTOP_VBGADJ ,Configure the analog behavior in stop mode" "VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" newline bitfld.long 0x08 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "Coarse,Bandgap-based" bitfld.long 0x08 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "Low,High" line.long 0x0C "CCM_ANALOG_MISC0_TOG,Miscellaneous Control Toggle Register" bitfld.long 0x0C 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x0C 30. " XTAL_24M_PWD ,24M crystal oscillator supply" "Powered up,Powered down" bitfld.long 0x0C 29. " RTC_XTAL_SOURCE ,Chip source for the RTC clock" "Internal ring oscillator,RTC_XTAL" newline bitfld.long 0x0C 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block" "0.5ms,1ms,2ms,3ms,4ms,5ms,6ms,7ms" bitfld.long 0x0C 25. " CLKGATE_CTRL ,Disabling the clock gate for the xtal 24MHz clock that clocks the digital logic in the analog block" "ALLOW_AUTO_GATE,NO_AUTO_GATE" bitfld.long 0x0C 16. " OSC_XTALOK_EN ,This bit enables the detector that signals when the 24MHz crystal oscillator is stable" "Disabled,Enabled" newline rbitfld.long 0x0C 15. " OSC_XTALOK ,Status bit that signals that the output of the 24-MHz crystal oscillator is stable" "Low,High" bitfld.long 0x0C 13.--14. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,-12.5%,-25%,-37.5%" bitfld.long 0x0C 12. " RTC_RINGOSC_EN ,Internal ring oscillator that can be used in lieu of an external 32k crystal" "Disabled,Enabled" newline bitfld.long 0x0C 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode [XtalOsc/RCOsc/Old BG/New BG]" "All down exc RTC,Certain regulators up,Off/On/On/Off,Off/On/Off/On" bitfld.long 0x0C 7. " REFTOP_VBGUP ,Analog bandgap voltage is up and stable" "Unstable,Stable" bitfld.long 0x0C 4.--6. " REFTOP_VBGADJ ,Configure the analog behavior in stop mode" "VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" newline bitfld.long 0x0C 3. " REFTOP_SELFBIASOFF ,Control bit to disable the self-bias circuit in the analog bandgap" "Coarse,Bandgap-based" bitfld.long 0x0C 0. " REFTOP_PWD ,Control bit to power-down the analog bandgap reference circuitry" "Low,High" line.long 0x10 "CCM_ANALOG_MISC1,Miscellaneous Control Register" eventfld.long 0x10 31. " IRQ_DIG_BO ,Any digital regulator brownout interrupt" "Not asserted,Asserted" eventfld.long 0x10 30. " IRQ_ANA_BO ,Any analog regulator brownout interrupt" "Not asserted,Asserted" eventfld.long 0x10 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt for high temperature" "Not asserted,Asserted" newline eventfld.long 0x10 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt for low temperature" "Not asserted,Asserted" eventfld.long 0x10 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt for a panic high temperature" "Not asserted,Asserted" bitfld.long 0x10 17. " PFD_528_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "Disabled,Enabled" newline bitfld.long 0x10 16. " PFD_480_AUTOGT_EN ,Feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x10 13. " LVDSCLK2_IBEN ,LVDS input buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x10 12. " LVDSCLK1_IBEN ,LVDS input buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x10 11. " LVDSCLK2_OBEN ,LVDS output buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x10 10. " LVDSCLK1_OBEN ,LVDS output buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x10 5.--9. " LVDS2_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,MLB_PLL,ETHERNET_REF,PCIE_REF,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x10 0.--4. " LVDS1_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,,,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x14 "CCM_ANALOG_MISC1_SET,Miscellaneous Control Set Register" rbitfld.long 0x14 31. " IRQ_DIG_BO ,Any digital regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x14 30. " IRQ_ANA_BO ,Any analog regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x14 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt for high temperature" "Not asserted,Asserted" newline rbitfld.long 0x14 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt for low temperature" "Not asserted,Asserted" rbitfld.long 0x14 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt for a panic high temperature" "Not asserted,Asserted" bitfld.long 0x14 17. " PFD_528_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "Disabled,Enabled" newline bitfld.long 0x14 16. " PFD_480_AUTOGT_EN ,Feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x14 13. " LVDSCLK2_IBEN ,LVDS input buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x14 12. " LVDSCLK1_IBEN ,LVDS input buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x14 11. " LVDSCLK2_OBEN ,LVDS output buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x14 10. " LVDSCLK1_OBEN ,LVDS output buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x14 5.--9. " LVDS2_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,MLB_PLL,ETHERNET_REF,PCIE_REF,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x14 0.--4. " LVDS1_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,,,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x18 "CCM_ANALOG_MISC1_CLR,Miscellaneous Control Clear Register" rbitfld.long 0x18 31. " IRQ_DIG_BO ,Any digital regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x18 30. " IRQ_ANA_BO ,Any analog regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x18 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt for high temperature" "Not asserted,Asserted" newline rbitfld.long 0x18 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt for low temperature" "Not asserted,Asserted" rbitfld.long 0x18 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt for a panic high temperature" "Not asserted,Asserted" bitfld.long 0x18 17. " PFD_528_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "Disabled,Enabled" newline bitfld.long 0x18 16. " PFD_480_AUTOGT_EN ,Feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x18 13. " LVDSCLK2_IBEN ,LVDS input buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x18 12. " LVDSCLK1_IBEN ,LVDS input buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x18 11. " LVDSCLK2_OBEN ,LVDS output buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x18 10. " LVDSCLK1_OBEN ,LVDS output buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x18 5.--9. " LVDS2_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,MLB_PLL,ETHERNET_REF,PCIE_REF,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x18 0.--4. " LVDS1_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,,,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x1C "CCM_ANALOG_MISC1_TOG,Miscellaneous Control Toggle Register" rbitfld.long 0x1C 31. " IRQ_DIG_BO ,Any digital regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x1C 30. " IRQ_ANA_BO ,Any analog regulator brownout interrupt" "Not asserted,Asserted" rbitfld.long 0x1C 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt for high temperature" "Not asserted,Asserted" newline rbitfld.long 0x1C 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt for low temperature" "Not asserted,Asserted" rbitfld.long 0x1C 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt for a panic high temperature" "Not asserted,Asserted" bitfld.long 0x1C 17. " PFD_528_AUTOGATE_EN ,Feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off" "Disabled,Enabled" newline bitfld.long 0x1C 16. " PFD_480_AUTOGT_EN ,Feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x1C 13. " LVDSCLK2_IBEN ,LVDS input buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x1C 12. " LVDSCLK1_IBEN ,LVDS input buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x1C 11. " LVDSCLK2_OBEN ,LVDS output buffer for anaclk2/2b" "Disabled,Enabled" bitfld.long 0x1C 10. " LVDSCLK1_OBEN ,LVDS output buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x1C 5.--9. " LVDS2_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,MLB_PLL,ETHERNET_REF,PCIE_REF,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,LVDS1,LVDS2,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" bitfld.long 0x1C 0.--4. " LVDS1_CLK_SEL ,Clk to be routed to anaclk2/2b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,,,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x20 "CCM_ANALOG_MISC2,Miscellaneous Control Register" bitfld.long 0x20 30.--31. " VIDEO_DIV ,Post-divider for video" "/1,/2,/1,/4" bitfld.long 0x20 28.--29. " REG2_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x20 26.--27. " REG1_STEP_TIME ,Number of clock periods" "64,128,256,512" newline bitfld.long 0x20 24.--25. " REG0_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x20 23. 15. " AUDIO_DIV ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" rbitfld.long 0x20 22. " REG2_OK ,Voltage level relative to the brownout level for the SOC supply" "Greater,Lower/Equal" newline bitfld.long 0x20 21. " REG2_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x20 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "Low,High" rbitfld.long 0x20 16.--18. " REG2_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" newline bitfld.long 0x20 13. " REG1_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x20 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "Low,High" rbitfld.long 0x20 8.--10. " REG1_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" newline bitfld.long 0x20 7. " PLL3_DISABLE ,PLL3 Disable" "No,Yes" newline bitfld.long 0x20 5. " REG0_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x20 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "Low,High" rbitfld.long 0x20 0.--2. " REG0_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" line.long 0x24 "CCM_ANALOG_MISC2_SET,Miscellaneous Control Set Register" bitfld.long 0x24 30.--31. " VIDEO_DIV ,Post-divider for video" "/1,/2,/1,/4" bitfld.long 0x24 28.--29. " REG2_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x24 26.--27. " REG1_STEP_TIME ,Number of clock periods" "64,128,256,512" newline bitfld.long 0x20 24.--25. " REG0_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x20 23. 15. " AUDIO_DIV ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" rbitfld.long 0x20 22. " REG2_OK ,Voltage level relative to the brownout level for the SOC supply" "Greater,Lower/Equal" newline bitfld.long 0x24 21. " REG2_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x24 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "Low,High" rbitfld.long 0x24 16.--18. " REG2_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" newline bitfld.long 0x24 13. " REG1_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x24 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "Low,High" rbitfld.long 0x24 8.--10. " REG1_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" newline bitfld.long 0x24 7. " PLL3_DISABLE ,PLL3 Disable" "Enabled,Disabled" newline bitfld.long 0x24 5. " REG0_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x24 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "Low,High" rbitfld.long 0x24 0.--2. " REG0_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" line.long 0x28 "CCM_ANALOG_MISC2_CLR,Miscellaneous Control Clear Register" bitfld.long 0x28 30.--31. " VIDEO_DIV ,Post-divider for video" "/1,/2,/1,/4" bitfld.long 0x28 28.--29. " REG2_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x28 26.--27. " REG1_STEP_TIME ,Number of clock periods" "64,128,256,512" newline bitfld.long 0x20 24.--25. " REG0_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x20 23. 15. " AUDIO_DIV ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" rbitfld.long 0x20 22. " REG2_OK ,Voltage level relative to the brownout level for the SOC supply" "Greater,Lower/Equal" newline bitfld.long 0x28 21. " REG2_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x28 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "Low,High" rbitfld.long 0x28 16.--18. " REG2_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" newline bitfld.long 0x28 13. " REG1_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x28 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "Low,High" rbitfld.long 0x28 8.--10. " REG1_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" newline bitfld.long 0x28 7. " PLL3_DISABLE ,PLL3 Disable" "Enabled,Disabled" newline bitfld.long 0x28 5. " REG0_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x28 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "Low,High" rbitfld.long 0x28 0.--2. " REG0_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" line.long 0x2C "CCM_ANALOG_MISC2_TOG,Miscellaneous Control Toggle Register" bitfld.long 0x2C 30.--31. " VIDEO_DIV ,Post-divider for video" "/1,/2,/1,/4" bitfld.long 0x2C 28.--29. " REG2_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x2C 26.--27. " REG1_STEP_TIME ,Number of clock periods" "64,128,256,512" newline bitfld.long 0x20 24.--25. " REG0_STEP_TIME ,Number of clock periods" "64,128,256,512" bitfld.long 0x20 23. 15. " AUDIO_DIV ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" rbitfld.long 0x20 22. " REG2_OK ,Voltage level relative to the brownout level for the SOC supply" "Greater,Lower/Equal" newline bitfld.long 0x2C 21. " REG2_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x2C 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "Low,High" rbitfld.long 0x2C 16.--18. " REG2_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" newline bitfld.long 0x2C 13. " REG1_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x2C 11. " REG1_BO_STATUS ,Reg1 brownout status bit" "Low,High" rbitfld.long 0x2C 8.--10. " REG1_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" newline bitfld.long 0x2C 7. " PLL3_DISABLE ,PLL3 Disable" "Enabled,Disabled" newline bitfld.long 0x2C 5. " REG0_ENABLE_BO ,Brownout detection" "Disabled,Enabled" rbitfld.long 0x2C 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "Low,High" rbitfld.long 0x2C 0.--2. " REG0_BO_OFFSET ,Brown out voltage offset for the xPU power domain" ",,,,0.100V,,,0.175V" width 0x0B tree.end tree.end tree "CSI (CMOS Sensor Interface)" base ad:0x020E8000 width 23. group.long 0x00++0x0B line.long 0x00 "CSICR1,CSI Control Register 1" bitfld.long 0x00 31. " SWAP16_EN ,SWAP 16-Bit enable" "Disabled,Enabled" bitfld.long 0x00 30. " EXT_VSYNC ,External VSYNC enable" "Internal,External" bitfld.long 0x00 29. " EOF_INT_EN ,End-of-Frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " PRP_IF_EN ,CSI-PrP interface enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CCIR_MODE ,CCIR mode select" "Progressive,Interlace" bitfld.long 0x00 26. " COF_INT_EN ,Change of image field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " SF_OR_INTEN ,STAT FIFO overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " RF_OR_INTEN ,RXFIFO overrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " SFF_DMA_DONE_INTEN ,STATFIFO DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " STATFF_INTEN ,STATFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " FB2_DMA_DONE_INTEN ,Frame buffer2 DMA transfer done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " FB1_DMA_DONE_INTEN ,Frame buffer1 DMA transfer done interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " RXFF_INTEN ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " SOF_POL ,SOF interrupt polarity" "Falling,Rising" bitfld.long 0x00 16. " SOF_INTEN ,Start of frame interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " HSYNC_POL ,HSYNC polarity Select" "Low,High" bitfld.long 0x00 10. " CCIR_EN ,CCIR656 interface enable" "Traditional,CCIR656" bitfld.long 0x00 8. " FCC ,FIFO clear control" "Asynchronous,Synchronous" bitfld.long 0x00 7. " PACK_DIR ,Data packing direction" "From LSB,From MSB" newline bitfld.long 0x00 6. " CLR_STATFIFO ,Asynchronous STATFIFO clear" "No effect,Clear" bitfld.long 0x00 5. " CLR_RXFIFO ,Asynchronous RXFIFO clear" "No effect,Clear" newline bitfld.long 0x00 4. " GCLK_MODE ,Gated clock mode enable" "Non-gated,Gated" bitfld.long 0x00 3. " INV_DATA ,This bit enables or disables internal inverters on the data lines" "Direct,Inverted" bitfld.long 0x00 2. " INV_PCLK ,Invert pixel clock input" "Direct,Inverted" newline bitfld.long 0x00 1. " REDGE ,Valid pixel clock edge select" "Falling,Rising" bitfld.long 0x00 0. " PIXEL_BIT ,This bit indicates the bayer data width for each pixel" "8-bit,10-bit" line.long 0x04 "CSICR2,CSI Control Register 2" bitfld.long 0x04 30.--31. " DMA_BURST_TYPE_RFF ,Burst type of DMA transfer from RXFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x04 28.--29. " DMA_BURST_TYPE_SFF ,Burst type of DMA transfer from STATFIFO" "INCR8,INCR4,INCR8,INCR16" bitfld.long 0x04 26. " DRM ,Controls size of statistics grid" "8x6,8x12" bitfld.long 0x04 24.--25. " AFS ,Selects which green pixels are used for auto-focus" "Consecutive,Every third,Every four,Every four" newline bitfld.long 0x04 23. " SCE ,Enables or disables the skip count feature" "Disabled,Enabled" bitfld.long 0x04 19.--20. " BTS ,Controls the bayer pattern starting point" "GR,RG,BG,GB" bitfld.long 0x04 16.--18. " LVRM ,Selects the grid size used for live view resolution" "512x384,448x336,384x288,384x256,320x240,288x216,400x300,?..." newline hexmask.long.byte 0x04 8.--15. 1. " VSC ,Number of rows to skip" hexmask.long.byte 0x04 0.--7. 1. " HSC ,Number of pixels to skip" line.long 0x08 "CSICR3,CSI Control Register 3" hexmask.long.word 0x08 16.--31. 1. " FRMCNT ,16-bit frame counter" bitfld.long 0x08 15. " FRMCNT_RST ,Frame count reset" "Not reset,Reset" bitfld.long 0x08 14. " DMA_REFLASH_RFF ,This bit reflash the embedded DMA controller for RXFIFO" "Not reflashed,Reflashed" bitfld.long 0x08 13. " DMA_REFLASH_SFF ,This bit reflash the embedded DMA controller for STATFIFO" "Not reflashed,Reflashed" newline bitfld.long 0x08 12. " DMA_REQ_EN_RFF ,DMA request enable for RXFIFO" "Disabled,Enabled" bitfld.long 0x08 11. " DMA_REQ_EN_SFF ,DMA request enable for STATFIFO" "Disabled,Enabled" bitfld.long 0x08 8.--10. " STATFF_LEVEL ,Number of data words in STATFIFO which generates an interrupt" "4,8,12,16,24,32,48,64" bitfld.long 0x08 7. " HRESP_ERR_EN ,Hresponse error interrupt" "Disabled,Enabled" newline bitfld.long 0x08 4.--6. " RXFF_LEVEL ,Number of data words after a RXFIFO full interrupt is generated" "4,8,16,24,32,48,64,96" bitfld.long 0x08 3. " TWO_8BIT_SENSOR ,Two 8-bit sensor mode" "Only one,Two 8-bit" bitfld.long 0x08 2. " ZERO_PACK_EN ,Dummy zero packing enable" "Disabled,Enabled" bitfld.long 0x08 1. " ECC_INT_EN ,Error detection interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " ECC_AUTO_EN ,Automatic error correction enable" "Disabled,Enabled" rgroup.long 0x0C++0x07 line.long 0x00 "CSISTATFIFO,CSI Statistic FIFO Register" line.long 0x04 "CSIRFIFO,CSI RX FIFO Register" group.long 0x14++0x07 line.long 0x00 "CSIRXCNT,CSI RX Count Register" hexmask.long.tbyte 0x00 0.--21. 1. " RXCNT ,22-bit counter for RXFIFO" line.long 0x04 "CSISR,CSI Status Register" eventfld.long 0x04 28. " BASEADDR_CHHANGE_ERROR ,Switching occurred before DMA completed" "No error,Error" eventfld.long 0x04 27. " DMA_FIELD0_DONE ,DMA field 0 is complete" "Not completed,Completed" eventfld.long 0x04 26. " DMA_FIELD1_DONE ,DMA field 1 is complete" "Not completed,Completed" eventfld.long 0x04 25. " SF_OR_INT ,STATFIFO overrun interrupt status" "Not overflowed,Overflowed" newline eventfld.long 0x04 24. " RF_OR_INT ,RXFIFO overrun interrupt status" "Not overflowed,Overflowed" eventfld.long 0x04 22. " DMA_TSF_DONE_SFF ,DMA transfer done from STATFIFO" "Not completed,Completed" bitfld.long 0x04 21. " STATFF_INT ,STATFIFO full interrupt status" "Not full,Full" eventfld.long 0x04 20. " DMA_TSF_DONE_FB2 ,DMA transfer done in frame buffer2" "Not completed,Completed" newline eventfld.long 0x04 19. " DMA_TSF_DONE_FB1 ,DMA transfer done in frame buffer1" "Not completed,Completed" bitfld.long 0x04 18. " RXFF_INT ,RXFIFO full interrupt status" "Not full,Full" eventfld.long 0x04 17. " EOF_INT ,End of frame (Eof) interrupt status" "Not detected,Detected" eventfld.long 0x04 16. " SOF_INT ,Start of frame interrupt status" "Not detected,Detected" newline bitfld.long 0x04 15. " F2_INT ,CCIR field 2 interrupt status" "Not detected,About to start" bitfld.long 0x04 14. " F1_INT ,CCIR field 1 interrupt status" "Not detected,About to start" eventfld.long 0x04 13. " COF_INT ,Change of field interrupt status" "Not changed,Change detected" newline eventfld.long 0x04 7. " HRESP_ERR_INT ,Hresponse error interrupt status" "No error,Error" eventfld.long 0x04 1. " ECC_INT ,CCIR error interrupt" "No error,Error" bitfld.long 0x04 0. " DRDY ,Presence of data that is ready for transfer in the RXFIFO" "Not ready,Ready" group.long 0x20++0x2F line.long 0x00 "CSIDMASA_STATFIFO,CSI DMA Start Address Register - For STATFIFO" hexmask.long 0x00 2.--31. 0x04 " DMA_START_ADDR_SFF ,Indicates the start address to write data" line.long 0x04 "CSIDMATS_STATFIFO,CSI DMA Transfer Size Register - For STATFIFO" line.long 0x08 "CSIDMASA_FB1,CSI DMA Start Address Register - For Frame Buffer1" hexmask.long 0x08 2.--31. 0x04 " DMA_START_ADDR_FB1 ,DMA start address in frame buffer1" line.long 0x0C "CSIDMASA_FB2,CSI DMA Transfer Size Register - For Frame Buffer2" hexmask.long 0x0C 2.--31. 0x04 " DMA_START_ADDR_FB2 ,DMA start address in frame buffer2" line.long 0x10 "CSIFBUF_PARA,CSI Frame Buffer Parameter Register" hexmask.long.word 0x10 0.--15. 1. " FBUF_STRIDE ,Indicates the stride of the frame buffer" line.long 0x14 "CSIIMAG_PARA,CSI Image Parameter Register" hexmask.long.word 0x14 16.--31. 1. " IMAGE_WIDTH ,Indicates how many pixels in a line of the image from the sensor" hexmask.long.word 0x14 0.--15. 1. " IMAGE_HEIGHT ,Indicates how many pixels in a column of the image from the sensor" width 0x0B tree.end tree "ECSPI (Enhanced Configurable SPI Registers)" tree "ECSPI 1" base ad:0x02008000 width 21. if (((per.l(ad:0x02008000+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI1_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI1_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI1_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI1_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" newline bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care,Falling edge,Low level,?..." bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" newline bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" newline bitfld.long 0x00 3. " SMC ,Start mode control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI block enable control" "Disabled,Enabled" if (((per.l(ad:0x02008000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip Select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip Select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02008000+0x08))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI1_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif group.long 0x10++0x13 line.long 0x00 "ECSPI1_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI1_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI1_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer completed status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO full bit" "Not full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO data request" "Not greater,Greater" newline rbitfld.long 0x08 3. " RR ,RXFIFO ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO data request" "Not greater,Greater" rbitfld.long 0x08 0. " TE ,TXFIFO empty" "Not empty,Empty" line.long 0x0C "ECSPI1_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip select delay control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock source control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 1. " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI1_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x10 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI1_MSGDATA,Message Data Register" width 0x0B tree.end tree "ECSPI 2" base ad:0x0200C000 width 21. if (((per.l(ad:0x0200C000+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI2_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI2_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI2_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI2_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" newline bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care,Falling edge,Low level,?..." bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" newline bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" newline bitfld.long 0x00 3. " SMC ,Start mode control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI block enable control" "Disabled,Enabled" if (((per.l(ad:0x0200C000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip Select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip Select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x0200C000+0x08))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI2_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif group.long 0x10++0x13 line.long 0x00 "ECSPI2_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI2_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI2_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer completed status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO full bit" "Not full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO data request" "Not greater,Greater" newline rbitfld.long 0x08 3. " RR ,RXFIFO ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO data request" "Not greater,Greater" rbitfld.long 0x08 0. " TE ,TXFIFO empty" "Not empty,Empty" line.long 0x0C "ECSPI2_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip select delay control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock source control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 1. " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI2_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x10 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI2_MSGDATA,Message Data Register" width 0x0B tree.end tree "ECSPI 3" base ad:0x02010000 width 21. if (((per.l(ad:0x02010000+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI3_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI3_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI3_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI3_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" newline bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care,Falling edge,Low level,?..." bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" newline bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" newline bitfld.long 0x00 3. " SMC ,Start mode control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI block enable control" "Disabled,Enabled" if (((per.l(ad:0x02010000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip Select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip Select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02010000+0x08))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI3_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif group.long 0x10++0x13 line.long 0x00 "ECSPI3_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI3_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI3_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer completed status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO full bit" "Not full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO data request" "Not greater,Greater" newline rbitfld.long 0x08 3. " RR ,RXFIFO ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO data request" "Not greater,Greater" rbitfld.long 0x08 0. " TE ,TXFIFO empty" "Not empty,Empty" line.long 0x0C "ECSPI3_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip select delay control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock source control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 1. " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI3_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x10 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI3_MSGDATA,Message Data Register" width 0x0B tree.end tree "ECSPI 4" base ad:0x02014000 width 21. if (((per.l(ad:0x02014000+0x10))&0x08)==0x08) rgroup.long 0x00++0x03 line.long 0x00 "ECSPI4_RXDATA,Receive Data Register" else hgroup.long 0x00++0x03 hide.long 0x00 "ECSPI4_RXDATA,Receive Data Register" in endif wgroup.long 0x04++0x03 line.long 0x00 "ECSPI4_TXDATA,Transmit Data Register" group.long 0x08++0x03 line.long 0x00 "ECSPI4_CONREG,Control Register" hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Length of a SPI burst to be transferred" newline bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI channel select bits" "Channel 0,Channel 1,Channel 2,Channel 3" bitfld.long 0x00 16.--17. " DRCTL ,SPI data ready control" "Don't care,Falling edge,Low level,?..." bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI pre divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI post divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" newline bitfld.long 0x00 7. " CHANNEL_MODE_3 ,Mode select for SPI channel 3" "Slave,Master" bitfld.long 0x00 6. " CHANNEL_MODE_2 ,Mode select for SPI channel 2" "Slave,Master" bitfld.long 0x00 5. " CHANNEL_MODE_1 ,Mode select for SPI channel 1" "Slave,Master" bitfld.long 0x00 4. " CHANNEL_MODE_0 ,Mode select for SPI channel 0" "Slave,Master" newline bitfld.long 0x00 3. " SMC ,Start mode control" "On XCH,Immediately" bitfld.long 0x00 2. " XCH ,SPI exchange bit" "Idle,Busy/Init" bitfld.long 0x00 1. " HT ,Hardware trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,SPI block enable control" "Disabled,Enabled" if (((per.l(ad:0x02014000+0x08))&0xF0)==0x00) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0x10) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0x20) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0x30) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0x40) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0x50) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0x60) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip Select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0x70) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip Select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip Select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip Select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip Select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "= BURST_LENGTH+1,?..." bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0x80) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0x90) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0xA0) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0xB0) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "= BURST_LENGTH+1,?..." bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0xC0) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0xD0) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "= BURST_LENGTH+1,?..." bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&0xF0)==0xE0) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "= BURST_LENGTH+1,?..." newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" elif (((per.l(ad:0x02014000+0x08))&(0xF0))==(0xF0)) group.long 0x0C++0x03 line.long 0x00 "ECSPI4_CONFIGREG,Config Register" bitfld.long 0x00 24.--28. " HT_LENGTH ,Message length in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 23. " SCK_CTL_3 ,Inactive state of SCLK for SPI channel 3" "Low,High" bitfld.long 0x00 22. " SCK_CTL_2 ,Inactive state of SCLK for SPI channel 2" "Low,High" bitfld.long 0x00 21. " SCK_CTL_1 ,Inactive state of SCLK for SPI channel 1" "Low,High" bitfld.long 0x00 20. " SCK_CTL_0 ,Inactive state of SCLK for SPI channel 0" "Low,High" newline bitfld.long 0x00 19. " DATA_CTL_3 ,Inactive state of data line for SPI channel 3" "High,Low" bitfld.long 0x00 18. " DATA_CTL_2 ,Inactive state of data line for SPI channel 2" "High,Low" bitfld.long 0x00 17. " DATA_CTL_1 ,Inactive state of data line for SPI channel 1" "High,Low" bitfld.long 0x00 16. " DATA_CTL_0 ,Inactive state of data line for SPI channel 0" "High,Low" newline bitfld.long 0x00 15. " SS_POL_3 ,Polarity of the chip select signal for SPI channel 3" "Low,High" bitfld.long 0x00 14. " SS_POL_2 ,Polarity of the chip select signal for SPI channel 2" "Low,High" bitfld.long 0x00 13. " SS_POL_1 ,Polarity of the chip select signal for SPI channel 1" "Low,High" bitfld.long 0x00 12. " SS_POL_0 ,Polarity of the chip select signal for SPI channel 0" "Low,High" newline bitfld.long 0x00 11. " SS_CTL_3 ,Output waveform of the chip select signal for SPI channel 3" "Single burst,Multiple bursts" bitfld.long 0x00 10. " SS_CTL_2 ,Output waveform of the chip select signal for SPI channel 2" "Single burst,Multiple bursts" bitfld.long 0x00 9. " SS_CTL_1 ,Output waveform of the chip select signal for SPI channel 1" "Single burst,Multiple bursts" bitfld.long 0x00 8. " SS_CTL_0 ,Output waveform of the chip select signal for SPI channel 0" "Single burst,Multiple bursts" newline bitfld.long 0x00 7. " SCLK_POL_3 ,Polarity of the SCLK signal for SPI channel 3" "High,Low" bitfld.long 0x00 6. " SCLK_POL_2 ,Polarity of the SCLK signal for SPI channel 2" "High,Low" bitfld.long 0x00 5. " SCLK_POL_1 ,Polarity of the SCLK signal for SPI channel 1" "High,Low" bitfld.long 0x00 4. " SCLK_POL_0 ,Polarity of the SCLK signal for SPI channel 0" "High,Low" newline bitfld.long 0x00 3. " SCLK_PHA_3 ,Control of the clock/data phase relationship for SPI channel 3" "Phase 0,Phase 1" bitfld.long 0x00 2. " SCLK_PHA_2 ,Control of the clock/data phase relationship for SPI channel 2" "Phase 0,Phase 1" bitfld.long 0x00 1. " SCLK_PHA_1 ,Control of the clock/data phase relationship for SPI channel 1" "Phase 0,Phase 1" bitfld.long 0x00 0. " SCLK_PHA_0 ,Control of the clock/data phase relationship for SPI channel 0" "Phase 0,Phase 1" endif group.long 0x10++0x13 line.long 0x00 "ECSPI4_INTREG,Interrupt Control Register" bitfld.long 0x00 7. " TCEN ,Transfer completed interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " ROEN ,RXFIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RFEN ,RXFIFO full Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RDREN ,RXFIFO data request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " RREN ,RXFIFO ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TFEN ,TXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TDREN ,TXFIFO data request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEEN ,TXFIFO empty interrupt enable" "Disabled,Enabled" line.long 0x04 "ECSPI4_DMAREG,DMA Control Register" bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA request enable" "Disabled,Enabled" bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,The burst length of a DMA operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA request enable" "Disabled,Enabled" bitfld.long 0x04 16.--21. " RX_THRESHOLD ,FIFO threshold that triggers a RX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA request enable" "Disabled,Enabled" bitfld.long 0x04 0.--5. " TX_THRESHOLD ,FIFO threshold that triggers a TX DMA/INT request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ECSPI4_STATREG,Status Register" eventfld.long 0x08 7. " TC ,Transfer completed status bit" "In progress,Completed" eventfld.long 0x08 6. " RO ,RXFIFO overflow" "No overflow,Overflow" rbitfld.long 0x08 5. " RF ,RXFIFO full bit" "Not full,Full" rbitfld.long 0x08 4. " RDR ,RXFIFO data request" "Not greater,Greater" newline rbitfld.long 0x08 3. " RR ,RXFIFO ready" "Not ready,Ready" rbitfld.long 0x08 2. " TF ,TXFIFO full" "Not full,Full" rbitfld.long 0x08 1. " TDR ,TXFIFO data request" "Not greater,Greater" rbitfld.long 0x08 0. " TE ,TXFIFO empty" "Not empty,Empty" line.long 0x0C "ECSPI4_PERIODREG,Sample Period Control Register" bitfld.long 0x0C 16.--21. " CSD_CTL ,Chip select delay control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 15. " CSRC ,Clock source control" "SPI Clock,Low-Freq Ref." hexmask.long.word 0x0C 0.--14. 1. " SAMPLE_PERIOD ,Number of wait states to be inserted in data transfers" line.long 0x10 "ECSPI4_TESTREG,Test Control Register" bitfld.long 0x10 31. " LBC ,Loop back control" "Not connected,Connected" hexmask.long.byte 0x10 8.--14. 1. " RXCNT ,RXFIFO counter" hexmask.long.byte 0x10 0.--6. 1. " TXCNT ,TXFIFO counter" wgroup.long 0x40++0x03 line.long 0x00 "ECSPI4_MSGDATA,Message Data Register" width 0x0B tree.end tree.end tree "ELCDIF (Enhanced LCD Interface)" base ad:0x020F8000 width 18. tree "Control Registers" group.long 0x00++0x2F line.long 0x00 "LCDIF1_CTRL,eLCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Operation of the eLCDIF" "Normal operation,Block level reset" bitfld.long 0x00 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x00 29. " YCBCR422_INPUT ,Color format" "RGB,YCbCr 422" newline bitfld.long 0x00 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "Low,High" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,Mode" "Low,High" bitfld.long 0x00 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command Mode polarity bit" "Command,Data" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endian,Half-words,Bytes/Half-word" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big Endian,Half-words,Bytes/Half-word" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16 bit,8 bit,18 bit,24 bit" newline bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between eLCDIF and ePXP" "Disabled,Enabled" newline bitfld.long 0x00 5. " MASTER ,eLCDIF mode" "PIO,Bus master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24bit data format" "All valid,Drop 2 bits" bitfld.long 0x00 0. " RUN ,Transferring data between the SoC and the display" "Not running,Running" line.long 0x04 "LCDIF1_CTRL_SET,eLCDIF General Control Register" bitfld.long 0x04 31. " SFTRST ,Operation of the eLCDIF" "Normal operation,Block level reset" bitfld.long 0x04 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x04 29. " YCBCR422_INPUT ,Color format" "RGB,YCbCr 422" newline bitfld.long 0x04 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x04 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "Low,High" bitfld.long 0x04 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x04 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20. " DVI_MODE ,Mode" "Low,High" bitfld.long 0x04 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x04 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x04 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x04 16. " DATA_SELECT ,Command Mode polarity bit" "Command,Data" newline bitfld.long 0x04 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endian,Half-words,Bytes/Half-word" bitfld.long 0x04 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big Endian,Half-words,Bytes/Half-word" bitfld.long 0x04 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16 bit,8 bit,18 bit,24 bit" newline bitfld.long 0x04 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x04 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x04 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between eLCDIF and ePXP" "Disabled,Enabled" newline bitfld.long 0x04 5. " MASTER ,eLCDIF mode" "PIO,Bus master" bitfld.long 0x04 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x04 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x04 1. " DATA_FORMAT_24_BIT ,24bit data format" "All valid,Drop 2 bits" bitfld.long 0x04 0. " RUN ,Transferring data between the SoC and the display" "Not running,Running" line.long 0x08 "LCDIF1_CTRL_CLR,eLCDIF General Control Register" bitfld.long 0x08 31. " SFTRST ,Operation of the eLCDIF" "Normal operation,Block level reset" bitfld.long 0x08 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x08 29. " YCBCR422_INPUT ,Color format" "RGB,YCbCr 422" newline bitfld.long 0x08 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x08 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "Low,High" bitfld.long 0x08 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x08 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20. " DVI_MODE ,Mode" "Low,High" bitfld.long 0x08 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x08 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x08 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x08 16. " DATA_SELECT ,Command Mode polarity bit" "Command,Data" newline bitfld.long 0x08 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endian,Half-words,Bytes/Half-word" bitfld.long 0x08 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big Endian,Half-words,Bytes/Half-word" bitfld.long 0x08 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16 bit,8 bit,18 bit,24 bit" newline bitfld.long 0x08 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x08 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x08 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between eLCDIF and ePXP" "Disabled,Enabled" newline bitfld.long 0x08 5. " MASTER ,eLCDIF mode" "PIO,Bus master" bitfld.long 0x08 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x08 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x08 1. " DATA_FORMAT_24_BIT ,24bit data format" "All valid,Drop 2 bits" bitfld.long 0x08 0. " RUN ,Transferring data between the SoC and the display" "Not running,Running" line.long 0x0C "LCDIF1_CTRL_TOG,eLCDIF General Control Register" bitfld.long 0x0C 31. " SFTRST ,Operation of the eLCDIF" "Normal operation,Block level reset" bitfld.long 0x0C 30. " CLKGATE ,Clock gating" "Normal,Gated off" bitfld.long 0x0C 29. " YCBCR422_INPUT ,Color format" "RGB,YCbCr 422" newline bitfld.long 0x0C 28. " READ_WRITEB ,Mode select" "Write mode,6800/8080 MPU read mode" bitfld.long 0x0C 27. " WAIT_FOR_VSYNC_EDGE ,VSYNC edge triggering" "Low,High" bitfld.long 0x0C 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x0C 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 20. " DVI_MODE ,Mode" "Low,High" bitfld.long 0x0C 19. " BYPASS_COUNT ,Block operation controller" "Transfer count,Block itself" newline bitfld.long 0x0C 18. " VSYNC_MODE ,VSYNC mode" "Disabled,Enabled" bitfld.long 0x0C 17. " DOTCLK_MODE ,DOTCLK mode" "Disabled,Enabled" bitfld.long 0x0C 16. " DATA_SELECT ,Command Mode polarity bit" "Command,Data" newline bitfld.long 0x0C 14.--15. " INPUT_DATA_SWIZZLE ,Swapping the bytes fetched by the bus master interface" "No swap,Big endian,Half-words,Bytes/Half-word" bitfld.long 0x0C 12.--13. " CSC_DATA_SWIZZLE ,Swapping the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "No swap,Big Endian,Half-words,Bytes/Half-word" bitfld.long 0x0C 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16 bit,8 bit,18 bit,24 bit" newline bitfld.long 0x0C 8.--9. " WORD_LENGTH ,Input data format" "16 bit,8 bit,18 bit,24 bit" bitfld.long 0x0C 7. " RGB_TO_YCBCR422_CSC ,Conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x0C 6. " ENABLE_PXP_HANDSHAKE ,Handshake mechanism between eLCDIF and ePXP" "Disabled,Enabled" newline bitfld.long 0x0C 5. " MASTER ,eLCDIF mode" "PIO,Bus master" bitfld.long 0x0C 3. " DATA_FORMAT_16_BIT ,16bit data format" "RGB565,ARGB555" bitfld.long 0x0C 2. " DATA_FORMAT_18_BIT ,18bit data format" "Lower,Upper" newline bitfld.long 0x0C 1. " DATA_FORMAT_24_BIT ,24bit data format" "All valid,Drop 2 bits" bitfld.long 0x0C 0. " RUN ,Transferring data between the SoC and the display" "Not running,Running" line.long 0x10 "LCDIF1_CTRL1,eLCDIF General Control1 Register" bitfld.long 0x10 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWn/LCD_RD_E,LCD_WR_RWn" bitfld.long 0x10 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" bitfld.long 0x10 25. " BM_ERROR_IRQ ,Interrupt request by the eLCDIF block" "Not requested,Requested" newline bitfld.long 0x10 24. " RECOVER_ON_UNDERFLOW ,eLCDIF block recovery in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x10 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by eLCDIF block" "Not required,Required" newline bitfld.long 0x10 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x10 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x10 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x10 19. " BYTE_PACKING_FORMAT_3 ,Bit field is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x10 18. " BYTE_PACKING_FORMAT_2 ,Bit field is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x10 17. " BYTE_PACKING_FORMAT_1 ,Bit field is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x10 16. " BYTE_PACKING_FORMAT_0 ,Bit field is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x10 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x10 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x10 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x10 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x10 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x10 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the eLCDIF block when" "Not requested,Requested" newline bitfld.long 0x10 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the eLCDIF block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x10 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the eLCDIF block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x10 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x10 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x10 0. " RESET ,Reset bit for the external LCD controller" "LCDRESET_LOW,LCDRESET_HIGH" line.long 0x14 "LCDIF1_CTRL1_SET,eLCDIF General Control1 Register" bitfld.long 0x14 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWn/LCD_RD_E,LCD_WR_RWn" bitfld.long 0x14 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" bitfld.long 0x14 25. " BM_ERROR_IRQ ,Interrupt request by the eLCDIF block" "Not requested,Requested" newline bitfld.long 0x14 24. " RECOVER_ON_UNDERFLOW ,eLCDIF block recovery in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x14 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by eLCDIF block" "Not required,Required" newline bitfld.long 0x14 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x14 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x14 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x14 19. " BYTE_PACKING_FORMAT_3 ,Bit field is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x14 18. " BYTE_PACKING_FORMAT_2 ,Bit field is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x14 17. " BYTE_PACKING_FORMAT_1 ,Bit field is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x14 16. " BYTE_PACKING_FORMAT_0 ,Bit field is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x14 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x14 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x14 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x14 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x14 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x14 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the eLCDIF block when" "Not requested,Requested" newline bitfld.long 0x14 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the eLCDIF block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x14 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the eLCDIF block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x14 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x14 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x14 0. " RESET ,Reset bit for the external LCD controller" "LCDRESET_LOW,LCDRESET_HIGH" line.long 0x18 "LCDIF1_CTRL1_CLR,eLCDIF General Control1 Register" bitfld.long 0x18 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWn/LCD_RD_E,LCD_WR_RWn" bitfld.long 0x18 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" bitfld.long 0x18 25. " BM_ERROR_IRQ ,Interrupt request by the eLCDIF block" "Not requested,Requested" newline bitfld.long 0x18 24. " RECOVER_ON_UNDERFLOW ,eLCDIF block recovery in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x18 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by eLCDIF block" "Not required,Required" newline bitfld.long 0x18 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x18 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x18 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x18 19. " BYTE_PACKING_FORMAT_3 ,Bit field is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x18 18. " BYTE_PACKING_FORMAT_2 ,Bit field is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x18 17. " BYTE_PACKING_FORMAT_1 ,Bit field is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x18 16. " BYTE_PACKING_FORMAT_0 ,Bit field is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x18 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x18 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x18 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x18 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x18 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x18 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the eLCDIF block when" "Not requested,Requested" newline bitfld.long 0x18 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the eLCDIF block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x18 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the eLCDIF block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x18 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x18 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x18 0. " RESET ,Reset bit for the external LCD controller" "LCDRESET_LOW,LCDRESET_HIGH" line.long 0x1C "LCDIF1_CTRL1_TOG,eLCDIF General Control1 Register" bitfld.long 0x1C 27. " COMBINE_MPU_WR_STRB ,Write strobe driving" "LCD_WR_RWn/LCD_RD_E,LCD_WR_RWn" bitfld.long 0x1C 26. " BM_ERROR_IRQ_EN ,Bus master error interrupt in the eLCDIF master mode" "Disabled,Enabled" bitfld.long 0x1C 25. " BM_ERROR_IRQ ,Interrupt request by the eLCDIF block" "Not requested,Requested" newline bitfld.long 0x1C 24. " RECOVER_ON_UNDERFLOW ,eLCDIF block recovery in the next field/frame if there was an underflow in the current field/frame" "Disabled,Enabled" bitfld.long 0x1C 23. " INTERLACE_FIELDS ,Fetching odd lines in one field and even lines in the other field by eLCDIF block" "Not required,Required" newline bitfld.long 0x1C 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grabbing the odd lines first and then the even lines" "Not required,Required" newline bitfld.long 0x1C 21. " FIFO_CLEAR ,Clearing all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x1C 20. " IRQ_ON_ALTERNATE_FIELDS ,Assertion of the cur_frame_done interrupt" "Odd and even fields,Alternate fields" bitfld.long 0x1C 19. " BYTE_PACKING_FORMAT_3 ,Bit field is used to show that 1st most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x1C 18. " BYTE_PACKING_FORMAT_2 ,Bit field is used to show that 2nd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x1C 17. " BYTE_PACKING_FORMAT_1 ,Bit field is used to show that 3rd most significant data byte in a 32-bit word is valid" "Not valid,Valid" bitfld.long 0x1C 16. " BYTE_PACKING_FORMAT_0 ,Bit field is used to show that 4th most significant data byte in a 32-bit word is valid" "Not valid,Valid" newline bitfld.long 0x1C 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x1C 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode" "Disabled,Enabled" bitfld.long 0x1C 13. " CUR_FRAME_DONE_IRQ_EN ,Hardware entered in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x1C 12. " VSYNC_EDGE_IRQ_EN ,Hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode" "Disabled,Enabled" bitfld.long 0x1C 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the eLCDIF block" "Not requested,Requested" bitfld.long 0x1C 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the eLCDIF block when" "Not requested,Requested" newline bitfld.long 0x1C 9. " CUR_FRAME_DONE_IRQ ,Interrupt is requested by the eLCDIF block when the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes" "Not requested,Requested" bitfld.long 0x1C 8. " VSYNC_EDGE_IRQ_EN ,Interrupt is requested by the eLCDIF block when VSYNC edge is detected in the VSYNC and DOTCLK modes" "Not requested,Requested" bitfld.long 0x1C 2. " BUSY_ENABLE ,Use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x1C 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080_MODE,6800_MODE" bitfld.long 0x1C 0. " RESET ,Reset bit for the external LCD controller" "LCDRESET_LOW,LCDRESET_HIGH" line.long 0x20 "LCDIF1_CTRL2,eLCDIF General Control2 Register" bitfld.long 0x20 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x20 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x20 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x20 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x20 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" newline bitfld.long 0x20 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data conversion to the RGB format given by WORD_LENGTH bit field" "Disabled,Enabled" newline bitfld.long 0x20 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x20 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x20 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x24 "LCDIF1_CTRL2_SET,eLCDIF General Control2 Register" bitfld.long 0x24 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x24 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x24 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x24 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x24 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" newline bitfld.long 0x24 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data conversion to the RGB format given by WORD_LENGTH bit field" "Disabled,Enabled" newline bitfld.long 0x24 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x24 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x24 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x28 "LCDIF1_CTRL2_CLR,eLCDIF General Control2 Register" bitfld.long 0x28 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x28 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x28 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x28 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x28 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" newline bitfld.long 0x28 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data conversion to the RGB format given by WORD_LENGTH bit field" "Disabled,Enabled" newline bitfld.long 0x28 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x28 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x28 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x2C "LCDIF1_CTRL2_TOG,eLCDIF General Control2 Register" bitfld.long 0x2C 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master" "REQ_1,REQ_2,REQ_4,REQ_8,REQ_16,?..." bitfld.long 0x2C 20. " BURST_LEN_8 ,Issuing bursts of length 8" "Disabled,Enabled" bitfld.long 0x2C 16.--18. " ODD_LINE_PATTERN ,Order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x2C 12.--14. " EVEN_LINE_PATTERN ,Order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x2C 10. " READ_PACK_DIR ,Direction of reading data bits" "Little endian,Big endian" newline bitfld.long 0x2C 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data conversion to the RGB format given by WORD_LENGTH bit field" "Disabled,Enabled" newline bitfld.long 0x2C 8. " READ_MODE_6_BIT_INPUT ,6 bit input mode" "Disabled,Enabled" bitfld.long 0x2C 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x2C 1.--3. " INITIAL_DUMMY_READ ,Indicates the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" tree.end newline width 23. group.long 0x30++0x03 line.long 0x00 "LCDIF1_TRANSFER_COUNT,eLCDIF Horizontal and Vertical Valid Data Count Register" hexmask.long.word 0x00 16.--31. 1. " V_COUNT ,Number of horizontal lines per frame which contain valid data" hexmask.long.word 0x00 0.--15. 1. " H_COUNT ,Total valid data (pixels) in each horizontal line" group.long 0x40++0x03 line.long 0x00 "LCDIF1_CUR_BUF,LCD Interface Current Buffer Address Register" group.long 0x50++0x03 line.long 0x00 "LCDIF1_NEXT_BUF,LCD Interface Next Buffer Address Register" group.long 0x60++0x03 line.long 0x00 "LCDIF1_TIMING,LCD Interface Timing Register" hexmask.long.byte 0x00 24.--31. 1. " CMD_HOLD ,Number of CLK_DIS_LCDIFn cycles that the DCn signal is active after CEn is deasserted" hexmask.long.byte 0x00 16.--23. 1. " CMD_SETUP ,Number of CLK_DIS_LCDIFn cycles that the DCn signal is active before CEn is asserted" hexmask.long.byte 0x00 8.--15. 1. " DATA_HOLD ,Data bus hold time in CLK_DIS_LCDIFn cycles" newline hexmask.long.byte 0x00 0.--7. 1. " DATA_SETUP ,Data bus setup time in CLK_DIS_LCDIFn cycles" width 20. tree "VDCTRL" group.long 0x70++0x0F line.long 0x00 "LCDIF1_VDCTRL0,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Enable present" "Low,High" bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity [launched/captured]" "Negative/Positive,Positive/Negative" bitfld.long 0x00 24. " ENABLE_POL ,Enable polarity" "Low,High" newline bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" bitfld.long 0x00 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" newline bitfld.long 0x00 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x04 "LCDIF1_VDCTRL0_SET,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x04 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x04 28. " ENABLE_PRESENT ,Enable present" "Low,High" bitfld.long 0x04 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x04 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" bitfld.long 0x04 25. " DOTCLK_POL ,DOTCLK polarity [launched/captured]" "Negative/Positive,Positive/Negative" bitfld.long 0x04 24. " ENABLE_POL ,Enable polarity" "Low,High" newline bitfld.long 0x04 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x04 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" bitfld.long 0x04 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" newline bitfld.long 0x04 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x04 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x08 "LCDIF1_VDCTRL0_CLR,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x08 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x08 28. " ENABLE_PRESENT ,Enable present" "Low,High" bitfld.long 0x08 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x08 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" bitfld.long 0x08 25. " DOTCLK_POL ,DOTCLK polarity [launched/captured]" "Negative/Positive,Positive/Negative" bitfld.long 0x08 24. " ENABLE_POL ,Enable polarity" "Low,High" newline bitfld.long 0x08 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x08 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" bitfld.long 0x08 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" newline bitfld.long 0x08 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x08 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x0C "LCDIF1_VDCTRL0_TOG,eLCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x0C 29. " VSYNC_OEB ,VSYNC mode" "Output,Input" bitfld.long 0x0C 28. " ENABLE_PRESENT ,Enable present" "Low,High" bitfld.long 0x0C 27. " VSYNC_POL ,VSYNC polarity" "Not inverted,Inverted" newline bitfld.long 0x0C 26. " HSYNC_POL ,HSYNC polarity" "Not inverted,Inverted" bitfld.long 0x0C 25. " DOTCLK_POL ,DOTCLK polarity [launched/captured]" "Negative/Positive,Positive/Negative" bitfld.long 0x0C 24. " ENABLE_POL ,Enable polarity" "Low,High" newline bitfld.long 0x0C 21. " VSYNC_PERIOD_UNIT ,Terms of counting VSYNC_PERIOD" "Cycles,Horizontal lines" bitfld.long 0x0C 20. " VSYNC_PULSE_WIDTH_UNIT ,Terms of counting VSYNC_PULSE_WIDTH" "Cycles,Horizontal lines" bitfld.long 0x0C 19. " HALF_LINE ,Adding to VSYNC_PERIOD half of the HORIZONTAL_PERIOD field" "Disabled,Enabled" newline bitfld.long 0x0C 18. " HALF_LINE_MODE ,Enable beginning with half a horizontal line" "Disabled,Enabled" hexmask.long.tbyte 0x0C 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" group.long 0x80++0x03 line.long 0x00 "LCDIF1_VDCTRL1,eLCDIF VSYNC Mode and Dotclk Mode Control Register 1" group.long 0x90++0x03 line.long 0x00 "LCDIF1_VDCTRL2,eLCDIF VSYNC Mode and Dotclk Mode Control Register 2" hexmask.long.word 0x00 18.--31. 1. " HSYNC_PULSE_WIDTH ,Number of CLK_DIS_LCDIFn cycles for which HSYNC signal is active" hexmask.long.tbyte 0x00 0.--17. 1. " HSYNC_PERIOD ,Total number of CLK_DIS_LCDIFn cycles between two positive or two negative edges of the HSYNC signal" group.long 0xA0++0x03 line.long 0x00 "LCDIF1_VDCTRL3,eLCDIF VSYNC Mode and Dotclk Mode Control Register 3" bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Internally multiplexed signals" "Separated,Multiplexed" bitfld.long 0x00 28. " VSYNC_ONLY ,Mode of operation" "DOTCLK,VSYNC" newline hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,Wait for this number of clocks from edge" newline hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Wait for this number of CLK_DIS_LCDIFn cycles from the VSYNC edge before starting LCD transactions" group.long 0xB0++0x03 line.long 0x00 "LCDIF1_VDCTRL4,eLCDIF VSYNC Mode and Dotclk Mode Control Register 4" bitfld.long 0x00 29.--31. " DOTCLK_DLY_SEL ,Amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin" "2ns,4ns,6ns,8ns,?..." newline bitfld.long 0x00 18. " SYNC_SIGNALS_ON ,VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame" "Low,High" hexmask.long.tbyte 0x00 0.--17. 1. " DOTCLK_H_VALID_DATA_CNT ,Total number of CLK_DIS_LCDIFn cycles on each horizontal line that carry valid data in DOTCLK mode" tree.end width 17. tree "DVICTRLx Registers" group.long 0xC0++0x03 line.long 0x00 "LCDIF1_DVICTRL0,Digital Video Interface Control 0 Register" hexmask.long.word 0x00 16.--27. 1. " H_ACTIVE_CNT ,Number of active video samples to be transmitted" hexmask.long.word 0x00 0.--11. 1. " H_BLANKING_CNT ,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval" group.long 0xD0++0x03 line.long 0x00 "LCDIF1_DVICTRL1,Digital Video Interface Control 1 Register" hexmask.long.word 0x00 20.--29. 1. " F1_START_LINE ,Vertical line number from which Field 1 begins" hexmask.long.word 0x00 10.--19. 1. " F1_END_LINE ,Vertical line number at which Field 1 ends" hexmask.long.word 0x00 0.--9. 1. " F2_START_LINE ,Vertical line number from which Field 2 begins" group.long 0xE0++0x03 line.long 0x00 "LCDIF1_DVICTRL2,Digital Video Interface Control 2 Register" hexmask.long.word 0x00 20.--29. 1. " F2_END_LINE ,Vertical line number at which Field 2 ends" hexmask.long.word 0x00 10.--19. 1. " V1_BLANK_START_LINE ,Vertical line number towards the end of Field1 where first Vertical Blanking interval starts" hexmask.long.word 0x00 0.--9. 1. " V1_BLANK_END_LINE ,Vertical line number in the beginning part of Field2 where first Vertical Blanking interval ends" group.long 0xF0++0x03 line.long 0x00 "LCDIF1_DVICTRL3,Digital Video Interface Control 3 Register" hexmask.long.word 0x00 20.--29. 1. " V2_BLANK_START_LINE ,Vertical line number towards the end of Field2 where second Vertical Blanking interval starts" hexmask.long.word 0x00 10.--19. 1. " V2_BLANK_END_LINE ,Vertical line number in the beginning part of Field1 where second Vertical Blanking interval ends" hexmask.long.word 0x00 0.--9. 1. " V_LINES_CNT ,Total number of vertical lines per frame" group.long 0x100++0x03 line.long 0x00 "LCDIF1_DVICTRL4,Digital Video Interface Control 4 Register" hexmask.long.byte 0x00 24.--31. 1. " Y_FILL_VALUE ,Value of Y component of filler data" hexmask.long.byte 0x00 16.--23. 1. " CB_FILL_VALUE ,Value of CB component of filler data" hexmask.long.byte 0x00 8.--15. 1. " CR_FILL_VALUE ,Value of CR component of filler data" newline hexmask.long.byte 0x00 0.--7. 1. " H_FILL_CNT ,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval" tree.end width 19. tree "COEFFx Registers" group.long 0x110++0x03 line.long 0x00 "LCDIF1_CSC_COEFF0,RGB to YCbCr 4:2:2 CSC Coefficient0 Register" hexmask.long.word 0x00 16.--25. 1. " C0 ,Two's complement red multiplier coefficient for Y" bitfld.long 0x00 0.--1. " CSC_SUBSAMPLE_FILTER ,Filtering and subsampling scheme to be performed on the chroma components in order to convert from YCbCr 4:4:4 to YCbCr 4:2:2 space" "Sample/Hold,,INTERSTITIAL,COSITED" group.long 0x120++0x03 line.long 0x00 "LCDIF1_CSC_COEFF1,RGB to YCbCr 4:2:2 CSC Coefficient1 Register" hexmask.long.word 0x00 16.--25. 1. " C2 ,Two's complement blue multiplier coefficient for Y" hexmask.long.word 0x00 0.--9. 1. " C1 ,Two's complement green multiplier coefficient for Y" group.long 0x130++0x03 line.long 0x00 "LCDIF1_CSC_COEFF2,RGB to YCbCr 4:2:2 CSC Coefficient2 Register" hexmask.long.word 0x00 16.--25. 1. " C4 ,Two's complement green multiplier coefficient for cb" hexmask.long.word 0x00 0.--9. 1. " C3 ,Two's complement red multiplier coefficient for cb" group.long 0x140++0x03 line.long 0x00 "LCDIF1_CSC_COEFF3,RGB to YCbCr 4:2:2 CSC Coefficient3 Register" hexmask.long.word 0x00 16.--25. 1. " C6 ,Two's complement red multiplier coefficient for cr" hexmask.long.word 0x00 0.--9. 1. " C5 ,Two's complement blue multiplier coefficient for cb" group.long 0x150++0x03 line.long 0x00 "LCDIF1_CSC_COEFF4,RGB to YCbCr 4:2:2 CSC Coefficient4 Register" hexmask.long.word 0x00 16.--25. 1. " C8 ,Two's complement blue multiplier coefficient for cr" hexmask.long.word 0x00 0.--9. 1. " C7 ,Two's complement green multiplier coefficient for cr" tree.end newline width 22. group.long 0x160++0x03 line.long 0x00 "LCDIF1_CSC_OFFSET,RGB to YCbCr 4:2:2 CSC Offset Register" hexmask.long.word 0x00 16.--24. 1. " CBCR_OFFSET ,Two's complement offset for the cb and cr components" hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two's complement offset for the Y component" group.long 0x170++0x03 line.long 0x00 "LCDIF1_CSC_LIMIT,RGB to YCbCr 4:2:2 CSC Limit Register" hexmask.long.byte 0x00 24.--31. 1. " CBCR_MIN ,Lower limit of cb and cr after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 16.--23. 1. " CBCR_MAX ,Upper limit of cb and cr after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 8.--15. 1. " Y_MIN ,Lower limit of Y after RGB to 4:2:2 YCbCr conversion" newline hexmask.long.byte 0x00 0.--7. 1. " Y_MAX ,Upper limit of Y after RGB to 4:2:2 YCbCr conversion" group.long 0x180++0x03 line.long 0x00 "LCDIF1_DATA,LCD Interface Data Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_THREE ,Byte 3 (most significant byte) of data written to LCDIF" hexmask.long.byte 0x00 16.--23. 1. " DATA_TWO ,Byte 2 of data written to eLCDIF" hexmask.long.byte 0x00 8.--15. 1. " DATA_ONE ,Byte 1 of data written to eLCDIF" newline hexmask.long.byte 0x00 0.--7. 1. " DATA_ZERO ,Byte 0 (least significant byte) of data written to eLCDIF" group.long 0x190++0x03 line.long 0x00 "LCDIFx_BM_ERROR_STAT,Bus Master Error Status Register" group.long 0x1A0++0x03 line.long 0x00 "LCDIFx_CRC_STAT,CRC Status Register" rgroup.long 0x1B0++0x03 line.long 0x00 "LCDIFx_STAT,LCD Interface Status Register" bitfld.long 0x00 31. " PRESENT ,eLCDIF presence" "Not present,Present" bitfld.long 0x00 29. " LFIFO_FULL ,Indicates that LCD read datapath FIFO is full" "Not full,Full" bitfld.long 0x00 28. " LFIFO_EMPTY ,Indicates that LCD read datapath FIFO is empty" "Not empty,Empty" newline bitfld.long 0x00 27. " TXFIFO_FULL ,Indicates that LCD write datapath FIFO is full" "Not full,Full" bitfld.long 0x00 26. " TXFIFO_EMPTY ,Indicates that LCD write datapath FIFO is empty" "Not empty,Empty" bitfld.long 0x00 25. " BUSY ,View of the input busy signal from the external LCD controller" "Not busy,Busy" newline bitfld.long 0x00 24. " DVI_CURRENT_FIELD ,View of the current field being transmitted" "Field 1,Field 2" hexmask.long.word 0x00 0.--8. 1. " LFIFO_COUNT ,Current count in Latency buffer" group.long 0x200++0x03 line.long 0x00 "LCDIF1_THRES,eLCDIF Threshold Register" hexmask.long.word 0x00 16.--24. 1. " FASTCLOCK ,Fast clock control output" hexmask.long.word 0x00 0.--8. 1. " PANIC ,Panic level" width 22. tree "AS registers" group.long 0x210++0x03 line.long 0x00 "LCDIF1_AS_CTRL,eLCDIF AS Buffer Control Register" bitfld.long 0x00 31. " CSI_VSYNC_ENABLE ,LCDIF work as sync mode with CSI input" "Disabled,Enabled" bitfld.long 0x00 30. " CSI_VSYNC_POL ,CSI VSYNC polarity" "Not inverted,Inverted" bitfld.long 0x00 29. " CSI_VSYNC_MODE ,Vsync generate mode" "Internal,External" newline bitfld.long 0x00 28. " CSI_SYNC_ON_IRQ_EN ,Interrupt when LCDIF lock with CSI vsync input" "Enabled,Disabled" bitfld.long 0x00 27. " CSI_SYNC_ON_IRQ ,Vsync generate mode" "Internal,External" bitfld.long 0x00 23. " PS_DISABLE ,LCDIF will disable PS buffer data" "No,Yes" newline bitfld.long 0x00 21.--22. " INPUT_DATA_SWIZZLE ,How to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF" "No swap,Big endian,Hafl-words,Bytes/Half-word" bitfld.long 0x00 20. " ALPHA_INVERT ,Alpha value inversion" "Unaffected,Inverted" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "MASKAS,MASKNOTAS,MASKASNOT,MERGEAS,MERGENOTAS,MERGEASNOT,NOTCOPYAS,NOT,NOTMASKAS,NOTMERGEAS,XORAS,NOTXORAS,?..." newline hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL" bitfld.long 0x00 4.--7. " FORMAT ,Indicates the input buffer format for AS" "ARGB8888,,,,RGB888,,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Color key functionality for alpha surface" "Disabled,Enabled" newline bitfld.long 0x00 1.--2. " ALPHA_CTRL ,Alpha value construction" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " AS_ENABLE ,Fetching AS buffer data in bus master mode and combine it with another buffer" "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "LCDIF1_AS_BUF,Alpha Surface Buffer Pointer" group.long 0x230++0x03 line.long 0x00 "LCDIF1_AS_NEXT_BUF,LCDIF1_AS_NEXT_BUF" group.long 0x240++0x03 line.long 0x00 "LCDIF1_AS_CLRKEYLOW,eLCDIF Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x250++0x03 line.long 0x00 "LCDIF1_AS_CLRKEYHIGH,eLCDIF Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x260++0x03 line.long 0x00 "LCDIF1_AS_CLRKEYHIGH,eLCDIF Overlay Color Key High" hexmask.long.word 0x00 16.--31. 1. " V_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" hexmask.long.word 0x00 0.--15. 1. " H_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" tree.end width 0x0B tree.end tree "EPDC (Electrophoretic Display Controller)" base ad:0x020F4000 width 18. group.long 0x00++0x0F line.long 0x00 "CTRL,EPDC Control Register" bitfld.long 0x00 31. " SFTRST ,Normal EPDC operation" "Enabled,Disabled" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Not gated,Gated" newline bitfld.long 0x00 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" bitfld.long 0x00 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" line.long 0x04 "CTRL_SET,EPDC Control Set Register" bitfld.long 0x04 31. " SFTRST ,Normal EPDC operation" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" newline bitfld.long 0x04 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap of the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" bitfld.long 0x04 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap of the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" line.long 0x08 "CTRL_CLR,EPDC Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Normal EPDC operation" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" newline bitfld.long 0x08 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" bitfld.long 0x08 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" line.long 0x0C "CTRL_TOG,EPDC Control Toggle Register" bitfld.long 0x0C 31. " SFTRST ,Normal EPDC operation" "Not toggled,Toggled" bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "Not toggled,Toggled" newline bitfld.long 0x0C 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" bitfld.long 0x0C 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped" group.long 0x10++0x03 line.long 0x00 "WB_ADDR_TCE,Working BUffer Address for TCE" group.long 0x20++0x03 line.long 0x00 "WVADDR,EPDC Waveform Address Pointer" group.long 0x30++0x03 line.long 0x00 "WB_ADDR,EPDC Working Buffer Address" group.long 0x40++0x03 line.long 0x00 "RES,EPDC Screen Resolution" hexmask.long.word 0x00 16.--28. 1. " VERTICAL ,Vertical Resolution (in pixels)" hexmask.long.word 0x00 0.--12. 1. " HORIZONTAL ,Horizontal Resolution (in pixels)" group.long 0x50++0x0F line.long 0x00 "FORMAT,EPDC Format Control Register" bitfld.long 0x00 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "Truncate,Rounding" hexmask.long.byte 0x00 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" newline bitfld.long 0x00 14. " WB_ADDR_NO_COPY ,WB address no copy" "Low,High" bitfld.long 0x00 12.--13. " WB_TYPE ,WB type" "INTERNAL,WAVEFORM,EXTERNAL16,EXTERNAL32" newline bitfld.long 0x00 8.--10. " BUF_PIX_FOR ,EPDC input buffer pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x00 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" line.long 0x04 "FORMAT_SET,EPDC Format Control Set Register" bitfld.long 0x04 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "No effect,Set" hexmask.long.byte 0x04 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" newline bitfld.long 0x04 14. " WB_ADDR_NO_COPY ,WB address no copy" "Low,High" bitfld.long 0x04 12.--13. " WB_TYPE ,WB type" "INTERNAL,WAVEFORM,EXTERNAL16,EXTERNAL32" newline bitfld.long 0x04 8.--10. " BUF_PIX_FOR ,EPDC input buffer pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x04 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" line.long 0x08 "FORMAT_CLR,EPDC Format Control Clear Register" bitfld.long 0x08 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "No effect,Clear" hexmask.long.byte 0x08 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" newline bitfld.long 0x08 14. " WB_ADDR_NO_COPY ,WB address no copy" "Low,High" bitfld.long 0x08 12.--13. " WB_TYPE ,WB type" "INTERNAL,WAVEFORM,EXTERNAL16,EXTERNAL32" newline bitfld.long 0x08 8.--10. " BUF_PIX_FOR ,EPDC input buffer pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x08 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" line.long 0x0C "FORMAT_TOG,EPDC Format Control Toggle Register" bitfld.long 0x0C 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "Not toggled,Toggled" hexmask.long.byte 0x0C 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value" newline bitfld.long 0x0C 14. " WB_ADDR_NO_COPY ,WB address no copy" "Low,High" bitfld.long 0x0C 12.--13. " WB_TYPE ,WB type" "INTERNAL,WAVEFORM,EXTERNAL16,EXTERNAL32" newline bitfld.long 0x0C 8.--10. " BUF_PIX_FOR ,EPDC input buffer pixel format" ",,2-bit,3-bit,4-bit,5-bit,?..." bitfld.long 0x0C 0.--1. " TFT_PIX_FOR ,EPDC TFT pixel format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM" group.long 0x60++0x03 line.long 0x00 "WB_FIELD0,Working Buffer Field Setting 0" hexmask.long.byte 0x00 24.--31. 1. " FIXED ,FIXED" bitfld.long 0x00 16.--17. " USE_FIXED ,Usage of the FIXED value" "NO,USE,NE,EQ" newline bitfld.long 0x00 13.--15. " USAGE ,USAGE" "Not used,,PARTIAL,LUT,CP,NP,PTS,?..." bitfld.long 0x00 8.--12. " FROM ,Source field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. " TO ,Target field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LEN ,Field length minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x70++0x03 line.long 0x00 "WB_FIELD1,Working Buffer Field Setting 1" hexmask.long.byte 0x00 24.--31. 1. " FIXED ,FIXED" bitfld.long 0x00 16.--17. " USE_FIXED ,Usage of the FIXED value" "NO,USE,NE,EQ" newline bitfld.long 0x00 13.--15. " USAGE ,USAGE" "Not used,,PARTIAL,LUT,CP,NP,PTS,?..." bitfld.long 0x00 8.--12. " FROM ,Source field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. " TO ,Target field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LEN ,Field length minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x03 line.long 0x00 "WB_FIELD2,Working Buffer Field Setting 2" hexmask.long.byte 0x00 24.--31. 1. " FIXED ,FIXED" bitfld.long 0x00 16.--17. " USE_FIXED ,Usage of the FIXED value" "NO,USE,NE,EQ" newline bitfld.long 0x00 13.--15. " USAGE ,USAGE" "Not used,,PARTIAL,LUT,CP,NP,PTS,?..." bitfld.long 0x00 8.--12. " FROM ,Source field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. " TO ,Target field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LEN ,Field length minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x03 line.long 0x00 "WB_FIELD3,Working Buffer Field Setting 3" hexmask.long.byte 0x00 24.--31. 1. " FIXED ,FIXED" bitfld.long 0x00 16.--17. " USE_FIXED ,Usage of the FIXED value" "NO,USE,NE,EQ" newline bitfld.long 0x00 13.--15. " USAGE ,USAGE" "Not used,,PARTIAL,LUT,CP,NP,PTS,?..." bitfld.long 0x00 8.--12. " FROM ,Source field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. " TO ,Target field's LSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " LEN ,Field length minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x0F line.long 0x00 "FIFOCTRL,EPDC FIFO control register" bitfld.long 0x00 31. " EN_PRIOR ,Watermark-based priority elevation mechanism" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo" newline hexmask.long.byte 0x00 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark" hexmask.long.byte 0x00 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark" line.long 0x04 "FIFOCTRL_SET,EPDC FIFO control set register" bitfld.long 0x04 31. " EN_PRIOR ,Watermark-based priority elevation mechanism" "No effect,Set" hexmask.long.byte 0x04 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo" newline hexmask.long.byte 0x04 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark" hexmask.long.byte 0x04 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark" line.long 0x08 "FIFOCTRL_CLR,EPDC FIFO control clear register" bitfld.long 0x08 31. " EN_PRIOR ,Watermark-based priority elevation mechanism" "No effect,Clear" hexmask.long.byte 0x08 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo" newline hexmask.long.byte 0x08 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark" hexmask.long.byte 0x08 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark" line.long 0x0C "FIFOCTRL_TOG,EPDC FIFO control toggle register" bitfld.long 0x0C 31. " EN_PRIOR ,Watermark-based priority elevation mechanism" "Not toggled,Toggled" hexmask.long.byte 0x0C 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo" newline hexmask.long.byte 0x0C 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark" hexmask.long.byte 0x0C 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark" group.long 0x100++0x03 line.long 0x00 "UPD_ADDR,EPDC Update Region Address" group.long 0x110++0x03 line.long 0x00 "UPD_STRIDE,EPDC Update Region Stride" group.long 0x120++0x03 line.long 0x00 "UPD_CORD,EPDC Update Command Co-ordinate" hexmask.long.word 0x00 16.--28. 1. " YCORD ,Y co-ordinate for incoming region update" hexmask.long.word 0x00 0.--12. 1. " XCORD ,X co-ordinate for incoming region update" group.long 0x140++0x03 line.long 0x00 "UPD_SIZE,EPDC Update Command Size" hexmask.long.word 0x00 16.--28. 1. " HEIGHT ,Height (in pixels)" hexmask.long.word 0x00 0.--12. 1. " WIDTH ,Width (in pixels)" group.long 0x160++0x0F line.long 0x00 "UPD_CTRL,EPDC Update Command Control" bitfld.long 0x00 31. " USE_FIXED ,Use fixed pixel values" "Not used,Used" bitfld.long 0x00 16.--21. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--15. 1. " WAVEFORM_MODE ,Waveform mode" bitfld.long 0x00 5. " STANDBY ,STANDBY" "Low,High" newline bitfld.long 0x00 4. " NOt_LUT_CANCEL ,EPDC will cancel LUT" "Low,High" bitfld.long 0x00 3. " AUTOWV_PAUSE ,Automatic waveform mode selection" "AUTO,MANUAL" newline bitfld.long 0x00 2. " AUTOWV ,Enable automatic waveform mode selection" "Disabled,Enabled" bitfld.long 0x00 1. " DRY_RUN ,Enable dry run mode" "Disabled,Enabled" newline bitfld.long 0x00 0. " UPDATE_MODE ,Update mode" "Partial,Full" line.long 0x04 "UPD_CTRL_SET,EPDC Update Command Control Set" bitfld.long 0x04 31. " USE_FIXED ,Use fixed pixel values" "No effect,Set" bitfld.long 0x04 16.--21. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x04 8.--15. 1. " WAVEFORM_MODE ,Waveform mode" bitfld.long 0x04 5. " STANDBY ,STANDBY" "Low,High" newline bitfld.long 0x04 4. " NOt_LUT_CANCEL ,EPDC will cancel LUT" "Low,High" bitfld.long 0x04 3. " AUTOWV_PAUSE ,Automatic waveform mode selection" "No effect,Set" newline bitfld.long 0x04 2. " AUTOWV ,Enable automatic waveform mode selection" "No effect,Set" bitfld.long 0x04 1. " DRY_RUN ,Enable dry run mode" "No effect,Set" newline bitfld.long 0x04 0. " UPDATE_MODE ,Update mode" "No effect,Set" line.long 0x08 "UPD_CTRL_CLR,EPDC Update Command Control Clear" bitfld.long 0x08 31. " USE_FIXED ,Use fixed pixel values" "No effect,Clear" bitfld.long 0x08 16.--21. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x08 8.--15. 1. " WAVEFORM_MODE ,Waveform mode" bitfld.long 0x08 5. " STANDBY ,STANDBY" "Low,High" newline bitfld.long 0x08 4. " NOt_LUT_CANCEL ,EPDC will cancel LUT" "Low,High" bitfld.long 0x08 3. " AUTOWV_PAUSE ,Automatic waveform mode selection" "No effect,Clear" newline bitfld.long 0x08 2. " AUTOWV ,Enable automatic waveform mode selection" "No effect,Clear" bitfld.long 0x08 1. " DRY_RUN ,Enable dry run mode" "No effect,Clear" newline bitfld.long 0x08 0. " UPDATE_MODE ,Update mode" "No effect,Clear" line.long 0x0C "UPD_CTRL,EPDC Update Command Control Toggle" bitfld.long 0x0C 31. " USE_FIXED ,Use fixed pixel values" "Not toggled,Toggled" bitfld.long 0x0C 16.--21. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x0C 8.--15. 1. " WAVEFORM_MODE ,Waveform mode" bitfld.long 0x0C 5. " STANDBY ,STANDBY" "Low,High" newline bitfld.long 0x0C 4. " NOt_LUT_CANCEL ,EPDC will cancel LUT" "Low,High" bitfld.long 0x0C 3. " AUTOWV_PAUSE ,Automatic waveform mode selection" "Not toggled,Toggled" newline bitfld.long 0x0C 2. " AUTOWV ,Enable automatic waveform mode selection" "Not toggled,Toggled" bitfld.long 0x0C 1. " DRY_RUN ,Enable Dry Run mode" "Not toggled,Toggled" newline bitfld.long 0x0C 0. " UPDATE_MODE ,Update mode" "Not toggled,Toggled" group.long 0x180++0x0F line.long 0x00 "UPD_FIXED,EPDC Update Fixed Pixel Control" bitfld.long 0x00 31. " FIXNP_EN ,Update region with NP value in FIXNP" "Not updated,Updated" bitfld.long 0x00 30. " FIXCP_EN ,Update region with CP value in FIXCP" "Not updated,Updated" newline hexmask.long.byte 0x00 8.--15. 1. " FIXNP ,NP value" hexmask.long.byte 0x00 0.--7. 1. " FIXCP ,CP value" line.long 0x04 "UPD_FIXED_SET,EPDC Update Fixed Pixel Control Set" bitfld.long 0x04 31. " FIXNP_EN ,Update region with NP value in FIXNP" "No effect,Set" bitfld.long 0x04 30. " FIXCP_EN ,Update region with CP value in FIXCP" "No effect,Set" newline hexmask.long.byte 0x04 8.--15. 1. " FIXNP ,NP value" hexmask.long.byte 0x04 0.--7. 1. " FIXCP ,CP value" line.long 0x08 "UPD_FIXED_CLR,EPDC Update Fixed Pixel Control Clear" bitfld.long 0x08 31. " FIXNP_EN ,Update region with NP value in FIXNP" "No effect,Clear" bitfld.long 0x08 30. " FIXCP_EN ,Update region with CP value in FIXCP" "No effect,Clear" newline hexmask.long.byte 0x08 8.--15. 1. " FIXNP ,NP value" hexmask.long.byte 0x08 0.--7. 1. " FIXCP ,CP value" line.long 0x0C "UPD_FIXED_TOG,EPDC Update Fixed Pixel Control Toggle" bitfld.long 0x0C 31. " FIXNP_EN ,Update region with NP value in FIXNP" "Not toggled,Toggled" bitfld.long 0x0C 30. " FIXCP_EN ,Update region with CP value in FIXCP" "Not toggled,Toggled" newline hexmask.long.byte 0x0C 8.--15. 1. " FIXNP ,NP value" hexmask.long.byte 0x0C 0.--7. 1. " FIXCP ,CP value" group.long 0x1A0++0x03 line.long 0x00 "TEMP,EPDC Temperature Register" group.long 0x1C0++0x03 line.long 0x00 "AUTOWV_LUT,Waveform Mode Lookup Table Control Register" hexmask.long.byte 0x00 16.--23. 1. " DATA ,DATA" bitfld.long 0x00 0.--2. " ADDR ,ADDR" "0,1,2,3,4,5,6,7" group.long 0x1E0++0x0F line.long 0x00 "LUT_STANDBY1,EPDC LUT Standby Register 1 For LUT 31~0" line.long 0x04 "LUT_STANDBY1_SET,EPDC LUT Standby Register 1 Set For LUT 31~0" line.long 0x08 "LUT_STANDBY1_CLR,EPDC LUT Standby Register 1 Clear For LUT 31~0" line.long 0x0C "LUT_STANDBY1_TOG,EPDC LUT Standby Register 1 Toggle For LUT 31~0" group.long 0x1F0++0x0F line.long 0x00 "LUT_STANDBY1,EPDC LUT Standby Register 1 For LUT 63~32" line.long 0x04 "LUT_STANDBY1_SET,EPDC LUT Standby Register 1 Set For LUT 63~32" line.long 0x08 "LUT_STANDBY1_CLR,EPDC LUT Standby Register 1 Clear For LUT 63~32" line.long 0x0C "LUT_STANDBY1_TOG,EPDC LUT Standby Register 1 Toggle For LUT 63~32" if (((per.l(ad:0x020F4000+0x200))&0x44)==0x44) group.long 0x200++0x0F line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register" hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto" bitfld.long 0x00 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not drove,Drove" newline bitfld.long 0x00 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "Not drove,Drove" bitfld.long 0x00 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "Not used,Used" newline bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down" bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down" newline bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "8-bit,16-bit" bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register" hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set" bitfld.long 0x04 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "No effect,Set" newline bitfld.long 0x04 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "No effect,Set" bitfld.long 0x04 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "No effect,Set" newline bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set" bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set" newline bitfld.long 0x04 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "No effect,Set" bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Set" newline bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register" hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Clear" bitfld.long 0x08 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "No effect,Clear" newline bitfld.long 0x08 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "No effect,Clear" bitfld.long 0x08 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "No effect,Clear" newline bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Clear" bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Clear" newline bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Clear" bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register" hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled" bitfld.long 0x0C 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not toggled,Toggled" newline bitfld.long 0x0C 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "Not toggled,Toggled" bitfld.long 0x0C 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "Not toggled,Toggled" newline bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" newline bitfld.long 0x0C 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "Not toggled,Toggled" bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "Not toggled,Toggled" newline bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" elif (((per.l(ad:0x020F4000+0x200))&0x44)==0x04) group.long 0x200++0x0F line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register" hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto" bitfld.long 0x00 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "Not used,Used" newline bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down" bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down" newline bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "8-bit,16-bit" bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register" hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set" bitfld.long 0x04 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "No effect,Set" newline bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set" bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set" newline bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Set" bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register" hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Clear" bitfld.long 0x08 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "No effect,Clear" newline bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Clear" bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Clear" newline bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Clear" bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register" hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled" bitfld.long 0x0C 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "Not toggled,Toggled" newline bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" newline bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "Not toggled,Toggled" bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" elif (((per.l(ad:0x020F4000+0x200))&0x44)==0x40) group.long 0x200++0x0F line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register" hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto" bitfld.long 0x00 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not drove,Drove" newline bitfld.long 0x00 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "Not used,Used" bitfld.long 0x00 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "Not drove,Drove" newline bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down" bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down" newline bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "8-bit,16-bit" bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register" hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set" bitfld.long 0x04 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "No effect,Set" newline bitfld.long 0x04 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "No effect,Set" bitfld.long 0x04 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "No effect,Set" newline bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set" bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set" newline bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Set" bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register" hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Clear" bitfld.long 0x08 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "No effect,Clear" newline bitfld.long 0x08 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "No effect,Clear" bitfld.long 0x08 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "No effect,Clear" newline bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Clear" bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Clear" newline bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Clear" bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register" hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled" bitfld.long 0x0C 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not toggled,Toggled" newline bitfld.long 0x0C 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "Not toggled,Toggled" bitfld.long 0x0C 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signaling" "Not toggled,Toggled" newline bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" newline bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "Not toggled,Toggled" bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" else group.long 0x200++0x0F line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register" hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto" bitfld.long 0x00 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not drove,Drove" newline bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down" bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down" newline bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "8-bit,16-bit" bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register" hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set" bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set" newline bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set" bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Set" newline bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register" hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Clear" bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Clear" newline bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Clear" bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Clear" newline bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register" hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated" bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3" newline bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled" bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" newline bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled" bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "Not toggled,Toggled" newline bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" ",Two,Four,Eight" endif group.long 0x220++0x0F line.long 0x00 "TCE_SDCFG,EPDC Timing Control Engine Source-Driver Config Register" bitfld.long 0x00 21. " SDCLK_HOLD ,Holds the SDCLK low during LINE_BEGIN" "Not held,Held" bitfld.long 0x00 20. " SDSHR ,Value for source-driver shift direction output port" "Low,High" newline bitfld.long 0x00 16.--19. " NUM_CE ,Number of source driver IC chip-enables" ",1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..." newline bitfld.long 0x00 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "Not reversed,Reversed" hexmask.long.word 0x00 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (outputs) per source-driver IC" line.long 0x04 "TCE_SDCFG_SET,EPDC Timing Control Engine Source-Driver Config Set Register" bitfld.long 0x04 21. " SDCLK_HOLD ,Holds the SDCLK low during LINE_BEGIN" "No effect,Set" bitfld.long 0x04 20. " SDSHR ,Value for source-driver shift direction output port" "No effect,Set" newline bitfld.long 0x04 16.--19. " NUM_CE ,Number of source driver IC chip-enables" ",1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x04 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..." newline bitfld.long 0x04 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "No effect,Set" hexmask.long.word 0x04 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (outputs) per source-driver IC" line.long 0x08 "TCE_SDCFG_CLR,EPDC Timing Control Engine Source-Driver Config Clear Register" bitfld.long 0x08 21. " SDCLK_HOLD ,Holds the SDCLK low during LINE_BEGIN" "No effect,Clear" bitfld.long 0x08 20. " SDSHR ,Value for source-driver shift direction output port" "No effect,Clear" newline bitfld.long 0x08 16.--19. " NUM_CE ,Number of source driver IC chip-enables" ",1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x08 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..." newline bitfld.long 0x08 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "No effect,Clear" hexmask.long.word 0x08 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (outputs) per source-driver IC" line.long 0x0C "TCE_SDCFG_TOG,EPDC Timing Control Engine Source-Driver Config Toggle Register" bitfld.long 0x0C 21. " SDCLK_HOLD ,Holds the SDCLK low during LINE_BEGIN" "Not toggled,Toggled" bitfld.long 0x0C 20. " SDSHR ,Value for source-driver shift direction output port" "Not toggled,Toggled" newline bitfld.long 0x0C 16.--19. " NUM_CE ,Number of source driver IC chip-enables" ",1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x0C 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..." newline bitfld.long 0x0C 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "Not toggled,Toggled" hexmask.long.word 0x0C 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (outputs) per source-driver IC" group.long 0x240++0x0F line.long 0x00 "TCE_GDCFG,EPDC Timing Control Engine Gate-Driver Config Register" hexmask.long.word 0x00 16.--31. 1. " PERIOD_VSCAN ,Counter period" bitfld.long 0x00 4. " GDRL ,Value for gate-driver right/left shift output port" "Low,High" newline bitfld.long 0x00 1. " GDOE_MODE ,Method for driving GDOE signal" "All times,Delayed" bitfld.long 0x00 0. " GDSP_MODE ,Method for driving GDSP pulse" "Fixed,FRAME_SYNC" line.long 0x04 "TCE_GDCFG_SET,EPDC Timing Control Engine Gate-Driver Config Set Register" hexmask.long.word 0x04 16.--31. 1. " PERIOD_VSCAN ,Counter period" bitfld.long 0x04 4. " GDRL ,Value for gate-driver right/left shift output port" "No effect,Set" newline bitfld.long 0x04 1. " GDOE_MODE ,Method for driving GDOE signal" "No effect,Set" bitfld.long 0x04 0. " GDSP_MODE ,Method for driving GDSP pulse" "No effect,Set" line.long 0x08 "TCE_GDCFG_CLR,EPDC Timing Control Engine Gate-Driver Config Clear Register" hexmask.long.word 0x08 16.--31. 1. " PERIOD_VSCAN ,Counter period" bitfld.long 0x08 4. " GDRL ,Value for gate-driver right/left shift output port" "No effect,Clear" newline bitfld.long 0x08 1. " GDOE_MODE ,Method for driving GDOE signal" "No effect,Clear" bitfld.long 0x08 0. " GDSP_MODE ,Method for driving GDSP pulse" "No effect,Clear" line.long 0x0C "TCE_GDCFG_TOG,EPDC Timing Control Engine Gate-Driver Config Toggle Register" hexmask.long.word 0x0C 16.--31. 1. " PERIOD_VSCAN ,Counter period" bitfld.long 0x0C 4. " GDRL ,Value for gate-driver right/left shift output port" "Not toggled,Toggled" newline bitfld.long 0x08 1. " GDOE_MODE ,Method for driving GDOE signal" "No effect,Clear" bitfld.long 0x08 0. " GDSP_MODE ,Method for driving GDSP pulse" "No effect,Clear" group.long 0x260++0x0F line.long 0x00 "TCE_HSCAN1,EPDC Timing Control Engine Horizontal Timing Register 1" hexmask.long.word 0x00 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time" hexmask.long.word 0x00 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration" line.long 0x04 "TCE_HSCAN1_SET,EPDC Timing Control Engine Horizontal Timing Set Register 1" hexmask.long.word 0x04 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time" hexmask.long.word 0x04 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration" line.long 0x08 "TCE_HSCAN1_CLR,EPDC Timing Control Engine Horizontal Timing Clear Register 1" hexmask.long.word 0x08 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time" hexmask.long.word 0x08 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration" line.long 0x0C "TCE_HSCAN1_TOG,EPDC Timing Control Engine Horizontal Timing Toggle Register 1" hexmask.long.word 0x0C 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time" hexmask.long.word 0x0C 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration" group.long 0x280++0x0F line.long 0x00 "TCE_HSCAN2,EPDC Timing Control Engine Horizontal Timing Register 2" hexmask.long.word 0x00 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration" hexmask.long.word 0x00 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration" line.long 0x04 "TCE_HSCAN2_SET,EPDC Timing Control Engine Horizontal Timing Set Register 2" hexmask.long.word 0x04 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration" hexmask.long.word 0x04 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration" line.long 0x08 "TCE_HSCAN2_CLR,EPDC Timing Control Engine Horizontal Timing Clear Register 2" hexmask.long.word 0x08 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration" hexmask.long.word 0x08 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration" line.long 0x0C "TCE_HSCAN2_TOG,EPDC Timing Control Engine Horizontal Timing Toggle Register 2" hexmask.long.word 0x0C 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration" hexmask.long.word 0x0C 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration" group.long 0x2A0++0x0F line.long 0x00 "TCE_VSCAN,EPDC Timing Control Engine Vertical Timing Register" hexmask.long.byte 0x00 16.--23. 1. " FRAME_END ,Number of lines for frame end duration" hexmask.long.byte 0x00 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration" newline hexmask.long.byte 0x00 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration" line.long 0x04 "TCE_VSCAN_SET,EPDC Timing Control Engine Vertical Timing Set Register" hexmask.long.byte 0x04 16.--23. 1. " FRAME_END ,Number of lines for frame end duration" hexmask.long.byte 0x04 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration" newline hexmask.long.byte 0x04 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration" line.long 0x08 "TCE_VSCAN_CLR,EPDC Timing Control Engine Vertical Timing Clear Register" hexmask.long.byte 0x08 16.--23. 1. " FRAME_END ,Number of lines for frame end duration" hexmask.long.byte 0x08 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration" newline hexmask.long.byte 0x08 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration" line.long 0x0C "TCE_VSCAN_TOG,EPDC Timing Control Engine Vertical Timing Toggle Register" hexmask.long.byte 0x0C 16.--23. 1. " FRAME_END ,Number of lines for frame end duration" hexmask.long.byte 0x0C 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration" newline hexmask.long.byte 0x0C 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration" group.long 0x2C0++0x0F line.long 0x00 "TCE_OE,EPDC Timing Control Engine OE timing control Register" hexmask.long.byte 0x00 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling" hexmask.long.byte 0x00 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising" newline hexmask.long.byte 0x00 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling" hexmask.long.byte 0x00 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising" line.long 0x04 "TCE_OE_SET,EPDC Timing Control Engine OE timing control set Register" hexmask.long.byte 0x04 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling" hexmask.long.byte 0x04 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising" newline hexmask.long.byte 0x04 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling" hexmask.long.byte 0x04 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising" line.long 0x08 "TCE_OE_CLR,EPDC Timing Control Engine OE timing control clear Register" hexmask.long.byte 0x08 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling" hexmask.long.byte 0x08 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising" newline hexmask.long.byte 0x08 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling" hexmask.long.byte 0x08 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising" line.long 0x0C "TCE_OE_TOG,EPDC Timing Control Engine OE timing control toggle Register" hexmask.long.byte 0x0C 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling" hexmask.long.byte 0x0C 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising" newline hexmask.long.byte 0x0C 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling" hexmask.long.byte 0x0C 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising" group.long 0x2E0++0x0F line.long 0x00 "TCE_POLARITY,EPDC Timing Control Engine Driver Polarity Register" bitfld.long 0x00 4. " GDSP_POL ,GDSP output" "Active low,Active high" bitfld.long 0x00 3. " GDOE_POL ,GDOE output" "Active low,Active high" newline bitfld.long 0x00 2. " SDOE_POL ,SDOE" "Active low,Active high" bitfld.long 0x00 1. " SDLE_POL ,SDLE output" "Active low,Active high" newline bitfld.long 0x00 0. " SDCE_POL ,All 10 SDCE outputs" "Active low,Active high" line.long 0x04 "TCE_POLARITY_SET,EPDC Timing Control Engine Driver Polarity Set Register" bitfld.long 0x04 4. " GDSP_POL ,GDSP output" "Active low,Active high" bitfld.long 0x04 3. " GDOE_POL ,GDOE output" "Active low,Active high" newline bitfld.long 0x04 2. " SDOE_POL ,SDOE" "Active low,Active high" bitfld.long 0x04 1. " SDLE_POL ,SDLE output" "Active low,Active high" newline bitfld.long 0x04 0. " SDCE_POL ,All 10 SDCE outputs" "Active low,Active high" line.long 0x08 "TCE_POLARITY_CLR,EPDC Timing Control Engine Driver Polarity Clear Register" bitfld.long 0x08 4. " GDSP_POL ,GDSP output" "Active low,Active high" bitfld.long 0x08 3. " GDOE_POL ,GDOE output" "Active low,Active high" newline bitfld.long 0x08 2. " SDOE_POL ,SDOE" "Active low,Active high" bitfld.long 0x08 1. " SDLE_POL ,SDLE output" "Active low,Active high" newline bitfld.long 0x08 0. " SDCE_POL ,All 10 SDCE outputs" "Active low,Active high" line.long 0x0C "TCE_POLARITY_TOG,EPDC Timing Control Engine Driver Polarity Toggle Register" bitfld.long 0x0C 4. " GDSP_POL ,GDSP output" "Active low,Active high" bitfld.long 0x0C 3. " GDOE_POL ,GDOE output" "Active low,Active high" newline bitfld.long 0x0C 2. " SDOE_POL ,SDOE" "Active low,Active high" bitfld.long 0x0C 1. " SDLE_POL ,SDLE output" "Active low,Active high" newline bitfld.long 0x0C 0. " SDCE_POL ,All 10 SDCE outputs" "Active low,Active high" group.long 0x300++0x2F line.long 0x00 "TCE_TIMING1,EPDC Timing Control Engine Timing Register 1" bitfld.long 0x00 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" bitfld.long 0x00 3. " SDCLK_INVERT ,Invert phase of SDCLK" "Not inverted,Inverted" newline bitfld.long 0x00 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" line.long 0x04 "TCE_TIMING1_SET,EPDC Timing Control Engine Timing Set Register 1" bitfld.long 0x04 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" bitfld.long 0x04 3. " SDCLK_INVERT ,Invert phase of SDCLK" "Not set,Set" newline bitfld.long 0x04 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" line.long 0x08 "TCE_TIMING1_CLR,EPDC Timing Control Engine Timing Clear Register 1" bitfld.long 0x08 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" bitfld.long 0x08 3. " SDCLK_INVERT ,Invert phase of SDCLK" "No effect,Clear" newline bitfld.long 0x08 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" line.long 0x0C "TCE_TIMING1_TOG,EPDC Timing Control Engine Timing Toggle Register 1" bitfld.long 0x0C 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" bitfld.long 0x0C 3. " SDCLK_INVERT ,Invert phase of SDCLK" "Not toggled,Toggled" newline bitfld.long 0x0C 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles" line.long 0x10 "TCE_TIMING2,EPDC Timing Control Engine Timing Register 2" hexmask.long.word 0x10 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width" hexmask.long.word 0x10 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by n PIXCLKs" line.long 0x14 "TCE_TIMING2_SET,EPDC Timing Control Engine Timing Set Register 2" hexmask.long.word 0x14 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width" hexmask.long.word 0x14 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by n PIXCLKs" line.long 0x18 "TCE_TIMING2_CLR,EPDC Timing Control Engine Timing Clear Register 2" hexmask.long.word 0x18 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width" hexmask.long.word 0x18 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by n PIXCLKs" line.long 0x1C "TCE_TIMING2_TOG,EPDC Timing Control Engine Timing Register 2" hexmask.long.word 0x1C 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width" hexmask.long.word 0x1C 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by n PIXCLKs" line.long 0x20 "TCE_TIMING3,EPDC Timing Control Engine Timing Register 3" hexmask.long.word 0x20 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of n PIXCLK cycles" hexmask.long.word 0x20 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by n PIXCLK cycles" line.long 0x24 "TCE_TIMING3_SET,EPDC Timing Control Engine Timing Register 3" hexmask.long.word 0x24 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of n PIXCLK cycles" hexmask.long.word 0x24 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by n PIXCLK cycles" line.long 0x28 "TCE_TIMING3_CLR,EPDC Timing Control Engine Timing Register 3" hexmask.long.word 0x28 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of n PIXCLK cycles" hexmask.long.word 0x28 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by n PIXCLK cycles" line.long 0x2C "TCE_TIMING3_TOG,EPDC Timing Control Engine Timing Register 3" hexmask.long.word 0x2C 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of n PIXCLK cycles" hexmask.long.word 0x2C 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by n PIXCLK cycles" group.long 0x380++0x1F line.long 0x00 "PIGEON_CTRL0,EPDC Pigeon Mode Control Register 0" hexmask.long.word 0x00 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x00 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x04 "PIGEON_CTRL0_SET,EPDC Pigeon Mode Control Set Register 0" hexmask.long.word 0x04 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x04 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x08 "PIGEON_CTRL0_CLR,EPDC Pigeon Mode Control Clear Register 0" hexmask.long.word 0x08 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x08 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x0C "PIGEON_CTRL0_TOG,EPDC Pigeon Mode Control Toggle Register 0" hexmask.long.word 0x0C 16.--27. 1. " LD_PERIOD ,Period of pclk counter during LD phase" hexmask.long.word 0x0C 0.--11. 1. " FD_PERIOD ,Period of line counter during FD phase" line.long 0x10 "PIGEON_CTRL1,EPDC Pigeon Mode Control Register 1" hexmask.long.word 0x10 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x10 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x14 "PIGEON_CTRL1_SET,EPDC Pigeon Mode Control Set Register 1" hexmask.long.word 0x14 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x14 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x18 "PIGEON_CTRL1_CLR,EPDC Pigeon Mode Control Clear Register 1" hexmask.long.word 0x18 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x18 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" line.long 0x1C "PIGEON_CTRL1_TOG,EPDC Pigeon Mode Control Register 1" hexmask.long.word 0x1C 16.--27. 1. " FRAME_CNT_CYCLES ,Max cycles of frame counter" hexmask.long.word 0x1C 0.--11. 1. " FRAME_CNT_PERIOD ,Period of frame counter" group.long 0x3C0++0x4F line.long 0x00 "IRQ_MASK1,EPDC IRQ Mask Register for LUT 0-31" bitfld.long 0x00 31. " LUT31_CMPLT_IRQ_EN ,LUT31 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,LUT30 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " [29] ,LUT29 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,LUT28 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,LUT27 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,LUT26 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,LUT25 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,LUT24 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,LUT23 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,LUT22 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " [21] ,LUT21 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,LUT20 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,LUT19 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,LUT18 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " [17] ,LUT17 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,LUT16 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,LUT15 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,LUT14 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,LUT13 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,LUT12 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,LUT11 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,LUT10 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,LUT9 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,LUT8 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,LUT7 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,LUT6 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,LUT5 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,LUT4 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,LUT3 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,LUT2 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,LUT1 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,LUT0 complete interrupt enable" "Disabled,Enabled" line.long 0x04 "IRQ_MASK1_SET,EPDC IRQ Mask Register for LUT 0-31" bitfld.long 0x04 31. " LUT31_CMPLT_IRQ_SET ,LUT31 complete interrupt set" "No effect,Set" bitfld.long 0x04 30. " [30] ,LUT30 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 29. " [29] ,LUT29 complete interrupt set" "No effect,Set" bitfld.long 0x04 28. " [28] ,LUT28 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 27. " [27] ,LUT27 complete interrupt set" "No effect,Set" bitfld.long 0x04 26. " [26] ,LUT26 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 25. " [25] ,LUT25 complete interrupt set" "No effect,Set" bitfld.long 0x04 24. " [24] ,LUT24 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 23. " [23] ,LUT23 complete interrupt set" "No effect,Set" bitfld.long 0x04 22. " [22] ,LUT22 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 21. " [21] ,LUT21 complete interrupt set" "No effect,Set" bitfld.long 0x04 20. " [20] ,LUT20 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 19. " [19] ,LUT19 complete interrupt set" "No effect,Set" bitfld.long 0x04 18. " [18] ,LUT18 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 17. " [17] ,LUT17 complete interrupt set" "No effect,Set" bitfld.long 0x04 16. " [16] ,LUT16 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 15. " [15] ,LUT15 complete interrupt set" "No effect,Set" bitfld.long 0x04 14. " [14] ,LUT14 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 13. " [13] ,LUT13 complete interrupt set" "No effect,Set" bitfld.long 0x04 12. " [12] ,LUT12 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 11. " [11] ,LUT11 complete interrupt set" "No effect,Set" bitfld.long 0x04 10. " [10] ,LUT10 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 9. " [9] ,LUT9 complete interrupt set" "No effect,Set" bitfld.long 0x04 8. " [8] ,LUT8 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 7. " [7] ,LUT7 complete interrupt set" "No effect,Set" bitfld.long 0x04 6. " [6] ,LUT6 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 5. " [5] ,LUT5 complete interrupt set" "No effect,Set" bitfld.long 0x04 4. " [4] ,LUT4 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 3. " [3] ,LUT3 complete interrupt set" "No effect,Set" bitfld.long 0x04 2. " [2] ,LUT2 complete interrupt set" "No effect,Set" newline bitfld.long 0x04 1. " [1] ,LUT1 complete interrupt set" "No effect,Set" bitfld.long 0x04 0. " [0] ,LUT0 complete interrupt set" "No effect,Set" line.long 0x08 "IRQ_MASK1_CLR,EPDC IRQ Mask Register for LUT 0-31" bitfld.long 0x08 31. " LUT31_CMPLT_IRQ_CLR ,LUT31 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 30. " [30] ,LUT30 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 29. " [29] ,LUT29 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 28. " [28] ,LUT28 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 27. " [27] ,LUT27 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 26. " [26] ,LUT26 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 25. " [25] ,LUT25 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 24. " [24] ,LUT24 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 23. " [23] ,LUT23 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 22. " [22] ,LUT22 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 21. " [21] ,LUT21 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 20. " [20] ,LUT20 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 19. " [19] ,LUT19 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 18. " [18] ,LUT18 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 17. " [17] ,LUT17 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 16. " [16] ,LUT16 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 15. " [15] ,LUT15 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 14. " [14] ,LUT14 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 13. " [13] ,LUT13 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 12. " [12] ,LUT12 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 11. " [11] ,LUT11 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 10. " [10] ,LUT10 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 9. " [9] ,LUT9 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 8. " [8] ,LUT8 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 7. " [7] ,LUT7 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 6. " [6] ,LUT6 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 5. " [5] ,LUT5 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 4. " [4] ,LUT4 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 3. " [3] ,LUT3 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 2. " [2] ,LUT2 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x08 1. " [1] ,LUT1 complete interrupt clear" "No effect,Clear" bitfld.long 0x08 0. " [0] ,LUT0 complete interrupt clear" "No effect,Clear" line.long 0x0C "IRQ_MASK1_TOG,EPDC IRQ Mask Toggle Register for LUT 0-31" bitfld.long 0x0C 31. " LUTN_CMPLT_IRQ_TOG ,LUT31 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 30. " [30] ,LUT30 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 29. " [29] ,LUT29 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 28. " [28] ,LUT28 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 27. " [27] ,LUT27 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 26. " [26] ,LUT26 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 25. " [25] ,LUT25 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 24. " [24] ,LUT24 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 23. " [23] ,LUT23 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 22. " [22] ,LUT22 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 21. " [21] ,LUT21 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 20. " [20] ,LUT20 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 19. " [19] ,LUT19 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 18. " [18] ,LUT18 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 17. " [17] ,LUT17 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 16. " [16] ,LUT16 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 15. " [15] ,LUT15 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 14. " [14] ,LUT14 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 13. " [13] ,LUT13 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 12. " [12] ,LUT12 Complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 11. " [11] ,LUT11 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 10. " [10] ,LUT10 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 9. " [9] ,LUT9 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 8. " [8] ,LUT8 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 7. " [7] ,LUT7 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 6. " [6] ,LUT6 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 5. " [5] ,LUT5 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 4. " [4] ,LUT4 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 3. " [3] ,LUT3 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 2. " [2] ,LUT2 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 1. " [1] ,LUT1 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 0. " [0] ,LUT0 complete interrupt toggle" "Not toggled,Toggled" line.long 0x10 "IRQ_MASK2,EPDC IRQ Mask Register for LUT 32-63" bitfld.long 0x10 31. " LUT63_CMPLT_IRQ_EN ,LUT63 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 30. " [62] ,LUT62 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 29. " [61] ,LUT61 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 28. " [60] ,LUT60 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 27. " [59] ,LUT59 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 26. " [58] ,LUT58 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 25. " [57] ,LUT57 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 24. " [56] ,LUT56 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 23. " [55] ,LUT55 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 22. " [54] ,LUT54 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 21. " [53] ,LUT53 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 20. " [52] ,LUT52 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 19. " [51] ,LUT51 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 18. " [50] ,LUT50 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 17. " [49] ,LUT49 complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x10 16. " [48] ,LUT48 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 15. " [47] ,LUT47 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 14. " [46] ,LUT46 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 13. " [45] ,LUT45 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 12. " [44] ,LUT44 Complete Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x10 11. " [43] ,LUT43 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 10. " [42] ,LUT42 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 9. " [41] ,LUT41 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 8. " [40] ,LUT40 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 7. " [39] ,LUT39 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 6. " [38] ,LUT38 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 5. " [37] ,LUT37 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 4. " [36] ,LUT36 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 3. " [35] ,LUT35 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 2. " [34] ,LUT34 complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 1. " [33] ,LUT33 complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 0. " [32] ,LUT32 complete interrupt enable" "Disabled,Enabled" line.long 0x14 "IRQ_MASK2_SET,EPDC IRQ Mask Set Register for LUT 32-63" bitfld.long 0x14 31. " LUT63_CMPLT_IRQ_SET ,LUT63 complete interrupt set" "No effect,Set" bitfld.long 0x14 30. " [62] ,LUT62 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 29. " [61] ,LUT61 complete interrupt set" "No effect,Set" bitfld.long 0x14 28. " [60] ,LUT60 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 27. " [59] ,LUT59 complete interrupt set" "No effect,Set" bitfld.long 0x14 26. " [58] ,LUT58 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 25. " [57] ,LUT57 complete interrupt set" "No effect,Set" bitfld.long 0x14 24. " [56] ,LUT56 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 23. " [55] ,LUT55 complete interrupt set" "No effect,Set" bitfld.long 0x14 22. " [54] ,LUT54 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 21. " [53] ,LUT53 complete interrupt set" "No effect,Set" bitfld.long 0x14 20. " [52] ,LUT52 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 19. " [51] ,LUT51 complete interrupt set" "No effect,Set" bitfld.long 0x14 18. " [50] ,LUT50 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 17. " [49] ,LUT49 complete interrupt set" "No effect,Set" bitfld.long 0x14 16. " [48] ,LUT48 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 15. " [47] ,LUT47 complete interrupt set" "No effect,Set" bitfld.long 0x14 14. " [46] ,LUT46 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 13. " [45] ,LUT45 complete interrupt set" "No effect,Set" bitfld.long 0x14 12. " [44] ,LUT44 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 11. " [43] ,LUT43 complete interrupt set" "No effect,Set" bitfld.long 0x14 10. " [42] ,LUT42 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 9. " [41] ,LUT41 complete interrupt set" "No effect,Set" bitfld.long 0x14 8. " [40] ,LUT40 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 7. " [39] ,LUT39 complete interrupt set" "No effect,Set" bitfld.long 0x14 6. " [38] ,LUT38 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 5. " [37] ,LUT37 complete interrupt set" "No effect,Set" bitfld.long 0x14 4. " [36] ,LUT36 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 3. " [35] ,LUT35 complete interrupt set" "No effect,Set" bitfld.long 0x14 2. " [34] ,LUT34 complete interrupt set" "No effect,Set" newline bitfld.long 0x14 1. " [33] ,LUT33 complete interrupt set" "No effect,Set" bitfld.long 0x14 0. " [32] ,LUT32 complete interrupt set" "No effect,Set" line.long 0x18 "IRQ_MASK2_CLR,EPDC IRQ Mask Clear Register for LUT 32-63" bitfld.long 0x18 31. " LUT63_CMPLT_IRQ_CLR ,LUT63 Complete Interrupt Clear" "No effect,Clear" bitfld.long 0x18 30. " [62] ,LUT62 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 29. " [61] ,LUT61 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 28. " [60] ,LUT60 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 27. " [59] ,LUT59 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 26. " [58] ,LUT58 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 25. " [57] ,LUT57 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 24. " [56] ,LUT56 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 23. " [55] ,LUT55 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 22. " [54] ,LUT54 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 21. " [53] ,LUT53 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 20. " [52] ,LUT52 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 19. " [51] ,LUT51 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 18. " [50] ,LUT50 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 17. " [49] ,LUT49 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 16. " [48] ,LUT48 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 15. " [47] ,LUT47 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 14. " [46] ,LUT46 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 13. " [45] ,LUT45 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 12. " [44] ,LUT44 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 11. " [43] ,LUT43 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 10. " [42] ,LUT42 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 9. " [41] ,LUT41 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 8. " [40] ,LUT40 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 7. " [39] ,LUT39 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 6. " [38] ,LUT38 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 5. " [37] ,LUT37 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 4. " [36] ,LUT36 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 3. " [35] ,LUT35 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 2. " [34] ,LUT34 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x18 1. " [33] ,LUT33 complete interrupt clear" "No effect,Clear" bitfld.long 0x18 0. " [32] ,LUT32 complete interrupt clear" "No effect,Clear" line.long 0x1C "IRQ_MASK2_TOG,EPDC IRQ Mask Toggle Register for LUT 32-63" bitfld.long 0x1C 31. " LUT63_CMPLT_IRQ_TOG ,LUT63 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 30. " [62] ,LUT62 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 29. " [61] ,LUT61 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 28. " [60] ,LUT60 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 27. " [59] ,LUT59 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 26. " [58] ,LUT58 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 25. " [57] ,LUT57 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 24. " [56] ,LUT56 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 23. " [55] ,LUT55 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 22. " [54] ,LUT54 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 21. " [53] ,LUT53 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 20. " [52] ,LUT52 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 19. " [51] ,LUT51 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 18. " [50] ,LUT50 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 17. " [49] ,LUT49 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 16. " [48] ,LUT48 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 15. " [47] ,LUT47 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 14. " [46] ,LUT46 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 13. " [45] ,LUT45 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 12. " [44] ,LUT44 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 11. " [43] ,LUT43 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 10. " [42] ,LUT42 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 9. " [41] ,LUT41 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 8. " [40] ,LUT40 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 7. " [39] ,LUT39 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 6. " [38] ,LUT38 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 5. " [37] ,LUT37 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 4. " [36] ,LUT36 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 3. " [35] ,LUT35 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 2. " [34] ,LUT34 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 1. " [33] ,LUT33 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x1C 0. " [32] ,LUT32 complete interrupt toggle" "Not toggled,Toggled" line.long 0x20 "IRQ1,EPDC Interrupt Register for LUT 0-31" bitfld.long 0x20 31. " LUT31_CMPLT_IRQ ,LUT31 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 30. " [30] ,LUT30 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 29. " [29] ,LUT29 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 28. " [28] ,LUT28 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 27. " [27] ,LUT27 Complete Interrupt" "No interrupt,Interrupt" bitfld.long 0x20 26. " [26] ,LUT26 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 25. " [25] ,LUT25 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 24. " [24] ,LUT24 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 23. " [23] ,LUT23 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 22. " [22] ,LUT22 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 21. " [21] ,LUT21 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 20. " [20] ,LUT20 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 19. " [19] ,LUT19 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 18. " [18] ,LUT18 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 17. " [17] ,LUT17 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 16. " [16] ,LUT16 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 15. " [15] ,LUT15 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 14. " [14] ,LUT14 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 13. " [13] ,LUT13 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 12. " [12] ,LUT12 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 11. " [11] ,LUT11 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 10. " [10] ,LUT10 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 9. " [9] ,LUT9 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 8. " [8] ,LUT8 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 7. " [7] ,LUT7 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 6. " [6] ,LUT6 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 5. " [5] ,LUT5 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 4. " [4] ,LUT4 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 3. " [3] ,LUT3 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 2. " [2] ,LUT2 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x20 1. " [1] ,LUT1 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x20 0. " [0] ,LUT0 complete interrupt" "No interrupt,Interrupt" line.long 0x24 "IRQ1_SET,EPDC Interrupt Set Register for LUT 0-31" bitfld.long 0x24 31. " LUT31_CMPLT_IRQ_SET ,LUT31 complete interrupt set" "No effect,Set" bitfld.long 0x24 30. " [30] ,LUT30 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 29. " [29] ,LUT29 complete interrupt set" "No effect,Set" bitfld.long 0x24 28. " [28] ,LUT28 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 27. " [27] ,LUT27 complete interrupt set" "No effect,Set" bitfld.long 0x24 26. " [26] ,LUT26 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 25. " [25] ,LUT25 complete interrupt set" "No effect,Set" bitfld.long 0x24 24. " [24] ,LUT24 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 23. " [23] ,LUT23 complete interrupt set" "No effect,Set" bitfld.long 0x24 22. " [22] ,LUT22 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 21. " [21] ,LUT21 complete interrupt set" "No effect,Set" bitfld.long 0x24 20. " [20] ,LUT20 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 19. " [19] ,LUT19 complete interrupt set" "No effect,Set" bitfld.long 0x24 18. " [18] ,LUT18 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 17. " [17] ,LUT17 complete interrupt set" "No effect,Set" bitfld.long 0x24 16. " [16] ,LUT16 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 15. " [15] ,LUT15 complete interrupt set" "No effect,Set" bitfld.long 0x24 14. " [14] ,LUT14 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 13. " [13] ,LUT13 complete interrupt set" "No effect,Set" bitfld.long 0x24 12. " [12] ,LUT12 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 11. " [11] ,LUT11 complete interrupt set" "No effect,Set" bitfld.long 0x24 10. " [10] ,LUT10 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 9. " [9] ,LUT9 complete interrupt set" "No effect,Set" bitfld.long 0x24 8. " [8] ,LUT8 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 7. " [7] ,LUT7 complete interrupt set" "No effect,Set" bitfld.long 0x24 6. " [6] ,LUT6 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 5. " [5] ,LUT5 complete interrupt set" "No effect,Set" bitfld.long 0x24 4. " [4] ,LUT4 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 3. " [3] ,LUT3 complete interrupt set" "No effect,Set" bitfld.long 0x24 2. " [2] ,LUT2 complete interrupt set" "No effect,Set" newline bitfld.long 0x24 1. " [1] ,LUT1 complete interrupt set" "No effect,Set" bitfld.long 0x24 0. " [0] ,LUT0 complete interrupt set" "No effect,Set" line.long 0x28 "IRQ1_CLR,EPDC Interrupt Clear Register for LUT 0-31" bitfld.long 0x28 31. " LUT31_CMPLT_IRQ_CLR ,LUT31 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 30. " [30] ,LUT30 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 29. " [29] ,LUT29 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 28. " [28] ,LUT28 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 27. " [27] ,LUT27 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 26. " [26] ,LUT26 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 25. " [25] ,LUT25 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 24. " [24] ,LUT24 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 23. " [23] ,LUT23 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 22. " [22] ,LUT22 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 21. " [21] ,LUT21 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 20. " [20] ,LUT20 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 19. " [19] ,LUT19 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 18. " [18] ,LUT18 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 17. " [17] ,LUT17 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 16. " [16] ,LUT16 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 15. " [15] ,LUT15 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 14. " [14] ,LUT14 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 13. " [13] ,LUT13 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 12. " [12] ,LUT12 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 11. " [11] ,LUT11 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 10. " [10] ,LUT10 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 9. " [9] ,LUT9 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 8. " [8] ,LUT8 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 7. " [7] ,LUT7 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 6. " [6] ,LUT6 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 5. " [5] ,LUT5 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 4. " [4] ,LUT4 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 3. " [3] ,LUT3 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 2. " [2] ,LUT2 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x28 1. " [1] ,LUT1 complete interrupt clear" "No effect,Clear" bitfld.long 0x28 0. " [0] ,LUT0 complete interrupt clear" "No effect,Clear" line.long 0x2C "IRQ1_TOG,EPDC Interrupt Toggle Register for LUT 0-31" bitfld.long 0x2C 31. " LUT31_CMPLT_IRQ_TOG ,LUT31 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 30. " [30] ,LUT30 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 29. " [29] ,LUT29 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 28. " [28] ,LUT28 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 27. " [27] ,LUT27 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 26. " [26] ,LUT26 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 25. " [25] ,LUT25 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 24. " [24] ,LUT24 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 23. " [23] ,LUT23 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 22. " [22] ,LUT22 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 21. " [21] ,LUT21 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 20. " [20] ,LUT20 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 19. " [19] ,LUT19 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 18. " [18] ,LUT18 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 17. " [17] ,LUT17 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 16. " [16] ,LUT16 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 15. " [15] ,LUT15 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 14. " [14] ,LUT14 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 13. " [13] ,LUT13 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 12. " [12] ,LUT12 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 11. " [11] ,LUT11 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 10. " [10] ,LUT10 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 9. " [9] ,LUT9 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 8. " [8] ,LUT8 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 7. " [7] ,LUT7 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 6. " [6] ,LUT6 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 5. " [5] ,LUT5 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 4. " [4] ,LUT4 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 3. " [3] ,LUT3 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 2. " [2] ,LUT2 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x2C 1. " [1] ,LUT1 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x2C 0. " [0] ,LUT0 complete interrupt toggle" "Not toggled,Toggled" line.long 0x30 "IRQ2,EPDC Interrupt Register for LUT 32-63" bitfld.long 0x30 31. " LUT63_CMPLT_IRQ ,LUT63 Complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 30. " [62] ,LUT62 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 29. " [61] ,LUT61 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 28. " [60] ,LUT60 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 27. " [59] ,LUT59 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 26. " [58] ,LUT58 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 25. " [57] ,LUT57 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 24. " [56] ,LUT56 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 23. " [55] ,LUT55 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 22. " [54] ,LUT54 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 21. " [53] ,LUT53 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 20. " [52] ,LUT52 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 19. " [51] ,LUT51 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 18. " [50] ,LUT50 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 17. " [49] ,LUT49 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 16. " [48] ,LUT48 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 15. " [47] ,LUT47 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 14. " [46] ,LUT46 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 13. " [45] ,LUT45 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 12. " [44] ,LUT44 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 11. " [43] ,LUT43 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 10. " [42] ,LUT42 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 9. " [41] ,LUT41 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 8. " [40] ,LUT40 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 7. " [39] ,LUT39 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 6. " [38] ,LUT38 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 5. " [37] ,LUT37 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 4. " [36] ,LUT36 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 3. " [35] ,LUT35 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 2. " [34] ,LUT34 complete interrupt" "No interrupt,Interrupt" newline bitfld.long 0x30 1. " [33] ,LUT33 complete interrupt" "No interrupt,Interrupt" bitfld.long 0x30 0. " [32] ,LUT32 complete interrupt" "No interrupt,Interrupt" line.long 0x34 "IRQ2_SET,EPDC Interrupt Set Register for LUT 32-63" bitfld.long 0x34 31. " LUT63_CMPLT_IRQ_SET ,LUT63 complete interrupt set" "No effect,Set" bitfld.long 0x34 30. " [62] ,LUT62 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 29. " [61] ,LUT61 complete interrupt set" "No effect,Set" bitfld.long 0x34 28. " [60] ,LUT60 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 27. " [59] ,LUT59 complete interrupt set" "No effect,Set" bitfld.long 0x34 26. " [58] ,LUT58 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 25. " [57] ,LUT57 complete interrupt set" "No effect,Set" bitfld.long 0x34 24. " [56] ,LUT56 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 23. " [55] ,LUT55 complete interrupt set" "No effect,Set" bitfld.long 0x34 22. " [54] ,LUT54 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 21. " [53] ,LUT53 complete interrupt set" "No effect,Set" bitfld.long 0x34 20. " [52] ,LUT52 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 19. " [51] ,LUT51 complete interrupt set" "No effect,Set" bitfld.long 0x34 18. " [50] ,LUT50 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 17. " [49] ,LUT49 complete interrupt set" "No effect,Set" bitfld.long 0x34 16. " [48] ,LUT48 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 15. " [47] ,LUT47 complete interrupt set" "No effect,Set" bitfld.long 0x34 14. " [46] ,LUT46 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 13. " [45] ,LUT45 complete interrupt set" "No effect,Set" bitfld.long 0x34 12. " [44] ,LUT44 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 11. " [43] ,LUT43 complete interrupt set" "No effect,Set" bitfld.long 0x34 10. " [42] ,LUT42 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 9. " [41] ,LUT41 complete interrupt set" "No effect,Set" bitfld.long 0x34 8. " [40] ,LUT40 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 7. " [39] ,LUT39 complete interrupt set" "No effect,Set" bitfld.long 0x34 6. " [38] ,LUT38 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 5. " [37] ,LUT37 complete interrupt set" "No effect,Set" bitfld.long 0x34 4. " [36] ,LUT36 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 3. " [35] ,LUT35 complete interrupt set" "No effect,Set" bitfld.long 0x34 2. " [34] ,LUT34 complete interrupt set" "No effect,Set" newline bitfld.long 0x34 1. " [33] ,LUT33 complete interrupt set" "No effect,Set" bitfld.long 0x34 0. " [32] ,LUT32 complete interrupt set" "No effect,Set" line.long 0x38 "IRQ2_CLR,EPDC Interrupt Clear Register for LUT 32-63" bitfld.long 0x38 31. " LUT63_CMPLT_IRQ_CLR ,LUT63 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 30. " [62] ,LUT62 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 29. " [61] ,LUT61 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 28. " [60] ,LUT60 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 27. " [59] ,LUT59 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 26. " [58] ,LUT58 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 25. " [57] ,LUT57 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 24. " [56] ,LUT56 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 23. " [55] ,LUT55 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 22. " [54] ,LUT54 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 21. " [53] ,LUT53 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 20. " [52] ,LUT52 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 19. " [51] ,LUT51 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 18. " [50] ,LUT50 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 17. " [49] ,LUT49 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 16. " [48] ,LUT48 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 15. " [47] ,LUT47 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 14. " [46] ,LUT46 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 13. " [45] ,LUT45 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 12. " [44] ,LUT44 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 11. " [43] ,LUT43 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 10. " [42] ,LUT42 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 9. " [41] ,LUT41 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 8. " [40] ,LUT40 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 7. " [39] ,LUT39 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 6. " [38] ,LUT38 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 5. " [37] ,LUT37 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 4. " [36] ,LUT36 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 3. " [35] ,LUT35 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 2. " [34] ,LUT34 complete interrupt clear" "No effect,Clear" newline bitfld.long 0x38 1. " [33] ,LUT33 complete interrupt clear" "No effect,Clear" bitfld.long 0x38 0. " [32] ,LUT32 complete interrupt clear" "No effect,Clear" line.long 0x3C "IRQ2_TOG,EPDC Interrupt Toggle Register for LUT 32-63" bitfld.long 0x3C 31. " LUT63_CMPLT_IRQ_TOG ,LUT63 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 30. " [62] ,LUT62 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 29. " [61] ,LUT61 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 28. " [60] ,LUT60 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 27. " [59] ,LUT59 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 26. " [58] ,LUT58 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 25. " [57] ,LUT57 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 24. " [56] ,LUT56 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 23. " [55] ,LUT55 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 22. " [54] ,LUT54 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 21. " [53] ,LUT53 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 20. " [52] ,LUT52 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 19. " [51] ,LUT51 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 18. " [50] ,LUT50 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 17. " [49] ,LUT49 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 16. " [48] ,LUT48 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 15. " [47] ,LUT47 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 14. " [46] ,LUT46 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 13. " [45] ,LUT45 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 12. " [44] ,LUT44 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 11. " [43] ,LUT43 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 10. " [42] ,LUT42 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 9. " [41] ,LUT41 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 8. " [40] ,LUT40 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 7. " [39] ,LUT39 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 6. " [38] ,LUT38 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 5. " [37] ,LUT37 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 4. " [36] ,LUT36 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 3. " [35] ,LUT35 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 2. " [34] ,LUT34 complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x3C 1. " [33] ,LUT33 complete interrupt toggle" "Not toggled,Toggled" bitfld.long 0x3C 0. " [32] ,LUT32 complete interrupt toggle" "Not toggled,Toggled" line.long 0x40 "IRQ_MASK,EPDC IRQ Mask Register" bitfld.long 0x40 23. " PWR_IRQ_EN ,Enable power interrupt" "Disabled,Enabled" bitfld.long 0x40 22. " UPD_DONE_IRQ_EN ,Enable UPD complete interrupt" "Disabled,Enabled" newline bitfld.long 0x40 21. " TCE_IDLE_IRQ_EN ,Enable TCE Idle interrupt detection" "Disabled,Enabled" bitfld.long 0x40 20. " BUS_ERROR_IRQ_EN ,Enable AXI BUS ERROR interrupt detection" "Disabled,Enabled" newline bitfld.long 0x40 19. " FRAME_END_IRQ_EN ,Assert the current frame end interrupt" "Disabled,Enabled" bitfld.long 0x40 18. " TCE_UNDERRUN_IRQ_EN ,Enable pixel FIFO under-run condition detection" "Disabled,Enabled" newline bitfld.long 0x40 17. " COL_IRQ_EN ,Enable collision detection interrupts for all LUTs" "Disabled,Enabled" bitfld.long 0x40 16. " WB_CMPLT_IRQ_EN ,Enable WB complete interrupt" "Disabled,Enabled" line.long 0x44 "IRQ_MASK_SET,EPDC IRQ Mask Set Register" bitfld.long 0x44 23. " PWR_IRQ_EN ,Enable power interrupt set" "No effect,Set" bitfld.long 0x44 22. " UPD_DONE_IRQ_EN ,Enable UPD complete interrupt set" "No effect,Set" newline bitfld.long 0x44 21. " TCE_IDLE_IRQ_EN ,Enable TCE Idle interrupt detection set" "No effect,Set" bitfld.long 0x44 20. " BUS_ERROR_IRQ_EN ,Enable AXI BUS ERROR interrupt detection set" "No effect,Set" newline bitfld.long 0x44 19. " FRAME_END_IRQ_EN ,Assert the current frame end interrupt set" "No effect,Set" bitfld.long 0x44 18. " TCE_UNDERRUN_IRQ_EN ,Enable pixel FIFO under-run condition detection set" "No effect,Set" newline bitfld.long 0x44 17. " COL_IRQ_EN ,Enable collision detection interrupts for all LUTs set" "No effect,Set" bitfld.long 0x44 16. " WB_CMPLT_IRQ_EN ,Enable WB complete interrupt set" "No effect,Set" line.long 0x48 "IRQ_MASK_CLR,EPDC IRQ Mask Clear Register" bitfld.long 0x48 23. " PWR_IRQ_EN ,Enable power interrupt clear" "No effect,Clear" bitfld.long 0x48 22. " UPD_DONE_IRQ_EN ,Enable UPD complete interrupt clear" "No effect,Clear" newline bitfld.long 0x48 21. " TCE_IDLE_IRQ_EN ,Enable TCE Idle interrupt detection clear" "No effect,Clear" bitfld.long 0x48 20. " BUS_ERROR_IRQ_EN ,Enable AXI BUS ERROR interrupt detection clear" "No effect,Clear" newline bitfld.long 0x48 19. " FRAME_END_IRQ_EN ,Assert the current frame end interrupt clear" "No effect,Clear" bitfld.long 0x48 18. " TCE_UNDERRUN_IRQ_EN ,Enable pixel FIFO under-run condition detection clear" "No effect,Clear" newline bitfld.long 0x48 17. " COL_IRQ_EN ,Enable collision detection interrupts for all LUTs clear" "No effect,Clear" bitfld.long 0x48 16. " WB_CMPLT_IRQ_EN ,Enable WB complete interrupt clear" "No effect,Clear" line.long 0x4C "IRQ_MASK_TOG,EPDC IRQ Mask Toggle Register" bitfld.long 0x4C 23. " PWR_IRQ_EN ,Enable power interrupt toggle" "Not toggled,Toggled" bitfld.long 0x4C 22. " UPD_DONE_IRQ_EN ,Enable UPD complete interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x4C 21. " TCE_IDLE_IRQ_EN ,Enable TCE Idle interrupt detection toggle" "Not toggled,Toggled" bitfld.long 0x4C 20. " BUS_ERROR_IRQ_EN ,Enable AXI BUS ERROR interrupt detection toggle" "Not toggled,Toggled" newline bitfld.long 0x4C 19. " FRAME_END_IRQ_EN ,Assert the current frame end interrupt toggle" "Not toggled,Toggled" bitfld.long 0x4C 18. " TCE_UNDERRUN_IRQ_EN ,Enable pixel FIFO under-run condition detection toggle" "Not toggled,Toggled" newline bitfld.long 0x4C 17. " COL_IRQ_EN ,Enable collision detection interrupts for all LUTs toggle" "Not toggled,Toggled" bitfld.long 0x4C 16. " WB_CMPLT_IRQ_EN ,Enable WB complete interrupt toggle" "Not toggled,Toggled" group.long 0x420++0x0F line.long 0x00 "IRQ,EPDC Interrupt Register" bitfld.long 0x00 23. " PWR_IRQ ,Power interrupt" "No interrupt,Interrupt" bitfld.long 0x00 22. " UPD_DONE_IRQ ,Working buffer process complete Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 21. " TCE_IDLE_IRQ ,Interrupt to indicate that the TCE has completed TFT frame scans and is in an idle state" "No interrupt,Interrupt" bitfld.long 0x00 20. " BUS_ERROR_IRQ ,Interrupt to indicate AXI BUS error occurs" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " FRAME_END_IRQ ,Interrupt to indicate EPDC has completed the current frame and is in the vertical blanking period" "No interrupt,Interrupt" bitfld.long 0x00 18. " TCE_UNDERRUN_IRQ ,Interrupt to indicate that a pixel FIFO under-run has occurred" "No interrupt,Interrupt" newline bitfld.long 0x00 17. " LUT_COL_IRQ ,Collision detection interrupt" "No interrupt,Interrupt" bitfld.long 0x00 16. " WB_CMPLT_IRQ ,Working buffer process complete Interrupt" "No interrupt,Interrupt" line.long 0x04 "IRQ_SET,EPDC Interrupt Set Register" bitfld.long 0x04 23. " PWR_IRQ ,Power interrupt set" "No effect,Set" bitfld.long 0x04 22. " UPD_DONE_IRQ ,Working buffer process complete Interrupt set" "No effect,Set" newline bitfld.long 0x04 21. " TCE_IDLE_IRQ ,Interrupt to indicate that the TCE has completed TFT frame scans and is in an idle state set" "No effect,Set" bitfld.long 0x04 20. " BUS_ERROR_IRQ ,Interrupt to indicate AXI BUS error occurs set" "No effect,Set" newline bitfld.long 0x04 19. " FRAME_END_IRQ ,Interrupt to indicate EPDC has completed the current frame and is in the vertical blanking period set" "No effect,Set" bitfld.long 0x04 18. " TCE_UNDERRUN_IRQ ,Interrupt to indicate that a pixel FIFO under-run has occurred set" "No effect,Set" newline bitfld.long 0x04 17. " LUT_COL_IRQ ,Collision detection interrupt set" "No effect,Set" bitfld.long 0x04 16. " WB_CMPLT_IRQ ,Working buffer process complete Interrupt set" "No effect,Set" line.long 0x08 "IRQ_CLR,EPDC Interrupt Clear Register" bitfld.long 0x08 23. " PWR_IRQ ,Power interrupt clear" "No effect,Clear" bitfld.long 0x08 22. " UPD_DONE_IRQ ,Working buffer process complete Interrupt clear" "No effect,Clear" newline bitfld.long 0x08 21. " TCE_IDLE_IRQ ,Interrupt to indicate that the TCE has completed TFT frame scans and is in an idle state clear" "No effect,Clear" bitfld.long 0x08 20. " BUS_ERROR_IRQ ,Interrupt to indicate AXI BUS error occurs clear" "No effect,Clear" newline bitfld.long 0x08 19. " FRAME_END_IRQ ,Interrupt to indicate EPDC has completed the current frame and is in the vertical blanking period clear" "No effect,Clear" bitfld.long 0x08 18. " TCE_UNDERRUN_IRQ ,Interrupt to indicate that a pixel FIFO under-run has occurred clear" "No effect,Clear" newline bitfld.long 0x08 17. " LUT_COL_IRQ ,Collision detection interrupt clear" "No effect,Clear" bitfld.long 0x08 16. " WB_CMPLT_IRQ ,Working buffer process complete Interrupt clear" "No effect,Clear" line.long 0x0C "IRQ_TOG,EPDC Interrupt Toggle Register" bitfld.long 0x0C 23. " PWR_IRQ ,Power interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 22. " UPD_DONE_IRQ ,Working buffer process complete Interrupt toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 21. " TCE_IDLE_IRQ ,Interrupt to indicate that the TCE has completed TFT frame scans and is in an idle state toggle" "Not toggled,Toggled" bitfld.long 0x0C 20. " BUS_ERROR_IRQ ,Interrupt to indicate AXI BUS error occurs toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 19. " FRAME_END_IRQ ,Interrupt to indicate EPDC has completed the current frame and is in the vertical blanking period toggle" "Not toggled,Toggled" bitfld.long 0x0C 18. " TCE_UNDERRUN_IRQ ,Interrupt to indicate that a pixel FIFO under-run has occurred toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 17. " LUT_COL_IRQ ,Collision detection interrupt toggle" "Not toggled,Toggled" bitfld.long 0x0C 16. " WB_CMPLT_IRQ ,Working buffer process complete Interrupt toggle" "Not toggled,Toggled" group.long 0x440++0x1F line.long 0x00 "STATUS_LUTS1,EPDC Status Register - LUTs" bitfld.long 0x00 31. " LUT31_STS ,LUT31 status" "Idle,Active" bitfld.long 0x00 30. " [30] ,LUT30 status" "Idle,Active" newline bitfld.long 0x00 29. " [29] ,LUT29 status" "Idle,Active" bitfld.long 0x00 28. " [28] ,LUT28 status" "Idle,Active" newline bitfld.long 0x00 27. " [27] ,LUT27 status" "Idle,Active" bitfld.long 0x00 26. " [26] ,LUT26 status" "Idle,Active" newline bitfld.long 0x00 25. " [25] ,LUT25 status" "Idle,Active" bitfld.long 0x00 24. " [24] ,LUT24 status" "Idle,Active" newline bitfld.long 0x00 23. " [23] ,LUT23 status" "Idle,Active" bitfld.long 0x00 22. " [22] ,LUT22 status" "Idle,Active" newline bitfld.long 0x00 21. " [21] ,LUT21 status" "Idle,Active" bitfld.long 0x00 20. " [20] ,LUT20 status" "Idle,Active" newline bitfld.long 0x00 19. " [19] ,LUT19 status" "Idle,Active" bitfld.long 0x00 18. " [18] ,LUT18 status" "Idle,Active" newline bitfld.long 0x00 17. " [17] ,LUT17 status" "Idle,Active" bitfld.long 0x00 16. " [16] ,LUT16 status" "Idle,Active" newline bitfld.long 0x00 15. " [15] ,LUT15 status" "Idle,Active" bitfld.long 0x00 14. " [14] ,LUT14 status" "Idle,Active" newline bitfld.long 0x00 13. " [13] ,LUT13 status" "Idle,Active" bitfld.long 0x00 12. " [12] ,LUT12 status" "Idle,Active" newline bitfld.long 0x00 11. " [11] ,LUT11 status" "Idle,Active" bitfld.long 0x00 10. " [10] ,LUT10 status" "Idle,Active" newline bitfld.long 0x00 9. " [9] ,LUT9 status" "Idle,Active" bitfld.long 0x00 8. " [8] ,LUT8 status" "Idle,Active" newline bitfld.long 0x00 7. " [7] ,LUT7 status" "Idle,Active" bitfld.long 0x00 6. " [6] ,LUT6 status" "Idle,Active" newline bitfld.long 0x00 5. " [5] ,LUT5 status" "Idle,Active" bitfld.long 0x00 4. " [4] ,LUT4 status" "Idle,Active" newline bitfld.long 0x00 3. " [3] ,LUT3 status" "Idle,Active" bitfld.long 0x00 2. " [2] ,LUT2 status" "Idle,Active" newline bitfld.long 0x00 1. " [1] ,LUT1 status" "Idle,Active" bitfld.long 0x00 0. " [0] ,LUT0 status" "Idle,Active" line.long 0x04 "STATUS_LUTS1_SET,EPDC Status Set Register - LUTs" bitfld.long 0x04 31. " LUT31_STS ,LUT31 status set" "No effect,Set" bitfld.long 0x04 30. " [30] ,LUT30 status set" "No effect,Set" newline bitfld.long 0x04 29. " [29] ,LUT29 status set" "No effect,Set" bitfld.long 0x04 28. " [28] ,LUT28 status set" "No effect,Set" newline bitfld.long 0x04 27. " [27] ,LUT27 status set" "No effect,Set" bitfld.long 0x04 26. " [26] ,LUT26 status set" "No effect,Set" newline bitfld.long 0x04 25. " [25] ,LUT25 status set" "No effect,Set" bitfld.long 0x04 24. " [24] ,LUT24 status set" "No effect,Set" newline bitfld.long 0x04 23. " [23] ,LUT23 status set" "No effect,Set" bitfld.long 0x04 22. " [22] ,LUT22 status set" "No effect,Set" newline bitfld.long 0x04 21. " [21] ,LUT21 status set" "No effect,Set" bitfld.long 0x04 20. " [20] ,LUT20 status set" "No effect,Set" newline bitfld.long 0x04 19. " [19] ,LUT19 status set" "No effect,Set" bitfld.long 0x04 18. " [18] ,LUT18 status set" "No effect,Set" newline bitfld.long 0x04 17. " [17] ,LUT17 status set" "No effect,Set" bitfld.long 0x04 16. " [16] ,LUT16 status set" "No effect,Set" newline bitfld.long 0x04 15. " [15] ,LUT15 status set" "No effect,Set" bitfld.long 0x04 14. " [14] ,LUT14 status set" "No effect,Set" newline bitfld.long 0x04 13. " [13] ,LUT13 status set" "No effect,Set" bitfld.long 0x04 12. " [12] ,LUT12 status set" "No effect,Set" newline bitfld.long 0x04 11. " [11] ,LUT11 status set" "No effect,Set" bitfld.long 0x04 10. " [10] ,LUT10 status set" "No effect,Set" newline bitfld.long 0x04 9. " [9] ,LUT9 status set" "No effect,Set" bitfld.long 0x04 8. " [8] ,LUT8 status set" "No effect,Set" newline bitfld.long 0x04 7. " [7] ,LUT7 status set" "No effect,Set" bitfld.long 0x04 6. " [6] ,LUT6 status set" "No effect,Set" newline bitfld.long 0x04 5. " [5] ,LUT5 status set" "No effect,Set" bitfld.long 0x04 4. " [4] ,LUT4 status set" "No effect,Set" newline bitfld.long 0x04 3. " [3] ,LUT3 status set" "No effect,Set" bitfld.long 0x04 2. " [2] ,LUT2 status set" "No effect,Set" newline bitfld.long 0x04 1. " [1] ,LUT1 status set" "No effect,Set" bitfld.long 0x04 0. " [0] ,LUT0 status set" "No effect,Set" line.long 0x08 "STATUS_LUTS1_CLR,EPDC Status Clear Register - LUTs" bitfld.long 0x08 31. " LUT31_STS ,LUT31 status clear" "No effect,Clear" bitfld.long 0x08 30. " [30] ,LUT30 status clear" "No effect,Clear" newline bitfld.long 0x08 29. " [29] ,LUT29 status clear" "No effect,Clear" bitfld.long 0x08 28. " [28] ,LUT28 status clear" "No effect,Clear" newline bitfld.long 0x08 27. " [27] ,LUT27 status clear" "No effect,Clear" bitfld.long 0x08 26. " [26] ,LUT26 status clear" "No effect,Clear" newline bitfld.long 0x08 25. " [25] ,LUT25 status clear" "No effect,Clear" bitfld.long 0x08 24. " [24] ,LUT24 status clear" "No effect,Clear" newline bitfld.long 0x08 23. " [23] ,LUT23 status clear" "No effect,Clear" bitfld.long 0x08 22. " [22] ,LUT22 status clear" "No effect,Clear" newline bitfld.long 0x08 21. " [21] ,LUT21 status clear" "No effect,Clear" bitfld.long 0x08 20. " [20] ,LUT20 status clear" "No effect,Clear" newline bitfld.long 0x08 19. " [19] ,LUT19 status clear" "No effect,Clear" bitfld.long 0x08 18. " [18] ,LUT18 status clear" "No effect,Clear" newline bitfld.long 0x08 17. " [17] ,LUT17 status clear" "No effect,Clear" bitfld.long 0x08 16. " [16] ,LUT16 status clear" "No effect,Clear" newline bitfld.long 0x08 15. " [15] ,LUT15 status clear" "No effect,Clear" bitfld.long 0x08 14. " [14] ,LUT14 status clear" "No effect,Clear" newline bitfld.long 0x08 13. " [13] ,LUT13 status clear" "No effect,Clear" bitfld.long 0x08 12. " [12] ,LUT12 status clear" "No effect,Clear" newline bitfld.long 0x08 11. " [11] ,LUT11 status clear" "No effect,Clear" bitfld.long 0x08 10. " [10] ,LUT10 status clear" "No effect,Clear" newline bitfld.long 0x08 9. " [9] ,LUT9 status clear" "No effect,Clear" bitfld.long 0x08 8. " [8] ,LUT8 status clear" "No effect,Clear" newline bitfld.long 0x08 7. " [7] ,LUT7 status clear" "No effect,Clear" bitfld.long 0x08 6. " [6] ,LUT6 status clear" "No effect,Clear" newline bitfld.long 0x08 5. " [5] ,LUT5 status clear" "No effect,Clear" bitfld.long 0x08 4. " [4] ,LUT4 status clear" "No effect,Clear" newline bitfld.long 0x08 3. " [3] ,LUT3 status clear" "No effect,Clear" bitfld.long 0x08 2. " [2] ,LUT2 status clear" "No effect,Clear" newline bitfld.long 0x08 1. " [1] ,LUT1 status clear" "No effect,Clear" bitfld.long 0x08 0. " [0] ,LUT0 status clear" "No effect,Clear" line.long 0x0C "STATUS_LUTS1_TOG,EPDC Status Toggle Register - LUTs" bitfld.long 0x0C 31. " LUT31_STS ,LUT31 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 30. " [30] ,LUT30 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 29. " [29] ,LUT29 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 28. " [28] ,LUT28 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 27. " [27] ,LUT27 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 26. " [26] ,LUT26 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 25. " [25] ,LUT25 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 24. " [24] ,LUT24 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 23. " [23] ,LUT23 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 22. " [22] ,LUT22 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 21. " [21] ,LUT21 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 20. " [20] ,LUT20 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 19. " [19] ,LUT19 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 18. " [18] ,LUT18 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 17. " [17] ,LUT17 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 16. " [16] ,LUT16 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 15. " [15] ,LUT15 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 14. " [14] ,LUT14 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 13. " [13] ,LUT13 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 12. " [12] ,LUT12 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 11. " [11] ,LUT11 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 10. " [10] ,LUT10 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 9. " [9] ,LUT9 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 8. " [8] ,LUT8 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 7. " [7] ,LUT7 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 6. " [6] ,LUT6 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 5. " [5] ,LUT5 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 4. " [4] ,LUT4 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 3. " [3] ,LUT3 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 2. " [2] ,LUT2 status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 1. " [1] ,LUT1 status toggle" "Not toggled,Toggled" bitfld.long 0x0C 0. " [0] ,LUT0 status toggle" "Not toggled,Toggled" line.long 0x10 "STATUS_LUTS2,EPDC Status Register - LUTs" bitfld.long 0x10 31. " LUT63_STS ,LUT63 status" "Idle,Active" bitfld.long 0x10 30. " [62] ,LUT62 status" "Idle,Active" newline bitfld.long 0x10 29. " [61] ,LUT61 status" "Idle,Active" bitfld.long 0x10 28. " [60] ,LUT60 status" "Idle,Active" newline bitfld.long 0x10 27. " [59] ,LUT59 status" "Idle,Active" bitfld.long 0x10 26. " [58] ,LUT58 status" "Idle,Active" newline bitfld.long 0x10 25. " [57] ,LUT57 status" "Idle,Active" bitfld.long 0x10 24. " [56] ,LUT56 status" "Idle,Active" newline bitfld.long 0x10 23. " [55] ,LUT55 status" "Idle,Active" bitfld.long 0x10 22. " [54] ,LUT54 status" "Idle,Active" newline bitfld.long 0x10 21. " [53] ,LUT53 status" "Idle,Active" bitfld.long 0x10 20. " [52] ,LUT52 status" "Idle,Active" newline bitfld.long 0x10 19. " [51] ,LUT51 status" "Idle,Active" bitfld.long 0x10 18. " [50] ,LUT50 status" "Idle,Active" newline bitfld.long 0x10 17. " [49] ,LUT49 status" "Idle,Active" bitfld.long 0x10 16. " [48] ,LUT48 status" "Idle,Active" newline bitfld.long 0x10 15. " [47] ,LUT47 status" "Idle,Active" bitfld.long 0x10 14. " [46] ,LUT46 status" "Idle,Active" newline bitfld.long 0x10 13. " [45] ,LUT45 status" "Idle,Active" bitfld.long 0x10 12. " [44] ,LUT44 status" "Idle,Active" newline bitfld.long 0x10 11. " [43] ,LUT43 status" "Idle,Active" bitfld.long 0x10 10. " [42] ,LUT42 status" "Idle,Active" newline bitfld.long 0x10 9. " [41] ,LUT41 status" "Idle,Active" bitfld.long 0x10 8. " [40] ,LUT40 status" "Idle,Active" newline bitfld.long 0x10 7. " [39] ,LUT39 status" "Idle,Active" bitfld.long 0x10 6. " [38] ,LUT38 status" "Idle,Active" newline bitfld.long 0x10 5. " [37] ,LUT37 status" "Idle,Active" bitfld.long 0x10 4. " [36] ,LUT36 status" "Idle,Active" newline bitfld.long 0x10 3. " [35] ,LUT35 status" "Idle,Active" bitfld.long 0x10 2. " [34] ,LUT34 status" "Idle,Active" newline bitfld.long 0x10 1. " [33] ,LUT33 status" "Idle,Active" bitfld.long 0x10 0. " [32] ,LUT32 status" "Idle,Active" line.long 0x14 "STATUS_LUTS2_SET,EPDC Status Set Register - LUTs" bitfld.long 0x14 31. " LUT63_STS ,LUT63 status set" "No effect,Set" bitfld.long 0x14 30. " [62] ,LUT62 status set" "No effect,Set" newline bitfld.long 0x14 29. " [61] ,LUT61 status set" "No effect,Set" bitfld.long 0x14 28. " [60] ,LUT60 status set" "No effect,Set" newline bitfld.long 0x14 27. " [59] ,LUT59 status set" "No effect,Set" bitfld.long 0x14 26. " [58] ,LUT58 status set" "No effect,Set" newline bitfld.long 0x14 25. " [57] ,LUT57 status set" "No effect,Set" bitfld.long 0x14 24. " [56] ,LUT56 status set" "No effect,Set" newline bitfld.long 0x14 23. " [55] ,LUT55 status set" "No effect,Set" bitfld.long 0x14 22. " [54] ,LUT54 status set" "No effect,Set" newline bitfld.long 0x14 21. " [53] ,LUT53 status set" "No effect,Set" bitfld.long 0x14 20. " [52] ,LUT52 status set" "No effect,Set" newline bitfld.long 0x14 19. " [51] ,LUT51 status set" "No effect,Set" bitfld.long 0x14 18. " [50] ,LUT50 status set" "No effect,Set" newline bitfld.long 0x14 17. " [49] ,LUT49 status set" "No effect,Set" bitfld.long 0x14 16. " [48] ,LUT48 status set" "No effect,Set" newline bitfld.long 0x14 15. " [47] ,LUT47 status set" "No effect,Set" bitfld.long 0x14 14. " [46] ,LUT46 status set" "No effect,Set" newline bitfld.long 0x14 13. " [45] ,LUT45 status set" "No effect,Set" bitfld.long 0x14 12. " [44] ,LUT44 status set" "No effect,Set" newline bitfld.long 0x14 11. " [43] ,LUT43 status set" "No effect,Set" bitfld.long 0x14 10. " [42] ,LUT42 status set" "No effect,Set" newline bitfld.long 0x14 9. " [41] ,LUT41 status set" "No effect,Set" bitfld.long 0x14 8. " [40] ,LUT40 status set" "No effect,Set" newline bitfld.long 0x14 7. " [39] ,LUT39 status set" "No effect,Set" bitfld.long 0x14 6. " [38] ,LUT38 status set" "No effect,Set" newline bitfld.long 0x14 5. " [37] ,LUT37 status set" "No effect,Set" bitfld.long 0x14 4. " [36] ,LUT36 status set" "No effect,Set" newline bitfld.long 0x14 3. " [35] ,LUT35 status set" "No effect,Set" bitfld.long 0x14 2. " [34] ,LUT34 status set" "No effect,Set" newline bitfld.long 0x14 1. " [33] ,LUT33 status set" "No effect,Set" bitfld.long 0x14 0. " [32] ,LUT32 status set" "No effect,Set" line.long 0x18 "STATUS_LUTS2_CLR,EPDC Status Clear Register - LUTs" bitfld.long 0x18 31. " LUT63_STS ,LUT63 status clear" "No effect,Clear" bitfld.long 0x18 30. " [62] ,LUT62 status set" "No effect,Set" newline bitfld.long 0x18 29. " [61] ,LUT61 status set" "No effect,Set" bitfld.long 0x18 28. " [60] ,LUT60 status set" "No effect,Set" newline bitfld.long 0x18 27. " [59] ,LUT59 status set" "No effect,Set" bitfld.long 0x18 26. " [58] ,LUT58 status set" "No effect,Set" newline bitfld.long 0x18 25. " [57] ,LUT57 status set" "No effect,Set" bitfld.long 0x18 24. " [56] ,LUT56 status set" "No effect,Set" newline bitfld.long 0x18 23. " [55] ,LUT55 status set" "No effect,Set" bitfld.long 0x18 22. " [54] ,LUT54 status set" "No effect,Set" newline bitfld.long 0x18 21. " [53] ,LUT53 status set" "No effect,Set" bitfld.long 0x18 20. " [52] ,LUT52 status set" "No effect,Set" newline bitfld.long 0x18 19. " [51] ,LUT51 status set" "No effect,Set" bitfld.long 0x18 18. " [50] ,LUT50 status set" "No effect,Set" newline bitfld.long 0x18 17. " [49] ,LUT49 status set" "No effect,Set" bitfld.long 0x18 16. " [48] ,LUT48 status set" "No effect,Set" newline bitfld.long 0x18 15. " [47] ,LUT47 status set" "No effect,Set" bitfld.long 0x18 14. " [46] ,LUT46 status set" "No effect,Set" newline bitfld.long 0x18 13. " [45] ,LUT45 status set" "No effect,Set" bitfld.long 0x18 12. " [44] ,LUT44 status set" "No effect,Set" newline bitfld.long 0x18 11. " [43] ,LUT43 status set" "No effect,Set" bitfld.long 0x18 10. " [42] ,LUT42 status set" "No effect,Set" newline bitfld.long 0x18 9. " [41] ,LUT41 status set" "No effect,Set" bitfld.long 0x18 8. " [40] ,LUT40 status set" "No effect,Set" newline bitfld.long 0x18 7. " [39] ,LUT39 status set" "No effect,Set" bitfld.long 0x18 6. " [38] ,LUT38 status set" "No effect,Set" newline bitfld.long 0x18 5. " [37] ,LUT37 status set" "No effect,Set" bitfld.long 0x18 4. " [36] ,LUT36 status set" "No effect,Set" newline bitfld.long 0x18 3. " [35] ,LUT35 status set" "No effect,Set" bitfld.long 0x18 2. " [34] ,LUT34 status set" "No effect,Set" newline bitfld.long 0x18 1. " [33] ,LUT33 status set" "No effect,Set" bitfld.long 0x18 0. " [32] ,LUT32 status set" "No effect,Set" line.long 0x1C "STATUS_LUTS2_TOG,EPDC Status Toggle Register - LUTs" bitfld.long 0x1C 31. " LUT63_STS ,LUT63 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 30. " [62] ,LUT62 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 29. " [61] ,LUT61 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 28. " [60] ,LUT60 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 27. " [59] ,LUT59 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 26. " [58] ,LUT58 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 25. " [57] ,LUT57 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 24. " [56] ,LUT56 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 23. " [55] ,LUT55 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 22. " [54] ,LUT54 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 21. " [53] ,LUT53 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 20. " [52] ,LUT52 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 19. " [51] ,LUT51 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 18. " [50] ,LUT50 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 17. " [49] ,LUT49 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 16. " [48] ,LUT48 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 15. " [47] ,LUT47 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 14. " [46] ,LUT46 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 13. " [45] ,LUT45 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 12. " [44] ,LUT44 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 11. " [43] ,LUT43 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 10. " [42] ,LUT42 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 9. " [41] ,LUT41 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 8. " [40] ,LUT40 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 7. " [39] ,LUT39 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 6. " [38] ,LUT38 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 5. " [37] ,LUT37 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 4. " [36] ,LUT36 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 3. " [35] ,LUT35 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 2. " [34] ,LUT34 status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 1. " [33] ,LUT33 status toggle" "Not toggled,Toggled" bitfld.long 0x1C 0. " [32] ,LUT32 status toggle" "Not toggled,Toggled" rgroup.long 0x460++0x03 line.long 0x00 "STATUS_NEXTLUT,EPDC Status Register - Next Available LUT" bitfld.long 0x00 8. " NEXT_LUT_VALID ,Checks against a LUTs full condition" "Not checked,Checked" bitfld.long 0x00 0.--5. " NEXT_LUT ,Next available LUT value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x480++0x1F line.long 0x00 "STATUS_COL1,EPDC LUT Collision Status" bitfld.long 0x00 31. " LUT31_COL_STS ,LUT31 collision status" "No collision,Collision" bitfld.long 0x00 30. " [30] ,LUT30 collision status" "No collision,Collision" newline bitfld.long 0x00 29. " [29] ,LUT29 collision status" "No collision,Collision" bitfld.long 0x00 28. " [28] ,LUT28 collision status" "No collision,Collision" newline bitfld.long 0x00 27. " [27] ,LUT27 collision status" "No collision,Collision" bitfld.long 0x00 26. " [26] ,LUT26 collision status" "No collision,Collision" newline bitfld.long 0x00 25. " [25] ,LUT25 collision status" "No collision,Collision" bitfld.long 0x00 24. " [24] ,LUT24 collision status" "No collision,Collision" newline bitfld.long 0x00 23. " [23] ,LUT23 collision status" "No collision,Collision" bitfld.long 0x00 22. " [22] ,LUT22 collision status" "No collision,Collision" newline bitfld.long 0x00 21. " [21] ,LUT21 collision status" "No collision,Collision" bitfld.long 0x00 20. " [20] ,LUT20 collision status" "No collision,Collision" newline bitfld.long 0x00 19. " [19] ,LUT19 collision status" "No collision,Collision" bitfld.long 0x00 18. " [18] ,LUT18 collision status" "No collision,Collision" newline bitfld.long 0x00 17. " [17] ,LUT17 collision status" "No collision,Collision" bitfld.long 0x00 16. " [16] ,LUT16 collision status" "No collision,Collision" newline bitfld.long 0x00 15. " [15] ,LUT15 collision status" "No collision,Collision" bitfld.long 0x00 14. " [14] ,LUT14 collision status" "No collision,Collision" newline bitfld.long 0x00 13. " [13] ,LUT13 collision status" "No collision,Collision" bitfld.long 0x00 12. " [12] ,LUT12 collision status" "No collision,Collision" newline bitfld.long 0x00 11. " [11] ,LUT11 collision status" "No collision,Collision" bitfld.long 0x00 10. " [10] ,LUT10 collision status" "No collision,Collision" newline bitfld.long 0x00 9. " [9] ,LUT9 collision status" "No collision,Collision" bitfld.long 0x00 8. " [8] ,LUT8 collision status" "No collision,Collision" newline bitfld.long 0x00 7. " [7] ,LUT7 collision status" "No collision,Collision" bitfld.long 0x00 6. " [6] ,LUT6 collision status" "No collision,Collision" newline bitfld.long 0x00 5. " [5] ,LUT5 collision status" "No collision,Collision" bitfld.long 0x00 4. " [4] ,LUT4 collision status" "No collision,Collision" newline bitfld.long 0x00 3. " [3] ,LUT3 collision status" "No collision,Collision" bitfld.long 0x00 2. " [2] ,LUT2 collision status" "No collision,Collision" newline bitfld.long 0x00 1. " [1] ,LUT1 collision status" "No collision,Collision" bitfld.long 0x00 0. " [0] ,LUT0 collision status" "No collision,Collision" line.long 0x04 "STATUS_COL1_SET,EPDC LUT Collision Status Set" bitfld.long 0x04 31. " LUT31_COL_STS ,LUT31 collision status set" "No effect,Set" bitfld.long 0x04 30. " [30] ,LUT30 collision status set" "No effect,Set" newline bitfld.long 0x04 29. " [29] ,LUT29 collision status set" "No effect,Set" bitfld.long 0x04 28. " [28] ,LUT28 collision status set" "No effect,Set" newline bitfld.long 0x04 27. " [27] ,LUT27 collision status set" "No effect,Set" bitfld.long 0x04 26. " [26] ,LUT26 collision status set" "No effect,Set" newline bitfld.long 0x04 25. " [25] ,LUT25 collision status set" "No effect,Set" bitfld.long 0x04 24. " [24] ,LUT24 collision status set" "No effect,Set" newline bitfld.long 0x04 23. " [23] ,LUT23 collision status set" "No effect,Set" bitfld.long 0x04 22. " [22] ,LUT22 collision status set" "No effect,Set" newline bitfld.long 0x04 21. " [21] ,LUT21 collision status set" "No effect,Set" bitfld.long 0x04 20. " [20] ,LUT20 collision status set" "No effect,Set" newline bitfld.long 0x04 19. " [19] ,LUT19 collision status set" "No effect,Set" bitfld.long 0x04 18. " [18] ,LUT18 collision status set" "No effect,Set" newline bitfld.long 0x04 17. " [17] ,LUT17 collision status set" "No effect,Set" bitfld.long 0x04 16. " [16] ,LUT16 collision status set" "No effect,Set" newline bitfld.long 0x04 15. " [15] ,LUT15 collision status set" "No effect,Set" bitfld.long 0x04 14. " [14] ,LUT14 collision status set" "No effect,Set" newline bitfld.long 0x04 13. " [13] ,LUT13 collision status set" "No effect,Set" bitfld.long 0x04 12. " [12] ,LUT12 collision status set" "No effect,Set" newline bitfld.long 0x04 11. " [11] ,LUT11 collision status set" "No effect,Set" bitfld.long 0x04 10. " [10] ,LUT10 collision status set" "No effect,Set" newline bitfld.long 0x04 9. " [9] ,LUT9 collision status set" "No effect,Set" bitfld.long 0x04 8. " [8] ,LUT8 collision status set" "No effect,Set" newline bitfld.long 0x04 7. " [7] ,LUT7 collision status set" "No effect,Set" bitfld.long 0x04 6. " [6] ,LUT6 collision status set" "No effect,Set" newline bitfld.long 0x04 5. " [5] ,LUT5 collision status set" "No effect,Set" bitfld.long 0x04 4. " [4] ,LUT4 collision status set" "No effect,Set" newline bitfld.long 0x04 3. " [3] ,LUT3 collision status set" "No effect,Set" bitfld.long 0x04 2. " [2] ,LUT2 collision status set" "No effect,Set" newline bitfld.long 0x04 1. " [1] ,LUT1 collision status set" "No effect,Set" bitfld.long 0x04 0. " [0] ,LUT0 collision status set" "No effect,Set" line.long 0x08 "STATUS_COL1_CLR,EPDC LUT Collision Status Clear" bitfld.long 0x08 31. " LUT31_COL_STS ,LUT31 collision status clear" "No effect,Clear" bitfld.long 0x08 30. " [30] ,LUT30 collision status clear" "No effect,Clear" newline bitfld.long 0x08 29. " [29] ,LUT29 collision status clear" "No effect,Clear" bitfld.long 0x08 28. " [28] ,LUT28 collision status clear" "No effect,Clear" newline bitfld.long 0x08 27. " [27] ,LUT27 collision status clear" "No effect,Clear" bitfld.long 0x08 26. " [26] ,LUT26 collision status clear" "No effect,Clear" newline bitfld.long 0x08 25. " [25] ,LUT25 collision status clear" "No effect,Clear" bitfld.long 0x08 24. " [24] ,LUT24 collision status clear" "No effect,Clear" newline bitfld.long 0x08 23. " [23] ,LUT23 collision status clear" "No effect,Clear" bitfld.long 0x08 22. " [22] ,LUT22 collision status clear" "No effect,Clear" newline bitfld.long 0x08 21. " [21] ,LUT21 collision status clear" "No effect,Clear" bitfld.long 0x08 20. " [20] ,LUT20 collision status clear" "No effect,Clear" newline bitfld.long 0x08 19. " [19] ,LUT19 collision status clear" "No effect,Clear" bitfld.long 0x08 18. " [18] ,LUT18 collision status clear" "No effect,Clear" newline bitfld.long 0x08 17. " [17] ,LUT17 collision status clear" "No effect,Clear" bitfld.long 0x08 16. " [16] ,LUT16 collision status clear" "No effect,Clear" newline bitfld.long 0x08 15. " [15] ,LUT15 collision status clear" "No effect,Clear" bitfld.long 0x08 14. " [14] ,LUT14 collision status clear" "No effect,Clear" newline bitfld.long 0x08 13. " [13] ,LUT13 collision status clear" "No effect,Clear" bitfld.long 0x08 12. " [12] ,LUT12 collision status clear" "No effect,Clear" newline bitfld.long 0x08 11. " [11] ,LUT11 collision status clear" "No effect,Clear" bitfld.long 0x08 10. " [10] ,LUT10 collision status clear" "No effect,Clear" newline bitfld.long 0x08 9. " [9] ,LUT9 collision status clear" "No effect,Clear" bitfld.long 0x08 8. " [8] ,LUT8 collision status clear" "No effect,Clear" newline bitfld.long 0x08 7. " [7] ,LUT7 collision status clear" "No effect,Clear" bitfld.long 0x08 6. " [6] ,LUT6 collision status clear" "No effect,Clear" newline bitfld.long 0x08 5. " [5] ,LUT5 collision status clear" "No effect,Clear" bitfld.long 0x08 4. " [4] ,LUT4 collision status clear" "No effect,Clear" newline bitfld.long 0x08 3. " [3] ,LUT3 collision status clear" "No effect,Clear" bitfld.long 0x08 2. " [2] ,LUT2 collision status clear" "No effect,Clear" newline bitfld.long 0x08 1. " [1] ,LUT1 collision status clear" "No effect,Clear" bitfld.long 0x08 0. " [0] ,LUT0 collision status clear" "No effect,Clear" line.long 0x0C "STATUS_COL1_TOG,EPDC LUT Collision Status Toggle" bitfld.long 0x0C 31. " LUT31_COL_STS ,LUT31 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 30. " [30] ,LUT30 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 29. " [29] ,LUT29 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 28. " [28] ,LUT28 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 27. " [27] ,LUT27 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 26. " [26] ,LUT26 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 25. " [25] ,LUT25 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 24. " [24] ,LUT24 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 23. " [23] ,LUT23 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 22. " [22] ,LUT22 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 21. " [21] ,LUT21 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 20. " [20] ,LUT20 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 19. " [19] ,LUT19 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 18. " [18] ,LUT18 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 17. " [17] ,LUT17 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 16. " [16] ,LUT16 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 15. " [15] ,LUT15 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 14. " [14] ,LUT14 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 13. " [13] ,LUT13 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 12. " [12] ,LUT12 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 11. " [11] ,LUT11 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 10. " [10] ,LUT10 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 9. " [9] ,LUT9 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 8. " [8] ,LUT8 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 7. " [7] ,LUT7 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 6. " [6] ,LUT6 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 5. " [5] ,LUT5 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 4. " [4] ,LUT4 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 3. " [3] ,LUT3 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 2. " [2] ,LUT2 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 1. " [1] ,LUT1 collision status toggle" "Not toggled,Toggled" bitfld.long 0x0C 0. " [0] ,LUT0 collision status toggle" "Not toggled,Toggled" line.long 0x10 "STATUS_COL2,EPDC LUT Collision Status" bitfld.long 0x10 31. " LUT63_COL_STS ,LUT63 collision status" "No collision,Collision" bitfld.long 0x10 30. " [62] ,LUT62 collision status" "No collision,Collision" newline bitfld.long 0x10 29. " [61] ,LUT61 collision status" "No collision,Collision" bitfld.long 0x10 28. " [60] ,LUT60 collision status" "No collision,Collision" newline bitfld.long 0x10 27. " [59] ,LUT59 collision status" "No collision,Collision" bitfld.long 0x10 26. " [58] ,LUT58 collision status" "No collision,Collision" newline bitfld.long 0x10 25. " [57] ,LUT57 collision status" "No collision,Collision" bitfld.long 0x10 24. " [56] ,LUT56 collision status" "No collision,Collision" newline bitfld.long 0x10 23. " [55] ,LUT55 collision status" "No collision,Collision" bitfld.long 0x10 22. " [54] ,LUT54 collision status" "No collision,Collision" newline bitfld.long 0x10 21. " [53] ,LUT53 collision status" "No collision,Collision" bitfld.long 0x10 20. " [52] ,LUT52 collision status" "No collision,Collision" newline bitfld.long 0x10 19. " [51] ,LUT51 collision status" "No collision,Collision" bitfld.long 0x10 18. " [50] ,LUT50 collision status" "No collision,Collision" newline bitfld.long 0x10 17. " [49] ,LUT49 collision status" "No collision,Collision" bitfld.long 0x10 16. " [48] ,LUT48 collision status" "No collision,Collision" newline bitfld.long 0x10 15. " [47] ,LUT47 collision status" "No collision,Collision" bitfld.long 0x10 14. " [46] ,LUT46 collision status" "No collision,Collision" newline bitfld.long 0x10 13. " [45] ,LUT45 collision status" "No collision,Collision" bitfld.long 0x10 12. " [44] ,LUT44 collision status" "No collision,Collision" newline bitfld.long 0x10 11. " [43] ,LUT43 collision status" "No collision,Collision" bitfld.long 0x10 10. " [42] ,LUT42 collision status" "No collision,Collision" newline bitfld.long 0x10 9. " [41] ,LUT41 collision status" "No collision,Collision" bitfld.long 0x10 8. " [40] ,LUT40 collision status" "No collision,Collision" newline bitfld.long 0x10 7. " [39] ,LUT39 collision status" "No collision,Collision" bitfld.long 0x10 6. " [38] ,LUT38 collision status" "No collision,Collision" newline bitfld.long 0x10 5. " [37] ,LUT37 collision status" "No collision,Collision" bitfld.long 0x10 4. " [36] ,LUT36 collision status" "No collision,Collision" newline bitfld.long 0x10 3. " [35] ,LUT35 collision status" "No collision,Collision" bitfld.long 0x10 2. " [34] ,LUT34 collision status" "No collision,Collision" newline bitfld.long 0x10 1. " [33] ,LUT33 collision status" "No collision,Collision" bitfld.long 0x10 0. " [32] ,LUT32 collision status" "No collision,Collision" line.long 0x14 "STATUS_COL2_SET,EPDC LUT Collision Status Set" bitfld.long 0x14 31. " LUTN_COL_STS ,LUT63 collision status set" "No effect,Set" bitfld.long 0x14 30. " [62] ,LUT62 collision status set" "No effect,Set" newline bitfld.long 0x14 29. " [61] ,LUT61 collision status set" "No effect,Set" bitfld.long 0x14 28. " [60] ,LUT60 collision status set" "No effect,Set" newline bitfld.long 0x14 27. " [59] ,LUT59 collision status set" "No effect,Set" bitfld.long 0x14 26. " [58] ,LUT58 collision status set" "No effect,Set" newline bitfld.long 0x14 25. " [57] ,LUT57 collision status set" "No effect,Set" bitfld.long 0x14 24. " [56] ,LUT56 collision status set" "No effect,Set" newline bitfld.long 0x14 23. " [55] ,LUT55 collision status set" "No effect,Set" bitfld.long 0x14 22. " [54] ,LUT54 collision status set" "No effect,Set" newline bitfld.long 0x14 21. " [53] ,LUT53 collision status set" "No effect,Set" bitfld.long 0x14 20. " [52] ,LUT52 collision status set" "No effect,Set" newline bitfld.long 0x14 19. " [51] ,LUT51 collision status set" "No effect,Set" bitfld.long 0x14 18. " [50] ,LUT50 collision status set" "No effect,Set" newline bitfld.long 0x14 17. " [49] ,LUT49 collision status set" "No effect,Set" bitfld.long 0x14 16. " [48] ,LUT48 collision status set" "No effect,Set" newline bitfld.long 0x14 15. " [47] ,LUT47 collision status set" "No effect,Set" bitfld.long 0x14 14. " [46] ,LUT46 collision status set" "No effect,Set" newline bitfld.long 0x14 13. " [45] ,LUT45 collision status set" "No effect,Set" bitfld.long 0x14 12. " [44] ,LUT44 collision status set" "No effect,Set" newline bitfld.long 0x14 11. " [43] ,LUT43 collision status set" "No effect,Set" bitfld.long 0x14 10. " [42] ,LUT42 collision status set" "No effect,Set" newline bitfld.long 0x14 9. " [41] ,LUT41 collision status set" "No effect,Set" bitfld.long 0x14 8. " [40] ,LUT40 collision status set" "No effect,Set" newline bitfld.long 0x14 7. " [39] ,LUT39 collision status set" "No effect,Set" bitfld.long 0x14 6. " [38] ,LUT38 collision status set" "No effect,Set" newline bitfld.long 0x14 5. " [37] ,LUT37 collision status set" "No effect,Set" bitfld.long 0x14 4. " [36] ,LUT36 collision status set" "No effect,Set" newline bitfld.long 0x14 3. " [35] ,LUT35 collision status set" "No effect,Set" bitfld.long 0x14 2. " [34] ,LUT34 collision status set" "No effect,Set" newline bitfld.long 0x14 1. " [33] ,LUT33 collision status set" "No effect,Set" bitfld.long 0x14 0. " [32] ,LUT32 collision status set" "No effect,Set" line.long 0x18 "STATUS_COL2_CLR,EPDC LUT Collision status Clear" bitfld.long 0x18 31. " LUTN_COL_STS ,LUT63 collision status clear" "No effect,Clear" bitfld.long 0x18 30. " [62] ,LUT62 collision status clear" "No effect,Clear" newline bitfld.long 0x18 29. " [61] ,LUT61 collision status clear" "No effect,Clear" bitfld.long 0x18 28. " [60] ,LUT60 collision status clear" "No effect,Clear" newline bitfld.long 0x18 27. " [59] ,LUT59 collision status clear" "No effect,Clear" bitfld.long 0x18 26. " [58] ,LUT58 collision status clear" "No effect,Clear" newline bitfld.long 0x18 25. " [57] ,LUT57 collision status clear" "No effect,Clear" bitfld.long 0x18 24. " [56] ,LUT56 collision status clear" "No effect,Clear" newline bitfld.long 0x18 23. " [55] ,LUT55 collision status clear" "No effect,Clear" bitfld.long 0x18 22. " [54] ,LUT54 collision status clear" "No effect,Clear" newline bitfld.long 0x18 21. " [53] ,LUT53 collision status clear" "No effect,Clear" bitfld.long 0x18 20. " [52] ,LUT52 collision status clear" "No effect,Clear" newline bitfld.long 0x18 19. " [51] ,LUT51 collision Status clear" "No effect,Clear" bitfld.long 0x18 18. " [50] ,LUT50 collision status clear" "No effect,Clear" newline bitfld.long 0x18 17. " [49] ,LUT49 collision status clear" "No effect,Clear" bitfld.long 0x18 16. " [48] ,LUT48 collision status clear" "No effect,Clear" newline bitfld.long 0x18 15. " [47] ,LUT47 collision status clear" "No effect,Clear" bitfld.long 0x18 14. " [46] ,LUT46 collision status clear" "No effect,Clear" newline bitfld.long 0x18 13. " [45] ,LUT45 collision status clear" "No effect,Clear" bitfld.long 0x18 12. " [44] ,LUT44 collision status clear" "No effect,Clear" newline bitfld.long 0x18 11. " [43] ,LUT43 collision status clear" "No effect,Clear" bitfld.long 0x18 10. " [42] ,LUT42 collision status clear" "No effect,Clear" newline bitfld.long 0x18 9. " [41] ,LUT41 collision status clear" "No effect,Clear" bitfld.long 0x18 8. " [40] ,LUT40 collision status clear" "No effect,Clear" newline bitfld.long 0x18 7. " [39] ,LUT39 collision status clear" "No effect,Clear" bitfld.long 0x18 6. " [38] ,LUT38 collision status clear" "No effect,Clear" newline bitfld.long 0x18 5. " [37] ,LUT37 collision status clear" "No effect,Clear" bitfld.long 0x18 4. " [36] ,LUT36 collision status clear" "No effect,Clear" newline bitfld.long 0x18 3. " [35] ,LUT35 collision status clear" "No effect,Clear" bitfld.long 0x18 2. " [34] ,LUT34 collision status clear" "No effect,Clear" newline bitfld.long 0x18 1. " [33] ,LUT33 collision status clear" "No effect,Clear" bitfld.long 0x18 0. " [32] ,LUT32 collision status clear" "No effect,Clear" line.long 0x1C "STATUS_COL2_TOG,EPDC LUT Collision Status Toggle" bitfld.long 0x1C 31. " LUTN_COL_STS ,LUT63 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 30. " [62] ,LUT62 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 29. " [61] ,LUT61 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 28. " [60] ,LUT60 collision status Toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 27. " [59] ,LUT59 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 26. " [58] ,LUT58 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 25. " [57] ,LUT57 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 24. " [56] ,LUT56 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 23. " [55] ,LUT55 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 22. " [54] ,LUT54 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 21. " [53] ,LUT53 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 20. " [52] ,LUT52 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 19. " [51] ,LUT51 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 18. " [50] ,LUT50 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 17. " [49] ,LUT49 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 16. " [48] ,LUT48 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 15. " [47] ,LUT47 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 14. " [46] ,LUT46 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 13. " [45] ,LUT45 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 12. " [44] ,LUT44 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 11. " [43] ,LUT43 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 10. " [42] ,LUT42 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 9. " [41] ,LUT41 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 8. " [40] ,LUT40 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 7. " [39] ,LUT39 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 6. " [38] ,LUT38 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 5. " [37] ,LUT37 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 4. " [36] ,LUT36 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 3. " [35] ,LUT35 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 2. " [34] ,LUT34 collision status toggle" "Not toggled,Toggled" newline bitfld.long 0x1C 1. " [33] ,LUT33 collision status toggle" "Not toggled,Toggled" bitfld.long 0x1C 0. " [32] ,LUT32 collision status toggle" "Not toggled,Toggled" group.long 0x4A0++0x0F line.long 0x00 "STATUS,EPDC General Status Register" bitfld.long 0x00 20. " HIST_CP4 ,Existing bitmap pixels fully contained within the HIST16 (4-bit grayscale) histogram" "Not contained,Contained" bitfld.long 0x00 19. " HIST_CP3 ,Existing bitmap pixels fully contained within the HIST8 (3-bit grayscale) histogram" "Not contained,Contained" newline bitfld.long 0x00 18. " HIST_CP2 ,Existing bitmap pixels fully contained within the HIST4 (2-bit grayscale) histogram" "Not contained,Contained" bitfld.long 0x00 17. " HIST_CP1 ,Existing bitmap pixels fully contained within the HIST2 (black/white) histogram" "Not contained,Contained" newline bitfld.long 0x00 16. " HIST_CP0 ,Existing bitmap pixels fully contained within the HIST1 (single color) histogram" "Not contained,Contained" bitfld.long 0x00 12. " HIST_NP4 ,Processed bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "Not contained,Contained" newline bitfld.long 0x00 11. " HIST_NP3 ,Processed bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "Not contained,Contained" bitfld.long 0x00 10. " HIST_NP2 ,Processed bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "Not contained,Contained" newline bitfld.long 0x00 9. " HIST_NP1 ,Processed bitmap pixels were fully contained within the HIST2 (black/white) histogram" "Not contained,Contained" bitfld.long 0x00 8. " HIST_NP0 ,Processed bitmap pixels were fully contained within the HIST1 (single color) histogram" "Not contained,Contained" newline rbitfld.long 0x00 2. " LUTS_UNDERRUN ,Status of LUT fill" "Completed all,Not enough time" rbitfld.long 0x00 1. " LUTS_BUSY ,Status of LUTs" "Not busy,Busy" newline rbitfld.long 0x00 0. " WB_BUSY ,Working buffer process" "Not busy,Busy" line.long 0x04 "STATUS_SET,EPDC General Status Set Register" bitfld.long 0x04 20. " HIST_CP4 ,Existing bitmap pixels fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Set" bitfld.long 0x04 19. " HIST_CP3 ,Existing bitmap pixels fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Set" newline bitfld.long 0x04 18. " HIST_CP2 ,Existing bitmap pixels fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Set" bitfld.long 0x04 17. " HIST_CP1 ,Existing bitmap pixels fully contained within the HIST2 (black/white) histogram" "No effect,Set" newline bitfld.long 0x04 16. " HIST_CP0 ,Existing bitmap pixels fully contained within the HIST1 (single color) histogram" "No effect,Set" bitfld.long 0x04 12. " HIST_NP4 ,Processed bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Set" newline bitfld.long 0x04 11. " HIST_NP3 ,Processed bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Set" bitfld.long 0x04 10. " HIST_NP2 ,Processed bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Set" newline bitfld.long 0x04 9. " HIST_NP1 ,Processed bitmap pixels were fully contained within the HIST2 (black/white) histogram" "No effect,Set" bitfld.long 0x04 8. " HIST_N0 ,Processed bitmap pixels were fully contained within the HIST1 (single color) histogram" "No effect,Set" newline rbitfld.long 0x04 2. " LUTS_UNDERRUN ,Status of LUT fill" "Completed all,Not enough time" rbitfld.long 0x04 1. " LUTS_BUSY ,Status of LUTs" "Not busy,Busy" newline rbitfld.long 0x04 0. " WB_BUSY ,Working buffer process" "Not busy,Busy" line.long 0x08 "STATUS_CLR,EPDC General Status Clear Register" bitfld.long 0x08 20. " HIST_CP4 ,Existing bitmap pixels fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Clear" bitfld.long 0x08 19. " HIST_CP3 ,Existing bitmap pixels fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Clear" newline bitfld.long 0x08 18. " HIST_CP2 ,Existing bitmap pixels fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Clear" bitfld.long 0x08 17. " HIST_CP1 ,Existing bitmap pixels fully contained within the HIST2 (black/white) histogram" "No effect,Clear" newline bitfld.long 0x08 16. " HIST_CP0 ,Existing bitmap pixels fully contained within the HIST1 (single color) histogram" "No effect,Clear" bitfld.long 0x08 12. " HIST_NP4 ,Processed bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Clear" newline bitfld.long 0x08 11. " HIST_NP3 ,Processed bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Clear" bitfld.long 0x08 10. " HIST_NP2 ,Processed bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Clear" newline bitfld.long 0x08 9. " HIST_NP1 ,Processed bitmap pixels were fully contained within the HIST2 (black/white) histogram" "No effect,Clear" bitfld.long 0x08 8. " HIST_N0 ,Processed bitmap pixels were fully contained within the HIST1 (single color) histogram" "No effect,Clear" newline rbitfld.long 0x08 2. " LUTS_UNDERRUN ,Status of LUT fill" "Completed all,Not enough time" rbitfld.long 0x08 1. " LUTS_BUSY ,Status of LUTs" "Not busy,Busy" newline rbitfld.long 0x08 0. " WB_BUSY ,Working buffer process" "Not busy,Busy" line.long 0x0C "STATUS_TOG,EPDC General Status Toggle Register" bitfld.long 0x0C 20. " HIST_CP4 ,Existing bitmap pixels fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Toggled" bitfld.long 0x0C 19. " HIST_CP3 ,Existing bitmap pixels fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Toggled" newline bitfld.long 0x0C 18. " HIST_CP2 ,Existing bitmap pixels fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Toggled" bitfld.long 0x0C 17. " HIST_CP1 ,Existing bitmap pixels fully contained within the HIST2 (black/white) histogram" "No effect,Toggled" newline bitfld.long 0x0C 16. " HIST_CP0 ,Existing bitmap pixels fully contained within the HIST1 (single color) histogram" "No effect,Toggled" bitfld.long 0x0C 12. " HIST_NP4 ,Processed bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "No effect,Toggled" newline bitfld.long 0x0C 11. " HIST_NP3 ,Processed bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "No effect,Toggled" bitfld.long 0x0C 10. " HIST_NP2 ,Processed bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "No effect,Toggled" newline bitfld.long 0x0C 9. " HIST_NP1 ,Processed bitmap pixels were fully contained within the HIST2 (black/white) histogram" "No effect,Toggled" bitfld.long 0x0C 8. " HIST_N0 ,Processed bitmap pixels were fully contained within the HIST1 (single color) histogram" "No effect,Toggled" newline rbitfld.long 0x0C 2. " LUTS_UNDERRUN ,Status of LUT fill" "Completed all,Not enough time" rbitfld.long 0x0C 1. " LUTS_BUSY ,Status of LUTs" "Not busy,Busy" newline rbitfld.long 0x0C 0. " WB_BUSY ,Working buffer process" "Not busy,Busy" rgroup.long 0x4C0++0x03 line.long 0x00 "UPD_COL_CORD,EPDC Collision Region Co-ordinate" hexmask.long.word 0x00 16.--28. 1. " YCORD ,Y co-ordinate for collision region of the latest completed update" hexmask.long.word 0x00 0.--12. 1. " XCORD ,X co-ordinate for collision region of the latest completed update" rgroup.long 0x4E0++0x03 line.long 0x00 "UPD_COL_SIZE,EPDC Collision Region Size" hexmask.long.word 0x00 16.--28. 1. " HEIGHT ,Height (in pixels)" hexmask.long.word 0x00 0.--12. 1. " WIDTH ,Width (in pixels)" group.long 0x600++0x03 line.long 0x00 "HIST1_PARAM,1-level Histogram Parameter Register" bitfld.long 0x00 0.--4. " VALUE0 ,Value for 1-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x610++0x03 line.long 0x00 "HIST2_PARAM,2-level Histogram Parameter Register" bitfld.long 0x00 8.--12. " VALUE1 ,White value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE0 ,Black value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x620++0x03 line.long 0x00 "HIST4_PARAM,4-level Histogram Parameter Register" bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 (White) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x630++0x03 line.long 0x00 "HIST8_PARAM0,8-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x640++0x03 line.long 0x00 "HIST8_PARAM1,8-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--28. " VALUE7 ,GRAY7 (White) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE6 ,GRAY6 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " VALUE5 ,GRAY5 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE4 ,GRAY4 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x650++0x03 line.long 0x00 "HIST16_PARAM0,16-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x660++0x03 line.long 0x00 "HIST16_PARAM1,16-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--28. " VALUE7 ,GRAY7 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE6 ,GRAY6 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " VALUE5 ,GRAY5 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE4 ,GRAY4 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x670++0x03 line.long 0x00 "HIST16_PARAM2,16-level Histogram Parameter 2 Register" bitfld.long 0x00 24.--28. " VALUE11 ,GRAY11 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE10 ,GRAY10 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " VALUE9 ,GRAY9 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE8 ,GRAY8 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x680++0x03 line.long 0x00 "HIST16_PARAM3,16-level Histogram Parameter 3 Register" bitfld.long 0x00 24.--28. " VALUE15 ,GRAY15 (White) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " VALUE14 ,GRAY14 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " VALUE13 ,GRAY13 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " VALUE12 ,GRAY12 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x700++0x0F line.long 0x00 "GPIO,EPDC General Purpose I/O Debug register" rbitfld.long 0x00 8. " PWRSTAT ,IPP_EPDC_PWRSTAT input" "Low,High" bitfld.long 0x00 7. " PWRWAKE ,IPP_EPDC_PWRWAKE output" "Low,High" newline bitfld.long 0x00 6. " PWRCOM ,IPP_EPDC_PWRCOM output" "Low,High" bitfld.long 0x00 5. " PWRCTRL3 ,IPP_EPDC_PWRCTRL[3] output" "Low,High" newline bitfld.long 0x00 4. " PWRCTRL2 ,IPP_EPDC_PWRCTRL[2] output" "Low,High" bitfld.long 0x00 3. " PWRCTRL1 ,IPP_EPDC_PWRCTRL[1] output" "Low,High" newline bitfld.long 0x00 2. " PWRCTRL0 ,IPP_EPDC_PWRCTRL[0] output" "Low,High" bitfld.long 0x00 1. " BDR1 ,IPP_EPDC_BDR[1] output" "Low,High" newline bitfld.long 0x00 0. " BDR0 ,IPP_EPDC_BDR[0] output" "Low,High" line.long 0x04 "GPIO_SET,EPDC General Purpose I/O Debug Set register" bitfld.long 0x04 8. " PWRSTAT ,IPP_EPDC_PWRSTAT input" "No effect,Set" bitfld.long 0x04 7. " PWRWAKE ,IPP_EPDC_PWRWAKE output" "No effect,Set" newline bitfld.long 0x04 6. " PWRCOM ,IPP_EPDC_PWRCOM output" "No effect,Set" bitfld.long 0x04 5. " PWRCTRL3 ,IPP_EPDC_PWRCTRL[3] output" "No effect,Set" newline bitfld.long 0x04 4. " PWRCTRL2 ,IPP_EPDC_PWRCTRL[2] output" "No effect,Set" bitfld.long 0x04 3. " PWRCTRL1 ,IPP_EPDC_PWRCTRL[1] output" "No effect,Set" newline bitfld.long 0x04 2. " PWRCTRL0 ,IPP_EPDC_PWRCTRL[0] output" "No effect,Set" bitfld.long 0x04 1. " BDR1 ,IPP_EPDC_BDR[1] output" "No effect,Set" newline bitfld.long 0x04 0. " BDR0 ,IPP_EPDC_BDR[0] output" "No effect,Set" line.long 0x08 "GPIO_CLR,EPDC General Purpose I/O Debug Clear register" bitfld.long 0x08 8. " PWRSTAT ,IPP_EPDC_PWRSTAT input" "No effect,Clear" bitfld.long 0x08 7. " PWRWAKE ,IPP_EPDC_PWRWAKE output" "No effect,Clear" newline bitfld.long 0x08 6. " PWRCOM ,IPP_EPDC_PWRCOM output" "No effect,Clear" bitfld.long 0x08 5. " PWRCTRL3 ,IPP_EPDC_PWRCTRL[3] output" "No effect,Clear" newline bitfld.long 0x08 4. " PWRCTRL2 ,IPP_EPDC_PWRCTRL[2] output" "No effect,Clear" bitfld.long 0x08 3. " PWRCTRL1 ,IPP_EPDC_PWRCTRL[1] output" "No effect,Clear" newline bitfld.long 0x08 2. " PWRCTRL0 ,IPP_EPDC_PWRCTRL[0] output" "No effect,Clear" bitfld.long 0x08 1. " BDR1 ,IPP_EPDC_BDR[1] output" "No effect,Clear" newline bitfld.long 0x08 0. " BDR0 ,IPP_EPDC_BDR[0] output" "No effect,Clear" line.long 0x0C "GPIO_TOG,EPDC General Purpose I/O Debug Toggle register" bitfld.long 0x0C 8. " PWRSTAT ,IPP_EPDC_PWRSTAT input" "Not toggled,Toggled" bitfld.long 0x0C 7. " PWRWAKE ,IPP_EPDC_PWRWAKE output" "Not toggled,Toggled" newline bitfld.long 0x0C 6. " PWRCOM ,IPP_EPDC_PWRCOM output" "Not toggled,Toggled" bitfld.long 0x0C 5. " PWRCTRL3 ,IPP_EPDC_PWRCTRL[3] output" "Not toggled,Toggled" newline bitfld.long 0x0C 4. " PWRCTRL2 ,IPP_EPDC_PWRCTRL[2] output" "Not toggled,Toggled" bitfld.long 0x0C 3. " PWRCTRL1 ,IPP_EPDC_PWRCTRL[1] output" "Not toggled,Toggled" newline bitfld.long 0x0C 2. " PWRCTRL0 ,IPP_EPDC_PWRCTRL[0] output" "Not toggled,Toggled" bitfld.long 0x0C 1. " BDR1 ,IPP_EPDC_BDR[1] output" "Not toggled,Toggled" newline bitfld.long 0x0C 0. " BDR0 ,IPP_EPDC_BDR[0] output" "Not toggled,Toggled" group.long 0x7F0++0x03 line.long 0x00 "VERSION,EPDC Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" newline hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0x800++0x03 line.long 0x00 "PIGEON_0 _0,Panel Interface Signal Generator Register 0 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x800+0x10)++0x03 line.long 0x00 "PIGEON_0 _1,Panel Interface Signal Generator Register 0 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x800+0x20)++0x03 line.long 0x00 "PIGEON_0 _2,Panel Interface Signal Generator Register 0 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0x840++0x03 line.long 0x00 "PIGEON_1 _0,Panel Interface Signal Generator Register 1 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x840+0x10)++0x03 line.long 0x00 "PIGEON_1 _1,Panel Interface Signal Generator Register 1 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x840+0x20)++0x03 line.long 0x00 "PIGEON_1 _2,Panel Interface Signal Generator Register 1 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0x880++0x03 line.long 0x00 "PIGEON_2 _0,Panel Interface Signal Generator Register 2 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x880+0x10)++0x03 line.long 0x00 "PIGEON_2 _1,Panel Interface Signal Generator Register 2 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x880+0x20)++0x03 line.long 0x00 "PIGEON_2 _2,Panel Interface Signal Generator Register 2 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0x8C0++0x03 line.long 0x00 "PIGEON_3 _0,Panel Interface Signal Generator Register 3 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x8C0+0x10)++0x03 line.long 0x00 "PIGEON_3 _1,Panel Interface Signal Generator Register 3 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x8C0+0x20)++0x03 line.long 0x00 "PIGEON_3 _2,Panel Interface Signal Generator Register 3 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0x900++0x03 line.long 0x00 "PIGEON_4 _0,Panel Interface Signal Generator Register 4 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x900+0x10)++0x03 line.long 0x00 "PIGEON_4 _1,Panel Interface Signal Generator Register 4 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x900+0x20)++0x03 line.long 0x00 "PIGEON_4 _2,Panel Interface Signal Generator Register 4 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0x940++0x03 line.long 0x00 "PIGEON_5 _0,Panel Interface Signal Generator Register 5 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x940+0x10)++0x03 line.long 0x00 "PIGEON_5 _1,Panel Interface Signal Generator Register 5 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x940+0x20)++0x03 line.long 0x00 "PIGEON_5 _2,Panel Interface Signal Generator Register 5 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0x980++0x03 line.long 0x00 "PIGEON_6 _0,Panel Interface Signal Generator Register 6 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x980+0x10)++0x03 line.long 0x00 "PIGEON_6 _1,Panel Interface Signal Generator Register 6 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x980+0x20)++0x03 line.long 0x00 "PIGEON_6 _2,Panel Interface Signal Generator Register 6 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0x9C0++0x03 line.long 0x00 "PIGEON_7 _0,Panel Interface Signal Generator Register 7 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0x9C0+0x10)++0x03 line.long 0x00 "PIGEON_7 _1,Panel Interface Signal Generator Register 7 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0x9C0+0x20)++0x03 line.long 0x00 "PIGEON_7 _2,Panel Interface Signal Generator Register 7 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0xA00++0x03 line.long 0x00 "PIGEON_8 _0,Panel Interface Signal Generator Register 8 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xA00+0x10)++0x03 line.long 0x00 "PIGEON_8 _1,Panel Interface Signal Generator Register 8 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xA00+0x20)++0x03 line.long 0x00 "PIGEON_8 _2,Panel Interface Signal Generator Register 8 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0xA40++0x03 line.long 0x00 "PIGEON_9 _0,Panel Interface Signal Generator Register 9 _0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xA40+0x10)++0x03 line.long 0x00 "PIGEON_9 _1,Panel Interface Signal Generator Register 9 _1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xA40+0x20)++0x03 line.long 0x00 "PIGEON_9 _2,Panel Interface Signal Generator Register 9 _2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0xA80++0x03 line.long 0x00 "PIGEON_10_0,Panel Interface Signal Generator Register 10_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xA80+0x10)++0x03 line.long 0x00 "PIGEON_10_1,Panel Interface Signal Generator Register 10_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xA80+0x20)++0x03 line.long 0x00 "PIGEON_10_2,Panel Interface Signal Generator Register 10_2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0xAC0++0x03 line.long 0x00 "PIGEON_11_0,Panel Interface Signal Generator Register 11_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xAC0+0x10)++0x03 line.long 0x00 "PIGEON_11_1,Panel Interface Signal Generator Register 11_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xAC0+0x20)++0x03 line.long 0x00 "PIGEON_11_2,Panel Interface Signal Generator Register 11_2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0xB00++0x03 line.long 0x00 "PIGEON_12_0,Panel Interface Signal Generator Register 12_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xB00+0x10)++0x03 line.long 0x00 "PIGEON_12_1,Panel Interface Signal Generator Register 12_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xB00+0x20)++0x03 line.long 0x00 "PIGEON_12_2,Panel Interface Signal Generator Register 12_2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0xB40++0x03 line.long 0x00 "PIGEON_13_0,Panel Interface Signal Generator Register 13_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xB40+0x10)++0x03 line.long 0x00 "PIGEON_13_1,Panel Interface Signal Generator Register 13_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xB40+0x20)++0x03 line.long 0x00 "PIGEON_13_2,Panel Interface Signal Generator Register 13_2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0xB80++0x03 line.long 0x00 "PIGEON_14_0,Panel Interface Signal Generator Register 14_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xB80+0x10)++0x03 line.long 0x00 "PIGEON_14_1,Panel Interface Signal Generator Register 14_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xB80+0x20)++0x03 line.long 0x00 "PIGEON_14_2,Panel Interface Signal Generator Register 14_2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0xBC0++0x03 line.long 0x00 "PIGEON_15_0,Panel Interface Signal Generator Register 15_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xBC0+0x10)++0x03 line.long 0x00 "PIGEON_15_1,Panel Interface Signal Generator Register 15_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xBC0+0x20)++0x03 line.long 0x00 "PIGEON_15_2,Panel Interface Signal Generator Register 15_2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." group.long 0xC00++0x03 line.long 0x00 "PIGEON_16_0,Panel Interface Signal Generator Register 16_0" hexmask.long.byte 0x00 24.--31. 1. " STATE_MASK ,Select any combination of scan states as reference point for local counter to start ticking" hexmask.long.word 0x00 12.--23. 1. " MASK_CNT ,This value matches to global counter selected" newline bitfld.long 0x00 8.--11. " MASK_CNT_SEL ,Select global counters as mask condition" "HSTATE_CNT,HSTATE_CYCLE,VSTATE_CNT,VSTATE_CYCLE,FRAME_CNT,FRAME_CYCLE,HCNT,VCNT,?..." bitfld.long 0x00 4.--7. " OFFSET ,Offset on pclk unit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2.--3. " INC_SEL ,Event to increment local counter" "PCLK,LINE,FRAME,SIG_ANOTHER" bitfld.long 0x00 1. " POL ,Polarity of signal output" "Active high,Active low" newline bitfld.long 0x00 0. " EN ,Enable pigeon mode on this signal" "Disabled,Enabled" group.long (0xC00+0x10)++0x03 line.long 0x00 "PIGEON_16_1,Panel Interface Signal Generator Register 16_1" hexmask.long.word 0x00 16.--31. 1. " CLR_CNT ,Deassert signal output when counter match this value" hexmask.long.word 0x00 0.--15. 1. " SET_CNT ,Assert signal output when counter match this value" group.long (0xC00+0x20)++0x03 line.long 0x00 "PIGEON_16_2,Panel Interface Signal Generator Register 16_2" bitfld.long 0x00 4.--8. " SIG_ANOTHER ,Select another signal for logic operation or as mask or counter tick event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " SIG_LOGIC ,Logic operation with another signal" "Disabled,AND,OR,MASK,?..." width 0x0B tree.end tree "EPIT (Enhanced Periodic Interrupt Timer)" tree "EPIT 1" base ad:0x020D0000 width 12. group.long 0x00++0x0F line.long 0x00 "EPIT1_CR,Control register" bitfld.long 0x00 24.--25. " CLKSRC ,Select clock source" "Off,Peripheral,High-freq,Low-freq" bitfld.long 0x00 22.--23. " OM ,EPIT output mode" "EPIT,Toggle,Clear,Set" bitfld.long 0x00 21. " STOPEN ,Operation of the EPIT during stop mode" "Disabled,Enabled" bitfld.long 0x00 19. " WAITEN ,Operation of the EPIT during wait mode" "Disabled,Enabled" newline bitfld.long 0x00 18. " DBGEN ,Operation of the EPIT during debug mode" "Inactive,Active" bitfld.long 0x00 17. " IOVW ,Counter data when the modulus register is written" "Not overwritten,Overwritten" eventfld.long 0x00 16. " SWR ,Software reset" "Out of,Undergoing" hexmask.long.word 0x00 4.--15. 1. " PRESCALAR ,Prescaler value by which the clock is divided before it goes to the counter" newline bitfld.long 0x00 3. " RLD ,Counter reload control" "Free-running,Set-and-forget" bitfld.long 0x00 2. " OCIEN ,Output compare interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENMOD ,EPIT enable mode" "Previous value,Loaded value" bitfld.long 0x00 0. " EN ,EPIT counter" "Disabled,Enabled" line.long 0x04 "EPIT1_SR,Status register" eventfld.long 0x04 0. " OCIF ,Output compare interrupt flag" "Not occurred,Occurred" line.long 0x08 "EPIT1_LR,Load register" line.long 0x0C "EPIT1_CMPR,Compare register" rgroup.long 0x10++0x03 line.long 0x00 "EPIT1_CNR,Counter register" width 0x0B tree.end tree "EPIT 2" base ad:0x020D4000 width 12. group.long 0x00++0x0F line.long 0x00 "EPIT2_CR,Control register" bitfld.long 0x00 24.--25. " CLKSRC ,Select clock source" "Off,Peripheral,High-freq,Low-freq" bitfld.long 0x00 22.--23. " OM ,EPIT output mode" "EPIT,Toggle,Clear,Set" bitfld.long 0x00 21. " STOPEN ,Operation of the EPIT during stop mode" "Disabled,Enabled" bitfld.long 0x00 19. " WAITEN ,Operation of the EPIT during wait mode" "Disabled,Enabled" newline bitfld.long 0x00 18. " DBGEN ,Operation of the EPIT during debug mode" "Inactive,Active" bitfld.long 0x00 17. " IOVW ,Counter data when the modulus register is written" "Not overwritten,Overwritten" eventfld.long 0x00 16. " SWR ,Software reset" "Out of,Undergoing" hexmask.long.word 0x00 4.--15. 1. " PRESCALAR ,Prescaler value by which the clock is divided before it goes to the counter" newline bitfld.long 0x00 3. " RLD ,Counter reload control" "Free-running,Set-and-forget" bitfld.long 0x00 2. " OCIEN ,Output compare interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENMOD ,EPIT enable mode" "Previous value,Loaded value" bitfld.long 0x00 0. " EN ,EPIT counter" "Disabled,Enabled" line.long 0x04 "EPIT2_SR,Status register" eventfld.long 0x04 0. " OCIF ,Output compare interrupt flag" "Not occurred,Occurred" line.long 0x08 "EPIT2_LR,Load register" line.long 0x0C "EPIT2_CMPR,Compare register" rgroup.long 0x10++0x03 line.long 0x00 "EPIT2_CNR,Counter register" width 0x0B tree.end tree.end tree "GPC (Global Power Controller)" tree "GPC" base ad:0x020DC000 width 8. group.long 0x00++0x17 line.long 0x00 "CNTR,GPC Interface control register" bitfld.long 0x00 22. " L2_PGE ,L2 Cache Power Gate" "Disabled,Enabled" bitfld.long 0x00 21. " GPCIRQM ,GPC interrupt/event masking" "Not masked,Masked" bitfld.long 0x00 18. " VADC_EXT_PWD_N ,VADC power down" "Power down,Power up" newline bitfld.long 0x00 17. " VADC_ANALOG_OFF ,The analog power to VADC" "Available,Not available" bitfld.long 0x00 5. " DISPLAY_PUP_REQ ,Display Power Up request" "Not requested,Requested" bitfld.long 0x00 4. " DISPLAY_PDN_REQ ,Display Power Down request" "Not requested,Requested" newline bitfld.long 0x00 3. " MEGA_PUP_REQ ,MEGA domain power up request" "Not requested,Requested" bitfld.long 0x00 2. " MEGA_PDN_REQ ,MEGA domain power down request" "Not requested,Requested" bitfld.long 0x00 1. " GPU_VPU_PUP_REQ ,GPU Power Up request" "Not requested,Requested" line.long 0x04 "PGR,GPC Power Gating Register" bitfld.long 0x04 29.--30. " DRCIC ,Debug ref cir in mux control" "ccm_cosr_1_clk_in,ccm_cosr_2_clk_in,?..." line.long 0x08 "IMR1,IRQ masking register 1" bitfld.long 0x08 31. " IRQ[63] ,Masking of IRQ 63" "Not masked,Masked" bitfld.long 0x08 30. " [62] ,Masking of IRQ 62" "Not masked,Masked" bitfld.long 0x08 29. " [61] ,Masking of IRQ 61" "Not masked,Masked" bitfld.long 0x08 28. " [60] ,Masking of IRQ 60" "Not masked,Masked" newline bitfld.long 0x08 27. " [59] ,Masking of IRQ 59" "Not masked,Masked" bitfld.long 0x08 26. " [58] ,Masking of IRQ 58" "Not masked,Masked" bitfld.long 0x08 25. " [57] ,Masking of IRQ 57" "Not masked,Masked" bitfld.long 0x08 24. " [56] ,Masking of IRQ 56" "Not masked,Masked" newline bitfld.long 0x08 23. " [55] ,Masking of IRQ 55" "Not masked,Masked" bitfld.long 0x08 22. " [54] ,Masking of IRQ 54" "Not masked,Masked" bitfld.long 0x08 21. " [53] ,Masking of IRQ 53" "Not masked,Masked" bitfld.long 0x08 20. " [52] ,Masking of IRQ 52" "Not masked,Masked" newline bitfld.long 0x08 19. " [51] ,Masking of IRQ 51" "Not masked,Masked" bitfld.long 0x08 18. " [50] ,Masking of IRQ 50" "Not masked,Masked" bitfld.long 0x08 17. " [49] ,Masking of IRQ 49" "Not masked,Masked" bitfld.long 0x08 16. " [48] ,Masking of IRQ 48" "Not masked,Masked" newline bitfld.long 0x08 15. " [47] ,Masking of IRQ 47" "Not masked,Masked" bitfld.long 0x08 14. " [46] ,Masking of IRQ 46" "Not masked,Masked" bitfld.long 0x08 13. " [45] ,Masking of IRQ 45" "Not masked,Masked" bitfld.long 0x08 12. " [44] ,Masking of IRQ 44" "Not masked,Masked" newline bitfld.long 0x08 11. " [43] ,Masking of IRQ 43" "Not masked,Masked" bitfld.long 0x08 10. " [42] ,Masking of IRQ 42" "Not masked,Masked" bitfld.long 0x08 9. " [41] ,Masking of IRQ 41" "Not masked,Masked" bitfld.long 0x08 8. " [40] ,Masking of IRQ 40" "Not masked,Masked" newline bitfld.long 0x08 7. " [39] ,Masking of IRQ 39" "Not masked,Masked" bitfld.long 0x08 6. " [38] ,Masking of IRQ 38" "Not masked,Masked" bitfld.long 0x08 5. " [37] ,Masking of IRQ 37" "Not masked,Masked" bitfld.long 0x08 4. " [36] ,Masking of IRQ 36" "Not masked,Masked" newline bitfld.long 0x08 3. " [35] ,Masking of IRQ 35" "Not masked,Masked" bitfld.long 0x08 2. " [34] ,Masking of IRQ 34" "Not masked,Masked" bitfld.long 0x08 1. " [33] ,Masking of IRQ 33" "Not masked,Masked" bitfld.long 0x08 0. " [32] ,Masking of IRQ 32" "Not masked,Masked" line.long 0x0C "IMR2,IRQ masking register 2" bitfld.long 0x0C 31. " [95] ,Masking of IRQ 95" "Not masked,Masked" bitfld.long 0x0C 30. " [94] ,Masking of IRQ 94" "Not masked,Masked" bitfld.long 0x0C 29. " [93] ,Masking of IRQ 93" "Not masked,Masked" bitfld.long 0x0C 28. " [92] ,Masking of IRQ 92" "Not masked,Masked" newline bitfld.long 0x0C 27. " [91] ,Masking of IRQ 91" "Not masked,Masked" bitfld.long 0x0C 26. " [90] ,Masking of IRQ 90" "Not masked,Masked" bitfld.long 0x0C 25. " [89] ,Masking of IRQ 89" "Not masked,Masked" bitfld.long 0x0C 24. " [88] ,Masking of IRQ 88" "Not masked,Masked" newline bitfld.long 0x0C 23. " [87] ,Masking of IRQ 87" "Not masked,Masked" bitfld.long 0x0C 22. " [86] ,Masking of IRQ 86" "Not masked,Masked" bitfld.long 0x0C 21. " [85] ,Masking of IRQ 85" "Not masked,Masked" bitfld.long 0x0C 20. " [84] ,Masking of IRQ 84" "Not masked,Masked" newline bitfld.long 0x0C 19. " [83] ,Masking of IRQ 83" "Not masked,Masked" bitfld.long 0x0C 18. " [82] ,Masking of IRQ 82" "Not masked,Masked" bitfld.long 0x0C 17. " [81] ,Masking of IRQ 81" "Not masked,Masked" bitfld.long 0x0C 16. " [80] ,Masking of IRQ 80" "Not masked,Masked" newline bitfld.long 0x0C 15. " [79] ,Masking of IRQ 79" "Not masked,Masked" bitfld.long 0x0C 14. " [78] ,Masking of IRQ 78" "Not masked,Masked" bitfld.long 0x0C 13. " [77] ,Masking of IRQ 77" "Not masked,Masked" bitfld.long 0x0C 12. " [76] ,Masking of IRQ 76" "Not masked,Masked" newline bitfld.long 0x0C 11. " [75] ,Masking of IRQ 75" "Not masked,Masked" bitfld.long 0x0C 10. " [74] ,Masking of IRQ 74" "Not masked,Masked" bitfld.long 0x0C 9. " [73] ,Masking of IRQ 73" "Not masked,Masked" bitfld.long 0x0C 8. " [72] ,Masking of IRQ 72" "Not masked,Masked" newline bitfld.long 0x0C 7. " [71] ,Masking of IRQ 71" "Not masked,Masked" bitfld.long 0x0C 6. " [70] ,Masking of IRQ 70" "Not masked,Masked" bitfld.long 0x0C 5. " [69] ,Masking of IRQ 69" "Not masked,Masked" bitfld.long 0x0C 4. " [68] ,Masking of IRQ 68" "Not masked,Masked" newline bitfld.long 0x0C 3. " [67] ,Masking of IRQ 67" "Not masked,Masked" bitfld.long 0x0C 2. " [66] ,Masking of IRQ 66" "Not masked,Masked" bitfld.long 0x0C 1. " [65] ,Masking of IRQ 65" "Not masked,Masked" bitfld.long 0x0C 0. " [64] ,Masking of IRQ 64" "Not masked,Masked" line.long 0x10 "IMR3,IRQ masking register 3" bitfld.long 0x10 31. " [127] ,Masking of IRQ 127" "Not masked,Masked" bitfld.long 0x10 30. " [126] ,Masking of IRQ 126" "Not masked,Masked" bitfld.long 0x10 29. " [125] ,Masking of IRQ 125" "Not masked,Masked" bitfld.long 0x10 28. " [124] ,Masking of IRQ 124" "Not masked,Masked" newline bitfld.long 0x10 27. " [123] ,Masking of IRQ 123" "Not masked,Masked" bitfld.long 0x10 26. " [122] ,Masking of IRQ 122" "Not masked,Masked" bitfld.long 0x10 25. " [121] ,Masking of IRQ 121" "Not masked,Masked" bitfld.long 0x10 24. " [120] ,Masking of IRQ 120" "Not masked,Masked" newline bitfld.long 0x10 23. " [119] ,Masking of IRQ 119" "Not masked,Masked" bitfld.long 0x10 22. " [118] ,Masking of IRQ 118" "Not masked,Masked" bitfld.long 0x10 21. " [117] ,Masking of IRQ 117" "Not masked,Masked" bitfld.long 0x10 20. " [116] ,Masking of IRQ 116" "Not masked,Masked" newline bitfld.long 0x10 19. " [115 ,Masking of IRQ 115" "Not masked,Masked" bitfld.long 0x10 18. " [114] ,Masking of IRQ 114" "Not masked,Masked" bitfld.long 0x10 17. " [113] ,Masking of IRQ 113" "Not masked,Masked" bitfld.long 0x10 16. " [112] ,Masking of IRQ 112" "Not masked,Masked" newline bitfld.long 0x10 15. " [111] ,Masking of IRQ 111" "Not masked,Masked" bitfld.long 0x10 14. " [110] ,Masking of IRQ 110" "Not masked,Masked" bitfld.long 0x10 13. " [109] ,Masking of IRQ 109" "Not masked,Masked" bitfld.long 0x10 12. " [108] ,Masking of IRQ 108" "Not masked,Masked" newline bitfld.long 0x10 11. " [107] ,Masking of IRQ 107" "Not masked,Masked" bitfld.long 0x10 10. " [106] ,Masking of IRQ 106" "Not masked,Masked" bitfld.long 0x10 9. " [105] ,Masking of IRQ 105" "Not masked,Masked" bitfld.long 0x10 8. " [104] ,Masking of IRQ 104" "Not masked,Masked" newline bitfld.long 0x10 7. " [103] ,Masking of IRQ 103" "Not masked,Masked" bitfld.long 0x10 6. " [102] ,Masking of IRQ 102" "Not masked,Masked" bitfld.long 0x10 5. " [101] ,Masking of IRQ 101" "Not masked,Masked" bitfld.long 0x10 4. " [100] ,Masking of IRQ 100" "Not masked,Masked" newline bitfld.long 0x10 3. " [99] ,Masking of IRQ 99" "Not masked,Masked" bitfld.long 0x10 2. " [98] ,Masking of IRQ 98" "Not masked,Masked" bitfld.long 0x10 1. " [97] ,Masking of IRQ 97" "Not masked,Masked" bitfld.long 0x10 0. " [96] ,Masking of IRQ 96" "Not masked,Masked" line.long 0x14 "IMR4,IRQ masking register 4" bitfld.long 0x14 31. " [159] ,Masking of IRQ 159" "Not masked,Masked" bitfld.long 0x14 30. " [158] ,Masking of IRQ 158" "Not masked,Masked" bitfld.long 0x14 29. " [157] ,Masking of IRQ 157" "Not masked,Masked" bitfld.long 0x14 28. " [156] ,Masking of IRQ 156" "Not masked,Masked" newline bitfld.long 0x14 27. " [155] ,Masking of IRQ 155" "Not masked,Masked" bitfld.long 0x14 26. " [154] ,Masking of IRQ 154" "Not masked,Masked" bitfld.long 0x14 25. " [153] ,Masking of IRQ 153" "Not masked,Masked" bitfld.long 0x14 24. " [152] ,Masking of IRQ 152" "Not masked,Masked" newline bitfld.long 0x14 23. " [151] ,Masking of IRQ 151" "Not masked,Masked" bitfld.long 0x14 22. " [150] ,Masking of IRQ 150" "Not masked,Masked" bitfld.long 0x14 21. " [149] ,Masking of IRQ 149" "Not masked,Masked" bitfld.long 0x14 20. " [148] ,Masking of IRQ 148" "Not masked,Masked" newline bitfld.long 0x14 19. " [147] ,Masking of IRQ 147" "Not masked,Masked" bitfld.long 0x14 18. " [146] ,Masking of IRQ 146" "Not masked,Masked" bitfld.long 0x14 17. " [145] ,Masking of IRQ 145" "Not masked,Masked" bitfld.long 0x14 16. " [144] ,Masking of IRQ 144" "Not masked,Masked" newline bitfld.long 0x14 15. " [143] ,Masking of IRQ 143" "Not masked,Masked" bitfld.long 0x14 14. " [142] ,Masking of IRQ 142" "Not masked,Masked" bitfld.long 0x14 13. " [141] ,Masking of IRQ 141" "Not masked,Masked" bitfld.long 0x14 12. " [140] ,Masking of IRQ 140" "Not masked,Masked" newline bitfld.long 0x14 11. " [139] ,Masking of IRQ 139" "Not masked,Masked" bitfld.long 0x14 10. " [138] ,Masking of IRQ 138" "Not masked,Masked" bitfld.long 0x14 9. " [137] ,Masking of IRQ 137" "Not masked,Masked" bitfld.long 0x14 8. " [136] ,Masking of IRQ 136" "Not masked,Masked" newline bitfld.long 0x14 7. " [135] ,Masking of IRQ 135" "Not masked,Masked" bitfld.long 0x14 6. " [134] ,Masking of IRQ 134" "Not masked,Masked" bitfld.long 0x14 5. " [133] ,Masking of IRQ 133" "Not masked,Masked" bitfld.long 0x14 4. " [132] ,Masking of IRQ 132" "Not masked,Masked" newline bitfld.long 0x14 3. " [131] ,Masking of IRQ 131" "Not masked,Masked" bitfld.long 0x14 2. " [130] ,Masking of IRQ 130" "Not masked,Masked" bitfld.long 0x14 1. " [129] ,Masking of IRQ 129" "Not masked,Masked" bitfld.long 0x14 0. " [128] ,Masking of IRQ 128" "Not masked,Masked" rgroup.long 0x18++0x0F line.long 0x00 "ISR1,IRQ status resister 1" bitfld.long 0x00 31. " IRQ[63] ,Status of IRQ 63" "Low,High" bitfld.long 0x00 30. " [62] ,Status of IRQ 62" "Low,High" bitfld.long 0x00 29. " [61] ,Status of IRQ 61" "Low,High" bitfld.long 0x00 28. " [60] ,Status of IRQ 60" "Low,High" newline bitfld.long 0x00 27. " [59] ,Status of IRQ 59" "Low,High" bitfld.long 0x00 26. " [58] ,Status of IRQ 58" "Low,High" bitfld.long 0x00 25. " [57] ,Status of IRQ 57" "Low,High" bitfld.long 0x00 24. " [56] ,Status of IRQ 56" "Low,High" newline bitfld.long 0x00 23. " [55] ,Status of IRQ 55" "Low,High" bitfld.long 0x00 22. " [54] ,Status of IRQ 54" "Low,High" bitfld.long 0x00 21. " [53] ,Status of IRQ 53" "Low,High" bitfld.long 0x00 20. " [52] ,Status of IRQ 52" "Low,High" newline bitfld.long 0x00 19. " [51] ,Status of IRQ 51" "Low,High" bitfld.long 0x00 18. " [50] ,Status of IRQ 50" "Low,High" bitfld.long 0x00 17. " [49] ,Status of IRQ 49" "Low,High" bitfld.long 0x00 16. " [48] ,Status of IRQ 48" "Low,High" newline bitfld.long 0x00 15. " [47] ,Status of IRQ 47" "Low,High" bitfld.long 0x00 14. " [46] ,Status of IRQ 46" "Low,High" bitfld.long 0x00 13. " [45] ,Status of IRQ 45" "Low,High" bitfld.long 0x00 12. " [44] ,Status of IRQ 44" "Low,High" newline bitfld.long 0x00 11. " [43] ,Status of IRQ 43" "Low,High" bitfld.long 0x00 10. " [42] ,Status of IRQ 42" "Low,High" bitfld.long 0x00 9. " [41] ,Status of IRQ 41" "Low,High" bitfld.long 0x00 8. " [40] ,Status of IRQ 40" "Low,High" newline bitfld.long 0x00 7. " [39] ,Status of IRQ 39" "Low,High" bitfld.long 0x00 6. " [38] ,Status of IRQ 38" "Low,High" bitfld.long 0x00 5. " [37] ,Status of IRQ 37" "Low,High" bitfld.long 0x00 4. " [36] ,Status of IRQ 36" "Low,High" newline bitfld.long 0x00 3. " [35] ,Status of IRQ 35" "Low,High" bitfld.long 0x00 2. " [34] ,Status of IRQ 34" "Low,High" bitfld.long 0x00 1. " [33] ,Status of IRQ 33" "Low,High" bitfld.long 0x00 0. " [32] ,Status of IRQ 32" "Low,High" line.long 0x04 "ISR2,IRQ status resister 2" bitfld.long 0x04 31. " [95] ,Status of IRQ 95" "Low,High" bitfld.long 0x04 30. " [94] ,Status of IRQ 94" "Low,High" bitfld.long 0x04 29. " [93] ,Status of IRQ 93" "Low,High" bitfld.long 0x04 28. " [92] ,Status of IRQ 92" "Low,High" newline bitfld.long 0x04 27. " [91] ,Status of IRQ 91" "Low,High" bitfld.long 0x04 26. " [90] ,Status of IRQ 90" "Low,High" bitfld.long 0x04 25. " [89] ,Status of IRQ 89" "Low,High" bitfld.long 0x04 24. " [88] ,Status of IRQ 88" "Low,High" newline bitfld.long 0x04 23. " [87] ,Status of IRQ 87" "Low,High" bitfld.long 0x04 22. " [86] ,Status of IRQ 86" "Low,High" bitfld.long 0x04 21. " [85] ,Status of IRQ 85" "Low,High" bitfld.long 0x04 20. " [84] ,Status of IRQ 84" "Low,High" newline bitfld.long 0x04 19. " [83] ,Status of IRQ 83" "Low,High" bitfld.long 0x04 18. " [82] ,Status of IRQ 82" "Low,High" bitfld.long 0x04 17. " [81] ,Status of IRQ 81" "Low,High" bitfld.long 0x04 16. " [80] ,Status of IRQ 80" "Low,High" newline bitfld.long 0x04 15. " [79] ,Status of IRQ 79" "Low,High" bitfld.long 0x04 14. " [78] ,Status of IRQ 78" "Low,High" bitfld.long 0x04 13. " [77] ,Status of IRQ 77" "Low,High" bitfld.long 0x04 12. " [76] ,Status of IRQ 76" "Low,High" newline bitfld.long 0x04 11. " [75] ,Status of IRQ 75" "Low,High" bitfld.long 0x04 10. " [74] ,Status of IRQ 74" "Low,High" bitfld.long 0x04 9. " [73] ,Status of IRQ 73" "Low,High" bitfld.long 0x04 8. " [72] ,Status of IRQ 72" "Low,High" newline bitfld.long 0x04 7. " [71] ,Status of IRQ 71" "Low,High" bitfld.long 0x04 6. " [70] ,Status of IRQ 70" "Low,High" bitfld.long 0x04 5. " [69] ,Status of IRQ 69" "Low,High" bitfld.long 0x04 4. " [68] ,Status of IRQ 68" "Low,High" newline bitfld.long 0x04 3. " [67] ,Status of IRQ 67" "Low,High" bitfld.long 0x04 2. " [66] ,Status of IRQ 66" "Low,High" bitfld.long 0x04 1. " [65] ,Status of IRQ 65" "Low,High" bitfld.long 0x04 0. " [64] ,Status of IRQ 64" "Low,High" line.long 0x08 "ISR3,IRQ status resister 3" bitfld.long 0x08 31. " [127] ,Status of IRQ 127" "Low,High" bitfld.long 0x08 30. " [126] ,Status of IRQ 126" "Low,High" bitfld.long 0x08 29. " [125] ,Status of IRQ 125" "Low,High" bitfld.long 0x08 28. " [124] ,Status of IRQ 124" "Low,High" newline bitfld.long 0x08 27. " [123] ,Status of IRQ 123" "Low,High" bitfld.long 0x08 26. " [122] ,Status of IRQ 122" "Low,High" bitfld.long 0x08 25. " [121] ,Status of IRQ 121" "Low,High" bitfld.long 0x08 24. " [120] ,Status of IRQ 120" "Low,High" newline bitfld.long 0x08 23. " [119] ,Status of IRQ 119" "Low,High" bitfld.long 0x08 22. " [118] ,Status of IRQ 118" "Low,High" bitfld.long 0x08 21. " [117] ,Status of IRQ 117" "Low,High" bitfld.long 0x08 20. " [116] ,Status of IRQ 116" "Low,High" newline bitfld.long 0x08 19. " [115] ,Status of IRQ 115" "Low,High" bitfld.long 0x08 18. " [114] ,Status of IRQ 114" "Low,High" bitfld.long 0x08 17. " [113] ,Status of IRQ 113" "Low,High" bitfld.long 0x08 16. " [112] ,Status of IRQ 112" "Low,High" newline bitfld.long 0x08 15. " [111] ,Status of IRQ 111" "Low,High" bitfld.long 0x08 14. " [110] ,Status of IRQ 110" "Low,High" bitfld.long 0x08 13. " [109] ,Status of IRQ 109" "Low,High" bitfld.long 0x08 12. " [108] ,Status of IRQ 108" "Low,High" newline bitfld.long 0x08 11. " [107] ,Status of IRQ 107" "Low,High" bitfld.long 0x08 10. " [106] ,Status of IRQ 106" "Low,High" bitfld.long 0x08 9. " [105] ,Status of IRQ 105" "Low,High" bitfld.long 0x08 8. " [104] ,Status of IRQ 104" "Low,High" newline bitfld.long 0x08 7. " [103] ,Status of IRQ 103" "Low,High" bitfld.long 0x08 6. " [102] ,Status of IRQ 102" "Low,High" bitfld.long 0x08 5. " [101] ,Status of IRQ 101" "Low,High" bitfld.long 0x08 4. " [100] ,Status of IRQ 100" "Low,High" newline bitfld.long 0x08 3. " [99] ,Status of IRQ 99" "Low,High" bitfld.long 0x08 2. " [98] ,Status of IRQ 98" "Low,High" bitfld.long 0x08 1. " [97] ,Status of IRQ 97" "Low,High" bitfld.long 0x08 0. " [96] ,Status of IRQ 96" "Low,High" line.long 0x0C "ISR4,IRQ status resister 4r" bitfld.long 0x0C 31. " [159] ,Status of IRQ 159" "Low,High" bitfld.long 0x0C 30. " [158] ,Status of IRQ 158" "Low,High" bitfld.long 0x0C 29. " [157] ,Status of IRQ 157" "Low,High" bitfld.long 0x0C 28. " [156] ,Status of IRQ 156" "Low,High" newline bitfld.long 0x0C 27. " [155] ,Status of IRQ 155" "Low,High" bitfld.long 0x0C 26. " [154] ,Status of IRQ 154" "Low,High" bitfld.long 0x0C 25. " [153] ,Status of IRQ 153" "Low,High" bitfld.long 0x0C 24. " [152] ,Status of IRQ 152" "Low,High" newline bitfld.long 0x0C 23. " [151] ,Status of IRQ 151" "Low,High" bitfld.long 0x0C 22. " [150] ,Status of IRQ 150" "Low,High" bitfld.long 0x0C 21. " [149] ,Status of IRQ 149" "Low,High" bitfld.long 0x0C 20. " [148] ,Status of IRQ 148" "Low,High" newline bitfld.long 0x0C 19. " [147] ,Status of IRQ 147" "Low,High" bitfld.long 0x0C 18. " [146] ,Status of IRQ 146" "Low,High" bitfld.long 0x0C 17. " [145] ,Status of IRQ 145" "Low,High" bitfld.long 0x0C 16. " [144] ,Status of IRQ 144" "Low,High" newline bitfld.long 0x0C 15. " [143] ,Status of IRQ 143" "Low,High" bitfld.long 0x0C 14. " [142] ,Status of IRQ 142" "Low,High" bitfld.long 0x0C 13. " [141] ,Status of IRQ 141" "Low,High" bitfld.long 0x0C 12. " [140] ,Status of IRQ 140" "Low,High" newline bitfld.long 0x0C 11. " [139] ,Status of IRQ 139" "Low,High" bitfld.long 0x0C 10. " [138] ,Status of IRQ 138" "Low,High" bitfld.long 0x0C 9. " [137] ,Status of IRQ 137" "Low,High" bitfld.long 0x0C 8. " [136] ,Status of IRQ 136" "Low,High" newline bitfld.long 0x0C 7. " [135] ,Status of IRQ 135" "Low,High" bitfld.long 0x0C 6. " [134] ,Status of IRQ 134" "Low,High" bitfld.long 0x0C 5. " [133] ,Status of IRQ 133" "Low,High" bitfld.long 0x0C 4. " [132] ,Status of IRQ 132" "Low,High" newline bitfld.long 0x0C 3. " [131] ,Status of IRQ 131" "Low,High" bitfld.long 0x0C 2. " [130] ,Status of IRQ 130" "Low,High" bitfld.long 0x0C 1. " [129] ,Status of IRQ 129" "Low,High" bitfld.long 0x0C 0. " [128] ,Status of IRQ 128" "Low,High" width 0x0B tree.end tree "PGC" base ad:0x020DC220 width 20. group.long 0x00++0xF line.long 0x00 "PGC_MEGA_CTRL,PGC Control Register" bitfld.long 0x00 0. " PCR ,Power control" "No switch off,Switch off" line.long 0x04 "PGC_MEGA_PUPSCR,Power Up Sequence Control Register" bitfld.long 0x04 8.--13. " SW2ISO ,Number of clocks before negating isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW ,Number of clocks before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PGC_MEGA_PDNSCR,Pull Down Sequence Control Register" bitfld.long 0x08 8.--13. " ISO2SW ,Number of clocks before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " ISO ,Number of clocks before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "PGC_MEGA_SR,Power Gating Controller Status Register" eventfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" group.long 0x20++0xF line.long 0x00 "PGC_DISPLAY_CTRL,PGC Control Register" bitfld.long 0x00 0. " PCR ,Power control" "No switch off,Switch off" line.long 0x04 "PGC_DISPLAY_PUPSCR,Power Up Sequence Control Register" bitfld.long 0x04 8.--13. " SW2ISO ,Number of clocks before negating isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW ,Number of clocks before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PGC_DISPLAY_PDNSCR,Pull Down Sequence Control Register" bitfld.long 0x08 8.--13. " ISO2SW ,Number of clocks before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " ISO ,Number of clocks before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "PGC_DISPLAY_SR,Power Gating Controller Status Register" eventfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" group.long 0x60++0xF line.long 0x00 "PGC_GPU_CTRL,PGC Control Register" bitfld.long 0x00 0. " PCR ,Power control" "No switch off,Switch off" line.long 0x04 "PGC_GPU_PUPSCR,Power Up Sequence Control Register" bitfld.long 0x04 8.--13. " SW2ISO ,Number of clocks before negating isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW ,Number of clocks before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PGC_GPU_PDNSCR,Pull Down Sequence Control Register" bitfld.long 0x08 8.--13. " ISO2SW ,Number of clocks before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " ISO ,Number of clocks before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "PGC_GPU_SR,Power Gating Controller Status Register" eventfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" group.long 0xA0++0xF line.long 0x00 "PGC_CPU_CTRL,PGC Control Register" bitfld.long 0x00 0. " PCR ,Power control" "No switch off,Switch off" line.long 0x04 "PGC_CPU_PUPSCR,Power Up Sequence Control Register" bitfld.long 0x04 8.--13. " SW2ISO ,Number of clocks before negating isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " SW ,Number of clocks before asserting switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PGC_CPU_PDNSCR,Pull Down Sequence Control Register" bitfld.long 0x08 8.--13. " ISO2SW ,Number of clocks before negating switch_b" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " ISO ,Number of clocks before asserting isolation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "PGC_CPU_SR,Power Gating Controller Status Register" eventfld.long 0x0C 0. " PSR ,Power status" "Not powered down,Powered down" width 0x0B tree.end tree.end tree "GPIO (General Purpose Input/Output)" tree "GPIO 1" base ad:0x0209C000 width 19. group.long 0x00++0x07 line.long 0x00 "GPIO1_DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High" bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High" bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" newline bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" newline bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" newline bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" newline bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" newline bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" newline bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GPIO1_GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" newline bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" newline bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" newline bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" newline bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" newline bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" newline bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "GPIO1_PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "Low,High" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "Low,High" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "Low,High" newline bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "Low,High" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "Low,High" newline bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "Low,High" newline bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "Low,High" newline bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "Low,High" newline bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "Low,High" newline bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "GPIO1_ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" newline bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" newline bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" newline bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" newline bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" newline bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "GPIO1_ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" newline bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" newline bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" newline bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" newline bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" newline bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "GPIO1_IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" newline bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" newline bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" newline bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" newline bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" newline bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" newline bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" newline bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" newline bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" newline bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" newline bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" line.long 0x0C "GPIO1_ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" newline eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" newline eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" newline eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" newline eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" newline eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "GPIO1_EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" newline bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" newline bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" newline bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" newline bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" newline bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" newline bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" newline bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" newline bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" newline bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" newline bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 0x0B tree.end tree "GPIO 2" base ad:0x020A0000 width 19. group.long 0x00++0x07 line.long 0x00 "GPIO2_DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High" bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High" bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" newline bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" newline bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" newline bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" newline bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" newline bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" newline bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GPIO2_GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" newline bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" newline bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" newline bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" newline bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" newline bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" newline bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "GPIO2_PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "Low,High" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "Low,High" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "Low,High" newline bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "Low,High" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "Low,High" newline bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "Low,High" newline bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "Low,High" newline bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "Low,High" newline bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "Low,High" newline bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "GPIO2_ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" newline bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" newline bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" newline bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" newline bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" newline bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "GPIO2_ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" newline bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" newline bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" newline bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" newline bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" newline bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "GPIO2_IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" newline bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" newline bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" newline bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" newline bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" newline bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" newline bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" newline bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" newline bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" newline bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" newline bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" line.long 0x0C "GPIO2_ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" newline eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" newline eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" newline eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" newline eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" newline eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "GPIO2_EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" newline bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" newline bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" newline bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" newline bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" newline bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" newline bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" newline bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" newline bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" newline bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" newline bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 0x0B tree.end tree "GPIO 3" base ad:0x020A4000 width 19. group.long 0x00++0x07 line.long 0x00 "GPIO3_DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High" bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High" bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" newline bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" newline bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" newline bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" newline bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" newline bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" newline bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GPIO3_GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" newline bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" newline bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" newline bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" newline bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" newline bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" newline bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "GPIO3_PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "Low,High" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "Low,High" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "Low,High" newline bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "Low,High" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "Low,High" newline bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "Low,High" newline bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "Low,High" newline bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "Low,High" newline bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "Low,High" newline bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "GPIO3_ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" newline bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" newline bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" newline bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" newline bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" newline bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "GPIO3_ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" newline bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" newline bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" newline bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" newline bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" newline bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "GPIO3_IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" newline bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" newline bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" newline bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" newline bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" newline bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" newline bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" newline bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" newline bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" newline bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" newline bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" line.long 0x0C "GPIO3_ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" newline eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" newline eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" newline eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" newline eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" newline eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "GPIO3_EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" newline bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" newline bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" newline bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" newline bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" newline bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" newline bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" newline bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" newline bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" newline bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" newline bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 0x0B tree.end tree "GPIO 4" base ad:0x020A8000 width 19. group.long 0x00++0x07 line.long 0x00 "GPIO4_DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High" bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High" bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" newline bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" newline bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" newline bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" newline bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" newline bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" newline bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GPIO4_GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" newline bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" newline bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" newline bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" newline bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" newline bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" newline bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "GPIO4_PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "Low,High" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "Low,High" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "Low,High" newline bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "Low,High" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "Low,High" newline bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "Low,High" newline bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "Low,High" newline bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "Low,High" newline bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "Low,High" newline bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "GPIO4_ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" newline bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" newline bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" newline bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" newline bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" newline bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "GPIO4_ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" newline bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" newline bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" newline bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" newline bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" newline bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "GPIO4_IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" newline bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" newline bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" newline bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" newline bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" newline bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" newline bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" newline bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" newline bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" newline bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" newline bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" line.long 0x0C "GPIO4_ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" newline eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" newline eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" newline eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" newline eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" newline eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "GPIO4_EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" newline bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" newline bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" newline bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" newline bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" newline bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" newline bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" newline bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" newline bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" newline bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" newline bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 0x0B tree.end tree "GPIO 5" base ad:0x020AC000 width 19. group.long 0x00++0x07 line.long 0x00 "GPIO5_DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High" bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High" bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" newline bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" newline bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" newline bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" newline bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" newline bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" newline bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GPIO5_GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" newline bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" newline bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" newline bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" newline bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" newline bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" newline bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "GPIO5_PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "Low,High" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "Low,High" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "Low,High" newline bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "Low,High" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "Low,High" newline bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "Low,High" newline bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "Low,High" newline bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "Low,High" newline bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "Low,High" newline bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "GPIO5_ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" newline bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" newline bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" newline bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" newline bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" newline bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "GPIO5_ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" newline bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" newline bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" newline bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" newline bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" newline bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "GPIO5_IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" newline bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" newline bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" newline bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" newline bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" newline bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" newline bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" newline bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" newline bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" newline bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" newline bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" line.long 0x0C "GPIO5_ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" newline eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" newline eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" newline eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" newline eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" newline eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "GPIO5_EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" newline bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" newline bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" newline bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" newline bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" newline bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" newline bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" newline bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" newline bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" newline bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" newline bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 0x0B tree.end tree "GPIO 6" base ad:0x020B0000 width 19. group.long 0x00++0x07 line.long 0x00 "GPIO6_DR,GPIO Data register" bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High" bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High" bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High" newline bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High" bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High" bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High" newline bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High" bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High" bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High" newline bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High" bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High" bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High" bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High" bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High" newline bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High" bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High" bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High" newline bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High" bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High" bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High" newline bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High" bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High" bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High" bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High" bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High" newline bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High" bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High" bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High" newline bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High" bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High" line.long 0x04 "GPIO6_GDIR,GPIO direction register" bitfld.long 0x04 31. " GDIR31 ,Direction bit 31" "Input,Output" bitfld.long 0x04 30. " GDIR30 ,Direction bit 30" "Input,Output" bitfld.long 0x04 29. " GDIR29 ,Direction bit 29" "Input,Output" newline bitfld.long 0x04 28. " GDIR28 ,Direction bit 28" "Input,Output" bitfld.long 0x04 27. " GDIR27 ,Direction bit 27" "Input,Output" bitfld.long 0x04 26. " GDIR26 ,Direction bit 26" "Input,Output" newline bitfld.long 0x04 25. " GDIR25 ,Direction bit 25" "Input,Output" bitfld.long 0x04 24. " GDIR24 ,Direction bit 24" "Input,Output" bitfld.long 0x04 23. " GDIR23 ,Direction bit 23" "Input,Output" newline bitfld.long 0x04 22. " GDIR22 ,Direction bit 22" "Input,Output" bitfld.long 0x04 21. " GDIR21 ,Direction bit 21" "Input,Output" bitfld.long 0x04 20. " GDIR20 ,Direction bit 20" "Input,Output" newline bitfld.long 0x04 19. " GDIR19 ,Direction bit 19" "Input,Output" bitfld.long 0x04 18. " GDIR18 ,Direction bit 18" "Input,Output" bitfld.long 0x04 17. " GDIR17 ,Direction bit 17" "Input,Output" newline bitfld.long 0x04 16. " GDIR16 ,Direction bit 16" "Input,Output" bitfld.long 0x04 15. " GDIR15 ,Direction bit 15" "Input,Output" bitfld.long 0x04 14. " GDIR14 ,Direction bit 14" "Input,Output" newline bitfld.long 0x04 13. " GDIR13 ,Direction bit 13" "Input,Output" bitfld.long 0x04 12. " GDIR12 ,Direction bit 12" "Input,Output" bitfld.long 0x04 11. " GDIR11 ,Direction bit 11" "Input,Output" newline bitfld.long 0x04 10. " GDIR10 ,Direction bit 10" "Input,Output" bitfld.long 0x04 9. " GDIR9 ,Direction bit 9" "Input,Output" bitfld.long 0x04 8. " GDIR8 ,Direction bit 8" "Input,Output" newline bitfld.long 0x04 7. " GDIR7 ,Direction bit 7" "Input,Output" bitfld.long 0x04 6. " GDIR6 ,Direction bit 6" "Input,Output" bitfld.long 0x04 5. " GDIR5 ,Direction bit 5" "Input,Output" newline bitfld.long 0x04 4. " GDIR4 ,Direction bit 4" "Input,Output" bitfld.long 0x04 3. " GDIR3 ,Direction bit 3" "Input,Output" bitfld.long 0x04 2. " GDIR2 ,Direction bit 2" "Input,Output" newline bitfld.long 0x04 1. " GDIR1 ,Direction bit 1" "Input,Output" bitfld.long 0x04 0. " GDIR0 ,Direction bit 0" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "GPIO6_PSR,GPIO pad status register" bitfld.long 0x00 31. " PSR31 ,Input signal status bit 31" "Low,High" bitfld.long 0x00 30. " PSR30 ,Input signal status bit 30" "Low,High" bitfld.long 0x00 29. " PSR29 ,Input signal status bit 29" "Low,High" newline bitfld.long 0x00 28. " PSR28 ,Input signal status bit 28" "Low,High" bitfld.long 0x00 27. " PSR27 ,Input signal status bit 27" "Low,High" bitfld.long 0x00 26. " PSR26 ,Input signal status bit 26" "Low,High" newline bitfld.long 0x00 25. " PSR25 ,Input signal status bit 25" "Low,High" bitfld.long 0x00 24. " PSR24 ,Input signal status bit 24" "Low,High" bitfld.long 0x00 23. " PSR23 ,Input signal status bit 23" "Low,High" newline bitfld.long 0x00 22. " PSR22 ,Input signal status bit 22" "Low,High" bitfld.long 0x00 21. " PSR21 ,Input signal status bit 21" "Low,High" bitfld.long 0x00 20. " PSR20 ,Input signal status bit 20" "Low,High" newline bitfld.long 0x00 19. " PSR19 ,Input signal status bit 19" "Low,High" bitfld.long 0x00 18. " PSR18 ,Input signal status bit 18" "Low,High" bitfld.long 0x00 17. " PSR17 ,Input signal status bit 17" "Low,High" newline bitfld.long 0x00 16. " PSR16 ,Input signal status bit 16" "Low,High" bitfld.long 0x00 15. " PSR15 ,Input signal status bit 15" "Low,High" bitfld.long 0x00 14. " PSR14 ,Input signal status bit 14" "Low,High" newline bitfld.long 0x00 13. " PSR13 ,Input signal status bit 13" "Low,High" bitfld.long 0x00 12. " PSR12 ,Input signal status bit 12" "Low,High" bitfld.long 0x00 11. " PSR11 ,Input signal status bit 11" "Low,High" newline bitfld.long 0x00 10. " PSR10 ,Input signal status bit 10" "Low,High" bitfld.long 0x00 9. " PSR9 ,Input signal status bit 9" "Low,High" bitfld.long 0x00 8. " PSR8 ,Input signal status bit 8" "Low,High" newline bitfld.long 0x00 7. " PSR7 ,Input signal status bit 7" "Low,High" bitfld.long 0x00 6. " PSR6 ,Input signal status bit 6" "Low,High" bitfld.long 0x00 5. " PSR5 ,Input signal status bit 5" "Low,High" newline bitfld.long 0x00 4. " PSR4 ,Input signal status bit 4" "Low,High" bitfld.long 0x00 3. " PSR3 ,Input signal status bit 3" "Low,High" bitfld.long 0x00 2. " PSR2 ,Input signal status bit 2" "Low,High" newline bitfld.long 0x00 1. " PSR1 ,Input signal status bit 1" "Low,High" bitfld.long 0x00 0. " PSR0 ,Input signal status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "GPIO6_ICR1,GPIO interrupt configuration register1" bitfld.long 0x00 30.--31. " ICR15 ,Active condition of the interrupt function for GPIO interrupt 15" "Low,High,Rising,Falling" bitfld.long 0x00 28.--29. " ICR14 ,Active condition of the interrupt function for GPIO interrupt 14" "Low,High,Rising,Falling" bitfld.long 0x00 26.--27. " ICR13 ,Active condition of the interrupt function for GPIO interrupt 13" "Low,High,Rising,Falling" newline bitfld.long 0x00 24.--25. " ICR12 ,Active condition of the interrupt function for GPIO interrupt 12" "Low,High,Rising,Falling" bitfld.long 0x00 22.--23. " ICR11 ,Active condition of the interrupt function for GPIO interrupt 11" "Low,High,Rising,Falling" bitfld.long 0x00 20.--21. " ICR10 ,Active condition of the interrupt function for GPIO interrupt 10" "Low,High,Rising,Falling" newline bitfld.long 0x00 18.--19. " ICR9 ,Active condition of the interrupt function for GPIO interrupt 9" "Low,High,Rising,Falling" bitfld.long 0x00 16.--17. " ICR8 ,Active condition of the interrupt function for GPIO interrupt 8" "Low,High,Rising,Falling" bitfld.long 0x00 14.--15. " ICR7 ,Active condition of the interrupt function for GPIO interrupt 7" "Low,High,Rising,Falling" newline bitfld.long 0x00 12.--13. " ICR6 ,Active condition of the interrupt function for GPIO interrupt 6" "Low,High,Rising,Falling" bitfld.long 0x00 10.--11. " ICR5 ,Active condition of the interrupt function for GPIO interrupt 5" "Low,High,Rising,Falling" bitfld.long 0x00 8.--9. " ICR4 ,Active condition of the interrupt function for GPIO interrupt 4" "Low,High,Rising,Falling" newline bitfld.long 0x00 6.--7. " ICR3 ,Active condition of the interrupt function for GPIO interrupt 3" "Low,High,Rising,Falling" bitfld.long 0x00 4.--5. " ICR2 ,Active condition of the interrupt function for GPIO interrupt 2" "Low,High,Rising,Falling" bitfld.long 0x00 2.--3. " ICR1 ,Active condition of the interrupt function for GPIO interrupt 1" "Low,High,Rising,Falling" newline bitfld.long 0x00 0.--1. " ICR0 ,Active condition of the interrupt function for GPIO interrupt 0" "Low,High,Rising,Falling" line.long 0x04 "GPIO6_ICR2,GPIO interrupt configuration register2" bitfld.long 0x04 30.--31. " ICR31 ,Active condition of the interrupt function for GPIO interrupt 31" "Low,High,Rising,Falling" bitfld.long 0x04 28.--29. " ICR30 ,Active condition of the interrupt function for GPIO interrupt 30" "Low,High,Rising,Falling" bitfld.long 0x04 26.--27. " ICR29 ,Active condition of the interrupt function for GPIO interrupt 29" "Low,High,Rising,Falling" newline bitfld.long 0x04 24.--25. " ICR28 ,Active condition of the interrupt function for GPIO interrupt 28" "Low,High,Rising,Falling" bitfld.long 0x04 22.--23. " ICR27 ,Active condition of the interrupt function for GPIO interrupt 27" "Low,High,Rising,Falling" bitfld.long 0x04 20.--21. " ICR26 ,Active condition of the interrupt function for GPIO interrupt 26" "Low,High,Rising,Falling" newline bitfld.long 0x04 18.--19. " ICR25 ,Active condition of the interrupt function for GPIO interrupt 25" "Low,High,Rising,Falling" bitfld.long 0x04 16.--17. " ICR24 ,Active condition of the interrupt function for GPIO interrupt 24" "Low,High,Rising,Falling" bitfld.long 0x04 14.--15. " ICR23 ,Active condition of the interrupt function for GPIO interrupt 23" "Low,High,Rising,Falling" newline bitfld.long 0x04 12.--13. " ICR22 ,Active condition of the interrupt function for GPIO interrupt 22" "Low,High,Rising,Falling" bitfld.long 0x04 10.--11. " ICR21 ,Active condition of the interrupt function for GPIO interrupt 21" "Low,High,Rising,Falling" bitfld.long 0x04 8.--9. " ICR20 ,Active condition of the interrupt function for GPIO interrupt 20" "Low,High,Rising,Falling" newline bitfld.long 0x04 6.--7. " ICR19 ,Active condition of the interrupt function for GPIO interrupt 19" "Low,High,Rising,Falling" bitfld.long 0x04 4.--5. " ICR18 ,Active condition of the interrupt function for GPIO interrupt 18" "Low,High,Rising,Falling" bitfld.long 0x04 2.--3. " ICR17 ,Active condition of the interrupt function for GPIO interrupt 17" "Low,High,Rising,Falling" newline bitfld.long 0x04 0.--1. " ICR16 ,Active condition of the interrupt function for GPIO interrupt 16" "Low,High,Rising,Falling" line.long 0x08 "GPIO6_IMR,GPIO interrupt mask register" bitfld.long 0x08 31. " IMR_31 ,Interrupt mask bit 31" "Unmasked,Masked" bitfld.long 0x08 30. " IMR_30 ,Interrupt mask bit 30" "Unmasked,Masked" bitfld.long 0x08 29. " IMR_29 ,Interrupt mask bit 29" "Unmasked,Masked" newline bitfld.long 0x08 28. " IMR_28 ,Interrupt mask bit 28" "Unmasked,Masked" bitfld.long 0x08 27. " IMR_27 ,Interrupt mask bit 27" "Unmasked,Masked" bitfld.long 0x08 26. " IMR_26 ,Interrupt mask bit 26" "Unmasked,Masked" newline bitfld.long 0x08 25. " IMR_25 ,Interrupt mask bit 25" "Unmasked,Masked" bitfld.long 0x08 24. " IMR_24 ,Interrupt mask bit 24" "Unmasked,Masked" bitfld.long 0x08 23. " IMR_23 ,Interrupt mask bit 23" "Unmasked,Masked" newline bitfld.long 0x08 22. " IMR_22 ,Interrupt mask bit 22" "Unmasked,Masked" bitfld.long 0x08 21. " IMR_21 ,Interrupt mask bit 21" "Unmasked,Masked" bitfld.long 0x08 20. " IMR_20 ,Interrupt mask bit 20" "Unmasked,Masked" newline bitfld.long 0x08 19. " IMR_19 ,Interrupt mask bit 19" "Unmasked,Masked" bitfld.long 0x08 18. " IMR_18 ,Interrupt mask bit 18" "Unmasked,Masked" bitfld.long 0x08 17. " IMR_17 ,Interrupt mask bit 17" "Unmasked,Masked" newline bitfld.long 0x08 16. " IMR_16 ,Interrupt mask bit 16" "Unmasked,Masked" bitfld.long 0x08 15. " IMR_15 ,Interrupt mask bit 15" "Unmasked,Masked" bitfld.long 0x08 14. " IMR_14 ,Interrupt mask bit 14" "Unmasked,Masked" newline bitfld.long 0x08 13. " IMR_13 ,Interrupt mask bit 13" "Unmasked,Masked" bitfld.long 0x08 12. " IMR_12 ,Interrupt mask bit 12" "Unmasked,Masked" bitfld.long 0x08 11. " IMR_11 ,Interrupt mask bit 11" "Unmasked,Masked" newline bitfld.long 0x08 10. " IMR_10 ,Interrupt mask bit 10" "Unmasked,Masked" bitfld.long 0x08 9. " IMR_9 ,Interrupt mask bit 9" "Unmasked,Masked" bitfld.long 0x08 8. " IMR_8 ,Interrupt mask bit 8" "Unmasked,Masked" newline bitfld.long 0x08 7. " IMR_7 ,Interrupt mask bit 7" "Unmasked,Masked" bitfld.long 0x08 6. " IMR_6 ,Interrupt mask bit 6" "Unmasked,Masked" bitfld.long 0x08 5. " IMR_5 ,Interrupt mask bit 5" "Unmasked,Masked" newline bitfld.long 0x08 4. " IMR_4 ,Interrupt mask bit 4" "Unmasked,Masked" bitfld.long 0x08 3. " IMR_3 ,Interrupt mask bit 3" "Unmasked,Masked" bitfld.long 0x08 2. " IMR_2 ,Interrupt mask bit 2" "Unmasked,Masked" newline bitfld.long 0x08 1. " IMR_1 ,Interrupt mask bit 1" "Unmasked,Masked" bitfld.long 0x08 0. " IMR_0 ,Interrupt mask bit 0" "Unmasked,Masked" line.long 0x0C "GPIO6_ISR,GPIO interrupt mask register" eventfld.long 0x0C 31. " ISR_31 ,Interrupt status bit 31" "No interrupt,Interrupt" eventfld.long 0x0C 30. " ISR_30 ,Interrupt status bit 30" "No interrupt,Interrupt" eventfld.long 0x0C 29. " ISR_29 ,Interrupt status bit 29" "No interrupt,Interrupt" newline eventfld.long 0x0C 28. " ISR_28 ,Interrupt status bit 28" "No interrupt,Interrupt" eventfld.long 0x0C 27. " ISR_27 ,Interrupt status bit 27" "No interrupt,Interrupt" eventfld.long 0x0C 26. " ISR_26 ,Interrupt status bit 26" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " ISR_25 ,Interrupt status bit 25" "No interrupt,Interrupt" eventfld.long 0x0C 24. " ISR_24 ,Interrupt status bit 24" "No interrupt,Interrupt" eventfld.long 0x0C 23. " ISR_23 ,Interrupt status bit 23" "No interrupt,Interrupt" newline eventfld.long 0x0C 22. " ISR_22 ,Interrupt status bit 22" "No interrupt,Interrupt" eventfld.long 0x0C 21. " ISR_21 ,Interrupt status bit 21" "No interrupt,Interrupt" eventfld.long 0x0C 20. " ISR_20 ,Interrupt status bit 20" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " ISR_19 ,Interrupt status bit 19" "No interrupt,Interrupt" eventfld.long 0x0C 18. " ISR_18 ,Interrupt status bit 18" "No interrupt,Interrupt" eventfld.long 0x0C 17. " ISR_17 ,Interrupt status bit 17" "No interrupt,Interrupt" newline eventfld.long 0x0C 16. " ISR_16 ,Interrupt status bit 16" "No interrupt,Interrupt" eventfld.long 0x0C 15. " ISR_15 ,Interrupt status bit 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " ISR_14 ,Interrupt status bit 14" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " ISR_13 ,Interrupt status bit 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " ISR_12 ,Interrupt status bit 12" "No interrupt,Interrupt" eventfld.long 0x0C 11. " ISR_11 ,Interrupt status bit 11" "No interrupt,Interrupt" newline eventfld.long 0x0C 10. " ISR_10 ,Interrupt status bit 10" "No interrupt,Interrupt" eventfld.long 0x0C 9. " ISR_9 ,Interrupt status bit 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " ISR_8 ,Interrupt status bit 8" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " ISR_7 ,Interrupt status bit 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " ISR_6 ,Interrupt status bit 6" "No interrupt,Interrupt" eventfld.long 0x0C 5. " ISR_5 ,Interrupt status bit 5" "No interrupt,Interrupt" newline eventfld.long 0x0C 4. " ISR_4 ,Interrupt status bit 4" "No interrupt,Interrupt" eventfld.long 0x0C 3. " ISR_3 ,Interrupt status bit 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " ISR_2 ,Interrupt status bit 2" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " ISR_1 ,Interrupt status bit 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " ISR_0 ,Interrupt status bit 0" "No interrupt,Interrupt" line.long 0x10 "GPIO6_EDGE_SEL,GPIO edge select register" bitfld.long 0x10 31. " ES31 ,Edge select bit 31 - overwrite ICR[31]" "Not overwritten,Overwritten" bitfld.long 0x10 30. " ES30 ,Edge select bit 30 - overwrite ICR[30]" "Not overwritten,Overwritten" bitfld.long 0x10 29. " ES29 ,Edge select bit 29 - overwrite ICR[29]" "Not overwritten,Overwritten" newline bitfld.long 0x10 28. " ES28 ,Edge select bit 28 - overwrite ICR[28]" "Not overwritten,Overwritten" bitfld.long 0x10 27. " ES27 ,Edge select bit 27 - overwrite ICR[27]" "Not overwritten,Overwritten" bitfld.long 0x10 26. " ES26 ,Edge select bit 26 - overwrite ICR[26]" "Not overwritten,Overwritten" newline bitfld.long 0x10 25. " ES25 ,Edge select bit 25 - overwrite ICR[25]" "Not overwritten,Overwritten" bitfld.long 0x10 24. " ES24 ,Edge select bit 24 - overwrite ICR[24]" "Not overwritten,Overwritten" bitfld.long 0x10 23. " ES23 ,Edge select bit 23 - overwrite ICR[23]" "Not overwritten,Overwritten" newline bitfld.long 0x10 22. " ES22 ,Edge select bit 22 - overwrite ICR[22]" "Not overwritten,Overwritten" bitfld.long 0x10 21. " ES21 ,Edge select bit 21 - overwrite ICR[21]" "Not overwritten,Overwritten" bitfld.long 0x10 20. " ES20 ,Edge select bit 20 - overwrite ICR[20]" "Not overwritten,Overwritten" newline bitfld.long 0x10 19. " ES19 ,Edge select bit 19 - overwrite ICR[19]" "Not overwritten,Overwritten" bitfld.long 0x10 18. " ES18 ,Edge select bit 18 - overwrite ICR[18]" "Not overwritten,Overwritten" bitfld.long 0x10 17. " ES17 ,Edge select bit 17 - overwrite ICR[17]" "Not overwritten,Overwritten" newline bitfld.long 0x10 16. " ES16 ,Edge select bit 16 - overwrite ICR[16]" "Not overwritten,Overwritten" bitfld.long 0x10 15. " ES15 ,Edge select bit 15 - overwrite ICR[15]" "Not overwritten,Overwritten" bitfld.long 0x10 14. " ES14 ,Edge select bit 14 - overwrite ICR[14]" "Not overwritten,Overwritten" newline bitfld.long 0x10 13. " ES13 ,Edge select bit 13 - overwrite ICR[13]" "Not overwritten,Overwritten" bitfld.long 0x10 12. " ES12 ,Edge select bit 12 - overwrite ICR[12]" "Not overwritten,Overwritten" bitfld.long 0x10 11. " ES11 ,Edge select bit 11 - overwrite ICR[11]" "Not overwritten,Overwritten" newline bitfld.long 0x10 10. " ES10 ,Edge select bit 10 - overwrite ICR[10]" "Not overwritten,Overwritten" bitfld.long 0x10 9. " ES9 ,Edge select bit 9 - overwrite ICR[9]" "Not overwritten,Overwritten" bitfld.long 0x10 8. " ES8 ,Edge select bit 8 - overwrite ICR[8]" "Not overwritten,Overwritten" newline bitfld.long 0x10 7. " ES7 ,Edge select bit 7 - overwrite ICR[7]" "Not overwritten,Overwritten" bitfld.long 0x10 6. " ES6 ,Edge select bit 6 - overwrite ICR[6]" "Not overwritten,Overwritten" bitfld.long 0x10 5. " ES5 ,Edge select bit 5 - overwrite ICR[5]" "Not overwritten,Overwritten" newline bitfld.long 0x10 4. " ES4 ,Edge select bit 4 - overwrite ICR[4]" "Not overwritten,Overwritten" bitfld.long 0x10 3. " ES3 ,Edge select bit 3 - overwrite ICR[3]" "Not overwritten,Overwritten" bitfld.long 0x10 2. " ES2 ,Edge select bit 2 - overwrite ICR[2]" "Not overwritten,Overwritten" newline bitfld.long 0x10 1. " ES1 ,Edge select bit 1 - overwrite ICR[1]" "Not overwritten,Overwritten" bitfld.long 0x10 0. " ES0 ,Edge select bit 0 - overwrite ICR[0]" "Not overwritten,Overwritten" width 0x0B tree.end tree.end tree "GPT (General Purpose Timer)" base ad:0x02098000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "I2C (I2C Controller)" tree "I2C 1" base ad:0x021A0000 width 11. group.word 0x00++0x01 line.word 0x00 "I2C1_IADR,I2C1 Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "I2C1_IFDR,I2C1 Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048" if (((per.w(ad:0x021A0000+0x08)&0x10)==0x00)) group.word 0x08++0x01 line.word 0x00 "I2C1_I2CR,I2C1 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "I2C1_I2CR,I2C1 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " rbitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" endif group.word 0x0C++0x01 line.word 0x00 "I2C1_I2SR,I2C1 Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" textline " " rbitfld.word 0x00 2. " SRW ,Slave read/write" "Slave receive/Master write,Slave transmit/Master receive" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "Acknowledged,No acknowledged" hgroup.word 0x10++0x01 hide.word 0x00 "I2C1_I2DR,I2C Data I/O Register" in width 0x0B tree.end tree "I2C 2" base ad:0x021A4000 width 11. group.word 0x00++0x01 line.word 0x00 "I2C2_IADR,I2C2 Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "I2C2_IFDR,I2C2 Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048" if (((per.w(ad:0x021A4000+0x08)&0x10)==0x00)) group.word 0x08++0x01 line.word 0x00 "I2C2_I2CR,I2C2 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "I2C2_I2CR,I2C2 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " rbitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" endif group.word 0x0C++0x01 line.word 0x00 "I2C2_I2SR,I2C2 Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" textline " " rbitfld.word 0x00 2. " SRW ,Slave read/write" "Slave receive/Master write,Slave transmit/Master receive" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "Acknowledged,No acknowledged" hgroup.word 0x10++0x01 hide.word 0x00 "I2C2_I2DR,I2C Data I/O Register" in width 0x0B tree.end tree "I2C 3" base ad:0x021A8000 width 11. group.word 0x00++0x01 line.word 0x00 "I2C3_IADR,I2C3 Address Register" hexmask.word.byte 0x00 1.--7. 0x02 " ADR ,Slave address" group.word 0x04++0x01 line.word 0x00 "I2C3_IFDR,I2C3 Frequency Divider Register" bitfld.word 0x00 0.--5. " IC ,I2C clock rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048" if (((per.w(ad:0x021A8000+0x08)&0x10)==0x00)) group.word 0x08++0x01 line.word 0x00 "I2C3_I2CR,I2C3 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " bitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "I2C3_I2CR,I2C3 Control Register" bitfld.word 0x00 7. " IEN ,I2C enable" "Disabled,Enabled" bitfld.word 0x00 6. " IIEN ,I2C interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " MSTA ,Master/Slave mode select bit" "Slave,Master" bitfld.word 0x00 4. " MTX ,Transmit/Receive mode select bit" "Receive,Transmit" textline " " rbitfld.word 0x00 3. " TXAK ,Transmit acknowledge enable" "ACK sent,No ACk sent" bitfld.word 0x00 2. " RSTA ,Repeat start enable" "Disabled,Enabled" endif group.word 0x0C++0x01 line.word 0x00 "I2C3_I2SR,I2C3 Status Register" rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed" rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed" rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy" bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost" textline " " rbitfld.word 0x00 2. " SRW ,Slave read/write" "Slave receive/Master write,Slave transmit/Master receive" bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt" rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "Acknowledged,No acknowledged" hgroup.word 0x10++0x01 hide.word 0x00 "I2C3_I2DR,I2C Data I/O Register" in width 0x0B tree.end tree.end tree "IOMUXC (IOMUX Controller)" tree "IOMUXC_SNVS" base ad:0x021C8000 width 30. group.long 0x00++0x27 line.long 0x00 "SW_MUX_CTL_PAD_TAMPER,SW_MUX_CTL_PAD_TAMPER Control Register" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "ALT0_snvs_lp_wrapper_SNVS_TD1,,,,ALT5_gpio6_GPIO[0],?..." line.long 0x04 "SW_MUX_CTL_PAD_PMIC_ON_REQ,SW_MUX_CTL_PAD_PMIC_ON_REQ Control Register" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "ALT0_snvs_lp_wrapper_SNVS_WAKEUP_ALARM,,,,ALT5_gpio6_GPIO[1],?..." line.long 0x08 "SW_MUX_CTL_PAD_PMIC_STBY_REQ,SW_MUX_CTL_PAD_PMIC_STBY_REQ Control Register" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "ALT0_ccm_PMIC_VSTBY_REQ,,,,ALT5_gpio6_GPIO[2],?..." line.long 0x0C "SW_MUX_CTL_PAD_BOOT_MODE0,SW_MUX_CTL_PAD_BOOT_MODE0 Control Register" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "ALT0_src_BOOT_MODE[0],,,,ALT5_gpio6_GPIO[3],?..." line.long 0x10 "SW_MUX_CTL_PAD_BOOT_MODE1,SW_MUX_CTL_PAD_BOOT_MODE1 Control Register" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "ALT0_src_BOOT_MODE[1],,,,ALT5_gpio6_GPIO[4],?..." line.long 0x14 "SW_PAD_CTL_PAD_TAMPER,SW_PAD_CTL_PAD_TAMPER Control Register" rbitfld.long 0x14 22. " LVE ,LVE field" "High voltage,?..." bitfld.long 0x14 16. " HYS ,Hyst enable field" "Disabled,Enabled" newline bitfld.long 0x14 14.--15. " PUS ,Pull up/down config field" "100k Ohm pull down,47k Ohm pull up,100k Ohm pull up,22k Ohm pull up" newline bitfld.long 0x14 13. " PUE ,Pull/keep select field" "Keep,Pull" bitfld.long 0x14 12. " ODE ,Pull/keep enable field" "Disabled,Enabled" newline bitfld.long 0x14 11. " PKE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed field" "50Mhz,100Mhz,150Mhz,200Mhz" newline bitfld.long 0x14 3.--5. " DSE ,Drive strength field" "Disabled,R0,R0/2,R0/3,R0/4,R0/5,R0/6,R0/7" bitfld.long 0x14 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x18 "SW_PAD_CTL_PAD_PMIC_ON_REQ,SW_PAD_CTL_PAD_PMIC_ON_REQ Control Register" rbitfld.long 0x18 22. " LVE ,LVE field" "High voltage,?..." bitfld.long 0x18 16. " HYS ,Hyst enable field" "Disabled,Enabled" newline bitfld.long 0x18 14.--15. " PUS ,Pull up/down config field" "100k Ohm pull down,47k Ohm pull up,100k Ohm pull up,22k Ohm pull up" newline bitfld.long 0x18 13. " PUE ,Pull/keep select field" "Keep,Pull" bitfld.long 0x18 12. " ODE ,Pull/keep enable field" "Disabled,Enabled" newline bitfld.long 0x18 11. " PKE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed field" "50Mhz,100Mhz,150Mhz,200Mhz" newline bitfld.long 0x18 3.--5. " DSE ,Drive strength field" "Disabled,R0,R0/2,R0/3,R0/4,R0/5,R0/6,R0/7" bitfld.long 0x18 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x1C "SW_PAD_CTL_PAD_PMIC_STBY_REQ,SW_PAD_CTL_PAD_PMIC_STBY_REQ Control Register" rbitfld.long 0x1C 22. " LVE ,LVE field" "High voltage,?..." bitfld.long 0x1C 16. " HYS ,Hyst enable field" "Disabled,Enabled" newline bitfld.long 0x1C 14.--15. " PUS ,Pull up/down config field" "100k Ohm pull down,47k Ohm pull up,100k Ohm pull up,22k Ohm pull up" newline bitfld.long 0x1C 13. " PUE ,Pull/keep select field" "Keep,Pull" bitfld.long 0x1C 12. " ODE ,Pull/keep enable field" "Disabled,Enabled" newline bitfld.long 0x1C 11. " PKE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed field" "50Mhz,100Mhz,150Mhz,200Mhz" newline bitfld.long 0x1C 3.--5. " DSE ,Drive strength field" "Disabled,R0,R0/2,R0/3,R0/4,R0/5,R0/6,R0/7" bitfld.long 0x1C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x20 "SW_PAD_CTL_PAD_BOOT,SW_PAD_CTL_PAD_TAMPER Control Register" rbitfld.long 0x20 22. " LVE ,LVE field" "High voltage,?..." bitfld.long 0x20 16. " HYS ,Hyst enable field" "Disabled,Enabled" newline bitfld.long 0x20 14.--15. " PUS ,Pull up/down config field" "100k Ohm pull down,47k Ohm pull up,100k Ohm pull up,22k Ohm pull up" newline bitfld.long 0x20 13. " PUE ,Pull/keep select field" "Keep,Pull" bitfld.long 0x20 12. " ODE ,Pull/keep enable field" "Disabled,Enabled" newline bitfld.long 0x20 11. " PKE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed field" "50Mhz,100Mhz,150Mhz,200Mhz" newline bitfld.long 0x20 3.--5. " DSE ,Drive strength field" "Disabled,R0,R0/2,R0/3,R0/4,R0/5,R0/6,R0/7" bitfld.long 0x20 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x24 "SW_PAD_CTL_PAD_TAMPER,SW_PAD_CTL_PAD_TAMPER Control Register" rbitfld.long 0x24 22. " LVE ,LVE field" "High voltage,?..." bitfld.long 0x24 16. " HYS ,Hyst enable field" "Disabled,Enabled" newline bitfld.long 0x24 14.--15. " PUS ,Pull up/down config field" "100k Ohm pull down,47k Ohm pull up,100k Ohm pull up,22k Ohm pull up" newline bitfld.long 0x24 13. " PUE ,Pull/keep select field" "Keep,Pull" bitfld.long 0x24 12. " ODE ,Pull/keep enable field" "Disabled,Enabled" newline bitfld.long 0x24 11. " PKE ,Open drain enable field" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed field" "50Mhz,100Mhz,150Mhz,200Mhz" newline bitfld.long 0x24 3.--5. " DSE ,Drive strength field" "Disabled,R0,R0/2,R0/3,R0/4,R0/5,R0/6,R0/7" bitfld.long 0x24 0. " SRE ,Slew rate field" "Slow,Fast" width 0x0B tree.end tree "IOMUXC_SNVS_GPR" base ad:0x021C4000 width 6. group.long 0x08++0x07 line.long 0x00 "GPR2,General Purpose 2 Register" bitfld.long 0x00 23. " LOCK_BOOT_MODE_OVERRIDE[1] ,_LOCK_BOOT_MODE_OVERRIDE bit 1" "Not locked,Locked" bitfld.long 0x00 22. " [0] ,LOCK_BOOT_MODE_OVERRIDE bit 0" "Not locked,Locked" newline bitfld.long 0x00 21. " LOCK_FORCE_GPIO6_B4_PRI ,LOCK_FORCE_GPIO6_B4_PRI bit" "Not locked,Locked" newline bitfld.long 0x00 20. " LOCK_FORCE_GPIO6_B3_PRI ,LOCK_FORCE_GPIO6_B3_PRI bit" "Not locked,Locked" newline bitfld.long 0x00 19. " LOCK_FORCE_GPIO6_B2_PRI ,LOCK_FORCE_GPIO6_B2_PRI bit" "Not locked,Locked" newline bitfld.long 0x00 18. " LOCK_FORCE_GPIO6_B1_PRI ,LOCK_FORCE_GPIO6_B1_PRI bit" "Not locked,Locked" newline bitfld.long 0x00 17. " LOCK_FORCE_GPIO6_B0_PRI ,LOCK_FORCE_GPIO6_B0_PRI bit" "Not locked,Locked" newline bitfld.long 0x00 16. " LOCK_BOOT_MODE_OVERRIDE_EN ,LOCK_BOOT_MODE_OVERRIDE_EN bit" "Not locked,Locked" newline bitfld.long 0x00 7. " BOOT_MODE_OVERRIDE[1] ,BOOT_MODE override function 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [0] ,BOOT_MODE override function 0 enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FORCE_GPIO6_B4_PRI ,Force bit 4 of GPIO6 to be its primary function instead of GPIO" "Not force,Forced" newline bitfld.long 0x00 4. " FORCE_GPIO6_B3_PRI ,Force bit 3 of GPIO6 to be its primary function instead of GPIO" "Not force,Forced" newline bitfld.long 0x00 3. " FORCE_GPIO6_B2_PRI ,Force bit 2 of GPIO6 to be its primary function instead of GPIO" "Not force,Forced" newline bitfld.long 0x00 2. " FORCE_GPIO6_B1_PRI ,Force bit 1 of GPIO6 to be its primary function instead of GPIO" "Not force,Forced" newline bitfld.long 0x00 1. " FORCE_GPIO6_B0_PRI ,Force bit 0 of GPIO6 to be its primary function instead of GPIO" "Not force,Forced" newline bitfld.long 0x00 0. " BOOT_MODE_OVERRIDE_EN ,BOOT_MODE override function enable" "Disabled,Enabled" line.long 0x04 "GPR3,General Purpose 3 Register" bitfld.long 0x04 31. " LPSR_MODE_ENABLE ,LPSR mode enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " WAKEUP_REQ_MASK ,Wakeup from GPIO module in SNVS disable" "No,Yes" newline bitfld.long 0x04 0.--1. " POR_PULL_TYPE ,POR_B PAD Control" "0,1,2,3" width 0x0B tree.end tree "IOMUXC_GPR" base ad:0x020E4000 width 10. group.long 0x00++0x18 line.long 0x00 "GPR0,General Purpose 0 Register" bitfld.long 0x00 7. " DMAREQ_MUX_SEL7 ,Selects between two possible sources for SDMA_EVENT[14]" "spdif.drq0_spdif_b,iomux.sdma_ext_events[1]" newline bitfld.long 0x00 5. " DMAREQ_MUX_SEL5 ,Selects between two possible sources for SDMA_EVENT[9]" "ecspi4.ipd_req_cspi_rdma_b,epit2.ipi_int_epit_oc" newline bitfld.long 0x00 4. " DMAREQ_MUX_SEL4 ,Selects between two possible sources for SDMA_EVENT[10]" "ecspi4.ipd_req_cspi_tdma_b,i2c1.ipi_int_b" newline bitfld.long 0x00 3. " DMAREQ_MUX_SEL3 ,Selects between two possible sources for SDMA_EVENT[5]" "ecspi2.ipd_req_cspi_rdma_b,i2c1.ipi_int_b" newline bitfld.long 0x00 2. " DMAREQ_MUX_SEL2 ,Selects between two possible sources for SDMA_EVENT[4]" "ecspi1.ipd_req_cspi_tdma_b,i2c2.ipi_int_b" newline bitfld.long 0x00 1. " DMAREQ_MUX_SEL1 ,Selects between two possible sources for SDMA_EVENT[3]" "ecspi1.ipd_req_cspi_rdma_b,i2c3.ipi_int_b" line.long 0x04 "GPR1,General Purpose 1 Register" bitfld.long 0x04 22. " EXC_MON ,Exclusive monitor response select of illegal command" "OKAY,SLVError" bitfld.long 0x04 16. " ADD_DS ,Setting ADD_DS to 0 will make the output driver of the SD3 pins ~10% stronger at highest drive strength" "Stronger,Normal" newline bitfld.long 0x04 15. " USB_EXP_MODE ,USB exposure mode enable" "Disabled,Enabled" bitfld.long 0x04 12. " GINT ,Global interrupt 0 bit assert" "Not asserted,Asserted" line.long 0x08 "GPR2,General Purpose 2 Register" bitfld.long 0x08 31. " DRAM_CKE_BYPASS ,DRAM CKE bypass select" "MMDC PHY controller,GPR2 bits" newline bitfld.long 0x08 30. " DRAM_CKE1 ,CKE1 bypass value" "0,1" bitfld.long 0x08 29. " DRAM_CKE0 ,CKE0 bypass value" "0,1" newline bitfld.long 0x08 22. " OCRAM_L2_MEM_RET ,Memory enter retention mode" "Non-retention,Retention" newline bitfld.long 0x08 20. " OCRAM_L2_MEM_EN_POWERSAVING ,OCRAM_L2_MEM_EN_POWERSAVING" "0,1" line.long 0x0C "GPR3,General Purpose 3 Register" bitfld.long 0x0C 26. " USDHCX_WR_CACHE_CTL ,Control uSDHCx blocks cacheable attribute of AXI write transactions" "Off,On" newline bitfld.long 0x0C 25. " USDHCX_RD_CACHE_CTL ,Control uSDHCx blocks cacheable attribute of AXI read transactions" "Off,On" newline bitfld.long 0x0C 24. " OCRAM_CTL[3] ,Write address pipeline control bit" "Disabled,Enabled" bitfld.long 0x0C 23. " [2] ,Write data pipeline control bit" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [1] ,Read address pipeline control bit" "Disabled,Enabled" bitfld.long 0x0C 21. " [0] ,Read data wait state control bit" "Disabled,Enabled" newline rbitfld.long 0x0C 20. " OCRAM_STATUS[3] ,Write address pipeline status" "Valid,Changed" rbitfld.long 0x0C 19. " [2] ,Write data pipeline status" "Valid,Changed" newline rbitfld.long 0x0C 18. " [1] ,Read address pipeline status" "Valid,Changed" rbitfld.long 0x0C 17. " [0] ,Read data pipeline status" "Valid,Changed" newline bitfld.long 0x0C 13. " CORE_DBG_ACK_EN ,Mask control of Core debug acknowledge to global debug acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x0C 11. " TZASC1_BOOT_LOCK ,TZASC-1 secure boot lock enable" "Disabled,Enabled" newline rbitfld.long 0x0C 7. " OCRAM_L2_STATUS[3] ,Write address pipeline status" "Valid,Changed" rbitfld.long 0x0C 6. " [2] ,Write data pipeline status" "Valid,Changed" newline rbitfld.long 0x0C 5. " [1] ,Read address pipeline status" "Valid,Changed" rbitfld.long 0x0C 4. " [0] ,Read data pipeline status" "Valid,Changed" line.long 0x10 "GPR4,General Purpose 4 Register" rbitfld.long 0x10 19. " SDMA_STOP_ACK ,SDMA stop acknowledge" "Not asserted,Asserted" newline rbitfld.long 0x10 16. " RNGB_STOP_REQ ,RNGB stop acknowledge" "Not asserted,Asserted" line.long 0x14 "GPR5,General Purpose 5 Register" bitfld.long 0x14 31. " REF_1M_CLK_EPIT2 ,EPIT2 1 MHz clock source select" "IPG_PERCLK,Anatop 1 MHz clock" bitfld.long 0x14 30. " REF_1M_CLK_EPIT1 ,EPIT1 1 MHz clock source select" "IPG_PERCLK,Anatop 1 MHz clock" newline bitfld.long 0x14 29. " LCDIF_HANDSHAKE ,LCDIF input handshake select" "CSI,PXP" bitfld.long 0x14 28. " VREF_1M_CLK_GPT ,GPT 1 MHz clock source select" "IPG_PERCLK,Anatop 1 MHz clock" newline bitfld.long 0x14 15. " AFCG_MAIN_BYPASS ,AFCG of sim_main bypass selection" "Sim_main enabled,Sim_main disabled" bitfld.long 0x14 13. " AFCG_M1_BYPASS ,AFCG of sim_m bypass selection" "Sim_m enabled,Sim_m disabled" newline bitfld.long 0x14 12. " AFCG_S_BYPASS ,AFCG of sim_s bypass selection" "Sim_s enabled,Sim_s disabled" bitfld.long 0x14 11. " AFCG_CPU_BYPASS ,AFCG of sim_cpu bypass selection" "Sim_cpu enabled,Sim_cpu enabled" newline bitfld.long 0x14 10. " WDOG2_MASK ,WDOG2 timeout mask" "Not masked,Masked" bitfld.long 0x14 9. " WDOG1_MASK ,WDOG1 timeout mask" "Not masked,Masked" newline rbitfld.long 0x14 8. " L2_CLK_STOP ,L2 cache clock stop indication" "Running,Stopped" newline rbitfld.long 0x14 4. " ARM_WFE ,ARM WFE event out indication on WFE state of the cores" "Not in WFE mode,In WFE mode" rbitfld.long 0x14 0. " ARM_WFI ,ARM WFI event out indicating on WFI state of the cores" "Not in WFE mode,In WFE mode" rgroup.long 0x24++0x03 line.long 0x00 "GPR9,General Purpose 9 Register" bitfld.long 0x00 0. " TZASC1_BYP ,TZASC-1 BYPASS MUX control" "Not checked,Checked" group.long 0x28++0x0F line.long 0x00 "GPR10,General Purpose 10 Register" bitfld.long 0x00 31. " LOCK_OCRAM_TZ_ADDR[4] ,Lock OCRAM_TZ_ADDR field for changes bit 4" "Not locked,Locked" bitfld.long 0x00 30. " [3] ,Lock OCRAM_TZ_ADDR field for changes bit 3" "Not locked,Locked" newline bitfld.long 0x00 29. " [2] ,Lock OCRAM_TZ_ADDR field for changes bit 2" "Not locked,Locked" bitfld.long 0x00 28. " [1] ,Lock OCRAM_TZ_ADDR field for changes bit 1" "Not locked,Locked" newline bitfld.long 0x00 27. " [0] ,Lock OCRAM_TZ_ADDR field for changes bit 0" "Not locked,Locked" newline bitfld.long 0x00 26. " LOCK_OCRAM_TZ_EN ,Lock OCRAM_TZ_EN field for changes" "Not locked,Locked" newline bitfld.long 0x00 25. " LOCK_OCRAM_L2_TZ_ADDR[5] ,Lock OCRAM_L2_TZ_ADDR field for changes bit 5" "Not locked,Locked" bitfld.long 0x00 24. " [4] ,Lock OCRAM_L2_TZ_ADDR field for changes bit 4" "Not locked,Locked" newline bitfld.long 0x00 23. " [3] ,Lock OCRAM_L2_TZ_ADDR field for changes bit 3" "Not locked,Locked" bitfld.long 0x00 22. " [2] ,Lock OCRAM_L2_TZ_ADDR field for changes bit 2" "Not locked,Locked" newline bitfld.long 0x00 21. " [1] ,Lock OCRAM_L2_TZ_ADDR field for changes bit 1" "Not locked,Locked" bitfld.long 0x00 20. " [0] ,Lock OCRAM_L2_TZ_ADDR field for changes bit 0" "Not locked,Locked" newline bitfld.long 0x00 19. " LOCK_OCRAM_L2_TZ_EN ,Lock OCRAM_L2_TZ_EN field for changes" "Not locked,Locked" newline bitfld.long 0x00 18. " LOCK_SEC_ERR_RESP ,Lock SEC_ERR_RESP field for changes" "Not locked,Locked" newline bitfld.long 0x00 17. " LOCK_DBG_CLK_EN ,Lock DBG_CLK_EN field for changes" "Not locked,Locked" newline bitfld.long 0x00 16. " LOCK_DBG_EN ,Lock DBG_EN field for changes" "Not locked,Locked" newline hexmask.long.byte 0x00 11.--15. 0x08 " OCRAM_TZ_ADDR ,OCRAM TrustZone start address" newline bitfld.long 0x00 10. " OCRAM_TZ_EN ,OCRAM TrustZone enable" "Disabled,Enabled" newline hexmask.long.word 0x00 4.--9. 0x10 " OCRAM_L2_TZ_ADDR ,OCRAM_L2 TrustZone start address" newline bitfld.long 0x00 3. " OCRAM_L2_TZ_EN ,OCRAM_L2 TrustZone enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SEC_ERR_RESP ,Security error response enable for all security gaskets" "OKEY,SLVError" newline bitfld.long 0x00 1. " DBG_CLK_EN ,ARM debug clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DBG_EN ,ARM non secure debug enable" "Disabled,Enabled" line.long 0x04 "GPR11,General Purpose 11 Register" bitfld.long 0x04 19. " LOCK_DCPKEY_OCOTP_OR_KEYMUX ,Lock DCP Key OCOTP/Key MUX selection bit" "Not locked,Locked" newline bitfld.long 0x04 18. " LOCK_DCPKEY_GP4_GP3_SELECT ,Lock DCP key GP4/GP3 selection bit" "Not locked,Locked" newline bitfld.long 0x04 17. " LOCK_OCRAM_L2_EN ,Lock OCRAM_L2 enable bit" "Not locked,Locked" newline bitfld.long 0x04 3. " DCPKEY_OCOTP_OR_KEYMUX ,DCP key selection bit" "SNVS/OTPMK,GP3/GP4" newline bitfld.long 0x04 2. " DCPKEY_GP4_GP3_SELECT ,DCP key selection bit" "GP3,GP4" newline bitfld.long 0x04 1. " OCRAM_L2_EN ,L2 as OCRAM use enable" "Disabled,Enabled" line.long 0x08 "GPR12,General Purpose 12 Register" bitfld.long 0x08 31. " DCP_KEY_SEL ,Select 128-bit DCP key from 256-bit key from SNVS/OCOTP" "128,256" newline bitfld.long 0x08 27. " ARMP_IPG_CLK_EN ,ARM platform IPG clock enable" "Disabled,Enabled" newline bitfld.long 0x08 26. " ARMP_AHB_CLK_EN ,ARM platform AHB clock enable" "Disabled,Enabled" newline bitfld.long 0x08 25. " ARMP_ATB_CLK_EN ,ARM platform ATB clock enable" "Disabled,Enabled" newline bitfld.long 0x08 24. " ARMP_APB_CLK_EN ,ARM platform APB clock enable" "Disabled,Enabled" line.long 0x0C "GPR13,General Purpose 13 Register" bitfld.long 0x0C 18. " LCDIF_RD_CACHE_SEL ,Cacheable attribute of LCDIF AXI read transactions" "LCDIF core,LCDIF_RD_CACHE_VAL" newline bitfld.long 0x0C 16. " LCDIF_RD_CACHE_VAL ,LCDIF block cacheable attribute value of AXI read transactions" "Off,On" newline bitfld.long 0x0C 15. " EPDC_WR_CACHE_SEL ,Cacheable attribute of EPDC AXI write transactions" "EPDC core,EPDC_WR_CACHE_VAL" newline bitfld.long 0x0C 14. " EPDC_RD_CACHE_SEL ,Cacheable attribute of EPDC AXI read transactions" "EPDC core,EPDC_RD_CACHE_VAL" newline bitfld.long 0x0C 13. " EPDC_WR_CACHE_VAL ,EPDC block cacheable attribute value of AXI write transactions" "Off,On" newline bitfld.long 0x0C 12. " EPDC_RD_CACHE_VAL ,EPDC block cacheable attribute value of AXI read transactions" "Off,On" newline bitfld.long 0x0C 11. " PXP_WR_CACHE_SEL ,Cacheable atribute of PXP AXI write transactions" "PXP core,PXP_WR_CACHE_VAL" newline bitfld.long 0x0C 10. " PXP_WR_CACHE_VAL ,PXP block cacheable attribute value of AXI write transactions" "PXP core,PXP_RD_CACHE_VAL" newline bitfld.long 0x0C 9. " PXP_WR_CACHE_VAL ,PXP block cacheable attribute value of AXI write transactions" "Off,On" newline bitfld.long 0x0C 8. " PXP_RD_CACHE_VAL ,PXP block cacheable attribute value of AXI read transactions" "Off,On" width 0x0B tree.end tree "IOMUXC" base ad:0x020E0000 width 13. tree "SW_MUX_CTL_PAD Registers" group.long 0x14++0x4F line.long 0x00 "WDOG_B,Watchdog Pad Mux Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "WDOG1_B,WDOG1_RESET_B_DEB,UART5_RI_B,,,,GPIO3_IO18,?..." line.long 0x04 "REF_CLK_24M,REF_CLK_24M Pad Mux Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "XTALOSC_REF_CLK_24M,I2C3_SCL,PWM3_OUT,USB_OTG2_ID,CCM_PMIC_READY,GPIO3_IO21,SD3_WP,?..." line.long 0x08 "REF_CLK_24M,REF_CLK_24M Pad Mux Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "XTALOSC_REF_CLK_32k,I2C3_SDA,PWM4_OUT,USB_OTG1_ID,SDI_LCTL,GPIO3_IO22,SD3_CD_B,?..." line.long 0x0C "PWM1,PWM1 Pad Mux Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "PWM1_OUT,CCM_CLKO,AUDIO_CLK_OUT,,CSI_MCLK,GPIO3_IO23,EPIT1_OUT,?..." line.long 0x10 "KEY_COL0,KEY_COL0 Pad Mux Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "KEY_COL0,I2C2_SCL,LCD_DATA00,,SD1_CD_B,GPIO3_IO24,?..." line.long 0x14 "KEY_ROW0,KEY_ROW0 Pad Mux Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "KEY_ROW0,I2C2_SDA,LCD_DATA01,,SD1_WP,GPIO3_IO25,?..." line.long 0x18 "KEY_COL1,KEY_COL1 Pad Mux Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" "KEY_COL1,ECSPI4_MOSI,LCD_DATA02,,SD3_DATA4,GPIO3_IO26,?..." line.long 0x1C "KEY_ROW1,KEY_ROW1 Pad Mux Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" "KEY_ROW1,ECSPI4_MISO,LCD_DATA03,CSI_FIELD,SD3_DATA5,GPIO3_IO27,?..." line.long 0x20 "KEY_COL2,KEY_COL2 Pad Mux Register" bitfld.long 0x20 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20 0.--2. " MUX_MODE ,MUX mode select field" "KEY_COL2,ECSPI4_SS0,LCD_DATA04,CSI_DATA12,SD3_DATA6,GPIO3_IO28,?..." line.long 0x24 "KEY_ROW2,KEY_ROW2 Pad Mux Register" bitfld.long 0x24 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24 0.--2. " MUX_MODE ,MUX mode select field" "KEY_ROW2,ECSPI4_SCLK,LCD_DATA05,CSI_DATA13,SD3_DATA7,GPIO3_IO29,?..." line.long 0x28 "KEY_COL3,KEY_COL3 Pad Mux Register" bitfld.long 0x28 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x28 0.--2. " MUX_MODE ,MUX mode select field" "KEY_COL3,AUD6_RXFS,LCD_DATA06,CSI_DATA14,,GPIO3_IO30,SD1_RESET,?..." line.long 0x2C "KEY_ROW3,KEY_ROW3 Pad Mux Register" bitfld.long 0x2C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x2C 0.--2. " MUX_MODE ,MUX mode select field" "KEY_ROW3,AUD6_RXC,LCD_DATA07,CSI_DATA15,,GPIO3_IO31,SD1_VSELECT,?..." line.long 0x30 "KEY_COL4,KEY_COL4 Pad Mux Register" bitfld.long 0x30 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x30 0.--2. " MUX_MODE ,MUX mode select field" "KEY_COL4,AUD6_RXD,LCD_DATA08,CSI_DATA16,,GPIO4_IO00,USB_OTG1_PWR,?..." line.long 0x34 "KEY_ROW4,KEY_ROW4 Pad Mux Register" bitfld.long 0x34 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x34 0.--2. " MUX_MODE ,MUX mode select field" "KEY_ROW4,AUD6_TXC,LCD_DATA09,CSI_DATA17,,GPIO4_IO01,USB_OTG1_OC,?..." line.long 0x38 "KEY_COL5,KEY_COL5 Pad Mux Register" bitfld.long 0x38 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x38 0.--2. " MUX_MODE ,MUX mode select field" "KEY_COL5,AUD6_TXFS,LCD_DATA10,CSI_DATA18,,GPIO4_IO02,USB_OTG2_PWR,?..." line.long 0x3C "KEY_ROW5,KEY_ROW5 Pad Mux Register" bitfld.long 0x3C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " MUX_MODE ,MUX mode select field" "KEY_ROW5,AUD6_TXD,LCD_DATA11,CSI_DATA19,,GPIO4_IO03,USB_OTG2_OC,?..." line.long 0x40 "KEY_COL6,KEY_COL6 Pad Mux Register" bitfld.long 0x40 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x40 0.--2. " MUX_MODE ,MUX mode select field" "KEY_COL6,UART4_RX_DATA,LCD_DATA12,CSI_DATA20,,GPIO4_IO04,SD3_RESET,?..." line.long 0x44 "KEY_ROW6,KEY_ROW6 Pad Mux Register" bitfld.long 0x44 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x44 0.--2. " MUX_MODE ,MUX mode select field" "KEY_ROW6,UART4_TX_DATA,LCD_DATA13,CSI_DATA21,,GPIO4_IO05,SD3_VSELECT,?..." line.long 0x48 "KEY_COL7,KEY_COL7 Pad Mux Register" bitfld.long 0x48 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x48 0.--2. " MUX_MODE ,MUX mode select field" "KEY_COL7,UART4_RTS_B,LCD_DATA14,CSI_DATA22,,GPIO4_IO06,SD1_WP,?..." line.long 0x4C "KEY_ROW7,KEY_ROW7 Pad Mux Register" bitfld.long 0x4C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x4C 0.--2. " MUX_MODE ,MUX mode select field" "KEY_ROW7,UART4_CTS_B,LCD_DATA15,CSI_DATA23,,GPIO4_IO07,SD1_CD_B,?..." newline width 13. tree "EPDC Mux Registers" group.long 0x64++0x9F line.long 0x00 "DATA00,DATA00 Pad Mux Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA00,ECSPI4_MOSI,LCD_DATA24,CSI_DATA00,,GPIO1_IO07,?..." line.long 0x04 "DATA01,DATA01 Pad Mux Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA01,ECSPI4_MISO,LCD_DATA25,CSI_DATA01,,GPIO1_IO08,?..." line.long 0x08 "DATA02,DATA02 Pad Mux Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA02,ECSPI4_SS0,LCD_DATA26,CSI_DATA06,,GPIO1_IO09,?..." line.long 0x0C "DATA03,DATA03 Pad Mux Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA03,ECSPI4_SCLK,LCD_DATA27,CSI_DATA03,,,GPIO1_IO10,?..." line.long 0x10 "DATA04,DATA04 Pad Mux Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA04,ECSPI4_SS1,LCD_DATA28,CSI_DATA04,,GPIO1_IO11,?..." line.long 0x14 "DATA05,DATA05 Pad Mux Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA05,ECSPI4_SS2,LCD_DATA29,CSI_DATA05,,GPIO1_IO12,?..." line.long 0x18 "DATA01,DATA01 Pad Mux Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA01,ECSPI4_SS3,LCD_DATA30,CSI_DATA01,,GPIO1_IO13,?..." line.long 0x1C "DATA07,DATA07 Pad Mux Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA07,ECSPI4_RDY,LCD_DATA31,CSI_DATA07,,GPIO1_IO14,?..." line.long 0x20 "DATA08,DATA08 Pad Mux Register" bitfld.long 0x20 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA08,ECSPI3_MOSI,EPDC_PWR_CTRL0,,,GPIO1_IO15,?..." line.long 0x24 "DATA09,DATA09 Pad Mux Register" bitfld.long 0x24 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA09,ECSPI3_MISO,EPDC_PWR_CTRL1,,,GPIO1_IO16,?..." line.long 0x28 "DATA10,DATA10 Pad Mux Register" bitfld.long 0x28 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x28 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA10,ECSPI3_SSO,EPDC_PWR_CTRL2,,,GPIO1_IO12,?..." line.long 0x2C "EPDC_DATA11,DATA11 Pad Mux Register" bitfld.long 0x2C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x2C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA11,ECSPI3_SCLK,EPDC_PWR_CTRL3,,,GPIO1_IO18,?..." line.long 0x30 "DATA12,DATA12 Pad Mux Register" bitfld.long 0x30 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x30 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA12,UART4_RX_DATA,EPDC_PWR_COM,,,GPIO1_IO19,ECSPI3_SS1,?..." line.long 0x34 "DATA13,DATA13 Pad Mux Register" bitfld.long 0x34 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x34 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA13,UART2_TX_DATA,EPDC_PWR_IRQ,,,GPIO1_IO20,ECSPI3_SS2,?..." line.long 0x38 "DATA14,DATA14 Pad Mux Register" bitfld.long 0x38 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x38 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA14,UART2_RTS_B,EPDC_PWR_STAT,,,GPIO1_IO21,ECSPI3_SS3,?..." line.long 0x3C "DATA15,DATA15 Pad Mux Register" bitfld.long 0x3C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_DATA15,UART2_CTS_B,EPDC_PWR_WAKE,,,GPIO1_IO22,ECSPI3_RDY,?..." line.long 0x40 "SDCLK,SDCLK Pad Mux Register" bitfld.long 0x40 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x40 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCLK_P,ECSPI2_MOSI,I2C2_SCL,CSI_DATA08,,GPIO_IO23,?..." line.long 0x44 "SDLE,SDLE Pad Mux Register" bitfld.long 0x44 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x44 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDLE,ECSPI2_MISO,I2C2_SDA,CSI_DATA04,,GPIO1_IO24,?..." line.long 0x48 "SDOE,SDOE Pad Mux Register" bitfld.long 0x48 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x48 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDOE,ECSPI2_SS0,,CSI_DATA10,,GPIO_IO25,?..." line.long 0x4C "SDSHR,SDSHR Pad Mux Register" bitfld.long 0x4C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x4C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDSHR,ECSPI2_SCLK,EPDC_SDCE4,CSI_DATA11,,GPIO1_IO26,?..." line.long 0x50 "SDCE0,SDCE0 Pad Mux Register" bitfld.long 0x50 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x50 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCE0,ECSPI2_SS1,PWM3_OUT,,,GPIO1_IO27,?..." line.long 0x54 "SDCE1,SDCE1 Pad Mux Register" bitfld.long 0x54 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x54 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCE1,WDOG2_B,PWM4_OUT,,,GPIO1_IO28,?..." line.long 0x58 "SDCE2,SDCE2 Pad Mux Register" bitfld.long 0x58 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x58 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCE2,I2C3_SCL,PWM1_OUT,,,GPIO1_IO29,?..." line.long 0x5C "SDCE3,SDCE3 Pad Mux Register" bitfld.long 0x5C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x5C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_SDCE3,I2C3_SDA,PWM2_OUT,,,GPIO1_IO30,?..." line.long 0x60 "GDCLK,GDCLK Pad Mux Register" bitfld.long 0x60 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x60 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_GDCLK,ECSPI2_SS2,,CSI_PIXCLK,,GPIO1_IO31,SD2_RESET,?..." line.long 0x64 "GDOE,GDOE Pad Mux Register" bitfld.long 0x64 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x64 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_GDOE,ECSPI2_SS3,,CSI_HSYNC,,GPIO2_IO00,SD2_VSELECT,?..." line.long 0x68 "GDRL,GDRL Pad Mux Register" bitfld.long 0x68 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x68 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_GDRL,ECSPI2_RDY,,CSI_MCLK,,GPIO2_IO01,SD2_WP,?..." line.long 0x6C "GDSP,GDSP Pad Mux Register" bitfld.long 0x6C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x6C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_GDSP,PWM4_OUT,,CSI_VSYNC,,GPIO2_IO02,SD2_CD_B,?..." line.long 0x70 "VCOM0,VCOM0 Pad Mux Register" bitfld.long 0x70 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x70 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_VCOM0,AUD5_RXFS,UART3_RX_DATA,,,GPIO2_IO03,EPDC_SDCE5,?..." line.long 0x74 "VCOM1,VCOM1 Pad Mux Register" bitfld.long 0x74 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x74 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_VCOM1,AUD5_RXD,UART3_TX_DATA,,,GPIO2_IO04,EPDC_SDCE6,?..." line.long 0x78 "BDR0,BDR0 Pad Mux Register" bitfld.long 0x78 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x78 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_BDR0,,UART3_RTS_B,,,GPIO2_IO05,EPDC_SDCE7,?..." line.long 0x7C "BDR1,BDR1 Pad Mux Register" bitfld.long 0x7C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x7C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_BDR1,,UART3_CTS_B,,,GPIO2_IO06,EPDC_SDCE8,?..." line.long 0x80 "PWR_CTRL0,PWR_CTRL0 Pad Mux Register" bitfld.long 0x80 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x80 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_CTRL0,AUD5_RXC,LCD_DATA16,,,GPIO2_IO07,?..." line.long 0x84 "PWR_CTRL1,PWR_CTRL1 Pad Mux Register" bitfld.long 0x84 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x84 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_CTRL1,AUD5_TXFS,LCD_DATA17,,,GPIO2_IO08,?..." line.long 0x88 "PWR_CTRL2,PWR_CTRL2 Pad Mux Register" bitfld.long 0x88 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x88 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_CTRL2,AUD5_TXD,LCD_DATA18,,,GPIO2_IO09,?..." line.long 0x8C "PWR_CTRL3,PWR_CTRL3 Pad Mux Register" bitfld.long 0x8C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x8C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_CTRL3,AUD5_TXC,LCD_DATA19,,,GPIO2_IO10,?..." line.long 0x90 "PWR_COM,PWR_COM Pad Mux Register" bitfld.long 0x90 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x90 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_COM,,LCD_DATA20,,USB_OTG1_ID,GPIO2_IO11,SD3_RESET,?..." line.long 0x94 "PWR_IRQ,PWR_IRQ Pad Mux Register" bitfld.long 0x94 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x94 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_IRQ,,LCD_DATA21,,USB_OTG2_ID,GPIO2_IO12,SD3_VSELECT,?..." line.long 0x98 "PWR_STAT,PWR_STAT Pad Mux Register" bitfld.long 0x98 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x98 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_STAT,,LCD_DATA22,,ARM_EVENTI,GPIO2_IO13,SD3_WP,?..." line.long 0x9C "PWR_WAKE,PWR_WAKE Pad Mux Register" bitfld.long 0x9C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x9C 0.--2. " MUX_MODE ,MUX mode select field" "EPDC_PWR_WAKE,,LCD_DATA23,,ARM_EVENTO,GPIO2_IO14,SD3_CD_B,?..." tree.end newline width 13. tree "LCD Mux Registers" group.long 0x104++0x73 line.long 0x00 "CLK,CLK Pad Mux Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "LCD_CLK,,LCD_WR_RWN,,PWM4_OUT,GPIO2_IO15,?..." line.long 0x04 "ENABLE,ENABLE Pad Mux Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "LCD_ENABLE,,LCD_RD_E,,UART2_RX_DATA,GPIO2_IO16,?..." line.long 0x08 "HSYNC,HSYNC Pad Mux Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "LCD_HSYNC,,LCD_CS,,UART2_TX_DATA,GPIO2_IO17,ARM_TRACE_CLK,?..." line.long 0x0C "VSYNC,VSYNC Pad Mux Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "LCD_VSYNC,,LCD_RS,,UART2_RTS_B,GPIO2_IO18,ARM_TRACE_CTL,?..." line.long 0x10 "RESET,RESET Pad Mux Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "LCD_RESET,,LCD_BUSY,,UART2_CTS_B,GPIO2_IO19,CCM_PMIC_READY,?..." line.long 0x14 "DAT00,DATA00 Pad Mux Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA00,ECSPI1_MOSI,USB_OTG2_ID,PWM1_OUT,UART5_DTR_B,GPIO2_IO20,ARM_TRACE00,SRC_BOOT_CFG00" line.long 0x18 "DAT01,DATA01 Pad Mux Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA01,ECSPI1_MISO,USB_OTG1_ID,PWM2_OUT,AUD4_RXFS,GPIO2_IO21,ARM_TRACE01,SRC_BOOT_CFG01" line.long 0x1C "DAT02,DATA02 Pad Mux Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA02,ECSPI1_SS0,EPIT2_OUT,PWM3_OUT,AUD4_RXC,GPIO2_IO22,ARM_TRACE02,SRC_BOOT_CFG02" line.long 0x20 "DAT03,DATA03 Pad Mux Register" bitfld.long 0x20 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA03,ECSPI1_SCLK,UART5_DSR_B,PWM4_OUT,AUD4_RXD,GPIO2_IO23,ARM_TRACE03,SRC_BOOT_CFG03" line.long 0x24 "DAT04,DATA04 Pad Mux Register" bitfld.long 0x24 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA04,ECSPI1_SS1,CSI_VSYNC,WDOG2_RESET_B_DEB,AUD4_TXC,GPIO2_IO24,ARM_TRACE04,SRC_BOOT_CFG04" line.long 0x28 "DAT05,DATA05 Pad Mux Register" bitfld.long 0x28 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x28 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA05,ECSPI1_SS2,CSI_HSYNC,,AUD4_TXFS,GPIO2_IO25,ARM_TRACE05,SRC_BOOT_CFG05" line.long 0x2C "DAT06,DATA06 Pad Mux Register" bitfld.long 0x2C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x2C 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA06,ECSPI1_SS3,CSI_PIXCLK,,AUD4_TXD,GPIO2_IO26,ARM_TRACE06,SRC_BOOT_CFG06" line.long 0x30 "DAT07,DATA07 Pad Mux Register" bitfld.long 0x30 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x30 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA07,ECSPI1_RDY,CSI_MCLK,,AUDIO_CLK_OUT,GPIO2_IO27,ARM_TRACE07,SRC_BOOT_CFG07" line.long 0x34 "DAT08,DATA08 Pad Mux Register" bitfld.long 0x34 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x34 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA08,KEY_COL0,CSI_DATA09,,ECSPI2_SCLK,GPIO2_IO28,ARM_TRACE08,SRC_BOOT_CFG08" line.long 0x38 "DAT09,DATA09 Pad Mux Register" bitfld.long 0x38 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x38 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA09,KEY_ROW0,CSI_DATA08,,ECSPI2_MOSI,GPIO2_IO29,ARM_TRACE09,SRC_BOOT_CFG09" line.long 0x3C "DAT10,DATA10 Pad Mux Register" bitfld.long 0x3C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA10,KEY_COL1,CSI_DATA07,,ECSPI2_MISO,GPIO2_IO30,ARM_TRACE10,SRC_BOOT_CFG10" line.long 0x40 "DAT11,DATA11 Pad Mux Register" bitfld.long 0x40 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x40 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA11,KEY_ROW1,CSI_DATA06,,ECSPI2_SS1,GPIO2_IO31,ARM_TRACE11,SRC_BOOT_CFG11" line.long 0x44 "DAT12,DATA12 Pad Mux Register" bitfld.long 0x44 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x44 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA12,KEY_COL2,CSI_DATA05,,UART5_RTS_B,GPIO3_IO00,ARM_TRACE12,SRC_BOOT_CFG12" line.long 0x48 "DATA13,DATA13 Pad Mux Register" bitfld.long 0x48 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x48 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA13,KEY_ROW2,CSI_DATA04,,UART5_CTS_B,GPIO3_IO01,ARM_TRACE13,SRC_BOOT_CFG13" line.long 0x4C "DATA14,DATA14 Pad Mux Register" bitfld.long 0x4C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x4C 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA14,KEY_COL3,CSI_DATA03,,UART5_RX_DATA,GPIO3_IO02,ARM_TRACE14,SRC_BOOT_CFG14" line.long 0x50 "DATA15,DATA15 Pad Mux Register" bitfld.long 0x50 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x50 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA15,KEY_ROW3,CSI_DATA02,,UART5_TX_DATA,GPIO3_IO03,ARM_TRACE15,SRC_BOOT_CFG15" line.long 0x54 "DATA16,DATA16 Pad Mux Register" bitfld.long 0x54 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x54 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA16,KEY_COL4,CSI_DATA01,,I2C2_SCL,GPIO3_IO04,ARM_TRACE13,SRC_BOOT_CFG24" line.long 0x58 "DATA17,DATA17 Pad Mux Register" bitfld.long 0x58 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x58 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA17,KEY_ROW4,CSI_DATA00,,I2C2_SDA,GPIO3_IO05,,SRC_BOOT_CFG25" line.long 0x5C "DATA18,DATA18 Pad Mux Register" bitfld.long 0x5C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x5C 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA18,KEY_COL5,CSI_DATA15,,GPT_CAPTURE1,GPIO3_IO06,,SRC_BOOT_CFG26" line.long 0x60 "DATA19,DATA19 Pad Mux Register" bitfld.long 0x60 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x60 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA19,KEY_ROW5,CSI_DATA14,,GPT_CAPTURE2,GPIO3_IO07,,SRC_BOOT_CFG17" line.long 0x64 "DATA20,DATA20 Pad Mux Register" bitfld.long 0x64 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x64 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA20,KEY_COL6,CSI_DATA13,,GPT_COMPARE1,GPIO3_IO08,,SRC_BOOT_CFG28" line.long 0x68 "DAT21,DATA21 Pad Mux Register" bitfld.long 0x68 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x68 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA21,KEY_ROW6,CSI_DATA12,,GPT_COMPARE2,GPIO3_IO09,,SRC_BOOT_CFG29" line.long 0x6C "DAT22,DATA22 Pad Mux Register" bitfld.long 0x6C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x6C 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA22,KEY_COL7,CSI_DATA11,,GPT_COMPARE3,GPIO3_IO10,,SRC_BOOT_CFG30" line.long 0x70 "DAT23,DATA23 Pad Mux Register" bitfld.long 0x70 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x70 0.--2. " MUX_MODE ,MUX mode select field" "LCD_DATA23,KEY_ROW7,CSI_DATA10,,GPT_CLKIN,GPIO3_IO11,,SRC_BOOT_CFG31" tree.end newline width 13. group.long 0x178++0x53 line.long 0x00 "AUD_RXFS,AUD_RXFS Pad Mux Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "AUD3_RXFS,I2C1_SCL,UART3_RX_DATA,,I2C3_SCL,GPIO1_IO00,ECSPI3_SS0,MBIST_BEND" line.long 0x04 "AUD_RXC,AUD_RXC Pad Mux Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "AUD3_RXC,I2C1_SDA,UART3_TX_DATA,,I2C3_SDA,GPIO1_IO01,ECSPI3_SS1,?..." line.long 0x08 "AUD_RXD,AUD_RXD Pad Mux Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "AUD3_RXD,ECSPI3_MOSI,UART4_RX_DATA,,SDI1_LCTL,GPIO1_IO02,?..." line.long 0x0C "AUD_TXC,AUD_TXC Pad Mux Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "AUD3_TXC,ECSPI3_MIS,UART4_TX_DATA,,SD2_LCTL,GPIO1_IO03,?..." line.long 0x10 "AUD_TXFS,AUD_TXFS Pad Mux Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "AUD3_TXFS,PWM3_OUT,UART4_RTS_B,,SD3_LCTL,GPIO1_IO04,?..." line.long 0x14 "AUD_TXD,AUD_TXD Pad Mux Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "AUD3_TXD,ECSPI3_SCLK,UART4_CTS_B,,,GPIO1_IO05,?..." line.long 0x18 "AUD_MCLK,AUD_MCLK Pad Mux Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" "AUDIO_CLK_OUT,PWM4_OUT,ECSPI3_RDY,,WDOG2_RESET_B_DEB,GPIO1_IO06,SPDIF_EXT_CLK,?..." line.long 0x1C "UART1_RXD,UART1_RXD Pad Mux Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" "UART1_RX_DATA,PWM1_OUT,UART4_RX_DATA,,UART5_RX_DATA,GPIO3_IO16,?..." line.long 0x20 "UART1_TXD,UART1_TXD Pad Mux Register" bitfld.long 0x20 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20 0.--2. " MUX_MODE ,MUX mode select field" "UART1_TX_DATA,PWM2_OUT,UART4_TX_DATA,,UART5_TX_DATA,GPIO3_IO17,UART5_DCD_B,?..." line.long 0x24 "I2C1_SCL,I2C1_SCL Pad Mux Register" bitfld.long 0x24 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24 0.--2. " MUX_MODE ,MUX mode select field" "I2C1_SCL,UART1_RTS_B,ECSPI3_SS2,,SD3_RESET,GPIO3_IO12,ECSPI1_SS1,?..." line.long 0x28 "I2C1_SDA,I2C1_SDA Pad Mux Register" bitfld.long 0x28 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x28 0.--2. " MUX_MODE ,MUX mode select field" "I2C1_SDA,UART1_CTS_B,ECSPI3_SS3,,SD3_VSELECT,GPIO3_IO13,ECSPI1_SS2,?..." line.long 0x2C "I2C2_SCL,I2C2_SCL Pad Mux Register" bitfld.long 0x2C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x2C 0.--2. " MUX_MODE ,MUX mode select field" "I2C2_SCL,AUD4_RXFS,SPDIF_IN,,SD3_WP,GPIO3_IO14,ECSPI1_RDY,?..." line.long 0x30 "I2C2_SDA,I2C2_SDA Pad Mux Register" bitfld.long 0x30 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x30 0.--2. " MUX_MODE ,MUX mode select field" "I2C2_SDA,AUD4_RXC,SPDIF_OUT,,SD3_CD_B,GPIO3_IO15,?..." line.long 0x34 "ECSPI1_SCLK,ECSPI1_SCLK Pad Mux Register" bitfld.long 0x34 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x34 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_SCLK,AUD4_TXD,UART5_RX_DATA,EPDC_VCOM0,SD2_RESET,GPIO4_IO08,USB_OTG2_OC,?..." line.long 0x38 "ECSPI1_MOSI,ECSPI1_MOSI Pad Mux Register" bitfld.long 0x38 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x38 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_MOSI,AUD4_TXC,UART5_TX_DATA,EPDC_VCOM1,SD2_VSELECT,GPIO4_IO09,?..." line.long 0x3C "ECSPI1_MISO,ECSPI1_MISO Pad Mux Register" bitfld.long 0x3C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x3C 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_MISO,AUD4_TXFS,UART5_RTS_B,EPDC_BDR0,SD2_WP,GPIO4_IO10,?..." line.long 0x40 "ECSPI1_SS0,ECSPI1_SS0 Pad Mux Register" bitfld.long 0x40 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x40 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI1_SS0,AUD4_RXD,UART5_CTS_B,EPDC_BDR1,SD2_CD_B,GPIO4_IO11,USB_OTG2_PWR,?..." line.long 0x44 "ECSPI2_SCLK,ECSPI2_SSCLK Pad Mux Register" bitfld.long 0x44 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x44 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_SCLK,SPDIF_EXT_CLK,UART3_RX_DATA,CSI_PIXCLK,SD1_RESET,GPIO4_IO12,USB_OTG2_OC,?..." line.long 0x48 "ECSP2_MOSI,ECSP2_MOSI Pad Mux Register" bitfld.long 0x48 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x48 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_MOSI,SDMA_EXT_EVENT1,UART3_TX_DATA,CSI_HSYNC,SD1_VSELECT,GPIO4_IO13,?..." line.long 0x4C "ECSPI2_MISO,ECSPI2_MISO Pad Mux Register" bitfld.long 0x4C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x4C 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_MISO,SDMA_EXT_EVENT0,UART3_RTS_B,CSI_MCLK,SD1_WP,GPIO4_IO14,USB_OTG1_OC,?..." line.long 0x50 "ECSPI2_SSO,ECSPI2_SSO Pad Mux Register" bitfld.long 0x50 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x50 0.--2. " MUX_MODE ,MUX mode select field" "ECSPI2_SSO,ECSPI1_SS3,UART3_CTS_B,CSI_VSYNC,SD1_CD_B,GPIO4_IO15,USB_OTG1_PWR,?..." newline width 7. tree "SD1 Mux Registers" group.long 0x1D4++0x27 line.long 0x00 "CLK,CLK Pad Mux Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "SD1_CLK,KEY_COL0,EPDC_SDCE4,,GPIO5_IO15,?..." line.long 0x04 "CMD,CMD Pad Mux Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "SD1_CMD,KEY_ROW0,EPDC_SDCE5,,GPIO5_IO14,?..." line.long 0x08 "DATA0,DATA0 Pad Mux Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA0,KEY_COL1,EPDC_SDCE6,,GPIO5_IO11,?..." line.long 0x0C "DATA1,DATA1 Pad Mux Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA1,KEY_ROW1,EPDC_SDCE7,,GPIO5_IO08,?..." line.long 0x10 "DATA2,DATA2 Pad Mux Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA2,KEY_COL2,EPDC_SDCE8,,GPIO5_IO13,?..." line.long 0x14 "DATA3,DATA3 Pad Mux Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA3,KEY_ROW2,EPDC_SDCE9,,GPIO5_IO06,?..." line.long 0x18 "DATA4,DATA4 Pad Mux Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA4,KEY_COL3,EPDC_SDCLK_N,UART4_RX_DATA,GPIO5_IO12,?..." line.long 0x1C "DATA5,DATA5 Pad Mux Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA5,KEY_ROW3,EPDC_SDOED,UART4_TX_DATA,GPIO5_IO09,?..." line.long 0x20 "DATA6,DATA6 Pad Mux Register" bitfld.long 0x20 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA6,KEY_COL4,EPDC_SDOEZ,UART4_RTS_B,GPIO5_IO07,?..." line.long 0x24 "DATA7,DATA7 Pad Mux Register" bitfld.long 0x24 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24 0.--2. " MUX_MODE ,MUX mode select field" "SD1_DATA7,KEY_ROW4,CCM_PMIC_READY,UART4_CTS_B,GPIO5_IO10,?..." tree.end newline tree "SD2 Mux Registers" group.long 0x1F4++0x2B line.long 0x00 "RESET,RESET Pad Mux Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "SD2_RESET,WDOG2_B,SPDIF_OUT,CSI_MCLK,GPIO4_IO27,?..." line.long 0x04 "CLK,CLK Pad Mux Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "SD2_CLK,AUD4_RXFS,ECSPI3_SCLK,CSI_DATA00,GPIO5_IO05,?..." line.long 0x08 "CMD,CMD Pad Mux Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "SD2_CMD,AUD4_RXC,ECSPI3_SS0,CSI_DATA01,EPIT1_OUT,GPIO5_IO14,?..." line.long 0x0C "DATA0,DATA0 Pad Mux Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA0,AUD4_RXD,ECSPI3_MOSI,CSI_DATA02,UART5_RTS_B,GPIO5_IO01,?..." line.long 0x10 "DATA1,DATA1 Pad Mux Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA1,AUD4_TXC,ECSPI3_MISO,CSI_DATA03,UART5_CTS_B,GPIO4_IO30,?..." line.long 0x14 "DATA2,DATA2 Pad Mux Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA2,AUD4_TXFS,,CSI_DATA04,UART5_RX_DATA,GPIO5_IO03,?..." line.long 0x18 "DATA3,DATA3 Pad Mux Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA3,AUD4_TXD,,CSI_DATA05,UART5_TX_DATA,GPIO4_IO28,?..." line.long 0x1C "DATA4,DATA4 Pad Mux Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA4,SD3_DATA4,UART2_RX_DATA,CSI_DATA06,SPDIF_OUT,GPIO5_IO02,?..." line.long 0x20 "DATA5,DATA5 Pad Mux Register" bitfld.long 0x20 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA5,SD3_DATA5,UART2_TX_DATA,CSI_DATA07,SPDIF_IN,GPIO4_IO31,?..." line.long 0x24 "DATA6,DATA6 Pad Mux Register" bitfld.long 0x24 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA6,SD3_DATA6,UART2_RTS_B,CSI_DATA08,SD2_WP,GPIO4_IO29,?..." line.long 0x28 "DATA7,DATA7 Pad Mux Register" bitfld.long 0x28 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x28 0.--2. " MUX_MODE ,MUX mode select field" "SD2_DATA7,SD3_DATA7,UART2_CTS_B,CSI_DATA09,SD2_CD_B,GPIO5_IO00,?..." tree.end newline tree "SD3 Mux Registers" group.long 0x220++0x17 line.long 0x00 "CLK,CLK Pad Mux Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "SD3_CLK,AUD5_RXFS,KEY_COL5,CSI_DATA10,WDOG1_RESET_B_DEB,GPIO5_IO18,USB_OTG1_PWR,?..." line.long 0x04 "CMD,CMD Pad Mux Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "SD3_CMD,AUD5_RXC,KEY_ROW5,CSI_DATA11,USB_OTG2_ID,GPIO5_IO21,USB_OTG2_PWR,?..." line.long 0x08 "DATA0,DATA0 Pad Mux Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA0,AUD5_RXD,KEY_COL6,CSI_DATA12,USB_OTG1_ID,GPIO5_IO19,?..." line.long 0x0C "DATA1,DATA1 Pad Mux Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA1,AUD5_TXC,KEY_ROW6,CSI_DATA13,SD1_VSELECT,GPIO5_IO20,JTAG_DE_B,?..." line.long 0x10 "DATA2,DATA2 Pad Mux Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA2,AUD5_TXFS,KEY_COL7,CSI_DATA14,EPIT1_OUT,GPIO5_IO16,USB_OTG2_OC,?..." line.long 0x14 "DATA3,DATA3 Pad Mux Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" "SD3_DATA3,AUD5_TXD,KEY_ROW7,CSI_DATA15,EPIT2_OUT,GPIO5_IO17,USB_OTG1_OC,?..." tree.end newline width 12. group.long 0x238++0x2B line.long 0x00 "GPIO4_IO20,GPIO4_IO20 Pad Mux Register" bitfld.long 0x00 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x00 0.--2. " MUX_MODE ,MUX mode select field" "SD1_STROBE,,AUD6_RXFS,ECSPI4_SS0,GPT_CAPTURE1,GPIO4_IO20,?..." line.long 0x04 "GPIO4_IO21,GPIO4_IO21 Pad Mux Register" bitfld.long 0x04 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x04 0.--2. " MUX_MODE ,MUX mode select field" "SD2_STROBE,,AUD6_RXC,ECSPI4_SCLK,GPT_CAPTURE2,GPIO4_IO21,?..." line.long 0x08 "GPIO4_IO19,GPIO4_IO19 Pad Mux Register" bitfld.long 0x08 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x08 0.--2. " MUX_MODE ,MUX mode select field" "SD3_STROBE,,AUD6_RXD,ECSPI4_MOSI,GPT_COMPARE1,GPIO4_IO19,?..." line.long 0x0C "GPIO4_IO25,GPIO4_IO25 Pad Mux Register" bitfld.long 0x0C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX mode select field" ",AUD6_TXC,ECSPI4_MISO,GPT_COMPARE2,GPIO4_IO25,?..." line.long 0x10 "GPIO4_IO18,GPIO4_IO18 Pad Mux Register" bitfld.long 0x10 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x10 0.--2. " MUX_MODE ,MUX mode select field" ",AUD6_TXFS,ECSPI4_SS1,GPT_COMPARE3,GPIO4_IO18,?..." line.long 0x14 "GPIO4_IO24,GPIO4_IO24 Pad Mux Register" bitfld.long 0x14 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x14 0.--2. " MUX_MODE ,MUX mode select field" ",AUD6_TXD,ECSPI4_SS2,GPT_CLKIN,GPIO4_IO24,?..." line.long 0x18 "GPIO4_IO23,GPIO4_IO23 Pad Mux Register" bitfld.long 0x18 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x18 0.--2. " MUX_MODE ,MUX mode select field" ",AUDIO_CLK_OUT,SD1_RESET,SD3_RESET,GPIO4_IO23,?..." line.long 0x1C "GPIO4_IO17,GPIO4_IO17 Pad Mux Register" bitfld.long 0x1C 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX mode select field" ",USB_OTG1_ID,SD1_VSELECT,SD3_VSELECT,GPIO4_IO17,?..." line.long 0x20 "GPIO4_IO22,GPIO4_IO22 Pad Mux Register" bitfld.long 0x20 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x20 0.--2. " MUX_MODE ,MUX mode select field" ",SPDIF_IN,SD1_WP,SD3_WP,GPIO4_IO22,?..." line.long 0x24 "GPIO4_IO16,GPIO4_IO16 Pad Mux Register" bitfld.long 0x24 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x24 0.--2. " MUX_MODE ,MUX mode select field" ",SPDIF_OUT,SD1_CD_B,SD3_CD_B,GPIO4_IO16,?..." line.long 0x28 "GPIO4_IO26,GPIO4_IO26 Pad Mux Register" bitfld.long 0x28 4. " SION ,Software input on field" "Disabled,Enabled" bitfld.long 0x28 0.--2. " MUX_MODE ,MUX mode select field" ",WDOG1_B,PWM4_OUT,CCM_PMIC_READY,GPIO4_IO26,SPDIF_EXT_CLK,?..." tree.end newline width 10. tree "SW_PAD_CTL_PAD Registers" tree "DRAM Control Registers" group.long 0x264++0x03 line.long 0x00 "ADDR00,ADDR00 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x268++0x03 line.long 0x00 "ADDR01,ADDR01 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x26C++0x03 line.long 0x00 "ADDR02,ADDR02 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x270++0x03 line.long 0x00 "ADDR03,ADDR03 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x274++0x03 line.long 0x00 "ADDR04,ADDR04 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x278++0x03 line.long 0x00 "ADDR05,ADDR05 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x27C++0x03 line.long 0x00 "ADDR06,ADDR06 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x280++0x03 line.long 0x00 "ADDR07,ADDR07 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x284++0x03 line.long 0x00 "ADDR08,ADDR08 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x288++0x03 line.long 0x00 "ADDR09,ADDR09 Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" "0,1,2,3" newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "0,1,2,3,4,5,6,7" group.long 0x28C++0x37 line.long 0x00 "CS0_B,CS0_B Pad Control Register" bitfld.long 0x00 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x00 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x00 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x04 "CS1_B,CS1_B Pad Control Register" bitfld.long 0x04 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x04 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x04 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x04 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x08 "DQM0,DQM0 Pad Control Register" bitfld.long 0x08 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x08 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x08 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x08 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x08 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" rbitfld.long 0x08 13. " PUE ,Pull / keep select field" "Keep,Pull" newline rbitfld.long 0x08 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x08 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x08 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x0C "DQM1,DQM1 Pad Control Register" bitfld.long 0x0C 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x0C 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x0C 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x0C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x0C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" rbitfld.long 0x0C 13. " PUE ,Pull / keep select field" "Keep,Pull" newline rbitfld.long 0x0C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x0C 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x0C 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x10 "DQM2,DQM2 Pad Control Register" bitfld.long 0x10 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x10 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x10 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x10 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x10 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" rbitfld.long 0x10 13. " PUE ,Pull / keep select field" "Keep,Pull" newline rbitfld.long 0x10 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x10 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x10 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x14 "DQM3,DQM3 Pad Control Register" bitfld.long 0x14 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x14 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x14 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x14 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x14 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" rbitfld.long 0x14 13. " PUE ,Pull / keep select field" "Keep,Pull" newline rbitfld.long 0x14 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x14 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x14 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x18 "SDCKE0,SDCKE0 Pad Control Register" bitfld.long 0x18 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x18 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x18 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x18 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x18 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x18 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x18 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x18 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x18 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x1C "SDCKE1,SDCKE1 Pad Control Register" bitfld.long 0x1C 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x1C 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x1C 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x1C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x1C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x1C 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x1C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x1C 8.--10. " ODT ,On die termination field" "Disabled,?..." newline rbitfld.long 0x1C 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x20 "SDCLK0_P,SDCLK0_P Pad Control Register" bitfld.long 0x20 24.--25. " DO_TRIM_PADN ,DO trim PADN field" "Min,50ps,100ps,150ps" newline bitfld.long 0x20 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x20 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x20 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x20 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x20 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" rbitfld.long 0x20 13. " PUE ,Pull / keep select field" "Keep,Pull" newline rbitfld.long 0x20 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x20 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x20 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x24 "SDQS0_P,SDQS0_P Pad Control Register" bitfld.long 0x24 24.--25. " DO_TRIM_PADN ,DO trim PADN field" "Min,50ps,100ps,150ps" newline bitfld.long 0x24 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x24 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline rbitfld.long 0x24 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" rbitfld.long 0x24 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x24 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x24 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x24 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x24 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x24 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x28 "SDQS1_P,SDQS1_P Pad Control Register" bitfld.long 0x28 24.--25. " DO_TRIM_PADN ,DO trim PADN field" "Min,50ps,100ps,150ps" newline bitfld.long 0x28 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x28 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline rbitfld.long 0x28 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" rbitfld.long 0x28 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x28 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x28 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x28 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x28 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x28 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x2C "SDQS2_P,SDQS2_P Pad Control Register" bitfld.long 0x2C 24.--25. " DO_TRIM_PADN ,DO trim PADN field" "Min,50ps,100ps,150ps" newline bitfld.long 0x2C 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x2C 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline rbitfld.long 0x2C 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" rbitfld.long 0x2C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x2C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x2C 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x2C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x2C 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x2C 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x30 "SDQS3_P,SDQS3_P Pad Control Register" bitfld.long 0x30 24.--25. " DO_TRIM_PADN ,DO trim PADN field" "Min,50ps,100ps,150ps" newline bitfld.long 0x30 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" rbitfld.long 0x30 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline rbitfld.long 0x30 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" rbitfld.long 0x30 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x30 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x30 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x30 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x30 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x30 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x34 "ZQPAD,ZQPAD Pad Control Register" bitfld.long 0x34 24.--25. " DO_TRIM_PADN ,DO trim PADN field" "Min,50ps,100ps,150ps" newline bitfld.long 0x34 20.--21. " DO_TRIM ,DO trim field" "Min,50ps,100ps,150ps" bitfld.long 0x34 18.--19. " DDR_SEL ,DDR select field" ",,LPDDR2/LPDDR3,?..." newline bitfld.long 0x34 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" bitfld.long 0x34 16. " HYS ,Hysteresis enable" "Disabled,Enabled" newline bitfld.long 0x34 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" bitfld.long 0x34 13. " PUE ,Pull / keep select field" "Keep,Pull" newline bitfld.long 0x34 12. " PKE ,Pull / keep enable" "Disabled,Enabled" bitfld.long 0x34 8.--10. " ODT ,On die termination field" "Disabled,?..." newline bitfld.long 0x34 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" tree.end newline width 13. group.long 0x2C4++0x27 line.long 0x00 "JTAG_TRSTB,JTAG_TRSTB Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "JTAG_TDI,JTAG_TDI Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x08 "JTAG_MOD,JTAG_MOD Pad Control Register" bitfld.long 0x08 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x08 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x08 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x08 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x08 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x08 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x08 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x08 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" bitfld.long 0x08 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x0C "JTAG_TCK,JTAG_TCK Pad Control Register" bitfld.long 0x0C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x0C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x0C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x0C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x0C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x0C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x0C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x0C 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" bitfld.long 0x0C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x10 "JTAG_TMS,JTAG_TMS Pad Control Register" bitfld.long 0x10 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x10 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x10 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x10 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x10 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x10 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x10 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" bitfld.long 0x10 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x14 "JTAG_TDO,JTAG_TD0 Pad Control Register" bitfld.long 0x14 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x14 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x14 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x14 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x14 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x14 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x14 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" bitfld.long 0x14 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x18 "WDOG_B,WDOG_B Pad Control Register" bitfld.long 0x18 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x18 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x18 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x18 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x18 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x18 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x18 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x18 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x1C "REF_CLK_24M,REF_CLK_24M Pad Control Register" bitfld.long 0x1C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x1C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x1C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x1C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x1C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x1C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x1C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x1C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x20 "REF_CLK_32K,REF_CLK_32K Pad Control Register" bitfld.long 0x20 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x20 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x20 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x20 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x20 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x20 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x20 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x20 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x24 "PWM1,PWM1 Pad Control Register" bitfld.long 0x24 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x24 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x24 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x24 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x24 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x24 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x24 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x24 0. " SRE ,Slew rate field" "Slow,Fast" newline width 11. group.long 0x2EC++0x07 line.long 0x00 "KEY_COL0,KEY_COL0 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "KEY_ROW0,KEY_ROW0 Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x2F0++0x07 line.long 0x00 "KEY_COL1,KEY_COL1 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "KEY_ROW1,KEY_ROW1 Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x2F4++0x07 line.long 0x00 "KEY_COL2,KEY_COL2 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "KEY_ROW2,KEY_ROW2 Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x2F8++0x07 line.long 0x00 "KEY_COL3,KEY_COL3 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "KEY_ROW3,KEY_ROW3 Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x2FC++0x07 line.long 0x00 "KEY_COL4,KEY_COL4 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "KEY_ROW4,KEY_ROW4 Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x300++0x07 line.long 0x00 "KEY_COL5,KEY_COL5 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "KEY_ROW5,KEY_ROW5 Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x304++0x07 line.long 0x00 "KEY_COL6,KEY_COL6 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "KEY_ROW6,KEY_ROW6 Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x308++0x07 line.long 0x00 "KEY_COL7,KEY_COL7 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "KEY_ROW7,KEY_ROW7 Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" newline width 14. tree "EPDC Control Registers" group.long 0x32C++0x07 line.long 0x00 "EPDC_DATA00,EPDC_DATA00 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x330++0x07 line.long 0x00 "EPDC_DATA01,EPDC_DATA01 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x334++0x07 line.long 0x00 "EPDC_DATA02,EPDC_DATA02 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x338++0x07 line.long 0x00 "EPDC_DATA03,EPDC_DATA03 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x33C++0x07 line.long 0x00 "EPDC_DATA04,EPDC_DATA04 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x340++0x07 line.long 0x00 "EPDC_DATA05,EPDC_DATA05 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x344++0x07 line.long 0x00 "EPDC_DATA06,EPDC_DATA06 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x348++0x07 line.long 0x00 "EPDC_DATA07,EPDC_DATA07 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x34C++0x07 line.long 0x00 "EPDC_DATA08,EPDC_DATA08 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x350++0x07 line.long 0x00 "EPDC_DATA09,EPDC_DATA09 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x354++0x07 line.long 0x00 "EPDC_DATA10,EPDC_DATA10 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x358++0x07 line.long 0x00 "EPDC_DATA11,EPDC_DATA11 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x35C++0x07 line.long 0x00 "EPDC_DATA12,EPDC_DATA12 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x360++0x07 line.long 0x00 "EPDC_DATA13,EPDC_DATA13 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x364++0x07 line.long 0x00 "EPDC_DATA14,EPDC_DATA14 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x368++0x07 line.long 0x00 "EPDC_DATA15,EPDC_DATA15 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x36C++0x5F line.long 0x00 "SDCLK,SDCLK Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "SDLE,SDLE Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x08 "SDOE,SDOE Pad Control Register" bitfld.long 0x08 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x08 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x08 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x08 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x08 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x08 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x08 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x08 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x08 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x0C "SDSHR,SDSHR Pad Control Register" bitfld.long 0x0C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x0C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x0C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x0C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x0C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x0C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x0C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x0C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x0C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x10 "SDCE0,SDCE0 Pad Control Register" bitfld.long 0x10 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x10 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x10 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x10 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x10 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x10 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x10 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x10 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x14 "SDCE1,SDCE1 Pad Control Register" bitfld.long 0x14 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x14 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x14 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x14 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x14 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x14 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x14 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x14 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x18 "SDCE2,SDCE2 Pad Control Register" bitfld.long 0x18 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x18 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x18 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x18 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x18 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x18 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x18 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x18 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x1C "SDCE3,SDCE3 Pad Control Register" bitfld.long 0x1C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x1C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x1C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x1C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x1C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x1C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x1C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x1C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x20 "GDCLK,GDCLK Pad Control Register" bitfld.long 0x20 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x20 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x20 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x20 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x20 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x20 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x20 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x20 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x24 "GDOE,GDOE Pad Control Register" bitfld.long 0x24 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x24 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x24 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x24 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x24 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x24 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x24 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x24 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x28 "GDRL,GDRL Pad Control Register" bitfld.long 0x28 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x28 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x28 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x28 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x28 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x28 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x28 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x28 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x2C "GDSP,GDSP Pad Control Register" bitfld.long 0x2C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x2C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x2C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x2C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x2C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x2C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x2C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x2C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x2C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x2C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x30 "VCOM0,VCOM0 Pad Control Register" bitfld.long 0x30 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x30 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x30 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x30 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x30 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x30 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x30 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x30 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x30 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x30 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x34 "VCOM1,VCOM1 Pad Control Register" bitfld.long 0x34 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x34 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x34 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x34 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x34 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x34 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x34 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x34 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x34 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x34 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x38 "BDR0,BDR0 Pad Control Register" bitfld.long 0x38 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x38 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x38 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x38 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x38 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x38 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x38 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x38 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x38 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x38 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x3C "BDR1,BDR1 Pad Control Register" bitfld.long 0x3C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x3C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x3C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x3C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x3C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x3C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x3C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x3C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x3C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x3C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x40 "PWR_CTRL0,PWR_CTRL0 Pad Control Register" bitfld.long 0x40 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x40 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x40 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x40 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x40 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x40 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x40 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x40 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x40 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x40 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x44 "PWR_CTRL1,PWR_CTRL1 Pad Control Register" bitfld.long 0x44 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x44 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x44 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x44 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x44 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x44 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x44 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x44 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x44 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x44 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x48 "PWR_CTRL2,PWR_CTRL2 Pad Control Register" bitfld.long 0x48 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x48 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x48 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x48 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x48 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x48 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x48 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x48 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x48 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x48 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x4C "PWR_CTRL3,PWR_CTRL3 Pad Control Register" bitfld.long 0x4C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x4C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x4C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x4C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x4C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x4C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x4C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x4C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x4C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x4C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x50 "PWR_COM,PWR_COM Pad Control Register" bitfld.long 0x50 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x50 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x50 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x50 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x50 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x50 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x50 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x50 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x50 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x50 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x54 "PWR_IRQ,PWR_IRQ Pad Control Register" bitfld.long 0x54 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x54 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x54 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x54 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x54 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x54 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x54 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x54 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x54 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x54 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x58 "PWR_STAT,PWR_STAT Pad Control Register" bitfld.long 0x58 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x58 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x58 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x58 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x58 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x58 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x58 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x58 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x58 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x58 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x5C "PWR_WAKE,PWR_WAKE Pad Control Register" bitfld.long 0x5C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x5C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x5C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x5C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x5C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x5C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x5C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x5C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x5C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x5C 0. " SRE ,Slew rate field" "Slow,Fast" tree.end newline width 9. tree "LCD Control Registers" group.long 0x3CC++0x13 line.long 0x00 "CLK,CLK Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "ENABLE,ENABLE Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x08 "HSYNC,HSYNC Pad Control Register" bitfld.long 0x08 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x08 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x08 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x08 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x08 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x08 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x08 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x08 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x08 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x0C "VSYNC,VSYNC Pad Control Register" bitfld.long 0x0C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x0C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x0C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x0C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x0C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x0C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x0C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x0C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x0C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x10 "RESET,RESET Pad Control Register" bitfld.long 0x10 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x10 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x10 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x10 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x10 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x10 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x10 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x10 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x3E0++0x03 line.long 0x00 "DATA00,DATA00 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x3E4++0x03 line.long 0x00 "DATA01,DATA01 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x3E8++0x03 line.long 0x00 "DATA02,DATA02 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x3EC++0x03 line.long 0x00 "DATA03,DATA03 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x3F0++0x03 line.long 0x00 "DATA04,DATA04 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x3F4++0x03 line.long 0x00 "DATA05,DATA05 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x3F8++0x03 line.long 0x00 "DATA06,DATA06 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x3FC++0x03 line.long 0x00 "DATA07,DATA07 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x400++0x03 line.long 0x00 "DATA08,DATA08 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x404++0x03 line.long 0x00 "DATA09,DATA09 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x408++0x03 line.long 0x00 "DATA10,DATA10 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x40C++0x03 line.long 0x00 "DATA11,DATA11 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x410++0x03 line.long 0x00 "DATA12,DATA12 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x414++0x03 line.long 0x00 "DATA13,DATA13 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x418++0x03 line.long 0x00 "DATA14,DATA14 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x41C++0x03 line.long 0x00 "DATA15,DATA15 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x420++0x03 line.long 0x00 "DATA16,DATA16 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x424++0x03 line.long 0x00 "DATA17,DATA17 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x428++0x03 line.long 0x00 "DATA18,DATA18 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x42C++0x03 line.long 0x00 "DATA19,DATA19 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x430++0x03 line.long 0x00 "DATA20,DATA20 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x434++0x03 line.long 0x00 "DATA21,DATA21 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x438++0x03 line.long 0x00 "DATA22,DATA22 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" group.long 0x43C++0x03 line.long 0x00 "DATA23,DATA23 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" tree.end newline width 13. group.long 0x440++0x11F line.long 0x00 "AUD_RXFS,AUD_RXFS Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "AUD_RXC,AUD_RXC Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x08 "AUD_RXD,AUD_RXD Pad Control Register" bitfld.long 0x08 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x08 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x08 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x08 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x08 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x08 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x08 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x08 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x08 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x0C "AUD_TXC,AUD_TXC Pad Control Register" bitfld.long 0x0C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x0C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x0C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x0C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x0C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x0C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x0C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x0C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x0C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x10 "AUD_TXFS,AUD_TXFS Pad Control Register" bitfld.long 0x10 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x10 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x10 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x10 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x10 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x10 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x10 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x10 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x14 "AUD_TXD,AUD_TXD Pad Control Register" bitfld.long 0x14 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x14 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x14 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x14 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x14 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x14 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x14 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x14 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x18 "AUD_MCLK,AUD_MCLK Pad Control Register" bitfld.long 0x18 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x18 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x18 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x18 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x18 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x18 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x18 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x18 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x1C "UART1_RXD,UART1_RXD Pad Control Register" bitfld.long 0x1C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x1C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x1C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x1C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x1C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x1C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x1C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x1C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x20 "UART1_TXD,UART1_TXD Pad Control Register" bitfld.long 0x20 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x20 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x20 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x20 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x20 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x20 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x20 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x20 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x24 "I2C1_SCL,I2C1_SCL Pad Control Register" bitfld.long 0x24 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x24 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x24 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x24 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x24 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x24 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x24 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x24 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x28 "I2C1_SDA,I2C1_SDA Pad Control Register" bitfld.long 0x28 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x28 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x28 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x28 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x28 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x28 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x28 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x28 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x2C "I2C2_SCL,I2C2_SCL Pad Control Register" bitfld.long 0x2C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x2C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x2C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x2C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x2C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x2C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x2C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x2C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x2C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x2C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x30 "I2C2_SDA,I2C2_SDA Pad Control Register" bitfld.long 0x30 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x30 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x30 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x30 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x30 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x30 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x30 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x30 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x30 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x30 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x34 "ECSPI1_SCLK,ECSPI1_SCLK Pad Control Register" bitfld.long 0x34 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x34 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x34 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x34 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x34 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x34 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x34 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x34 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x34 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x34 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x38 "ECSPI1_MOSI,ECSPI1_MOSI Pad Control Register" bitfld.long 0x38 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x38 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x38 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x38 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x38 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x38 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x38 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x38 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x38 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x38 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x3C "ECSPI1_MISO,ECSPI1_MISO Pad Control Register" bitfld.long 0x3C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x3C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x3C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x3C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x3C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x3C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x3C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x3C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x3C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x3C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x40 "ECSPI1_SS0,ECSPI1_SS0 Pad Control Register" bitfld.long 0x40 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x40 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x40 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x40 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x40 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x40 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x40 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x40 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x40 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x40 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x44 "ECSPI2_SCLK,ECSPI2_SCLK Pad Control Register" bitfld.long 0x44 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x44 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x44 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x44 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x44 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x44 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x44 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x44 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x44 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x44 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x48 "ECSPI2_MOSI,ECSPI2_MOSI Pad Control Register" bitfld.long 0x48 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x48 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x48 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x48 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x48 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x48 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x48 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x48 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x48 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x48 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x4C "ECSPI2_MISO,ECSPI2_MISO Pad Control Register" bitfld.long 0x4C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x4C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x4C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x4C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x4C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x4C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x4C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x4C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x4C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x4C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x50 "ECSPI2_SS0,ECSPI2_SS0 Pad Control Register" bitfld.long 0x50 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x50 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x50 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x50 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x50 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x50 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x50 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x50 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x50 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x50 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x54 "SD1_CLK,SD1_CLK Pad Control Register" bitfld.long 0x54 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x54 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x54 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x54 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x54 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x54 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x54 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x54 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x54 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x54 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x58 "SD1_CMD,SD1_CMD Pad Control Register" bitfld.long 0x58 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x58 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x58 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x58 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x58 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x58 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x58 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x58 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x58 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x58 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x5C "SD1_DATA0,SD1_DATA0 Pad Control Register" bitfld.long 0x5C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x5C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x5C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x5C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x5C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x5C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x5C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x5C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x5C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x5C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x60 "SD1_DATA1,SD1_DATA1 Pad Control Register" bitfld.long 0x60 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x60 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x60 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x60 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x60 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x60 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x60 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x60 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x60 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x60 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x64 "SD1_DATA2,SD1_DATA2 Pad Control Register" bitfld.long 0x64 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x64 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x64 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x64 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x64 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x64 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x64 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x64 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x64 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x64 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x68 "SD1_DATA3,SD1_DATA3 Pad Control Register" bitfld.long 0x68 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x68 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x68 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x68 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x68 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x68 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x68 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x68 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x68 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x68 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x6C "SD1_DATA4,SD1_DATA4 Pad Control Register" bitfld.long 0x6C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x6C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x6C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x6C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x6C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x6C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x6C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x6C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x6C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x6C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x70 "SD1_DATA5,SD1_DATA5 Pad Control Register" bitfld.long 0x70 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x70 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x70 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x70 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x70 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x70 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x70 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x70 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x70 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x70 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x74 "SD1_DATA6,SD1_DATA6 Pad Control Register" bitfld.long 0x74 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x74 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x74 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x74 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x74 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x74 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x74 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x74 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x74 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x74 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x78 "SD1_DATA7,SD1_DATA7 Pad Control Register" bitfld.long 0x78 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x78 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x78 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x78 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x78 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x78 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x78 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x78 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x78 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x78 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x7C "SD2_RESET,SD2_RESET Pad Control Register" bitfld.long 0x7C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x7C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x7C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x7C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x7C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x7C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x7C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x7C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x7C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x7C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x80 "SD2_CLK,SD2_CLK Pad Control Register" bitfld.long 0x80 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x80 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x80 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x80 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x80 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x80 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x80 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x80 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x80 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x80 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x84 "SD2_CMD,SD2_CMD Pad Control Register" bitfld.long 0x84 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x84 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x84 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x84 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x84 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x84 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x84 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x84 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x84 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x84 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x88 "SD2_DATA0,SD2_DATA0 Pad Control Register" bitfld.long 0x88 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x88 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x88 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x88 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x88 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x88 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x88 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x88 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x88 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x88 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x8C "SD2_DATA1,SD2_DATA1 Pad Control Register" bitfld.long 0x8C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x8C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x8C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x8C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x8C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x8C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x8C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x8C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x8C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x8C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x90 "SD2_DATA2,SD2_DATA2 Pad Control Register" bitfld.long 0x90 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x90 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x90 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x90 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x90 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x90 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x90 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x90 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x90 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x90 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x94 "SD2_DATA3,SD2_DATA3 Pad Control Register" bitfld.long 0x94 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x94 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x94 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x94 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x94 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x94 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x94 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x94 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x94 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x94 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x98 "SD2_DATA4,SD2_DATA4 Pad Control Register" bitfld.long 0x98 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x98 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x98 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x98 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x98 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x98 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x98 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x98 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x98 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x98 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x9C "SD2_DATA5,SD2_DATA5 Pad Control Register" bitfld.long 0x9C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x9C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x9C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x9C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x9C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x9C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x9C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x9C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x9C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x9C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x100 "SD2_DATA6,SD2_DATA6 Pad Control Register" bitfld.long 0x100 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x100 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x100 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x100 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x100 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x100 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x100 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x100 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x100 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x100 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x104 "SD2_DATA7,SD2_DATA7 Pad Control Register" bitfld.long 0x104 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x104 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x104 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x104 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x104 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x104 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x104 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x104 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x104 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x104 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x108 "SD3_CLK,SD3_CLK Pad Control Register" bitfld.long 0x108 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x108 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x108 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x108 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x108 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x108 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x108 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x108 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x108 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x108 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x10C "SD3_CMD,SD3_CMD Pad Control Register" bitfld.long 0x10C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x10C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x10C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x10C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x10C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x10C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x10C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x10C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x10C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x10C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x110 "SD3_DATA0,SD3_DATA0 Pad Control Register" bitfld.long 0x110 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x110 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x110 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x110 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x110 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x110 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x110 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x110 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x110 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x110 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x114 "SD3_DATA1,SD3_DATA1 Pad Control Register" bitfld.long 0x114 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x114 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x114 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x114 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x114 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x114 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x114 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x114 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x114 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x114 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x118 "SD3_DATA2,SD3_DATA2 Pad Control Register" bitfld.long 0x118 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x118 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x118 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x118 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x118 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x118 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x118 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x118 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x118 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x118 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x11C "SD3_DATA3,SD3_DATA3 Pad Control Register" bitfld.long 0x11C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x11C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x11C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x11C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x11C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x11C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x11C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x11C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x11C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x11C 0. " SRE ,Slew rate field" "Slow,Fast" newline width 6. tree "GPIO4 Control Registers" group.long 0x500++0x2B line.long 0x00 "IO20,IO20 Pad Control Register" bitfld.long 0x00 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x00 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x00 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x00 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x00 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x04 "IO21,IO21 Pad Control Register" bitfld.long 0x04 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x04 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x04 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x04 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x04 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x04 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x08 "IO19,IO19 Pad Control Register" bitfld.long 0x08 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x08 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x08 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x08 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x08 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x08 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x08 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x08 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x08 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x0C "IO25,IO25 Pad Control Register" bitfld.long 0x0C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x0C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x0C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x0C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x0C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x0C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x0C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x0C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x0C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x10 "IO18,IO18 Pad Control Register" bitfld.long 0x10 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x10 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x10 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x10 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x10 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x10 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x10 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x10 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x10 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x10 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x14 "IO24,IO24 Pad Control Register" bitfld.long 0x14 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x14 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x14 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x14 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x14 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x14 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x14 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x14 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x14 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x14 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x18 "IO23,IO23 Pad Control Register" bitfld.long 0x18 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x18 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x18 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x18 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x18 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x18 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x18 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x18 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x18 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x18 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x1C "IO17,IO17 Pad Control Register" bitfld.long 0x1C 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x1C 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x1C 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x1C 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x1C 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x1C 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x1C 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x1C 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x1C 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x1C 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x20 "IO22,IO22 Pad Control Register" bitfld.long 0x20 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x20 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x20 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x20 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x20 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x20 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x20 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x20 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x20 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x20 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x24 "IO16,IO16 Pad Control Register" bitfld.long 0x24 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x24 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x24 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x24 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x24 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x24 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x24 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x24 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x24 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x24 0. " SRE ,Slew rate field" "Slow,Fast" line.long 0x28 "IO26,IO26 Pad Control Register" bitfld.long 0x28 27. " IPD ,IPD field disable" "No,Yes" bitfld.long 0x28 22. " LVE ,Low voltage enable" "Disabled,Enabled" newline bitfld.long 0x28 16. " HYS ,Hysteresis enable" "Disabled,Enabled" bitfld.long 0x28 14.--15. " PUS ,Pull up / down config field" "100k,47k,100k,22k" newline bitfld.long 0x28 13. " PUE ,Pull / keep select field" "Keep,Pull" bitfld.long 0x28 12. " PKE ,Pull / keep enable" "Disabled,Enabled" newline bitfld.long 0x28 11. " ODE ,Open drain enable" "Disabled,Enabled" bitfld.long 0x28 6.--7. " SPEED ,Speed field" "50MHz,100MHz,100MHz,200Mhz" newline bitfld.long 0x28 3.--5. " DSE ,Drive strength field" "HIZ,260,130,86,65,52,43,37" bitfld.long 0x28 0. " SRE ,Slew rate field" "Slow,Fast" tree.end tree.end newline width 13. tree "Group Control Registers" group.long 0x00++0x2F line.long 0x00 "GRP_ADDDS,Group Address Control Register" bitfld.long 0x00 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x04 "DDRMODE_CTL,DDR Mode Control Register" bitfld.long 0x04 17. " DDR_INPUT ,DDR / CMOS input mode field" "CMOS,Differential" line.long 0x08 "DDRPKE,DDR Pull / Keep Control Register" bitfld.long 0x08 12. " PKE ,Pull / Keep enable field" "Disabled,Enabled" line.long 0x0C "DDRPK,Pull / Keep Select Control Register" bitfld.long 0x0C 13. " PUE ,Pull / Keep select field" "Keep,Pull" line.long 0x10 "DDRHYS,DDR Hysteresis Control Register" bitfld.long 0x10 16. " HYS ,Hysteresis enable" "Disabled,Enabled" line.long 0x14 "DDRMODE,DDR Mode Input Control Register" bitfld.long 0x14 17. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,Differential" line.long 0x18 "B0DS,B0DS Control Register" bitfld.long 0x18 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x1C "CTLDS,CTLDS Control Register" bitfld.long 0x1C 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x20 "B1DS,B1DS Control Register" bitfld.long 0x20 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x24 "DDR_TYPE,DDR_TYPE Control Register" bitfld.long 0x24 18.--19. " DDR_SEL ,DDR select field" ",LPDDR2/LPDDR3,?..." line.long 0x28 "B2DS,B2DS Control Register" bitfld.long 0x28 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" line.long 0x2C "B3DS,B3DS Control Register" bitfld.long 0x2C 3.--5. " DSE ,Drive strength field" "HIZ,240,120,80,60,48,40,34" tree.end newline width 35. group.long 0x55C++0x53 line.long 0x00 "ANALOG_USB_OTG_ID_SELECT_INPUT,Analog USB OTG ID Select Input Register" bitfld.long 0x00 0.--2. " DAISY ,Pads involved in Daisy Chain" "REF_CLK_32K_ALT3,SD3_DATA0_ALT4,GPIO4_IO17_ALT2,LCD_DATA01_ALT2,EPDC_PWR_COM_ALT4,?..." line.long 0x04 "ANALOG_USB_H1_ID_SELECT_INPUT,Analog USB H1 ID Select Input Register" bitfld.long 0x04 0.--1. " DAISY ,Pads involved in Daisy Chain" "REF_CLK_24M_ALT3,SD3_CMD_ALT4,LCD_DATA00_ALT2,EPDC_PWR_IRQ_ALT4" line.long 0x08 "AUD4_INPUT_DA_AMX_SELECT_INPUT,Audio 4 Input DA AMX Select Input Register" bitfld.long 0x08 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA03_ALT4,ECSPI1_SS0_ALT1,SD2_DATA0_ALT1,?..." line.long 0x0C "AUD4_INPUT_DB_AMX_SELECT_INPUT,Audio 4 Input DB AMX Select Input Register" bitfld.long 0x0C 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA06_ALT4,ECSPI1_SCLK_ALT1,SD2_DATA3_ALT1,?..." line.long 0x10 "AUD4_INPUT_RXCLK_AMX_SELECT_INPUT,Audio 4 Input RXCLK AMX Select Input Register" bitfld.long 0x10 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA02_ALT4,SD2_CMD_ALT1,I2C2_SDA_ALT1,?..." line.long 0x14 "AUD4_INPUT_RXFS_AMX_SELECT_INPUT,Audio 4 Input RXFS AMX Select Input Register" bitfld.long 0x14 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA01_ALT4,SD2_CLK_ALT1,I2C2_SCL_ALT1,?..." line.long 0x18 "AUD4_INPUT_TXCLK_AMX_SELECT_INPUT,Audio 4 Input TXCCLK AMX Select Input Register" bitfld.long 0x18 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA04_ALT4,ECSPI1_MOSI_ALT1,SD2_DATA1_ALT1,?..." line.long 0x1C "AUD4_INPUT_TXFS_AMX_SELECT_INPUT,Audio 4 Input TXFS AMX Select Input Register" bitfld.long 0x1C 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA05_ALT4,ECSPI1_MISO_ALT1,SD2_DATA2_ALT1,?..." line.long 0x20 "AUD5_INPUT_DA_AMX_SELECT_INPUT,Audio 5 Input DA MAX Select Input Register" bitfld.long 0x20 0. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA0_ALT1,EPDC_VCOM1_ALT1" line.long 0x24 "AUD5_INPUT_DB_AMX_SELECT_INPUT,Audio 5 Input DB AMX Select Input Register" bitfld.long 0x24 0. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA3_ALT1,EPDC_PWR_CTRL2_ALT1" line.long 0x28 "AUD5_INPUT_RXCLK_AMX_SELECT_INPUT,Audio 5 Input RXCLK AMX Select Input Register" bitfld.long 0x28 0. " DAISY ,Pads involved in Daisy Chain" "SD3_CMD_ALT1,EPDC_PWR_CTRL0_ALT1" line.long 0x2C "AUD5_INPUT_RXFS_AMX_SELECT_INPUT,Audio 5 Input RXFS AMX Select Input Register" bitfld.long 0x2C 0. " DAISY ,Pads involved in Daisy Chain" "SD3_CLK_ALT1,EPDC_VCOM0_ALT1" line.long 0x30 "AUD5_INPUT_TXCLK_AMX_SELECT_INPUT,Audio 5 Input TXCLK AMX Select Input Register" bitfld.long 0x30 0. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA1_ALT1,EPDC_PWR_CTRL3_ALT1" line.long 0x34 "AUD5_INPUT_TXFS_AMX_SELECT_INPUT,Audio 5 Input TXFS AMX Select Input Register" bitfld.long 0x34 0. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA2_ALT1,EPDC_PWR_CTRL1_ALT1" line.long 0x38 "AUD6_INPUT_DA_AMX_SELECT_INPUT,Audio 6 Input DA AMX Select Input Register" bitfld.long 0x38 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO19_ALT2,KEY_COL4_ALT1" line.long 0x3C "AUD6_INPUT_DB_AMX_SELECT_INPUT,Audio 6 Input DB AMX Select Input Register" bitfld.long 0x3C 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO24_ALT2,KEY_ROW5_ALT1" line.long 0x40 "AUD6_INPUT_RXCLK_AMX_SELECT_INPUT,Audio 6 Input RXCLK AMX Select Input Register" bitfld.long 0x40 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO21_ALT2,KEY_ROW3_ALT1" line.long 0x44 "AUD6_INPUT_RXFS_AMX_SELECT_INPUT,Audio 6 Input RXFS AMX Select Input Register" bitfld.long 0x44 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO20_ALT2,KEY_COL3_ALT1" line.long 0x48 "AUD6_INPUT_TXCLK_AMX_SELECT_INPUT,Audio 6 Input TXCLK AMX Select Input Register" bitfld.long 0x48 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO25_ALT2,KEY_ROW4_ALT1" line.long 0x4C "AUD6_INPUT_TXFS_AMX_SELECT_INPUT,Audio 6 Input TXFS AMX Select Input Register" bitfld.long 0x4C 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO18_ALT2,KEY_COL5_ALT1" line.long 0x50 "CCM_PMIC_READY_SELECT_INPUT,CCM PMIC Ready Select Input Register" bitfld.long 0x50 0.--1. " DAISY ,Pads involved in Daisy Chain" "REF_CLK_24M_ALT4,GPIO4_IO26_ALT4,LCD_RESET_ALT6,SD1_DATA7_ALT3" newline width 8. tree "CSI_CSI Select Input Registers" group.long 0x5B0++0x4B line.long 0x00 "DATA10,Data 10 Select Input Register" bitfld.long 0x00 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_CLK_ALT3,LCD_DATA23_ALT2,EPDC_SDOE_ALT3,?..." line.long 0x04 "DATA11,Data 11 Select Input Register" bitfld.long 0x04 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_CMD_ALT3,LCD_DATA22_ALT2,EPDC_SDSHR_ALT3,?..." line.long 0x08 "DATA12,Data 12 Select Input Register" bitfld.long 0x08 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA0_ALT3,KEY_COL2_ALT3,LCD_DATA21_ALT2,?..." line.long 0x0C "DATA13,Data 13 Select Input Register" bitfld.long 0x0C 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA1_ALT3,KEY_ROW2_ALT3,LCD_DATA20_ALT2,?..." line.long 0x10 "DATA14,Data 14 Select Input Register" bitfld.long 0x10 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA2_ALT3,KEY_COL3_ALT3,LCD_DATA19_ALT2,?..." line.long 0x14 "DATA15,Data 15 Select Input Register" bitfld.long 0x14 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA3_ALT3,LCD_DATA18_ALT2,KEY_ROW3_ALT3,?..." line.long 0x18 "DATA00,Data 0 Select Input Register" bitfld.long 0x18 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA17_ALT2,SD2_CLK_ALT3,EPDC_DATA00_ALT3,?..." line.long 0x1C "DATA01,Data 1 Select Input Register" bitfld.long 0x1C 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA16_ALT2,SD2_CMD_ALT3,EPDC_DATA01_ALT3,?..." line.long 0x20 "DATA02,Data 2 Select Input Register" bitfld.long 0x20 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA15_ALT2,SD2_DATA0_ALT3,EPDC_DATA02_ALT3,?..." line.long 0x24 "DATA03,Data 3 Select Input Register" bitfld.long 0x24 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA14_ALT2,SD2_DATA1_ALT3,EPDC_DATA03_ALT3,?..." line.long 0x28 "DATA04,Data 4 Select Input Register" bitfld.long 0x28 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA13_ALT2,SD2_DATA2_ALT3,EPDC_DATA04_ALT3,?..." line.long 0x2C "DATA05,Data 5 Select Input Register" bitfld.long 0x2C 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA12_ALT2,SD2_DATA2_ALT3,EPDC_DATA05_ALT3,?..." line.long 0x30 "DATA06,Data 6 Select Input Register" bitfld.long 0x30 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA11_ALT2,SD2_DATA4_ALT3,EPDC_DATA06_ALT3,?..." line.long 0x34 "DATA07,Data 7 Select Input Register" bitfld.long 0x34 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA10_ALT2,SD2_DATA5_ALT3,EPDC_DATA07_ALT3,?..." line.long 0x38 "DATA08,Data 8 Select Input Register" bitfld.long 0x38 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA09_ALT2,SD2_DATA6_ALT3,EPDC_SDCLK_ALT3,?..." line.long 0x3C "DATA09,Data 9 Select Input Register" bitfld.long 0x3C 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA08_ALT2,SD2_DATA7_ALT3,EPDC_SDLE_ALT3,?..." line.long 0x40 "HSYNC,HSYNC Select Input Register" bitfld.long 0x40 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA05_ALT2,ECSPI2_MOSI_ALT3,EPDC_GDOE_ALT3,?..." line.long 0x44 "PIXCLK,PIXCLK Select Input Register" bitfld.long 0x44 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA06_ALT2,ECSPI2_SCLK_ALT3,EPDC_GDCLK_ALT3,?..." line.long 0x48 "VSYNC,VSYNC Select Input Register" bitfld.long 0x48 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA04_ALT2,ECSPI2_SS0_ALT3,EPDC_GDSP_ALT3,?..." tree.end newline width 13. tree "ECSPI1 Select Input Register" group.long 0x5FC++0x1F line.long 0x00 "CSPI_CLK_IN,CSPI_CLK_IN Select Input Register" bitfld.long 0x00 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA03_ALT1,ECSPI1_SCLK_ALT0" line.long 0x04 "DATAREADY_B,Data Ready B Select Input Register" bitfld.long 0x04 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA07_ALT1,I2C2_SCL_ALT6" line.long 0x08 "MISO,MISO Select Input Register" bitfld.long 0x08 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA01_ALT1,ECSPI1_MISO_ALT0" line.long 0x0C "MOSI,MOSI Select Input Register" bitfld.long 0x0C 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA00_ALT1,ECSPI1_MOSI_ALT0" line.long 0x10 "SS1,SS1 Select Input Register" bitfld.long 0x10 0. " DAISY ,Pads involved in Daisy Chain" "I2C1_SCL_ALT6,LCD_DATA04_ALT1" line.long 0x14 "SS2,SS2 Select Input Register" bitfld.long 0x14 0. " DAISY ,Pads involved in Daisy Chain" "I2C1_SDA_ALT6,LCD_DATA05_ALT1" line.long 0x18 "SS0,SS0 Select Input Register" bitfld.long 0x18 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA02_ALT1,ECSPI1_SS0_ALT0" line.long 0x1C "SS3,SS3 Select Input Register" bitfld.long 0x1C 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA06_ALT1,ECSPI2_SS0_ALT1" tree.end newline width 13. tree "ECSPI2 Select Input Register" group.long 0x61C++0x13 line.long 0x00 "CSPI_CLK_IN,CSPI_CLK_IN Select Input Register" bitfld.long 0x00 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA08_ALT4,ECSPI2_SCLK_ALT0,EPDC_SDSHR_ALT1,?..." line.long 0x04 "MISO,MISO Select Input Register" bitfld.long 0x04 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA10_ALT4,ECSPI2_MISO_ALT0,EPDC_SDLE_ALT1,?..." line.long 0x08 "MOSI,MOSI Select Input Register" bitfld.long 0x08 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA09_ALT4,ECSPI2_MOSI_ALT0,EPDC_SDCLK_ALT1,?..." line.long 0x0C "SS0,SS0 Select Input Register" bitfld.long 0x0C 0. " DAISY ,Pads involved in Daisy Chain" "ECSPI2_SS0_ALT0,EPDC_SDOE_ALT1" line.long 0x10 "SS1,SS1 Select Input Register" bitfld.long 0x10 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA11_ALT4,EPDC_SDCE0_ALT1" tree.end newline width 13. tree "ECSPI3 Select Input Register" group.long 0x630++0x1F line.long 0x00 "CSPI_CLK_IN,CSPI_CLK_IN Select Input Register" bitfld.long 0x00 0.--1. " DAISY ,Pads involved in Daisy Chain" "AUD_TXD_ALT1,SD2_CLK_ALT2,EPDC_DATA11_ALT1,?..." line.long 0x04 "DATAREADY_B,Data Ready B Select Input Register" bitfld.long 0x04 0. " DAISY ,Pads involved in Daisy Chain" "AUD_MCLK_ALT2,EPDC_DATA15_ALT6" line.long 0x08 "MISO,MISO Select Input Register" bitfld.long 0x08 0.--1. " DAISY ,Pads involved in Daisy Chain" "AUD_TXC_ALT1,SD2_DATA1_ALT2,EPDC_DATA09_ALT1,?..." line.long 0x0C "MOSI,MOSI Select Input Register" bitfld.long 0x0C 0.--1. " DAISY ,Pads involved in Daisy Chain" "AUD_RXD_ALT1,SD2_DATA0_ALT2,EPDC_DATA08_ALT1,?..." line.long 0x10 "SS2,SS2 Select Input Register" bitfld.long 0x10 0. " DAISY ,Pads involved in Daisy Chain" "I2C1_SCL_ALT1,EPDC_DATA13_ALT6" line.long 0x14 "SS3,SS3 Select Input Register" bitfld.long 0x14 0. " DAISY ,Pads involved in Daisy Chain" "I2C1_SDA_ALT2,EPDC_DATA14_ALT6" line.long 0x18 "SS0,SS0 Select Input Register" bitfld.long 0x18 0.--1. " DAISY ,Pads involved in Daisy Chain" "AUD_RXFS_ALT6,SD2_CMD_ALT2,EPDC_DATA10_ALT1,?..." line.long 0x1C "SS1,SS1 Select Input Register" bitfld.long 0x1C 0. " DAISY ,Pads involved in Daisy Chain" "AUD_RXC_ALT6,EPDC_DATA12_ALT6" tree.end newline width 13. tree "ECSPI4 Select Input Register" group.long 0x650++0x17 line.long 0x00 "CSPI_CLK_IN,CSPI_CLK_IN Select Input Register" bitfld.long 0x00 0.--1. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO21_ALT3,KEY_ROW2_ALT1,EPDC_DATA03_ALT1,?..." line.long 0x04 "MISO,MISO Select Input Register" bitfld.long 0x04 0.--1. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO25_ALT3,KEY_ROW1_ALT1,EPDC_DATA01_ALT1,?..." line.long 0x08 "MOSI,MOSI Select Input Register" bitfld.long 0x08 0.--1. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO19_ALT3,KEY_COL1_ALT1,EPDC_DATA00_ALT1,?..." line.long 0x0C "SS0,SS0 Select Input Register" bitfld.long 0x0C 0.--1. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO20_ALT3,KEY_COL2_ALT1,EPDC_DATA02_ALT1,?..." line.long 0x10 "SS1,SS1 Select Input Register" bitfld.long 0x10 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO18_ALT3,EPDC_DATA04_ALT1" line.long 0x14 "SS2,SS2 Select Input Register" bitfld.long 0x14 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO24_ALT3,EPDC_DATA05_ALT1" tree.end newline width 33. group.long 0x668++0x2B line.long 0x00 "EPDC_EPDC_PWR_IRQ_SELECT_INPUT,EPDC_EPDC_PWR_IRQ Select Input Register" bitfld.long 0x00 0. " DAISY ,Pads involved in Daisy Chain" "EPDC_DATA13_ALT2,EPDC_PWR_IRQ_ALT0" line.long 0x04 "EPDC_EPDC_PWR_STAT_SELECT_INPUT,EPDC_EPDC_PWR_STAT Select Input Register" bitfld.long 0x04 0. " DAISY ,Pads involved in Daisy Chain" "EPDC_DATA14_ALT2,EPDC_PWR_STAT_ALT0" line.long 0x08 "GPT_CAPIN1_SELECT_INPUT,GPT_CAPIN1 Select Input Register" bitfld.long 0x08 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO20_ALT4,LCD_DATA18_ALT4" line.long 0x0C "GPT_CAPIN2_SELECT_INPUT,GPT_CAPIN2 Select Input Register" bitfld.long 0x0C 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO21_ALT4,LCD_DATA19_ALT4" line.long 0x10 "GPT_CLKIN_SELECT_INPUT,GPT_CLKIN Select Input Register" bitfld.long 0x10 0. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO24_ALT4,LCD_DATA23_ALT4" line.long 0x14 "I2C1_SCL_IN_SELECT_INPUT,I2C1_SCL_IN Select Input Register" bitfld.long 0x14 0. " DAISY ,Pads involved in Daisy Chain" "I2C1_SCL_ALT0,AUD_RXFS_ALT1" line.long 0x18 "I2C1_SDA_IN_SELECT_INPUT,I2C1_SDA_IN Select Input Register" bitfld.long 0x18 0. " DAISY ,Pads involved in Daisy Chain" "I2C1_SDA_ALT0,AUD_RXC_ALT1" line.long 0x1C "I2C2_SCL_IN_SELECT_INPUT,I2C2_SCL_IN Select Input Register" bitfld.long 0x1C 0.--1. " DAISY ,Pads involved in Daisy Chain" "KEY_COL0_ALT1,LCD_DATA16_ALT4,EPDC_SDCLK_ALT2,I2C2_SCL_ALT0" line.long 0x20 "I2C2_SDA_IN_SELECT_INPUT,I2C2_SDA_IN Select Input Register" bitfld.long 0x20 0.--1. " DAISY ,Pads involved in Daisy Chain" "KEY_ROW0_ALT1,LCD_DATA17_ALT4,EPDC_SDLE_ALT2,I2C2_SCL_ALT0" line.long 0x24 "I2C3_SCL_IN_SELECT_INPUT,I2C3_SCL_IN Select Input Register" bitfld.long 0x24 0.--1. " DAISY ,Pads involved in Daisy Chain" "REF_CLK_24M_ALT1,AUD_RXFS_ALT4,EPDC_SDCCE2_ALT1,?..." line.long 0x28 "I2C3_SDA_IN_SELECT_INPUT,I2C3_SDA_IN Select Input Register" bitfld.long 0x28 0.--1. " DAISY ,Pads involved in Daisy Chain" "REF_CLK_32K_ALT1,AUD_RXC_ALT4,EPDC_SDCCE3_ALT1,?..." newline width 10. tree "KEY_COL Select Input Registers" group.long 0x694++0x1F line.long 0x00 "KEY_COL5,Key Col 5 Select Input Register" bitfld.long 0x00 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_CLK_ALT2,KEY_COL5_ALT0,LCD_DATA18_ALT1,?..." line.long 0x04 "KEY_COL6,Key Col 6 Select Input Register" bitfld.long 0x04 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA0_ALT2,LCD_DATA20_ALT1,KEY_COL6_ALT0,?..." line.long 0x08 "KEY_COL7,Key Col 7 Select Input Register" bitfld.long 0x08 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA2_ALT2,LCD_DATA2_ALT1,KEY_COL7_ALT0,?..." line.long 0x0C "KEY_COL0,Key Col 0 Select Input Register" bitfld.long 0x0C 0.--1. " DAISY ,Pads involved in Daisy Chain" "KEY_COL0_ALT0,LCD_DATA08_ALT1,SD1_CLK_ALT2,?..." line.long 0x10 "KEY_COL1,Key Col 1 Select Input Register" bitfld.long 0x10 0.--1. " DAISY ,Pads involved in Daisy Chain" "KEY_COL1_ALT0,LCD_DATA10_ALT1,SD1_DATA0_ALT2,?..." line.long 0x14 "KEY_COL2,Key Col 2 Select Input Register" bitfld.long 0x14 0.--1. " DAISY ,Pads involved in Daisy Chain" "KEY_COL2_ALT0,LCD_DATA12_ALT1,SD1_DATA1_ALT2,?..." line.long 0x18 "KEY_COL3,Key Col 3 Select Input Register" bitfld.long 0x18 0.--1. " DAISY ,Pads involved in Daisy Chain" "KEY_COL3_ALT0,LCD_DATA14_ALT1,SD1_DATA4_ALT2,?..." line.long 0x1C "KEY_COL4,Key Col 4 Select Input Register" bitfld.long 0x1C 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA16_ALT1,KEY_COL4_ALT0,SD1_DATA6_ALT2,?..." tree.end newline width 10. tree "KEY_ROW Select Input Registers" group.long 0x6B4++0x1F line.long 0x00 "KEY_ROW5,Key Row 5 Select Input Register" bitfld.long 0x00 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_CMD_ALT2,LCD_DATA19_ALT1,KEY_ROW5_ALT0,?..." line.long 0x04 "KEY_ROW6,Key Row 6 Select Input Register" bitfld.long 0x04 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA1_ALT2,LCD_DATA21_ALT1,KEY_ROW6_ALT0,?..." line.long 0x08 "KEY_ROW7,Key Row 7 Select Input Register" bitfld.long 0x08 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA3_ALT2,LCD_DATA23_ALT1,KEY_ROW7_ALT0,?..." line.long 0x0C "KEY_ROW0,Key Row 0 Select Input Register" bitfld.long 0x0C 0.--1. " DAISY ,Pads involved in Daisy Chain" "KEY_ROW0_ALT0,LCD_DATA09_ALT1,SD1_CMD_ALT2,?..." line.long 0x10 "KEY_ROW1,Key Row 1 Select Input Register" bitfld.long 0x10 0.--1. " DAISY ,Pads involved in Daisy Chain" "KEY_ROW1_ALT0,LCD_DATA11_ALT1,SD1_DATA1_ALT2,?..." line.long 0x14 "KEY_ROW2,Key Row 2 Select Input Register" bitfld.long 0x14 0.--1. " DAISY ,Pads involved in Daisy Chain" "KEY_ROW2_ALT0,LCD_DATA13_ALT1,SD1_DATA3_ALT2,?..." line.long 0x18 "KEY_ROW3,Key Row 3 Select Input Register" bitfld.long 0x18 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA15_ALT1,KEY_ROW3_ALT0,SD1_DATA5_ALT2,?..." line.long 0x1C "KEY_ROW4,Key Row 4 Select Input Register" bitfld.long 0x1C 0.--1. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA17_ALT1,KEY_ROW4_ALT0,SD1_DATA7_ALT2,?..." tree.end newline width 8. tree "LCD Select Input Registers" group.long 0x6D4++0x63 line.long 0x00 "BUSY,Busy Select Input Register" bitfld.long 0x00 0. " DAISY ,Pads involved in Daisy Chain" "LCD_HSYNC_ALT0,LCD_RESET_ALT2" line.long 0x04 "DATA00,Data 0 Select Input Register" bitfld.long 0x04 0. " DAISY ,Pads involved in Daisy Chain" "KEY_COL0_ALT2,LCD_DATA00_ALT0" line.long 0x08 "DATA01,Data 1 Select Input Register" bitfld.long 0x08 0. " DAISY ,Pads involved in Daisy Chain" "KEY_ROW0_ALT2,LCD_DATA01_ALT0" line.long 0x0C "DATA02,Data 2 Select Input Register" bitfld.long 0x0C 0. " DAISY ,Pads involved in Daisy Chain" "KEY_COL1_ALT2,LCD_DATA02_ALT0" line.long 0x10 "DATA03,Data 3 Select Input Register" bitfld.long 0x10 0. " DAISY ,Pads involved in Daisy Chain" "KEY_ROW1_ALT2,LCD_DATA03_ALT0" line.long 0x14 "DATA04,Data 4 Select Input Register" bitfld.long 0x14 0. " DAISY ,Pads involved in Daisy Chain" "KEY_COL2_ALT2,LCD_DATA04_ALT0" line.long 0x18 "DATA05,Data 5 Select Input Register" bitfld.long 0x18 0. " DAISY ,Pads involved in Daisy Chain" "KEY_ROW2_ALT2,LCD_DATA05_ALT0" line.long 0x1C "DATA06,Data 6 Select Input Register" bitfld.long 0x1C 0. " DAISY ,Pads involved in Daisy Chain" "KEY_COL3_ALT2,LCD_DATA06_ALT0" line.long 0x20 "DATA07,Data 7 Select Input Register" bitfld.long 0x20 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA07_ALT0,KEY_ROW3_ALT2" line.long 0x24 "DATA08,Data 8 Select Input Register" bitfld.long 0x24 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA08_ALT0,KEY_COL4_ALT2" line.long 0x28 "DATA09,Data 9 Select Input Register" bitfld.long 0x28 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA08_ALT0,KEY_ROW4_ALT2" line.long 0x2C "DATA10,Data 10 Select Input Register" bitfld.long 0x2C 0. " DAISY ,Pads involved in Daisy Chain" "KEY_COL5_ALT2,LCD_DATA10_ALT0" line.long 0x30 "DATA11,Data 11 Select Input Register" bitfld.long 0x30 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA11_ALT0,KEY_ROW5_ALT2" line.long 0x34 "DATA12,Data 12 Select Input Register" bitfld.long 0x34 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA12_ALT0,KEY_COL6_ALT2" line.long 0x38 "DATA13,Data 13 Select Input Register" bitfld.long 0x38 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA13_ALT0,KEY_ROW6_ALT2" line.long 0x3C "DATA14,Data 14 Select Input Register" bitfld.long 0x3C 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA14_ALT0,KEY_COL7_ALT2" line.long 0x40 "DATA15,Data 15 Select Input Register" bitfld.long 0x40 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA15_ALT0,KEY_ROW7_ALT2" line.long 0x44 "DATA16,Data 16 Select Input Register" bitfld.long 0x44 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA16_ALT0,EPDC_PWR_CTRL0_ALT2" line.long 0x48 "DATA17,Data 17 Select Input Register" bitfld.long 0x48 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA17_ALT0,EPDC_PWR_CTRL1_ALT2" line.long 0x4C "DATA18,Data 18 Select Input Register" bitfld.long 0x4C 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA18_ALT0,EPDC_PWR_CTRL2_ALT2" line.long 0x50 "DATA19,Data 19 Select Input Register" bitfld.long 0x50 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA19_ALT0,EPDC_PWR_CTRL3_ALT2" line.long 0x54 "DATA20,Data 20 Select Input Register" bitfld.long 0x54 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA20_ALT0,EPDC_PWR_COM_ALT2" line.long 0x58 "DATA21,Data 21 Select Input Register" bitfld.long 0x58 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA21_ALT0,EPDC_PWR_IRQ_ALT2" line.long 0x5C "DATA22,Data 22 Select Input Register" bitfld.long 0x5C 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA22_ALT0,EPDC_PWR_STAT_ALT2" line.long 0x60 "DATA23,Data 23 Select Input Register" bitfld.long 0x60 0. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA23_ALT0,EPDC_PWR_WAKE_ALT2" tree.end newline width 30. group.long 0x738++0x07 line.long 0x00 "SPDIF_SPDIF_IN1_SELECT_INPUT,SPDIF_SPDIF_IN1 Select Input Register" bitfld.long 0x00 0.--1. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO22_ALT2,SD2_DATA5_ALT4,I2C2_SCL_ALT2,?..." line.long 0x04 "SPDIF_TX_CLK2_SELECT_INPUT,SPDIF_TX_CLK2 Select Input Register" bitfld.long 0x04 0.--1. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO26_ALT6,AUD_MCLK_ALT6,ECSPI2_SCLK_ALT1,?..." newline width 15. tree "UART Select Input Registers" group.long 0x740++0x27 line.long 0x00 "UART1_RTS_B,UART 1 RTS_B Select Input Register" bitfld.long 0x00 0. " DAISY ,Pads involved in Daisy Chain" "I2C1_SCL_ALT1,I2C1_SDA_ALT1" line.long 0x04 "UART1_RX_DATA,UART 1 RX_DATA Select Input Register" bitfld.long 0x04 0. " DAISY ,Pads involved in Daisy Chain" "UART1_RXD_ALT0,UART1_TXD_ALT0" newline line.long 0x08 "UART2_RTS_B,UART 2 RTS_B Select Input Register" bitfld.long 0x08 0.--2. " DAISY ,Pads involved in Daisy Chain" "LCD_VSYNC_ALT4,LCD_RESET_ALT4,SD2_DATA6_ALT2,SD2_DATA7_ALT2,EPDC_DATA14_ALT1,EPDC_DATA15_ALT1,?..." line.long 0x0C "UART2_RX_DATA,UART 2 RX_DATA Select Input Register" bitfld.long 0x0C 0.--2. " DAISY ,Pads involved in Daisy Chain" ",LCD_HSYN_ALT4,SD2_DATA4_ALT2,SD2_DATA5_ALT2,EPDC_DATA12_ALT1,EPDC_DATA13_ALT1,?..." newline line.long 0x10 "UART3_RTS_B,UART 3 RTS_B Select Input Register" bitfld.long 0x10 0.--1. " DAISY ,Pads involved in Daisy Chain" "ECSPI2_MISO_ALT2,ECSPI2_SS0_ALT2,EPDC_BDR0_ALT2,EPDC_BDR1_ALT2" line.long 0x14 "UART3_RX_DATA,UART 3 RX_DATA Select Input Register" bitfld.long 0x14 0.--2. " DAISY ,Pads involved in Daisy Chain" "AUD_RXFS_ALT2,AUD_RXC_ALT2,ECSPI2_SCLK_ALT2,ECSPI2_MOSI_ALT2,EPDC_VCOM0_ALT2,EPDC_VCOM1_ALT2,?..." newline line.long 0x18 "UART4_RTS_B,UART 4 RTS_B Select Input Register" bitfld.long 0x18 0.--2. " DAISY ,Pads involved in Daisy Chain" "AUD_TXFS_ALT2,AUD_TXD_ALT2,KEY_COL7_ALT1,KEY_ROW7_ALT1,SD1_DATA6_AL4,SD1_DATA7_ALT4,?..." line.long 0x1C "UART4_RX_DATA,UART 4 RX_DATA Select Input Register" bitfld.long 0x1C 0.--2. " DAISY ,Pads involved in Daisy Chain" "AUD_RXD_ALT2,AUD_TXC_ALT2,KEY_COL6_ALT1,KEY_ROW6_ALT1,UART1_RXD_ALT2,UART1_TXD_ALT2,SD1_DATA4_ALT4,SD1_DATA5_ALT4" newline line.long 0x20 "UART5_RTS_B,UART 5 RTS_B Select Input Register" bitfld.long 0x20 0.--2. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA12_ALT4,LCD_DATA13_ALT4,ECSPI1_MISO_ALT2,ECSPI1_SS0_ALT2,SD2_DATA0_ALT4,SD2_DATA1_ALT4,?..." line.long 0x24 "UART5_RX_DATA,UART 5 RX_DATA Select Input Register" bitfld.long 0x24 0.--2. " DAISY ,Pads involved in Daisy Chain" "LCD_DATA14_ALT4,LCD_DATA15_ALT4,ECSPI1_SCLK_ALT2,ECSPI1_MOSI_ALT2,SD2_DATA2_ALT4,SD2_DATA3_ALT4,UART1_RXD_ALT4,UART1_TXD_ALT4" tree.end newline width 26. group.long 0x768++0x07 line.long 0x00 "USB_OTG2_OC_SELECT_INPUT,USB OTG 2 OC Select Input Register" bitfld.long 0x00 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA2_ALT6,ECSPI1_SCLK_ALT6,ECSPI2_SCLK_ALT6,KEY_ROW5_ALT6" line.long 0x04 "USB_OTG1_OC_SELECT_INPUT,USB OTG 1 OC Select Input Register" bitfld.long 0x04 0.--1. " DAISY ,Pads involved in Daisy Chain" "SD3_DATA3_ALT6,ECSPI2_MISO_ALT6,KEY_ROW4_ALT6,?..." newline width 17. tree "USDHC Select Input Registers" group.long 0x770++0x27 line.long 0x00 "USDHC1_CARD_DET,USDHC 1 Card Detection Select Input Register" bitfld.long 0x00 0.--1. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO16_ALT3,KEY_COL0_ALT4,ECSPI2_SS0_ALT4,KEY_ROW7_ALT6" line.long 0x04 "USDHC1_WP_ON,USDHC 1 WP ON Select Input Register" bitfld.long 0x04 0.--1. " DAISY ,Pads involved in Daisy Chain" "GPIO4_IO22_ALT3,KEY_ROW0_ALT4,ECSPI2_MISO_ALT4,KEY_COL7_ALT6" line.long 0x08 "USDHC2_CARD_DET,USDHC 2 Card Detection Select Input Register" bitfld.long 0x08 0.--1. " DAISY ,Pads involved in Daisy Chain" "ECSPI1_SS0_ALT4,SD2_DATA7_ALT4,EPDC_GDSP_ALT6,?..." line.long 0x0C "USDHC1_WP_ON,USDHC 1 WP ON Select Input Register" bitfld.long 0x0C 0.--1. " DAISY ,Pads involved in Daisy Chain" "ECSPI1_MISO_ALT4,SD2_DATA6_ALT4,EPDC_GDRL_ALT6,?..." line.long 0x10 "USDHC3_CARD_DET,USDHC 3 Card Detection Select Input Register" bitfld.long 0x10 0.--1. " DAISY ,Pads involved in Daisy Chain" "REF_CLK_32K_ALT6,GPIO4_IO16_ALT4,EPDC_PWR_WAKE_ALT6,I2C2_SDA_ALT4" line.long 0x14 "USDHC3_DATA4_IN,USDHC 3 DATA 4 In Select Input Register" bitfld.long 0x14 0. " DAISY ,Pads involved in Daisy Chain" "KEY_COL1_ALT4,SD2_DATA4_ALT1" line.long 0x18 "USDHC3_DATA5_IN,USDHC 3 DATA 5 In Select Input Register" bitfld.long 0x18 0. " DAISY ,Pads involved in Daisy Chain" "KEY_ROW1_ALT4,SD2_DATA5_ALT1" line.long 0x1C "USDHC3_DATA6_IN,USDHC 3 DATA In Select Input Register" bitfld.long 0x1C 0. " DAISY ,Pads involved in Daisy Chain" "KEY_COL2_ALT4,SD2_DATA6_ALT1" line.long 0x20 "USDHC3_DATA7_IN,USDHC 3 DATA 7 In Select Input Register" bitfld.long 0x20 0. " DAISY ,Pads involved in Daisy Chain" "KEY_ROW2_ALT4,SD2_DATA7_ALT1" line.long 0x24 "USDHC3_WP_ON,USDHC 3 WP ON Select Input Register" bitfld.long 0x24 0.--1. " DAISY ,Pads involved in Daisy Chain" "REF_CLK_24M_ALT6,GPIO4_IO22_ALT4,EPDC_PWR_STAT_ALT6,I2C2_SCL_ALT4" tree.end width 0x0B tree.end tree.end tree "KPP (Keypad Port Registers)" base ad:0x020B8000 width 10. group.word 0x00++0x07 line.word 0x00 "KPCR,Control Register" bitfld.word 0x00 15. " KCO_7 ,Keypad column strobe open-drain enable 7" "Totem pole,Open drain" bitfld.word 0x00 14. " KCO_6 ,Keypad column strobe open-drain enable 6" "Totem pole,Open drain" bitfld.word 0x00 13. " KCO_5 ,Keypad column strobe open-drain enable 5" "Totem pole,Open drain" bitfld.word 0x00 12. " KCO_4 ,Keypad column strobe open-drain enable 4" "Totem pole,Open drain" newline bitfld.word 0x00 11. " KCO_3 ,Keypad column strobe open-drain enable 3" "Totem pole,Open drain" bitfld.word 0x00 10. " KCO_2 ,Keypad column strobe open-drain enable 2" "Totem pole,Open drain" bitfld.word 0x00 9. " KCO_1 ,Keypad column strobe open-drain enable 1" "Totem pole,Open drain" bitfld.word 0x00 8. " KCO_0 ,Keypad column strobe open-drain enable 0" "Totem pole,Open drain" newline bitfld.word 0x00 7. " KRE_7 ,Keypad row enable 7" "Not included,Included" bitfld.word 0x00 6. " KRE_6 ,Keypad row enable 6" "Not included,Included" bitfld.word 0x00 5. " KRE_5 ,Keypad row enable 5" "Not included,Included" bitfld.word 0x00 4. " KRE_4 ,Keypad row enable 4" "Not included,Included" newline bitfld.word 0x00 3. " KRE_3 ,Keypad row enable 3" "Not included,Included" bitfld.word 0x00 2. " KRE_2 ,Keypad row enable 2" "Not included,Included" bitfld.word 0x00 1. " KRE_1 ,Keypad row enable 1" "Not included,Included" bitfld.word 0x00 0. " KRE_0 ,Keypad row enable 0" "Not included,Included" line.word 0x02 "KPSR,Status Register" bitfld.word 0x02 9. " KRIE ,Keypad release interrupt enable" "No interrupt,Interrupted" bitfld.word 0x02 8. " KDIE ,Keypad key depress interrupt enable" "No interrupt,Interrupted" bitfld.word 0x02 3. " KRSS ,Key release synchronizer set" "No effect,Release" bitfld.word 0x02 2. " KDSC ,Key depress synchronizer clear" "No effect,Clear" newline eventfld.word 0x02 1. " KPKR ,Keypad key release" "Not released,Released" eventfld.word 0x02 0. " KPKD ,Keypad key depress" "Not pressed,Depressed" line.word 0x04 "KDDR,Data Direction Register" bitfld.word 0x04 15. " KCCD_7 ,Keypad column data direction register 7" "Input,Output" bitfld.word 0x04 14. " KCCD_6 ,Keypad column data direction register 6" "Input,Output" bitfld.word 0x04 13. " KCCD_5 ,Keypad column data direction register 5" "Input,Output" bitfld.word 0x04 12. " KCCD_4 ,Keypad column data direction register 4" "Input,Output" newline bitfld.word 0x04 11. " KCCD_3 ,Keypad column data direction register 3" "Input,Output" bitfld.word 0x04 10. " KCCD_2 ,Keypad column data direction register 2" "Input,Output" bitfld.word 0x04 9. " KCCD_1 ,Keypad column data direction register 1" "Input,Output" bitfld.word 0x04 8. " KCCD_0 ,Keypad column data direction register 0" "Input,Output" newline bitfld.word 0x04 7. " KRDD_7 ,Keypad row data direction 7" "Input,Output" bitfld.word 0x04 6. " KRDD_6 ,Keypad row data direction 6" "Input,Output" bitfld.word 0x04 5. " KRDD_5 ,Keypad row data direction 5" "Input,Output" bitfld.word 0x04 4. " KRDD_4 ,Keypad row data direction 4" "Input,Output" newline bitfld.word 0x04 3. " KRDD_3 ,Keypad row data direction 3" "Input,Output" bitfld.word 0x04 2. " KRDD_2 ,Keypad row data direction 2" "Input,Output" bitfld.word 0x04 1. " KRDD_1 ,Keypad row data direction 1" "Input,Output" bitfld.word 0x04 0. " KRDD_0 ,Keypad row data direction 0" "Input,Output" line.word 0x06 "KPDR,Data Register" bitfld.word 0x06 15. " KCD_7 ,Keypad column data 7" "Low,High" bitfld.word 0x06 14. " KCD_6 ,Keypad column data 6" "Low,High" bitfld.word 0x06 13. " KCD_5 ,Keypad column data 5" "Low,High" bitfld.word 0x06 12. " KCD_4 ,Keypad column data 4" "Low,High" newline bitfld.word 0x06 11. " KCD_3 ,Keypad column data 3" "Low,High" bitfld.word 0x06 10. " KCD_2 ,Keypad column data 2" "Low,High" bitfld.word 0x06 9. " KCD_1 ,Keypad column data 1" "Low,High" bitfld.word 0x06 8. " KCD_0 ,Keypad column data 0" "Low,High" newline bitfld.word 0x06 7. " KRD_7 ,Keypad row data 7" "Low,High" bitfld.word 0x06 6. " KRD_6 ,Keypad row data 6" "Low,High" bitfld.word 0x06 5. " KRD_5 ,Keypad row data 5" "Low,High" bitfld.word 0x06 4. " KRD_4 ,Keypad row data 4" "Low,High" newline bitfld.word 0x06 3. " KRD_3 ,Keypad row data 3" "Low,High" bitfld.word 0x06 2. " KRD_2 ,Keypad row data 2" "Low,High" bitfld.word 0x06 1. " KRD_1 ,Keypad row data 1" "Low,High" bitfld.word 0x06 0. " KRD_0 ,Keypad row data 0" "Low,High" width 0x0B tree.end tree "MMDC (Multi Mode DDR Controller)" base ad:0x021B0000 width 13. if (((per.l(ad:0x021B0000+0x18))&0x18)==0x08) group.long 0x00++0x07 line.long 0x00 "MDCTL,MMDC Core Control Register" bitfld.long 0x00 31. " SDE_0 ,MMDC enable CS0" "Disabled,Enabled" bitfld.long 0x00 30. " SDE_1 ,MMDC enable CS1" "Disabled,Enabled" newline bitfld.long 0x00 24.--26. " ROW ,Row address width" "11-bits,12-bits,13-bits,14-bits,15-bits,16-bits,?..." bitfld.long 0x00 20.--22. " COL ,Column address width" "9-bits,10-bits,11-bits,8-bits,12-bits,?..." newline bitfld.long 0x00 19. " BL ,Burst length" "4,8" bitfld.long 0x00 16.--17. " DSIZ ,DDR data bus size" "16-bit,32-bit,?..." line.long 0x04 "MDPDC,MMDC Core Power Down Control Register" bitfld.long 0x04 28.--30. " PRCT_1 ,Precharge timer - chip select 1" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x04 24.--26. " PRCT_0 ,Precharge timer - chip select 0" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" newline bitfld.long 0x04 16.--18. " TCKE ,CKE minimum pulse width" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 12.--15. " PWDT_1 ,Power down timer - chip select 1" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,?..." newline bitfld.long 0x04 8.--11. " PWDT_0 ,Power down timer - chip select 0" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,?..." bitfld.long 0x04 7. " SLOW_PD ,Slow/fast power down" "Fast,Slow" newline bitfld.long 0x04 6. " BOTH_CS_PD ,Both chip selects power-down" "Independently,Both" bitfld.long 0x04 3.--5. " TCKSRX ,Valid clock requirement before self-refresh exit" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" newline bitfld.long 0x04 0.--2. " TCKSRE ,Valid clock requirement after self-refresh entry" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" hgroup.long 0x08++0x03 hide.long 0x00 "MDOTC,MMDC Core ODT Timing Control Register" group.long 0x0C++0x17 line.long 0x00 "MDCFG0,MMDC Core Timing Configuration Register 0" hexmask.long.byte 0x00 24.--31. 1. " TRFC ,Refresh command to active or refresh command time" hexmask.long.byte 0x00 16.--23. 1. " TXS ,Exit self refresh to non READ command" newline bitfld.long 0x00 13.--15. " TXP ,Exit power-down to next valid command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 4.--8. " TFAW ,Four active window" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" newline bitfld.long 0x00 0.--3. " TRL ,CAS read latency" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,?..." line.long 0x04 "MDCFG1,MMDC Core Timing Configuration Register 1" bitfld.long 0x04 29.--31. " TRCD_LP ,Active command to internal read or write delay time" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x04 26.--28. " TRPPB_LP ,Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" newline bitfld.long 0x04 21.--25. " TRC_LP ,Active to active or refresh command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 cloks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x04 16.--20. " TRAS ,Active to precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,?..." newline bitfld.long 0x04 15. " TRPAB_LP ,Precharge-all command period" "TRP,TRP+1" bitfld.long 0x04 9.--11. " TWR ,WRITE recovery time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" newline bitfld.long 0x04 5.--8. " TMRD ,Mode register set command cycle" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x04 0.--2. " WL ,CAS write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,?..." line.long 0x08 "MDCFG2,MMDC Core Timing Configuration Register 2" bitfld.long 0x08 6.--8. " TRTP ,Internal READ command to precharge command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x08 3.--5. " TWTR ,Internal WRITE to READ command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" newline bitfld.long 0x08 0.--2. " TRRD ,ACTIVE to ACTIVE command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,?..." line.long 0x0C "MDMISC,MMDC Core Miscellaneous Register" rbitfld.long 0x0C 31. " CS0_RDY ,External status device on CS0" "Wake-up,Ready" rbitfld.long 0x0C 30. " CS1_RDY ,External status device on CS1" "Wake-up,Ready" newline bitfld.long 0x0C 21. " CK1_GATING ,Gating the secondary DDR clock" "Not gated,Gated" bitfld.long 0x0C 20. " CALIB_PER_CS ,Defines the CS number that the associated calibration is targeted" "CS0,CS1" newline bitfld.long 0x0C 18. " LHD ,Latency hiding disable" "No,Yes" bitfld.long 0x0C 16.--17. " WALAT ,Write additional latency" "Not required,1 cycles,2 cycles,3 cycles" newline bitfld.long 0x0C 12. " BI_ON ,Bank interleaving on" "Not interleaved,Interleaved" bitfld.long 0x0C 11. " LPDDR2_S2 ,LPDDR2 S2 device type indication" "LPDDR2-S4,LPDDR2-S2" newline bitfld.long 0x0C 9.--10. " MIF3_MODE ,Command prediction working mode" "Disabled,First pipe line stage,First pipe line stage/axi bus,First pipe line stage/axi bus/access queue" newline bitfld.long 0x0C 6.--8. " RALAT ,Read additional latency" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x0C 5. " DDR_4_BANK ,DDR device with 4 Banks" "8 banks,4 banks" newline bitfld.long 0x0C 3.--4. " DDR_TYPE ,DDR TYPE" "DDR3,LPDDR2,?..." bitfld.long 0x0C 2. " LPDDR2_2CH ,LPDDR2_2CH" "Low,High" newline bitfld.long 0x0C 1. " RST ,Software reset" "No operation,Asserted" line.long 0x10 "MDSCR,MMDC Core Special Command Register" hexmask.long.byte 0x10 24.--31. 1. " MR_OP ,MRW 8 bit operand" hexmask.long.byte 0x10 16.--23. 1. " MR_ADDR , MRR/MRW ADDRESS" newline bitfld.long 0x10 15. " CON_REQ ,Configuration request" "Not requested,Requested" rbitfld.long 0x10 14. " CON_ACK ,Configuration acknowledge" "Forbidden,Permitted" newline rbitfld.long 0x10 10. " MRR_READ_DATA_VALID ,MRR READ DATA VALID" "Cleared,Set" bitfld.long 0x10 9. " WL_EN ,Write level enable" "Disabled,Enabled" newline bitfld.long 0x10 4.--6. " CMD ,Command" "Normal operation,Precharge all,Auto-refresh,MRW Command,ZQ calibration,Precharge all,MRR,?..." bitfld.long 0x10 3. " CMD_CS ,Chip Select" "Low,High" newline bitfld.long 0x10 0.--2. " CMD_BA ,Bank address" "0,1,2,3,4,5,6,7" line.long 0x14 "MDREF,MMDC Core Refresh Control Register" hexmask.long.word 0x14 16.--31. 1. " REF_CNT ,Refresh counter" bitfld.long 0x14 14.--15. " REF_SEL ,Refresh selector" "64KHz,32KHz,REF_CNT,Disabled" newline bitfld.long 0x14 11.--13. " REFR ,Number of refresh commands every refresh cycle" "1 refresh,2 refreshes,3 refreshes,4 refreshes,5 refreshes,6 refreshes,7 refreshes,8 refreshes" bitfld.long 0x14 0. " START_REF ,Start Refresh cycle" "No operation,Started" group.long 0x2C++0x7 line.long 0x00 "MDRWD,MMDC Core Read/Write Command Delay Register" hexmask.long.word 0x00 16.--28. 1. " TDAI ,Device auto initialization period" bitfld.long 0x00 12.--14. " RTW_SAME ,Controls the cycles delay between Read to Write commands in same chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" newline bitfld.long 0x00 9.--11. " WTR_DIFF ,Controls the cycles delay between Write to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 6.--8. " WTW_DIFF ,Controls the cycles delay between Write to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" newline bitfld.long 0x00 3.--5. " RTW_DIFF ,Controls the cycles delay between Read to Write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--2. " RTR_DIFF ,Controls the cycles delay between Read to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" line.long 0x04 "MDOR,MMDC Core Out of Reset Delays Register" bitfld.long 0x04 0.--5. " RST_TO_CKE ,Idle time after first CKE assertion" ",,,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles" newline width 13. rgroup.long 0x34++0x03 line.long 0x00 "MDMRR,MMDC Core MRR Data Register" hexmask.long.byte 0x00 24.--31. 1. " MRR_READ_DATA3 ,MRR DATA that arrived on DQ[31:24]" hexmask.long.byte 0x00 16.--23. 1. " MRR_READ_DATA2 ,MRR DATA that arrived on DQ[23:16]" hexmask.long.byte 0x00 8.--15. 1. " MRR_READ_DATA1 ,MRR DATA that arrived on DQ[15:8]" newline hexmask.long.byte 0x00 0.--7. 1. " MRR_READ_DATA0 ,MRR DATA that arrived on DQ[7:0]" group.long 0x38++0x0B line.long 0x00 "MDCFG3LP,MMDC Core Timing Configuration Register 3" bitfld.long 0x00 16.--21. " RC_LP ,ACT to ACT or REF command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks,33 clocks,34 clocks,35 clocks,36 clocks,37 clocks,38 clocks,39 clocks,40 clocks,41 clocks,42 clocks,43 clocks,44 clocks,45 clocks,46 clocks,47 clocks,48 clocks,49 clocks,50 clocks,51 clocks,52 clocks,53 clocks,54 clocks,55 clocks,56 clocks,57 clocks,58 clocks,59 clocks,60 clocks,61 clocks,62 clocks,63 clocks,?..." bitfld.long 0x00 8.--11. " TRCD_LP ,ACT command to internal read or write delay time" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,?..." bitfld.long 0x00 4.--7. " TRPPB_LP ,PRECHARGE (per bank) command period (same bank)" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,?..." newline bitfld.long 0x00 0.--3. " TRPAB_LP ,PRECHARGE (all banks) command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,?..." line.long 0x04 "MDMR4,MMDC Core MR4 Derating Register" bitfld.long 0x04 8. " TRRD_DE ,TRRD derating value" "None,1 cycle" bitfld.long 0x04 7. " TRP_DE ,TRP derating value" "None,1 cycle" bitfld.long 0x04 6. " TRAS_DE ,TRAS derating value" "None,1 cycle" newline bitfld.long 0x04 5. " TRC_DE ,TRC derating value" "None,1 cycle" bitfld.long 0x04 4. " TRCD_DE ,TRCD derating value" "None,1 cycle" rbitfld.long 0x04 1. " UPDATE_DE_ACK ,Update derated values acknowledge" "No update,Updated" newline bitfld.long 0x04 0. " UPDATE_DE_REQ ,Update derated values request" "No operation,Requested" line.long 0x08 "MDASP,MMDC Core Address Space Partition Register" hexmask.long.byte 0x08 0.--6. 1. " CS0_END ,Define the absolute last address associated with CS0" group.long 0x400++0x0F line.long 0x00 "MAARCR,MMDC Core AXI Re-ordering Control Register" bitfld.long 0x00 31. " ARCR_SEC_ERR_LOCK ,ARCR_SEC_ERR_EN lock" "Unlocked,Locked" bitfld.long 0x00 30. " ARCR_SEC_ERR_EN ,Security read/write access violation in OKAY/SLV Error response " "OKAY,SLAVE error" bitfld.long 0x00 28. " ARCR_EXC_ERR_EN ,Exclusive read/write access violation of AXI 6.2.4 rule in OKAY/SLV Error response " "OKAY,SLAVE error" newline bitfld.long 0x00 24. " ARCR_RCH_EN ,Real time channel enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ARCR_PAG_HIT ,ARCR page hit rate" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " ARCR_ACC_HIT ,ARCR access hit rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--11. " ARCR_DYN_JMP ,ARCR dynamic jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ARCR_DYN_MAX ,ARCR dynamic maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARCR_GUARD ,ARCR guard" "15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30" line.long 0x04 "MAPSR,MMDC Core Power Saving Control and Status Register" rbitfld.long 0x04 25. " DVACK ,General DVFS acknowledge" "Not asserted,Asserted" rbitfld.long 0x04 24. " LPACK ,General low-power acknowledge" "Not asserted,Asserted" bitfld.long 0x04 21. " DVFS ,General DVFS request" "Not requested,Requested" newline bitfld.long 0x04 20. " LPMD ,General LPMD request" "Not requested,Requested" hexmask.long.byte 0x04 8.--15. 1. " PST ,Automatic power saving timer" rbitfld.long 0x04 6. " WIS ,Write idle Status" "Idle,Not Idle" newline rbitfld.long 0x04 5. " RIS ,Read idle status" "Idle,Not Idle" rbitfld.long 0x04 4. " PSS ,Power saving status" "Disabled,Enabled" bitfld.long 0x04 0. " PSD ,Automatic power saving disable" "No,Yes" line.long 0x08 "MAEXIDR0,MMDC Core Exclusive ID Monitor Register 0" hexmask.long.word 0x08 16.--31. 1. " EXC_ID_MONITOR1 ,Defines ID for exclusive monitor #1" hexmask.long.word 0x08 0.--15. 1. " EXC_ID_MONITOR0 ,Defines ID for exclusive monitor #0" line.long 0x0C "MAEXIDR1,MMDC Core Exclusive ID Monitor Register 1" hexmask.long.word 0x0C 16.--31. 1. " EXC_ID_MONITOR3 ,Defines ID for exclusive monitor #3" hexmask.long.word 0x0C 0.--15. 1. " EXC_ID_MONITOR2 ,Defines ID for exclusive monitor #2" group.long 0x410++0x07 line.long 0x00 "MADPCR0,MMDC Core Debug and Profiling Control Register 0" bitfld.long 0x00 9. " SBS ,Step by step trigger" "Not launched,Launched" bitfld.long 0x00 8. " SBS_EN ,Step by step debug enable" "Disabled,Enabled" eventfld.long 0x00 3. " CYC_OVF ,Total cycles count overflow" "No overflow,Overflow" newline bitfld.long 0x00 2. " PRF_FRZ ,Profiling freeze" "Not frozen,Frozen" bitfld.long 0x00 1. " DBG_RST ,Debug and profiling reset" "No reset,Reset" bitfld.long 0x00 0. " DBG_EN ,Debug and profiling enable" "Disabled,Enabled" newline line.long 0x04 "MADPCR1,MMDC Core Debug and Profiling Control Register 1" bitfld.long 0x04 31. " PRF_AXI_ID_MASK_31 ,Profiling AXI ID mask 31" "Masked,Not masked" bitfld.long 0x04 30. " PRF_AXI_ID_MASK_30 ,Profiling AXI ID mask 30" "Masked,Not masked" bitfld.long 0x04 29. " PRF_AXI_ID_MASK_29 ,Profiling AXI ID mask 29" "Masked,Not masked" newline bitfld.long 0x04 28. " PRF_AXI_ID_MASK_28 ,Profiling AXI ID mask 28" "Masked,Not masked" bitfld.long 0x04 27. " PRF_AXI_ID_MASK_27 ,Profiling AXI ID mask 27" "Masked,Not masked" bitfld.long 0x04 26. " PRF_AXI_ID_MASK_26 ,Profiling AXI ID mask 26" "Masked,Not masked" newline bitfld.long 0x04 25. " PRF_AXI_ID_MASK_25 ,Profiling AXI ID mask 25" "Masked,Not masked" bitfld.long 0x04 24. " PRF_AXI_ID_MASK_24 ,Profiling AXI ID mask 24" "Masked,Not masked" bitfld.long 0x04 23. " PRF_AXI_ID_MASK_23 ,Profiling AXI ID mask 23" "Masked,Not masked" newline bitfld.long 0x04 22. " PRF_AXI_ID_MASK_22 ,Profiling AXI ID mask 22" "Masked,Not masked" bitfld.long 0x04 21. " PRF_AXI_ID_MASK_21 ,Profiling AXI ID mask 21" "Masked,Not masked" bitfld.long 0x04 20. " PRF_AXI_ID_MASK_20 ,Profiling AXI ID mask 20" "Masked,Not masked" newline bitfld.long 0x04 19. " PRF_AXI_ID_MASK_19 ,Profiling AXI ID mask 19" "Masked,Not masked" bitfld.long 0x04 18. " PRF_AXI_ID_MASK_18 ,Profiling AXI ID mask 18" "Masked,Not masked" bitfld.long 0x04 17. " PRF_AXI_ID_MASK_17 ,Profiling AXI ID mask 17" "Masked,Not masked" newline bitfld.long 0x04 16. " PRF_AXI_ID_MASK_16 ,Profiling AXI ID mask 16" "Masked,Not masked" bitfld.long 0x04 15. " PRF_AXI_ID[15] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 14. " PRF_AXI_ID[14] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 13. " PRF_AXI_ID[13] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 12. " PRF_AXI_ID[12] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 11. " PRF_AXI_ID[11] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 10. " PRF_AXI_ID[10] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 9. " PRF_AXI_ID[9] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 8. " PRF_AXI_ID[8] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 7. " PRF_AXI_ID[7] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 6. " PRF_AXI_ID[6] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 5. " PRF_AXI_ID[5] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 4. " PRF_AXI_ID[4] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 3. " PRF_AXI_ID[3] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 2. " PRF_AXI_ID[2] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 1. " PRF_AXI_ID[1] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 0. " PRF_AXI_ID[0] ,Profiling AXI ID" "Low,High" rgroup.long 0x418++0x1F line.long 0x00 "MADPSR0,MMDC Core Debug and Profiling Status Register 0" line.long 0x04 "MADPSR1,MMDC Core Debug and Profiling Status Register 1" line.long 0x08 "MADPSR2,MMDC Core Debug and Profiling Status Register 2" line.long 0x0C "MADPSR3,MMDC Core Debug and Profiling Status Register 3" line.long 0x10 "MADPSR4,MMDC Core Debug and Profiling Status Register 4" line.long 0x14 "MADPSR5,MMDC Core Debug and Profiling Status Register 5" line.long 0x18 "MASBS0,MMDC Core Step By Step Address" line.long 0x1C "MASBS1,MMDC Core Step By Step Address Attributes" hexmask.long.word 0x1C 16.--31. 1. " SBS_AXI_ID ,Step by step AXI ID" bitfld.long 0x1C 13.--15. " SBS_LEN ,Step by step length" "1,2,3,4,5,6,7,8" bitfld.long 0x1C 12. " SBS_BUFF ,Step by step buffered" "Low,High" newline bitfld.long 0x1C 10.--11. " SBS_BURST ,Step by step burst" "Fixed,INCR,WRAP,?..." bitfld.long 0x1C 7.--9. " SBS_SIZE ,Step by step size" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x1C 4.--6. " SBS_PROT ,Step by step protection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 2.--3. " SBS_LOCK ,Step by step lock" "0,1,2,3" bitfld.long 0x1C 1. " SBS_TYPE ,Step by step request type" "Write,Read" bitfld.long 0x1C 0. " SBS_VLD ,Step by step valid" "Not valid,Valid" group.long 0x440++0x03 line.long 0x00 "MAGENP,MMDC Core General Purpose Register" bitfld.long 0x00 31. " GP31 ,General purpose read/write bit 31" "Low,High" bitfld.long 0x00 30. " GP30 ,General purpose read/write bit 30" "Low,High" bitfld.long 0x00 29. " GP29 ,General purpose read/write bit 29" "Low,High" newline bitfld.long 0x00 28. " GP28 ,General purpose read/write bit 28" "Low,High" bitfld.long 0x00 27. " GP27 ,General purpose read/write bit 27" "Low,High" bitfld.long 0x00 26. " GP26 ,General purpose read/write bit 26" "Low,High" newline bitfld.long 0x00 25. " GP25 ,General purpose read/write bit 25" "Low,High" bitfld.long 0x00 24. " GP24 ,General purpose read/write bit 24" "Low,High" bitfld.long 0x00 23. " GP23 ,General purpose read/write bit 23" "Low,High" newline bitfld.long 0x00 22. " GP22 ,General purpose read/write bit 22" "Low,High" bitfld.long 0x00 21. " GP21 ,General purpose read/write bit 21" "Low,High" bitfld.long 0x00 20. " GP20 ,General purpose read/write bit 20" "Low,High" newline bitfld.long 0x00 19. " GP19 ,General purpose read/write bit 19" "Low,High" bitfld.long 0x00 18. " GP18 ,General purpose read/write bit 18" "Low,High" bitfld.long 0x00 17. " GP17 ,General purpose read/write bit 17" "Low,High" newline bitfld.long 0x00 16. " GP16 ,General purpose read/write bit 16" "Low,High" bitfld.long 0x00 15. " GP15 ,General purpose read/write bit 15" "Low,High" bitfld.long 0x00 14. " GP14 ,General purpose read/write bit 14" "Low,High" newline bitfld.long 0x00 13. " GP13 ,General purpose read/write bit 13" "Low,High" bitfld.long 0x00 12. " GP12 ,General purpose read/write bit 12" "Low,High" bitfld.long 0x00 11. " GP11 ,General purpose read/write bit 11" "Low,High" newline bitfld.long 0x00 10. " GP10 ,General purpose read/write bit 10" "Low,High" bitfld.long 0x00 9. " GP9 ,General purpose read/write bit 9" "Low,High" bitfld.long 0x00 8. " GP8 ,General purpose read/write bit 8" "Low,High" newline bitfld.long 0x00 7. " GP7 ,General purpose read/write bit 7" "Low,High" bitfld.long 0x00 6. " GP6 ,General purpose read/write bit 6" "Low,High" bitfld.long 0x00 5. " GP5 ,General purpose read/write bit 5" "Low,High" newline bitfld.long 0x00 4. " GP4 ,General purpose read/write bit 4" "Low,High" bitfld.long 0x00 3. " GP3 ,General purpose read/write bit 3" "Low,High" bitfld.long 0x00 2. " GP2 ,General purpose read/write bit 2" "Low,High" newline bitfld.long 0x00 1. " GP1 ,General purpose read/write bit 1" "Low,High" bitfld.long 0x00 0. " GP0 ,General purpose read/write bit 0" "Low,High" group.long 0x800++0x13 line.long 0x00 "MPZQHWCTRL,MMDC PHY ZQ HW Control Register" bitfld.long 0x00 27.--31. " ZQ_EARLY_COMPARATOR_EN_TIMER ,ZQ early comparator enable timer" ",,,,,,,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" bitfld.long 0x00 23.--25. " TZQ_CS ,Device ZQ short time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." bitfld.long 0x00 20.--22. " TZQ_OPER ,Device ZQ long/oper time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." newline bitfld.long 0x00 17.--19. " TZQ_INIT ,Device ZQ long/init time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." bitfld.long 0x00 16. " ZQ_HW_FOR ,Force ZQ automatic calibration process with the i.MX ZQ calibration pad" "Not forced,Forced" rbitfld.long 0x00 11.--15. " ZQ_HW_PD_RES ,ZQ HW calibration pull-down result" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 6.--10. " ZQ_HW_PU_RES ,ZQ automatic calibration pull-up result" "0 (minimum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--5. " ZQ_HW_PER ,ZQ periodic calibration time" "1 ms,2 ms,4 ms,8 ms,16 ms,32 ms,64 ms,128 ms,256 ms,512 ms,1 sec,2 sec,4 sec,8 sec,16 sec,32 sec" newline bitfld.long 0x00 0.--1. " ZQ_MODE ,ZQ calibration mode" "Not issued,i.MX ZQ calibration pad/External DDR (when exiting),External DDR,i.MX ZQ calibration pad/External DDR (periodic/when exiting)" line.long 0x04 "MPZQSWCTRL,MMDC PHY ZQ SW control register" bitfld.long 0x04 16.--17. " ZQ_CMP_OUT_SMP ,Amount of cycles between driving the ZQ signals to the ZQ pad" "7 cycles,15 cycles,23 cycles,31 cycles" newline bitfld.long 0x04 13. " USE_ZQ_SW_VAL ,Use SW ZQ configured value for I/O pads resistor controls" "ZQ_HW_PD_VAL & ZQ_HW_PU_VAL,ZQ_SW_PD_VAL & ZQ_SW_PU_VAL" newline bitfld.long 0x04 12. " ZQ_SW_PD ,ZQ software PU/PD calibration" "PU,PD" newline bitfld.long 0x04 7.--11. " ZQ_SW_PD_VAL ,ZQ software pull-down resistence" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 2.--6. " ZQ_SW_PU_VAL ,ZQ software pull-up resistence" "0 (minimum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 1. " ZQ_SW_RES ,ZQ software calibration result" "VDD/2" newline bitfld.long 0x04 0. " ZQ_SW_FOR ,Force ZQ SW calibration" "Not forced,Forced" line.long 0x08 "MPWLGCR0,MMDC PHY Write Leveling Error Status Register 0" rbitfld.long 0x08 11. " WL_HW_ERR3 ,Byte3 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x08 10. " WL_HW_ERR2 ,Byte2 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x08 9. " WL_HW_ERR1 ,Byte1 write-leveling HW calibration error" "No error,Error" newline rbitfld.long 0x08 8. " WL_HW_ERR0 ,Byte0 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x08 7. " WL_SW_RES3 ,Byte3 write-leveling software result" "Low,High" rbitfld.long 0x08 6. " WL_SW_RES2 ,Byte2 write-leveling software result" "Low,High" newline rbitfld.long 0x08 5. " WL_SW_RES1 ,Byte1 write-leveling software result" "Low,High" rbitfld.long 0x08 4. " WL_SW_RES0 ,Byte0 write-leveling software result" "Low,High" bitfld.long 0x08 2. " SW_WL_CNT_EN ,SW WL count down enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " SW_WL_EN ,Enable WL SW update" "Disabled,Enabled" bitfld.long 0x08 0. " HW_WL_EN ,Enable WL HW enable" "Disabled,Enabled" line.long 0x0C "MPWLDECTRL0,MMDC PHY Write Leveling Delay Control Register 0" bitfld.long 0x0C 25.--26. " WL_CYC_DEL1 ,Write level cycle delay for Byte 1" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x0C 24. " WL_HC_DEL1 ,Write level half cycle delay for Byte 1" "No delay,Half cycle" hexmask.long.byte 0x0C 16.--22. 1. " WR_DL_ABS_OFFSET1 ,Absolute write-leveling delay offset for Byte 1" newline bitfld.long 0x0C 9.--10. " WL_CYC_DEL0 ,Write level cycle delay for Byte 0" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x0C 8. " WL_HC_DEL0 ,Write level half cycle delay for Byte 0" "No delay,Half cycle" hexmask.long.byte 0x0C 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute write-leveling delay offset for Byte 0" line.long 0x10 "MPWLDECTRL1,MMDC PHY Write Leveling Delay Control Register 1" bitfld.long 0x10 25.--26. " WL_CYC_DEL3 ,Write level cycle delay for Byte 3" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x10 24. " WL_HC_DEL3 ,Write level half cycle delay for Byte 3" "No delay,Half cycle" hexmask.long.byte 0x10 16.--22. 1. " WR_DL_ABS_OFFSET3 ,Absolute delay offset for Byte 3" newline bitfld.long 0x10 9.--10. " WL_CYC_DEL2 ,Write level cycle delay for Byte 2" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x10 8. " WL_HC_DEL2 ,Write level half cycle delay for Byte 2" "No delay,Half cycle" hexmask.long.byte 0x10 0.--6. 1. " WR_DL_ABS_OFFSET2 ,Absolute delay offset for Byte 2" rgroup.long 0x814++0x03 line.long 0x00 "MPWLDLST,MMDC PHY Write Leveling Delay Line Status Register" hexmask.long.byte 0x00 24.--30. 1. " WL_DL_UNIT_NUM3 ,Number of delay units that is actually used by write leveling delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WL_DL_UNIT_NUM2 ,Number of delay units that is actually used by write leveling delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WL_DL_UNIT_NUM1 ,Number of delay units that is actually used by write leveling delay line 1" newline hexmask.long.byte 0x00 0.--6. 1. " WL_DL_UNIT_NUM0 ,Number of delay units that is actually used by write leveling delay line 0" group.long 0x81C++0x1F line.long 0x00 "MPRDDQBY0DL,MMDC PHY Read DQ Byte0 Delay Register" bitfld.long 0x00 28.--30. " RD_DQ7_DEL ,Read dqs0 to dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 24.--26. " RD_DQ6_DEL ,Read dqs0 to dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 20.--22. " RD_DQ5_DEL ,Read dqs0 to dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x00 16.--18. " RD_DQ4_DEL ,Read dqs0 to dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 12.--14. " RD_DQ3_DEL ,Read dqs0 to dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 8.--10. " RD_DQ2_DEL ,Read dqs0 to dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x00 4.--6. " RD_DQ1_DEL ,Read dqs0 to dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x00 0.--2. " RD_DQ0_DEL ,Read dqs0 to dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x04 "MPRDDQBY1DL,MMDC PHY Read DQ Byte1 Delay Register" bitfld.long 0x04 28.--30. " RD_DQ15_DEL ,Read dqs1 to dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 24.--26. " RD_DQ14_DEL ,Read dqs1 to dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 20.--22. " RD_DQ13_DEL ,Read dqs1 to dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x04 16.--18. " RD_DQ12_DEL ,Read dqs1 to dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 12.--14. " RD_DQ11_DEL ,Read dqs1 to dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 8.--10. " RD_DQ10_DEL ,Read dqs1 to dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x04 4.--6. " RD_DQ9_DEL ,Read dqs1 to dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 0.--2. " RD_DQ8_DEL ,Read dqs1 to dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x08 "MPRDDQBY2DL,MMDC PHY Read DQ Byte2 Delay Register" bitfld.long 0x08 28.--30. " RD_DQ23_DEL ,Read dqs2 to dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 24.--26. " RD_DQ22_DEL ,Read dqs2 to dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 20.--22. " RD_DQ21_DEL ,Read dqs2 to dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x08 16.--18. " RD_DQ20_DEL ,Read dqs2 to dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 12.--14. " RD_DQ19_DEL ,Read dqs2 to dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 8.--10. " RD_DQ18_DEL ,Read dqs2 to dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x08 4.--6. " RD_DQ17_DEL ,Read dqs2 to dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 0.--2. " RD_DQ16_DEL ,Read dqs2 to dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x0C "MPRDDQBY3DL,MMDC PHY Read DQ Byte3 Delay Register" bitfld.long 0x0C 28.--30. " RD_DQ31_DEL ,Read dqs3 to dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 24.--26. " RD_DQ30_DEL ,Read dqs3 to dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 20.--22. " RD_DQ29_DEL ,Read dqs3 to dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x0C 16.--18. " RD_DQ28_DEL ,Read dqs3 to dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 12.--14. " RD_DQ27_DEL ,Read dqs3 to dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 8.--10. " RD_DQ26_DEL ,Read dqs3 to dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x0C 4.--6. " RD_DQ25_DEL ,Read dqs3 to dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 0.--2. " RD_DQ24_DEL ,Read dqs3 to dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x10 "MPWRDQBY0DL,MMDC PHY Write DQ Byte0 Delay Register" bitfld.long 0x10 30.--31. " WR_DM0_DEL ,Write dm0 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 28.--29. " WR_DQ7_DEL ,Write dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 24.--25. " WR_DQ6_DEL ,Write dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x10 20.--21. " WR_DQ5_DEL ,Write dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 16.--17. " WR_DQ4_DEL ,Write dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 12.--13. " WR_DQ3_DEL ,Write dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x10 8.--9. " WR_DQ2_DEL ,Write dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 4.--5. " WR_DQ1_DEL ,Write dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x10 0.--1. " WR_DQ0_DEL ,Write dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x14 "MPWRDQBY1DL,MMDC PHY Write DQ Byte1 Delay Register" bitfld.long 0x14 30.--31. " WR_DM1_DEL ,Write dm1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 28.--29. " WR_DQ15_DEL ,Write dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 24.--25. " WR_DQ14_DEL ,Write dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x14 20.--21. " WR_DQ13_DEL ,Write dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 16.--17. " WR_DQ12_DEL ,Write dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 12.--13. " WR_D11_DEL ,Write dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x14 8.--9. " WR_DQ10_DEL ,Write dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 4.--5. " WR_DQ9_DEL ,Write dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 0.--1. " WR_DQ8_DEL ,Write dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x18 "MPWRDQBY2DL, MMDC PHY Write DQ Byte2 Delay Register" bitfld.long 0x18 30.--31. " WR_DM2_DEL ,Write dm2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 28.--29. " WR_DQ23_DEL ,Write dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 24.--25. " WR_DQ22_DEL ,Write dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x18 20.--21. " WR_DQ21_DEL ,Write dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 16.--17. " WR_DQ20_DEL ,Write dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 12.--13. " WR_D19_DEL ,Write dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x18 8.--9. " WR_DQ18_DEL ,Write dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 4.--5. " WR_DQ17_DEL ,Write dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 0.--1. " WR_DQ16_DEL ,Write dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x1C "MPWRDQBY3DL, MMDC PHY Write DQ Byte3 Delay Register" bitfld.long 0x1C 30.--31. " WR_DM3_DEL ,Write dm3 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 28.--29. " WR_DQ31_DEL ,Write dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 24.--25. " WR_DQ30_DEL ,Write dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x1C 20.--21. " WR_DQ29_DEL ,Write dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 16.--17. " WR_DQ28_DEL ,Write dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 12.--13. " WR_D27_DEL ,Write dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x1C 8.--9. " WR_DQ26_DEL ,Write dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 4.--5. " WR_DQ25_DEL ,Write dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 0.--1. " WR_DQ24_DEL ,Write dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays" group.long 0x83C++0x07 line.long 0x00 "MPDGCTRL0,MMDC PHY Read DQS gating control register 0" bitfld.long 0x00 31. " RST_RD_FIFO ,Reset read data FIFO & pointers" "No reset,Reset" bitfld.long 0x00 30. " DG_CMP_CYC ,Read DQS gating sample cycle" "16 cycles,32 cycles" bitfld.long 0x00 29. " DG_DIS ,Read DQS gating disable" "No,Yes" newline bitfld.long 0x00 28. " HW_DG_EN ,Enable automatic read DQS gating calibration" "Disabled,Enabled" bitfld.long 0x00 24.--27. " DG_HC_DEL1 ,Read Dqs1 gating half cycles delay for Byte 1" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,?..." bitfld.long 0x00 23. " DG_EXT_UP ,DG extend upper boundary" "Not extended,Extended" newline hexmask.long.byte 0x00 16.--22. 1. " DG_DL_ABS_OFFSET1 ,Absolute delay offset" rbitfld.long 0x00 12. " HW_DG_ERR ,HW DQS gating error" "No error,Error" bitfld.long 0x00 8.--11. " DG_HC_DEL0 ,Read DQS0 gating half cycles delay for Byte 0" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,?..." newline hexmask.long.byte 0x00 0.--6. 1. " DG_DL_ABS_OFFSET0 ,Absolute read DQS gating delay offset" line.long 0x04 "MPDGCTRL1,MMDC PHY Read DQS gating control register 1" bitfld.long 0x04 24.--27. " DG_HC_DEL3 ,Read DQS3 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,?..." hexmask.long.byte 0x04 16.--22. 1. " DG_DL_ABS_OFFSET3 ,Absolute read DQS gating delay offset for Byte 3" bitfld.long 0x04 8.--11. " DG_HC_DEL2 ,Read DQS2 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,?..." newline hexmask.long.byte 0x04 0.--6. 1. " DG_DL_ABS_OFFSET2 ,Absolute read DQS gating delay offset" rgroup.long 0x844++0x03 line.long 0x00 "MPDGDLST0,MMDC PHY Read DQS gating Delay Line Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " DG_DL_UNIT_NUM3 ,Number of delay units that is actually used by DQS gating delay line 3" hexmask.long.byte 0x00 16.--22. 1. " DG_DL_UNIT_NUM2 ,Number of delay units that is actually used by DQS gating delay line 2" hexmask.long.byte 0x00 8.--14. 1. " DG_DL_UNIT_NUM1 ,Number of delay units that is actually used by DQS gating delay line 1" newline hexmask.long.byte 0x00 0.--6. 1. " DG_DL_UNIT_NUM0 ,Number of delay units that is actually used by DQS gating delay line 0" group.long 0x848++0x03 line.long 0x00 "MPRDDLCTL,MMDC PHY Read Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_ABS_OFFSET3 ,Absolute read delay offset byte 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_ABS_OFFSET2 ,Absolute read delay offset byte 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_ABS_OFFSET1 ,Absolute read delay offset byte 1" newline hexmask.long.byte 0x00 0.--6. 1. " RD_DL_ABS_OFFSET0 ,Absolute read delay offset byte 0" rgroup.long 0x84C++0x03 line.long 0x00 "MPRDDLST0,MMDC PHY Read Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_UNIT_NUM3 ,Number of delay units that is actually used by read delay line 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_UNIT_NUM2 ,Number of delay units that is actually used by read delay line 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_UNIT_NUM1 ,Number of delay units that is actually used by read delay line 1" newline hexmask.long.byte 0x00 0.--6. 1. " RD_DL_UNIT_NUM0 ,Number of delay units that is actually used by read delay line 0" group.long 0x850++0x03 line.long 0x00 "MPWRDLCTL0,MMDC PHY Write Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_ABS_OFFSET3 ,Absolute write delay offset for Byte 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_ABS_OFFSET2 ,Absolute write delay offset for Byte 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_ABS_OFFSET1 ,Absolute write delay offset for Byte 1" newline hexmask.long.byte 0x00 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute write delay offset for Byte 30" rgroup.long 0x854++0x03 line.long 0x00 "MPWRDLST0,MMDC PHY Write Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_UNIT_NUM3 ,Number of delay units that is actually used by write delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_UNIT_NUM2 ,Number of delay units that is actually used by write delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_UNIT_NUM1 ,Number of delay units that is actually used by write delay line 1" newline hexmask.long.byte 0x00 0.--6. 1. " WR_DL_UNIT_NUM0 ,Number of delay units that is actually used by write delay line 0" group.long 0x858++0x0F line.long 0x00 "MPSDCTRL,MMDC PHY CK control Register" bitfld.long 0x00 8.--9. " SDCLK1_DEL ,SDCLK0 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x00 10.--11. " SDCLK0_DEL ,SDCLK0 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x04 "MPZQLP2CTL,MMDC PHY ZQ LPDDR2 HW Control Register" hexmask.long.byte 0x04 24.--30. 1. " ZQ_LP2_HW_ZQCS ,Period in cycles that it takes the memory device to perform a Short ZQ calibration" hexmask.long.byte 0x04 16.--23. 1. " ZQ_LP2_HW_ZQCL ,Period in cycles that it takes the memory device to perform a Long ZQ calibration" hexmask.long.word 0x04 0.--8. 1. " ZQ_LP2_HW_ZQINIT ,Period in cycles that it takes the memory device to perform a Init ZQ calibration" line.long 0x08 "MPRDDLHWCTL,MMDC PHY Read Delay HW Calibration Control Register" bitfld.long 0x08 5. " HW_RD_DL_CMP_CYC ,HW RD DL sample cycle" "Not compared,Compared" bitfld.long 0x08 4. " HW_RD_DL_EN ,Enable HW RD DL calibration" "Disabled,Enabled" rbitfld.long 0x08 3. " HW_RD_DL_ERR3 ,HW RD DL3 error" "No error,Error" newline rbitfld.long 0x08 2. " HW_RD_DL_ERR2 ,HW RD DL2 error" "No error,Error" rbitfld.long 0x08 1. " HW_RD_DL_ERR1 ,HW RD DL1 error" "No error,Error" rbitfld.long 0x08 0. " HW_RD_DL_ERR0 ,HW RD DL0 error" "No error,Error" line.long 0x0C "MPWRDLHWCTL,MMDC PHY Write Delay HW Calibration Control Register" bitfld.long 0x0C 5. " HW_WR_DL_CMP_CYC ,HW WR DL sample cycle" "Not compared,Compared" bitfld.long 0x0C 4. " HW_WR_DL_EN ,Enable HW WR DL calibration" "Disabled,Enabled" rbitfld.long 0x0C 3. " HW_WR_DL_ERR3 ,HW WR DL3 error" "No error,Error" newline rbitfld.long 0x0C 2. " HW_WR_DL_ERR2 ,HW WR DL2 error" "No error,Error" rbitfld.long 0x0C 1. " HW_WR_DL_ERR1 ,HW WR DL1 error" "No error,Error" rbitfld.long 0x0C 0. " HW_WR_DL_ERR0 ,HW WR DL0 error" "No error,Error" rgroup.long 0x868++0x13 line.long 0x00 "MPRDDLHWST0,MMDC PHY Read Delay HW Calibration Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " HW_RD_DL_UP1 ,HW RD DL1 upper boundary" hexmask.long.byte 0x00 16.--22. 1. " HW_RD_DL_LOW1 ,HW RD DL1 lower boundary" hexmask.long.byte 0x00 8.--14. 1. " HW_RD_DL_UP0 ,HW RD DL0 upper boundary" newline hexmask.long.byte 0x00 0.--6. 1. " HW_RD_DL_LOW0 ,HW RD DL0 lower boundary" line.long 0x04 "MPRDDLHWST1,MMDC PHY Read Delay HW Calibration Status Register 1" hexmask.long.byte 0x04 24.--30. 1. " HW_RD_DL_UP3 ,HW RD DL3 upper boundary" hexmask.long.byte 0x04 16.--22. 1. " HW_RD_DL_LOW3 ,HW RD DL3 lower boundary" hexmask.long.byte 0x04 8.--14. 1. " HW_RD_DL_UP2 ,HW RD DL2 upper boundary" newline hexmask.long.byte 0x04 0.--6. 1. " HW_RD_DL_LOW2 ,HW RD DL2 lower boundary" line.long 0x08 "MPWRDLHWST0,MMDC PHY Write Delay HW Calibration Status Register 0" hexmask.long.byte 0x08 24.--30. 1. " HW_WR_DL_UP1 ,HW WR DL1 upper boundary" hexmask.long.byte 0x08 16.--22. 1. " HW_WR_DL_LOW1 ,HW WR DL1 lower boundary" hexmask.long.byte 0x08 8.--14. 1. " HW_WR_DL_UP0 ,HW WR DL0 upper boundary" newline hexmask.long.byte 0x08 0.--6. 1. " HW_WR_DL_LOW0 ,HW WR DL0 lower boundary" line.long 0x0C "MPWRDLHWST1,MMDC PHY Write Delay HW Calibration Status Register 1" hexmask.long.byte 0x0C 24.--30. 1. " HW_WR_DL_UP3 ,HW WR DL3 upper boundary" hexmask.long.byte 0x0C 16.--22. 1. " HW_WR_DL_LOW3 ,HW WR DL3 lower boundary" hexmask.long.byte 0x0C 8.--14. 1. " HW_WR_DL_UP2 ,HW WR DL2 upper boundary" newline hexmask.long.byte 0x0C 0.--6. 1. " HW_WR_DL_LOW2 ,HW WR DL2 lower boundary" line.long 0x10 "MPWLHWERR0,MMDC PHY Write Leveling HW Error Register 0 " hexmask.long.byte 0x10 24.--31. 1. " HW_WL3_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 16.--23. 1. " HW_WL2_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 8.--15. 1. " HW_WL1_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" newline hexmask.long.byte 0x10 0.--7. 1. " HW_WL0_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" rgroup.long 0x87C++0x0F line.long 0x00 "MPDGHWST0,MMDC PHY Read DQS Gating HW Status Register 0" hexmask.long.word 0x00 16.--26. 1. " HW_DG_UP0 ,HW DG0 upper boundary" hexmask.long.word 0x00 0.--10. 1. " HW_DG_LOW0 ,HW DG0 lower boundary" line.long 0x04 "MPDGHWST1,MMDC PHY Read DQS Gating HW Status Register 1" hexmask.long.word 0x04 16.--26. 1. " HW_DG_UP1 ,HW DG1 upper boundary" hexmask.long.word 0x04 0.--10. 1. " HW_DG_LOW1 ,HW DG1 lower boundary" line.long 0x08 "MPDGHWST2,MMDC PHY Read DQS Gating HW Status Register 2" hexmask.long.word 0x08 16.--26. 1. " HW_DG_UP2 ,HW DG2 upper boundary" hexmask.long.word 0x08 0.--10. 1. " HW_DG_LOW2 ,HW DG2 lower boundary" line.long 0x0C "MPDGHWST3,MMDC PHY Read DQS Gating HW Status Register 3" hexmask.long.word 0x0C 16.--26. 1. " HW_DG_UP3 ,HW DG3 upper boundary" hexmask.long.word 0x0C 0.--10. 1. " HW_DG_LOW3 ,HW DG3 lower boundary" group.long 0x88C++0x0B line.long 0x00 "MPPDCMPR1,MMDC PHY Pre-defined Compare Register 1" hexmask.long.word 0x00 16.--31. 1. " PDV2 ,Pre defined compare value2" hexmask.long.word 0x00 0.--15. 1. " PDV1 ,Pre defined compare value2" line.long 0x04 "MPPDCMPR2,MMDC PHY Pre-defined Compare and CA Delay Line Configuration Register" hexmask.long.byte 0x04 24.--30. 1. " PHY_CA_DL_UNIT ,Number of delay units that is actually used by phy CA delay unit" hexmask.long.byte 0x04 16.--22. 1. " CA_DL_ABS_OFFSET ,Absolute delay offset" bitfld.long 0x04 2. " READ_LEVEL_PATTERN ,DQ calibration Read level pattern" "1010,0011" newline bitfld.long 0x04 1. " MPR_FULL_CMP ,DQ calibration full compare enable" "Disabled,Enabled" bitfld.long 0x04 0. " MPR_CMP ,DQ calibration compare enable" "Disabled,Enabled" line.long 0x08 "MPSWDAR0,MMDC PHY SW Dummy Access Register 0" rbitfld.long 0x08 5. " SW_DUM_CMP3 ,SW dummy read byte3 compare results" "Failed,Passed" rbitfld.long 0x08 4. " SW_DUM_CMP2 ,SW dummy read byte2 compare results" "Failed,Passed" rbitfld.long 0x08 3. " SW_DUM_CMP1 ,SW dummy read byte1 compare results" "Failed,Passed" newline rbitfld.long 0x08 2. " SW_DUM_CMP0 ,SW dummy read byte0 compare results" "Failed,Passed" bitfld.long 0x08 1. " SW_DUMMY_RD ,SW dummy read" "Not generated,Generated" bitfld.long 0x08 0. " SW_DUMMY_WR ,SW dummy write" "Not generated,Generated" rgroup.long 0x898++0x1F line.long 0x00 "MPSWDRDR0,MMDC PHY SW Dummy Read Data Register 0" line.long 0x04 "MPSWDRDR1,MMDC PHY SW Dummy Read Data Register 1" line.long 0x08 "MPSWDRDR2,MMDC PHY SW Dummy Read Data Register 2" line.long 0x0C "MPSWDRDR3,MMDC PHY SW Dummy Read Data Register 3" line.long 0x10 "MPSWDRDR4,MMDC PHY SW Dummy Read Data Register 4" line.long 0x14 "MPSWDRDR5,MMDC PHY SW Dummy Read Data Register 5" line.long 0x18 "MPSWDRDR6,MMDC PHY SW Dummy Read Data Register 6" line.long 0x1C "MPSWDRDR7,MMDC PHY SW Dummy Read Data Register 7" group.long 0x8B8++0x07 line.long 0x00 "MPMUR0,MMDC PHY Measure Unit Register for DQ0-3" hexmask.long.word 0x00 16.--25. 1. " MU_UNIT_DEL_NUM ,Measure unit measured number of unit delay per cycle" bitfld.long 0x00 11. " FRC_MSR ,Force measuement on delay-lines" "Not forced,Forced" bitfld.long 0x00 10. " MU_BYP_EN ,Measure unit bypass enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--9. 1. " MU_BYP_VAL ,Measure unit bypass value" line.long 0x04 "MPWRCADL,MMDC PHY Write CA Delay Control Register" bitfld.long 0x04 18.--19. " WR_CA9_DEL ,CA9 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 16.--17. " WR_CA8_DEL ,CA8 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 14.--15. " WR_CA7_DEL ,CA7 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x04 12.--13. " WR_CA6_DEL ,CA6 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 10.--11. " WR_CA5_DEL ,CA5 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 8.--9. " WR_CA4_DEL ,CA4 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x04 6.--7. " WR_CA3_DEL ,CA3 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 4.--5. " WR_CA2_DEL ,CA2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x04 2.--3. " WR_CA1_DEL ,CA1 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline width 8. rgroup.long 0x8C0++0x03 line.long 0x00 "MPDCCR,MMDC PHY Duty Cycle Control Register" bitfld.long 0x00 28.--30. " RD_DQS3_FT_DCC ,Read dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 25.--27. " RD_DQS2_FT_DCC ,Read dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 22.--24. " RD_DQS1_FT_DCC ,Read dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." newline bitfld.long 0x00 19.--21. " RD_DQS0_FT_DCC ,Read dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 16.--18. " CK_FT1_DCC ,Secondary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 12.--14. " CK_FT0_DCC ,Primary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." newline bitfld.long 0x00 9.--11. " WR_DQS3_FT_DCC ,Write dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 6.--8. " WR_DQS2_FT_DCC ,Write dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 3.--5. " WR_DQS1_FT_DCC ,Write dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." newline bitfld.long 0x00 0.--2. " WR_DQS0_FT_DCC ,Write dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." elif (((per.l(ad:0x021B0000+0x18))&0x18)==0x00) width 10. group.long 0x00++0x07 line.long 0x00 "MDCTL,MMDC Core Control Register" bitfld.long 0x00 31. " SDE_0 ,MMDC enable CS0" "Disabled,Enabled" bitfld.long 0x00 30. " SDE_1 ,MMDC enable CS1" "Disabled,Enabled" newline bitfld.long 0x00 24.--26. " ROW ,Row address width" "11-bits,12-bits,13-bits,14-bits,15-bits,16-bits,?..." bitfld.long 0x00 20.--22. " COL ,Column address width" "9-bits,10-bits,11-bits,8-bits,12-bits,?..." newline bitfld.long 0x00 19. " BL ,Burst length" ",8" bitfld.long 0x00 16.--17. " DSIZ ,SDRAM memory data width" "16-bit,32-bit,64-bit,?..." line.long 0x04 "MDPDC,MMDC Core Power Down Control Register" bitfld.long 0x04 28.--30. " PRCT_1 ,Precharge timer - chip select 1" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x04 24.--26. " PRCT_0 ,Precharge timer - chip select 0" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" newline bitfld.long 0x04 16.--18. " TCKE ,CKE minimum pulse width" "1 cycle,2 cycles,,,,,7 cycles,8 cycles" bitfld.long 0x04 12.--15. " PWDT_1 ,Power down timer - chip select 1" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,?..." newline bitfld.long 0x04 8.--11. " PWDT_0 ,Power down timer - chip select 0" "Disabled,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8196 cycles,16384 cycles,32768 cycles,?..." bitfld.long 0x04 7. " SLOW_PD ,Slow precharge power-down" "Fast,Slow" newline bitfld.long 0x04 6. " BOTH_CS_PD ,Both chip selects power-down" "Independently,Both" bitfld.long 0x04 3.--5. " TCKSRX ,Valid clock requirement before self-refresh exit" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" newline bitfld.long 0x04 0.--2. " TCKSRE ,Valid clock requirement after self-refresh entry" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" group.long 0x08++0x03 line.long 0x00 "MDOTC,MMDC Core ODT Timing Control Register" bitfld.long 0x00 27.--29. " TAOFPD ,Asynchronous RTT turn-off delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 24.--26. " TAONPD ,Asynchronous RTT turn-on delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" newline bitfld.long 0x00 20.--23. " TANPD ,ODT to power down entry latency" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x00 16.--19. " TAXPD ,ODT power down exit latency" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" newline bitfld.long 0x00 12.--14. " TODTLON ,ODT turn on latency" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,?..." bitfld.long 0x00 4.--8. " TODT_IDLE_OFF ,Idle period before turning memory ODT off" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles" group.long 0x0C++0x17 line.long 0x00 "MDCFG0,MMDC Core Timing Configuration Register 0" hexmask.long.byte 0x00 24.--31. 1. " TRFC ,Refresh command to Active or Refresh command time" hexmask.long.byte 0x00 16.--23. 1. " TXS ,Self-refresh exit to next valid command delay" newline bitfld.long 0x00 13.--15. " TXP ,Exit power down with DLL-on to any valid command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 9.--12. " TXPDLL ,Exit precharge power down with DLL frozen to commands requiring DLL" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" newline bitfld.long 0x00 4.--8. " TFAW ,Four active window" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x00 0.--3. " TCL ,CAS read latency" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,?..." line.long 0x04 "MDCFG1,MMDC Core Timing Configuration Register 1" bitfld.long 0x04 29.--31. " TRCD ,Active command to internal read or write delay time" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x04 26.--28. " TRP ,Precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" newline bitfld.long 0x04 21.--25. " TRC ,Active to active or refresh command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 cloks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x04 16.--20. " TRAS ,Active to precharge command period" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,?..." newline bitfld.long 0x04 15. " TRPA ,Precharge-all command period" "tRP,tRP+1" bitfld.long 0x04 9.--11. " TWR ,WRITE recovery time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" newline bitfld.long 0x04 5.--8. " TMRD ,Mode register set command cycle" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x04 0.--2. " TCWL ,CAS write latency" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..." line.long 0x08 "MDCFG2,MMDC Core Timing Configuration Register 2" hexmask.long.word 0x08 16.--24. 1. " TDLLK ,DLL locking time" bitfld.long 0x08 6.--8. " TRTP ,Internal READ command to PRECHARGE command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" newline bitfld.long 0x08 3.--5. " TWTR ,Internal WRITE to READ command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x08 0.--2. " TRRD ,ACTIVE to ACTIVE command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,?..." line.long 0x0C "MDMISC,MMDC Core Miscellaneous Register" rbitfld.long 0x0C 31. " CS0_RDY ,External status device on CS0" "Wake-up,Ready" rbitfld.long 0x0C 30. " CS1_RDY ,External status device on CS1" "Wake-up,Ready" newline bitfld.long 0x0C 20. " CALIB_PER_CS ,Defines the CS number that the associated calibration is targetted" "CS0,CS1" bitfld.long 0x0C 19. " ADDR_MIRROR ,Address mirroring" "Disabled,Enabled" newline bitfld.long 0x0C 18. " LHD ,Latency hiding disable" "No,Yes" bitfld.long 0x0C 16.--17. " WALAT ,Write additional latency" "Not required,1 cycle,2 cycles,3 cycles" newline bitfld.long 0x0C 12. " BI_ON ,Bank interleaving on" "Not interleaved,Interleaved" newline bitfld.long 0x0C 9.--10. " MIF3_MODE ,Command prediction working mode" "Disabled,First pipe line stage,First pipe line stage/axi bus,First pipe line stage/axi bus/access queue" newline bitfld.long 0x0C 6.--8. " RALAT ,Read additional latency" "ASAP,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x0C 5. " DDR_4_BANK ,DDR device with 4 Banks" "8 banks,4 banks" newline bitfld.long 0x0C 3.--4. " DDR_TYPE ,DDR TYPE" "DDR3,LPDDR2,?..." bitfld.long 0x0C 1. " RST ,Software reset" "No operation,Asserted" line.long 0x10 "MDSCR,MMDC Core Special Command Register" hexmask.long.byte 0x10 24.--31. 1. " CMD_ADDR_MSB ,Command/Address MSB" hexmask.long.byte 0x10 16.--23. 1. " CMD_ADDR_LSB , Command/Address LSB" newline bitfld.long 0x10 15. " CON_REQ ,Configuration request" "Not requested,Requested" rbitfld.long 0x10 14. " CON_ACK ,Configuration acknowledge" "Forbidden,Permitted" newline bitfld.long 0x10 9. " WL_EN ,Write level enable" "Disabled,Enabled" bitfld.long 0x10 4.--6. " CMD ,Command" "Normal operation,Precharge all,Auto-Refresh,Load Mode Register,ZQ calibration,Precharge all,?..." newline bitfld.long 0x10 3. " CMD_CS ,Chip select" "Low,High" bitfld.long 0x10 0.--2. " CMD_BA ,Bank address" "0,1,2,3,4,5,6,7" line.long 0x14 "MDREF,MMDC Core Refresh Control Register" hexmask.long.word 0x14 16.--31. 1. " REF_CNT ,Refresh counter" bitfld.long 0x14 14.--15. " REF_SEL ,Refresh selector" "64KHz,32KHz,REF_CNT,Disabled" newline bitfld.long 0x14 11.--13. " REFR ,Refresh Rate" "1 refresh,2 refreshes,3 refreshes,4 refreshes,5 refreshes,6 refreshes,7 refreshes,8 refreshes" bitfld.long 0x14 0. " START_REF ,Start Refresh cycle" "No operation,Started" group.long 0x2C++0x07 line.long 0x00 "MDRWD,MMDC Core Read/Write Command Delay Register" bitfld.long 0x00 12.--14. " RTW_SAME ,Controls the cycles delay between read to write commands in same chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 9.--11. " WTR_DIFF ,Controls the cycles delay between write to Read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" newline bitfld.long 0x00 6.--8. " WTW_DIFF ,Controls the cycles delay between write to write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 3.--5. " RTW_DIFF ,Controls the cycles delay between read to write commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" newline bitfld.long 0x00 0.--2. " RTR_DIFF ,Controls the cycles delay between read to read commands in different chip select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" line.long 0x04 "MDOR,MMDC Core Out of Reset Delays Register" hexmask.long.byte 0x04 16.--23. 1. " TXPR ,CKE HIGH to a valid command" bitfld.long 0x04 8.--13. " SDE_TO_RST , Time from SDE enable until DDR reset is high" ",,1 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles" newline bitfld.long 0x04 0.--5. " RST_TO_CKE ,Time from SDE enable to CKE rise" ",,,1 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles" newline width 13. hgroup.long 0x34++0x0B hide.long 0x00 "MDMRR,MMDC Core MRR Data Register" hide.long 0x04 "MDCFG3LP,MMDC Core Timing Configuration Register 3" hide.long 0x08 "MDMR4,MMDC Core MR4 Derating Register" group.long 0x40++0x03 line.long 0x00 "MDASP,MMDC Core Address Space Partition Register" hexmask.long.byte 0x00 0.--6. 1. " CS0_END ,Define the absolute last address associated with CS0" group.long 0x400++0x0F line.long 0x00 "MAARCR,MMDC Core AXI Re-ordering Control Register" bitfld.long 0x00 31. " ARCR_SEC_ERR_LOCK ,ARCR_SEC_ERR_EN lock" "Not locked,Locked" bitfld.long 0x00 30. " ARCR_SEC_ERR_EN ,Security read/write access violation in OKAY/SLV Error response " "OKAY,SLAVE error" bitfld.long 0x00 28. " ARCR_EXC_ERR_EN ,Exclusive read/write access violation of AXI 6.2.4 rule in OKAY/SLV Error response " "OKAY,SLAVE error" newline bitfld.long 0x00 24. " ARCR_RCH_EN ,Real time channel enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ARCR_PAG_HIT ,ARCR page hit rate" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " ARCR_ACC_HIT ,ARCR access hit rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--11. " ARCR_DYN_JMP ,ARCR dynamic jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ARCR_DYN_MAX ,ARCR dynamic maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARCR_GUARD ,ARCR guard" "15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30" line.long 0x04 "MAPSR,MMDC Core Power Saving Control and Status Register" rbitfld.long 0x04 25. " DVACK ,General DVFS acknowledge" "Not asserted,Asserted" rbitfld.long 0x04 24. " LPACK ,General low-power acknowledge" "Not asserted,Asserted" bitfld.long 0x04 21. " DVFS ,General DVFS request" "Not requested,Requested" newline bitfld.long 0x04 20. " LPMD ,General LPMD request" "Not requested,Requested" hexmask.long.byte 0x04 8.--15. 1. " PST ,Automatic power saving timer" rbitfld.long 0x04 6. " WIS ,Write idle status" "Idle,Busy" newline rbitfld.long 0x04 5. " RIS ,Read idle status" "Idle,Busy" rbitfld.long 0x04 4. " PSS ,Power saving status" "Disabled,Enabled" bitfld.long 0x04 0. " PSD ,Automatic power saving disable" "No,Yes" line.long 0x08 "MAEXIDR0,MMDC Core Exclusive ID Monitor Register 0" hexmask.long.word 0x08 16.--31. 1. " EXC_ID_MONITOR1 ,Defines ID for exclusive monitor#1" hexmask.long.word 0x08 0.--15. 1. " EXC_ID_MONITOR0 ,Defines ID for exclusive monitor#0" line.long 0x0C "MAEXIDR1,MMDC Core Exclusive ID Monitor Register 1" hexmask.long.word 0x0C 16.--31. 1. " EXC_ID_MONITOR3 ,Defines ID for exclusive monitor#3" hexmask.long.word 0x0C 0.--15. 1. " EXC_ID_MONITOR2 ,Defines ID for exclusive monitor#2" group.long 0x410++0x07 line.long 0x00 "MADPCR0,MMDC Core Debug and Profiling Control Register 0" bitfld.long 0x00 9. " SBS ,Step by step trigger" "Not launched,Launched" bitfld.long 0x00 8. " SBS_EN ,Step by step debug enable" "Disabled,Enabled" eventfld.long 0x00 3. " CYC_OVF ,Total cycles count overflow" "No overflow,Overflow" newline bitfld.long 0x00 2. " PRF_FRZ ,Profiling freeze" "Not frozen,Frozen" bitfld.long 0x00 1. " DBG_RST ,Debug and profiling reset" "No reset,Reset" bitfld.long 0x00 0. " DBG_EN ,Debug and profiling enable" "Disabled,Enabled" line.long 0x04 "MADPCR1,MMDC Core Debug and Profiling Control Register 1" bitfld.long 0x04 31. " PRF_AXI_ID_MASK_31 ,Profiling AXI ID mask 31" "Masked,Not masked" bitfld.long 0x04 30. " PRF_AXI_ID_MASK_30 ,Profiling AXI ID mask 30" "Masked,Not masked" bitfld.long 0x04 29. " PRF_AXI_ID_MASK_29 ,Profiling AXI ID mask 29" "Masked,Not masked" newline bitfld.long 0x04 28. " PRF_AXI_ID_MASK_28 ,Profiling AXI ID mask 28" "Masked,Not masked" bitfld.long 0x04 27. " PRF_AXI_ID_MASK_27 ,Profiling AXI ID mask 27" "Masked,Not masked" bitfld.long 0x04 26. " PRF_AXI_ID_MASK_26 ,Profiling AXI ID mask 26" "Masked,Not masked" newline bitfld.long 0x04 25. " PRF_AXI_ID_MASK_25 ,Profiling AXI ID mask 25" "Masked,Not masked" bitfld.long 0x04 24. " PRF_AXI_ID_MASK_24 ,Profiling AXI ID mask 24" "Masked,Not masked" bitfld.long 0x04 23. " PRF_AXI_ID_MASK_23 ,Profiling AXI ID mask 23" "Masked,Not masked" newline bitfld.long 0x04 22. " PRF_AXI_ID_MASK_22 ,Profiling AXI ID mask 22" "Masked,Not masked" bitfld.long 0x04 21. " PRF_AXI_ID_MASK_21 ,Profiling AXI ID mask 21" "Masked,Not masked" bitfld.long 0x04 20. " PRF_AXI_ID_MASK_20 ,Profiling AXI ID mask 20" "Masked,Not masked" newline bitfld.long 0x04 19. " PRF_AXI_ID_MASK_19 ,Profiling AXI ID mask 19" "Masked,Not masked" bitfld.long 0x04 18. " PRF_AXI_ID_MASK_18 ,Profiling AXI ID mask 18" "Masked,Not masked" bitfld.long 0x04 17. " PRF_AXI_ID_MASK_17 ,Profiling AXI ID mask 17" "Masked,Not masked" newline bitfld.long 0x04 16. " PRF_AXI_ID_MASK_16 ,Profiling AXI ID mask 16" "Masked,Not masked" bitfld.long 0x04 15. " PRF_AXI_ID[15] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 14. " PRF_AXI_ID[14] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 13. " PRF_AXI_ID[13] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 12. " PRF_AXI_ID[12] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 11. " PRF_AXI_ID[11] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 10. " PRF_AXI_ID[10] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 9. " PRF_AXI_ID[9] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 8. " PRF_AXI_ID[8] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 7. " PRF_AXI_ID[7] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 6. " PRF_AXI_ID[6] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 5. " PRF_AXI_ID[5] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 4. " PRF_AXI_ID[4] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 3. " PRF_AXI_ID[3] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 2. " PRF_AXI_ID[2] ,Profiling AXI ID" "Low,High" newline bitfld.long 0x04 1. " PRF_AXI_ID[1] ,Profiling AXI ID" "Low,High" bitfld.long 0x04 0. " PRF_AXI_ID[0] ,Profiling AXI ID" "Low,High" rgroup.long 0x418++0x1F line.long 0x00 "MADPSR0,MMDC Core Debug and Profiling Status Register 0" line.long 0x04 "MADPSR1,MMDC Core Debug and Profiling Status Register 1" line.long 0x08 "MADPSR2,MMDC Core Debug and Profiling Status Register 2" line.long 0x0C "MADPSR3,MMDC Core Debug and Profiling Status Register 3" line.long 0x10 "MADPSR4,MMDC Core Debug and Profiling Status Register 4" line.long 0x14 "MADPSR5,MMDC Core Debug and Profiling Status Register 5" line.long 0x18 "MASBS0,MMDC Core Step By Step Address" line.long 0x1C "MASBS1,MMDC Core Step By Step Address Attributes" hexmask.long.word 0x1C 16.--31. 1. " SBS_AXI_ID ,Step by step AXI ID" bitfld.long 0x1C 13.--15. " SBS_LEN ,Step by step length" "1,2,3,4,5,6,7,8" bitfld.long 0x1C 12. " SBS_BUFF ,Step by step buffered" "Low,High" newline bitfld.long 0x1C 10.--11. " SBS_BURST ,Step by step burst" "Fixed,INCR,WRAP,?..." bitfld.long 0x1C 7.--9. " SBS_SIZE ,Step by step size" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x1C 4.--6. " SBS_PROT ,Step by step protection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 2.--3. " SBS_LOCK ,Step by step lock" "0,1,2,3" bitfld.long 0x1C 1. " SBS_TYPE ,Step by step request type" "Write,Read" bitfld.long 0x1C 0. " SBS_VLD ,Step by step balid" "Not valid,Valid" group.long 0x440++0x03 line.long 0x00 "MAGENP,MMDC Core General Purpose Register" bitfld.long 0x00 31. " GP31 ,General purpose read/write bit 31" "Low,High" bitfld.long 0x00 30. " GP30 ,General purpose read/write bit 30" "Low,High" bitfld.long 0x00 29. " GP29 ,General purpose read/write bit 29" "Low,High" newline bitfld.long 0x00 28. " GP28 ,General purpose read/write bit 28" "Low,High" bitfld.long 0x00 27. " GP27 ,General purpose read/write bit 27" "Low,High" bitfld.long 0x00 26. " GP26 ,General purpose read/write bit 26" "Low,High" newline bitfld.long 0x00 25. " GP25 ,General purpose read/write bit 25" "Low,High" bitfld.long 0x00 24. " GP24 ,General purpose read/write bit 24" "Low,High" bitfld.long 0x00 23. " GP23 ,General purpose read/write bit 23" "Low,High" newline bitfld.long 0x00 22. " GP22 ,General purpose read/write bit 22" "Low,High" bitfld.long 0x00 21. " GP21 ,General purpose read/write bit 21" "Low,High" bitfld.long 0x00 20. " GP20 ,General purpose read/write bit 20" "Low,High" newline bitfld.long 0x00 19. " GP19 ,General purpose read/write bit 19" "Low,High" bitfld.long 0x00 18. " GP18 ,General purpose read/write bit 18" "Low,High" bitfld.long 0x00 17. " GP17 ,General purpose read/write bit 17" "Low,High" newline bitfld.long 0x00 16. " GP16 ,General purpose read/write bit 16" "Low,High" bitfld.long 0x00 15. " GP15 ,General purpose read/write bit 15" "Low,High" bitfld.long 0x00 14. " GP14 ,General purpose read/write bit 14" "Low,High" newline bitfld.long 0x00 13. " GP13 ,General purpose read/write bit 13" "Low,High" bitfld.long 0x00 12. " GP12 ,General purpose read/write bit 12" "Low,High" bitfld.long 0x00 11. " GP11 ,General purpose read/write bit 11" "Low,High" newline bitfld.long 0x00 10. " GP10 ,General purpose read/write bit 10" "Low,High" bitfld.long 0x00 9. " GP9 ,General purpose read/write bit 9" "Low,High" bitfld.long 0x00 8. " GP8 ,General purpose read/write bit 8" "Low,High" newline bitfld.long 0x00 7. " GP7 ,General purpose read/write bit 7" "Low,High" bitfld.long 0x00 6. " GP6 ,General purpose read/write bit 6" "Low,High" bitfld.long 0x00 5. " GP5 ,General purpose read/write bit 5" "Low,High" newline bitfld.long 0x00 4. " GP4 ,General purpose read/write bit 4" "Low,High" bitfld.long 0x00 3. " GP3 ,General purpose read/write bit 3" "Low,High" bitfld.long 0x00 2. " GP2 ,General purpose read/write bit 2" "Low,High" newline bitfld.long 0x00 1. " GP1 ,General purpose read/write bit 1" "Low,High" bitfld.long 0x00 0. " GP0 ,General purpose read/write bit 0" "Low,High" width 13. group.long 0x800++0x07 line.long 0x00 "MPZQHWCTRL,MMDC PHY ZQ HW Control Register" bitfld.long 0x00 27.--31. " ZQ_EARLY_COMPARATOR_EN_TIMER ,ZQ early comparator enable timer" ",,,,,,,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" bitfld.long 0x00 23.--25. " TZQ_CS ,Device ZQ short time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." bitfld.long 0x00 20.--22. " TZQ_OPER ,Device ZQ long/oper time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." newline bitfld.long 0x00 17.--19. " TZQ_INIT ,Device ZQ long/init time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." bitfld.long 0x00 16. " ZQ_HW_FOR ,Force ZQ automatic calibration process with the i.MX ZQ calibration pad" "Not forced,Forced" rbitfld.long 0x00 11.--15. " ZQ_HW_PD_RES ,ZQ HW calibration pull-down result" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 6.--10. " ZQ_HW_PU_RES ,ZQ automatic calibration pull-up result" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--5. " ZQ_HW_PER ,ZQ periodic calibration time" "1 ms,2 ms,4 ms,8 ms,16 ms,32 ms,64 ms,128 ms,256 ms,512 ms,1 sec,2 sec,4 sec,8 sec,16 sec,32 sec" newline bitfld.long 0x00 0.--1. " ZQ_MODE ,ZQ calibration mode" "Not issued,i.MX ZQ calibration pad/External DDR(when exiting),External DDR,i.MX ZQ calibration pad/External DDR(periodic/when exiting)" line.long 0x04 "MPZQSWCTRL,MMDC PHY ZQ SW control register" bitfld.long 0x04 16.--17. " ZQ_CMP_OUT_SMP ,Amount of cycles between driving the ZQ signals to the ZQ pad" "7 cycles,15 cycles,23 cycles,31 cycles" newline bitfld.long 0x04 13. " USE_ZQ_SW_VAL ,Use SW ZQ configured value for I/O pads resistor controls" "ZQ_HW_PD_VAL & ZQ_HW_PU_VAL,ZQ_SW_PD_VAL & ZQ_SW_PU_VAL" newline bitfld.long 0x04 12. " ZQ_SW_PD ,ZQ software PU/PD calibration" "PU,PD" newline bitfld.long 0x04 7.--11. " ZQ_SW_PD_VAL ,ZQ software pull-down resistence" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 2.--6. " ZQ_SW_PU_VAL ,ZQ software pull-up resistence" "0 (maximum),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 1. " ZQ_SW_RES ,ZQ software calibration result" "VDD/2" newline bitfld.long 0x04 0. " ZQ_SW_FOR ,Force ZQ SW calibration" "Not forced,Forced" group.long 0x808++0x0B line.long 0x00 "MPWLGCR0,MMDC PHY Write Leveling Error Status Register 0" rbitfld.long 0x00 11. " WL_HW_ERR3 ,Byte3 WL HW calibration error" "No error,Error" rbitfld.long 0x00 10. " WL_HW_ERR2 ,Byte2 WL HW calibration error" "No error,Error" rbitfld.long 0x00 9. " WL_HW_ERR1 ,Byte1 WL HW calibration error" "No error,Error" newline rbitfld.long 0x00 8. " WL_HW_ERR0 ,Byte0 WL HW calibration error" "No error,Error" rbitfld.long 0x00 7. " WL_SW_RES3 ,Byte3 WL software result" "Low,High" rbitfld.long 0x00 6. " WL_SW_RES2 ,Byte2 WL software result" "Low,High" newline rbitfld.long 0x00 5. " WL_SW_RES1 ,Byte1 WL software result" "Low,High" rbitfld.long 0x00 4. " WL_SW_RES0 ,Byte0 WL software result" "Low,High" bitfld.long 0x00 2. " SW_WL_CNT_EN ,SW WL count down enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SW_WL_EN ,Enable WL SW update" "Disabled,Enabled" bitfld.long 0x00 0. " HW_WL_EN ,Enable WL HW enable" "Disabled,Enabled" line.long 0x04 "MPWLDECTRL0,MMDC PHY Write Leveling Delay Control Register 0" bitfld.long 0x04 25.--26. " WL_CYC_DEL1 ,Write level cycle delay for byte 1" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x04 24. " WL_HC_DEL1 ,Write level half cycle delay for byte 1" "No delay,Half cycle" hexmask.long.byte 0x04 16.--22. 1. " WR_DL_ABS_OFFSET1 ,Absolute delay offset for Byte 1" newline bitfld.long 0x04 9.--10. " WL_CYC_DEL0 ,Write level cycle delay for Byte 0" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x04 8. " WL_HC_DEL0 ,Write level half cycle delay for byte 0" "No delay,Half cycle" hexmask.long.byte 0x04 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute delay offset for Byte 0" line.long 0x08 "MPWLDECTRL1,MMDC PHY Write Leveling Delay Control Register 1" bitfld.long 0x08 25.--26. " WL_CYC_DEL3 ,Write level cycle delay for Byte 3" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x08 24. " WL_HC_DEL3 ,Write level half cycle delay for byte 3" "No delay,Half cycle" hexmask.long.byte 0x08 16.--22. 1. " WR_DL_ABS_OFFSET3 ,Absolute delay offset for Byte 3" newline bitfld.long 0x08 9.--10. " WL_CYC_DEL2 ,Write level cycle delay for Byte 2" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x08 8. " WL_HC_DEL2 ,Write level half cycle delay for byte 2" "No delay,Half cycle" hexmask.long.byte 0x08 0.--6. 1. " WR_DL_ABS_OFFSET2 ,Absolute delay offset for Byte 2" rgroup.long 0x814++0x03 line.long 0x00 "MPWLDLST0,MMDC PHY Write Leveling Delay Line Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " WL_DL_UNIT_NUM3 ,Number of delay units that is actually used by write leveling delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WL_DL_UNIT_NUM2 ,Number of delay units that is actually used by write leveling delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WL_DL_UNIT_NUM1 ,Number of delay units that is actually used by write leveling delay line 1" group.long 0x818++0x2B line.long 0x00 "MPODTCTRL,MMDC PHY ODT Control Register" bitfld.long 0x00 16.--18. " ODT3_INT_RES ,On chip ODT byte3 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 12.--14. " ODT2_INT_RES ,On chip ODT byte2 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 8.--10. " ODT1_INT_RES ,On chip ODT byte1 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" newline bitfld.long 0x00 4.--6. " ODT0_INT_RES ,On chip ODT byte0 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 3. " ODT_RD_ACT_EN ,Active read CS ODT enable" "Disabled,Enabled" bitfld.long 0x00 2. " ODT_RD_PAS_EN ,Inactive read CS ODT enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ODT_WR_ACT_EN ,Active write CS ODT enable" "Disabled,Enabled" bitfld.long 0x00 0. " ODT_WR_PAS_EN ,Inactive write CS ODT enable" "Disabled,Enabled" line.long 0x04 "MPRDDQBY0DL,MMDC PHY Read DQ Byte0 Delay Register" bitfld.long 0x04 28.--30. " RD_DQ7_DEL ,Read dqs0 to dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 24.--26. " RD_DQ6_DEL ,Read dqs0 to dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 20.--22. " RD_DQ5_DEL ,Read dqs0 to dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x04 16.--18. " RD_DQ4_DEL ,Read dqs0 to dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 12.--14. " RD_DQ3_DEL ,Read dqs0 to dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 8.--10. " RD_DQ2_DEL ,Read dqs0 to dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x04 4.--6. " RD_DQ1_DEL ,Read dqs0 to dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x04 0.--2. " RD_DQ0_DEL ,Read dqs0 to dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x08 "MPRDDQBY1DL,MMDC PHY Read DQ Byte1 Delay Register" bitfld.long 0x08 28.--30. " RD_DQ15_DEL ,Read dqs1 to dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 24.--26. " RD_DQ14_DEL ,Read dqs1 to dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 20.--22. " RD_DQ13_DEL ,Read dqs1 to dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x08 16.--18. " RD_DQ12_DEL ,Read dqs1 to dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 12.--14. " RD_DQ11_DEL ,Read dqs1 to dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 8.--10. " RD_DQ10_DEL ,Read dqs1 to dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x08 4.--6. " RD_DQ9_DEL ,Read dqs1 to dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x08 0.--2. " RD_DQ8_DEL ,Read dqs1 to dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x0C "MPRDDQBY2DL,MMDC PHY Read DQ Byte2 Delay Register" bitfld.long 0x0C 28.--30. " RD_DQ23_DEL ,Read dqs2 to dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 24.--26. " RD_DQ22_DEL ,Read dqs2 to dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 20.--22. " RD_DQ21_DEL ,Read dqs2 to dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x0C 16.--18. " RD_DQ20_DEL ,Read dqs2 to dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 12.--14. " RD_DQ19_DEL ,Read dqs2 to dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 8.--10. " RD_DQ18_DEL ,Read dqs2 to dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x0C 4.--6. " RD_DQ17_DEL ,Read dqs2 to dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x0C 0.--2. " RD_DQ16_DEL ,Read dqs2 to dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x10 "MPRDDQBY3DL,MMDC PHY Read DQ Byte3 Delay Register" bitfld.long 0x10 28.--30. " RD_DQ31_DEL ,Read dqs3 to dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 24.--26. " RD_DQ30_DEL ,Read dqs3 to dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 20.--22. " RD_DQ29_DEL ,Read dqs3 to dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x10 16.--18. " RD_DQ28_DEL ,Read dqs3 to dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 12.--14. " RD_DQ27_DEL ,Read dqs3 to dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 8.--10. " RD_DQ26_DEL ,Read dqs3 to dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" newline bitfld.long 0x10 4.--6. " RD_DQ25_DEL ,Read dqs3 to dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" bitfld.long 0x10 0.--2. " RD_DQ24_DEL ,Read dqs3 to dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays,4 delays,5 delays,6 delays,7 delays" line.long 0x14 "MPWRDQBY0DL,MMDC PHY Write DQ Byte0 Delay Register" bitfld.long 0x14 30.--31. " WR_DM0_DEL ,Write dm0 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 28.--29. " WR_DQ7_DEL ,Write dq7 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 24.--25. " WR_DQ6_DEL ,Write dq6 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x14 20.--21. " WR_DQ5_DEL ,Write dq5 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 16.--17. " WR_DQ4_DEL ,Write dq4 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 12.--13. " WR_DQ3_DEL ,Write dq3 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x14 8.--9. " WR_DQ2_DEL ,Write dq2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 4.--5. " WR_DQ1_DEL ,Write dq1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x14 0.--1. " WR_DQ0_DEL ,Write dq0 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x18 "MPWRDQBY1DL,MMDC PHY Write DQ Byte1 Delay Register" bitfld.long 0x18 30.--31. " WR_DM1_DEL ,Write dm1 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 28.--29. " WR_DQ15_DEL ,Write dq15 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 24.--25. " WR_DQ14_DEL ,Write dq14 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x18 20.--21. " WR_DQ13_DEL ,Write dq13 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 16.--17. " WR_DQ12_DEL ,Write dq12 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 12.--13. " WR_D11_DEL ,Write dq11 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x18 8.--9. " WR_DQ10_DEL ,Write dq10 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 4.--5. " WR_DQ9_DEL ,Write dq9 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x18 0.--1. " WR_DQ8_DEL ,Write dq8 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x1C "MPWRDQBY2DL, MMDC PHY Write DQ Byte2 Delay Register" bitfld.long 0x1C 30.--31. " WR_DM2_DEL ,Write dm2 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 28.--29. " WR_DQ23_DEL ,Write dq23 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 24.--25. " WR_DQ22_DEL ,Write dq22 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x1C 20.--21. " WR_DQ21_DEL ,Write dq21 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 16.--17. " WR_DQ20_DEL ,Write dq20 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 12.--13. " WR_D19_DEL ,Write dq19 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x1C 8.--9. " WR_DQ18_DEL ,Write dq18 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 4.--5. " WR_DQ17_DEL ,Write dq17 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x1C 0.--1. " WR_DQ16_DEL ,Write dq16 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x20 "MPWRDQBY3DL, MMDC PHY Write DQ Byte3 Delay Register" bitfld.long 0x20 30.--31. " WR_DM3_DEL ,Write dm3 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 28.--29. " WR_DQ31_DEL ,Write dq31 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 24.--25. " WR_DQ30_DEL ,Write dq30 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x20 20.--21. " WR_DQ29_DEL ,Write dq29 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 16.--17. " WR_DQ28_DEL ,Write dq28 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 12.--13. " WR_D27_DEL ,Write dq27 delay fine tuning" "No change,1 delay,2 delays,3 delays" newline bitfld.long 0x20 8.--9. " WR_DQ26_DEL ,Write dq26 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 4.--5. " WR_DQ25_DEL ,Write dq25 delay fine tuning" "No change,1 delay,2 delays,3 delays" bitfld.long 0x20 0.--1. " WR_DQ24_DEL ,Write dq24 delay fine tuning" "No change,1 delay,2 delays,3 delays" line.long 0x24 "MPDGCTRL0,MMDC PHY Read DQS gating control register 0" bitfld.long 0x24 31. " RST_RD_FIFO ,Reset Read Data FIFO & pointers" "No reset,Reset" bitfld.long 0x24 30. " DG_CMP_CYC ,Read DQS gating sample cycle" "16 cycles,32 cycles" bitfld.long 0x24 29. " DG_DIS ,Read DQS gating disable" "No,Yes" newline bitfld.long 0x24 28. " HW_DG_EN ,Enable automatic read DQS gating calibration" "Disabled,Enabled" bitfld.long 0x24 24.--27. " DG_HC_DEL1 ,Read Dqs1 gating half cycles delay for Byte 1" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,?..." bitfld.long 0x24 23. " DG_EXT_UP ,DG extend upper boundary" "Not extended,Extended" newline hexmask.long.byte 0x24 16.--22. 1. " DG_DL_ABS_OFFSET1 ,Absolute delay offset" rbitfld.long 0x24 12. " HW_DG_ERR ,HW DQS gating error " "No error,Error" bitfld.long 0x24 8.--11. " DG_HC_DEL0 ,Read DQS0 gating half cycles delay for Byte 0" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,?..." newline hexmask.long.byte 0x24 0.--6. 1. " DG_DL_ABS_OFFSET0 ,Absolute read DQS gating delay offset" line.long 0x28 "MPDGCTRL1,MMDC PHY Read DQS gating control register 1" bitfld.long 0x28 24.--27. " DG_HC_DEL3 ,Read DQS3 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,?..." hexmask.long.byte 0x28 16.--22. 1. " DG_DL_ABS_OFFSET3 ,Absolute read DQS gating delay offset for Byte 3" bitfld.long 0x28 8.--11. " DG_HC_DEL2 ,Read DQS2 gating half cycles delay for Byte 3" "0,0.5,1,1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,?..." newline hexmask.long.byte 0x28 0.--6. 1. " DG_DL_ABS_OFFSET2 ,Absolute read DQS gating delay offset" rgroup.long 0x844++0x03 line.long 0x00 "MPDGDLST0,MMDC PHY Read DQS gating Delay Line Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " DG_DL_UNIT_NUM3 ,Number of delay units that is actually used by DQS gating delay line 3" hexmask.long.byte 0x00 16.--22. 1. " DG_DL_UNIT_NUM2 ,Number of delay units that is actually used by DQS gating delay line 2" hexmask.long.byte 0x00 8.--14. 1. " DG_DL_UNIT_NUM1 ,Number of delay units that is actually used by DQS gating delay line 1" newline hexmask.long.byte 0x00 0.--6. 1. " DG_DL_UNIT_NUM0 ,Number of delay units that is actually used by DQS gating delay line 0" group.long 0x848++0x03 line.long 0x00 "MPRDDLCTL,MMDC PHY Read Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_ABS_OFFSET3 ,Absolute read delay offset byte 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_ABS_OFFSET2 ,Absolute read delay offset byte 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_ABS_OFFSET1 ,Absolute read delay offset byte 1" newline hexmask.long.byte 0x00 0.--6. 1. " RD_DL_ABS_OFFSET0 ,Absolute read delay offset byte 0" rgroup.long 0x84C++0x03 line.long 0x00 "MPRDDLST0,MMDC PHY Read Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " RD_DL_UNIT_NUM3 ,Number of delay units that is actually used by read delay line 3" hexmask.long.byte 0x00 16.--22. 1. " RD_DL_UNIT_NUM2 ,Number of delay units that is actually used by read delay line 2" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_UNIT_NUM1 ,Number of delay units that is actually used by read delay line 1" newline hexmask.long.byte 0x00 0.--6. 1. " RD_DL_UNIT_NUM0 ,Number of delay units that is actually used by read delay line 0" group.long 0x850++0x03 line.long 0x00 "MPWRDLCTL0,MMDC PHY Write Delay Lines Configuration Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_ABS_OFFSET3 ,Absolute write delay offset for Byte 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_ABS_OFFSET2 ,Absolute write delay offset for Byte 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_ABS_OFFSET1 ,Absolute write delay offset for Byte 1" newline hexmask.long.byte 0x00 0.--6. 1. " WR_DL_ABS_OFFSET0 ,Absolute write delay offset for Byte 0" rgroup.long 0x854++0x03 line.long 0x00 "MPWRDLST0,MMDC PHY Write Delay Lines Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR_DL_UNIT_NUM3 ,Number of delay units that is actually used by write delay line 3" hexmask.long.byte 0x00 16.--22. 1. " WR_DL_UNIT_NUM2 ,Number of delay units that is actually used by write delay line 2" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_UNIT_NUM1 ,Number of delay units that is actually used by write delay line 1" newline hexmask.long.byte 0x00 0.--6. 1. " WR_DL_UNIT_NUM0 ,Number of delay units that is actually used by write delay line 0" group.long 0x858++0x03 line.long 0x00 "MPSDCTRL,MMDC PHY CK control Register" bitfld.long 0x00 8.--9. " SDCLK_DEL ,SDCLK0 delay fine tuning" "No change,1 delay,2 delays,3 delays" hgroup.long 0x85C++0x03 hide.long 0x00 "MPZQLP2CTL,MMDC PHY ZQ LPDDR2 HW Control Register" group.long 0x860++0x07 line.long 0x00 "MPRDDLHWCTL,MMDC PHY Read Delay HW Calibration Control Register" bitfld.long 0x00 5. " HW_RDL_CMP_CYC ,HW RD DL sample cycle" "Not compared,Compared" bitfld.long 0x00 4. " HW_RDL_EN ,Enable HW RD DL calibration" "Disabled,Enabled" rbitfld.long 0x00 3. " HW_RDL_ERR3 ,HW RD DL3 error" "No error,Error" newline rbitfld.long 0x00 2. " HW_RDL_ERR2 ,HW RD DL2 error" "No error,Error" rbitfld.long 0x00 1. " HW_RDL_ERR1 ,HW RD DL1 error" "No error,Error" rbitfld.long 0x00 0. " HW_RDL_ERR0 ,HW RD DL0 error" "No error,Error" line.long 0x04 "MPWRDLHWCTL,MMDC PHY Write Delay HW Calibration Control Register" bitfld.long 0x04 5. " HW_WDL_CMP_CYC ,HW RD DL sample cycle" "Not compared,Compared" bitfld.long 0x04 4. " HW_WDL_EN ,Enable HW RD DL calibration" "Disabled,Enabled" rbitfld.long 0x04 3. " HW_WDL_ERR3 ,HW RD DL3 error" "No error,Error" newline rbitfld.long 0x04 2. " HW_WDL_ERR2 ,HW RD DL2 error" "No error,Error" rbitfld.long 0x04 1. " HW_WDL_ERR1 ,HW RD DL1 error" "No error,Error" rbitfld.long 0x04 0. " HW_WDL_ERR0 ,HW RD DL0 error" "No error,Error" rgroup.long 0x868++0x23 line.long 0x00 "MPRDDLHWST0,MMDC PHY Read Delay HW Calibration Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " HW_RD_DL_UP1 ,HW RD DL1 upper boundary" hexmask.long.byte 0x00 16.--22. 1. " HW_RD_DL_LOW1 ,HW RD DL1 lower boundary" hexmask.long.byte 0x00 8.--14. 1. " HW_RD_DL_UP0 ,HW RD DL0 upper boundary" newline hexmask.long.byte 0x00 0.--6. 1. " HW_RD_DL_LOW0 ,HW RD DL0 lower boundary" line.long 0x04 "MPRDDLHWST1,MMDC PHY Read Delay HW Calibration Status Register 1" hexmask.long.byte 0x04 24.--30. 1. " HW_RD_DL_UP3 ,HW RD DL3 upper boundary" hexmask.long.byte 0x04 16.--22. 1. " HW_RD_DL_LOW3 ,HW RD DL3 lower boundary" hexmask.long.byte 0x04 8.--14. 1. " HW_RD_DL_UP2 ,HW RD DL2 upper boundary" newline hexmask.long.byte 0x04 0.--6. 1. " HW_RD_DL_LOW2 ,HW RD DL2 lower boundary" line.long 0x08 "MPWRDLHWST0,MMDC PHY Write Delay HW Calibration Status Register 0" hexmask.long.byte 0x08 24.--30. 1. " HW_WR_DL_UP1 ,HW WR DL1 upper boundary" hexmask.long.byte 0x08 16.--22. 1. " HW_WR_DL_LOW1 ,HW WR DL1 lower boundary" hexmask.long.byte 0x08 8.--14. 1. " HW_WR_DL_UP0 ,HW WR DL0 upper boundary" newline hexmask.long.byte 0x08 0.--6. 1. " HW_WR_DL_LOW0 ,HW WR DL0 lower boundary" line.long 0x0C "MPWRDLHWST1,MMDC PHY Write Delay HW Calibration Status Register 1" hexmask.long.byte 0x0C 24.--30. 1. " HW_WR_DL_UP3 ,HW WR DL3 upper boundary" hexmask.long.byte 0x0C 16.--22. 1. " HW_WR_DL_LOW3 ,HW WR DL3 lower boundary" hexmask.long.byte 0x0C 8.--14. 1. " HW_WR_DL_UP2 ,HW WR DL2 upper boundary" newline hexmask.long.byte 0x0C 0.--6. 1. " HW_WR_DL_LOW2 ,HW WR DL2 lower boundary" line.long 0x10 "MPWLHWERR0,MMDC PHY Write Leveling HW Error Register 0" hexmask.long.byte 0x10 24.--31. 1. " HW_WL3_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 16.--23. 1. " HW_WL2_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" hexmask.long.byte 0x10 8.--15. 1. " HW_WL1_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" newline hexmask.long.byte 0x10 0.--7. 1. " HW_WL0_DQ ,Holds the DQ results for all the 8 configurable hw wl delays" line.long 0x14 "MPDGHWST0,MMDC PHY Read DQS Gating HW Status Register 0" hexmask.long.word 0x14 16.--26. 1. " HW_DG_UP0 ,HW DG0 upper boundary" hexmask.long.word 0x14 0.--10. 1. " HW_DG_LOW0 ,HW DG0 lower boundary" line.long 0x18 "MPDGHWST1,MMDC PHY Read DQS Gating HW Status Register 1" hexmask.long.word 0x18 16.--26. 1. " HW_DG_UP1 ,HW DG1 upper boundary" hexmask.long.word 0x18 0.--10. 1. " HW_DG_LOW1 ,HW DG1 lower boundary" line.long 0x1C "MPDGHWST2,MMDC PHY Read DQS Gating HW Status Register 2" hexmask.long.word 0x1C 16.--26. 1. " HW_DG_UP2 ,HW DG2 upper boundary" hexmask.long.word 0x1C 0.--10. 1. " HW_DG_LOW2 ,HW DG2 lower boundary" line.long 0x20 "MPDGHWST3,MMDC PHY Read DQS Gating HW Status Register 3" hexmask.long.word 0x20 16.--26. 1. " HW_DG_UP3 ,HW DG3 upper boundary" hexmask.long.word 0x20 0.--10. 1. " HW_DG_LOW3 ,HW DG3 lower boundary" group.long 0x88C++0x0B line.long 0x00 "MPPDCMPR1,MMDC PHY Pre-defined Compare Register 1" hexmask.long.word 0x00 16.--31. 1. " PDV2 ,Pre defined compare value2" hexmask.long.word 0x00 0.--15. 1. " PDV1 ,Pre defined compare value2" line.long 0x04 "MPPDCMPR2,MMDC PHY Pre-defined Compare and CA Delay Line Configuration Register" bitfld.long 0x04 2. " READ_LEVEL_PATTERN ,MPR calibration Read level pattern" "1010,?..." bitfld.long 0x04 1. " MPR_FULL_CMP ,MPR full compare enable" "Disabled,Enabled" bitfld.long 0x04 0. " MPR_CMP ,MPR compare enable" "Disabled,Enabled" line.long 0x08 "MPSWDAR0,MMDC PHY SW Dummy Access Register 0" rbitfld.long 0x08 5. " SW_DUM_CMP3 ,SW dummy read byte3 compare results" "Failed,Passed" rbitfld.long 0x08 4. " SW_DUM_CMP2 ,SW dummy read byte2 compare results" "Failed,Passed" rbitfld.long 0x08 3. " SW_DUM_CMP1 ,SW dummy read byte1 compare results" "Failed,Passed" newline rbitfld.long 0x08 2. " SW_DUM_CMP0 ,SW dummy read byte0 compare results" "Failed,Passed" bitfld.long 0x08 1. " SW_DUMMY_RD ,SW dummy read" "Not generated,Generated" bitfld.long 0x08 0. " SW_DUMMY_WR ,SW dummy write" "Not generated,Generated" rgroup.long 0x898++0x1F line.long 0x00 "MPSWDRDR0,MMDC PHY SW Dummy Read Data Register 0" line.long 0x04 "MPSWDRDR1,MMDC PHY SW Dummy Read Data Register 1" line.long 0x08 "MPSWDRDR2,MMDC PHY SW Dummy Read Data Register 2" line.long 0x0C "MPSWDRDR3,MMDC PHY SW Dummy Read Data Register 3" line.long 0x10 "MPSWDRDR4,MMDC PHY SW Dummy Read Data Register 4" line.long 0x14 "MPSWDRDR5,MMDC PHY SW Dummy Read Data Register 5" line.long 0x18 "MPSWDRDR6,MMDC PHY SW Dummy Read Data Register 6" line.long 0x1C "MPSWDRDR7,MMDC PHY SW Dummy Read Data Register 7" group.long 0x8B8++0x03 line.long 0x00 "MPMUR0,MMDC PHY Measure Unit Register for DQ0-3" hexmask.long.word 0x00 16.--25. 1. " MU_UNIT_DEL_NUM ,Measure unit measured number of unit delay per cycle" bitfld.long 0x00 11. " FRC_MSR ,Force measurement on delay line" "Not forced,Forced" bitfld.long 0x00 10. " MU_BYP_EN ,Measure unit bypass enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--9. 1. " MU_BYP_VAL ,Measure unit bypass value" hgroup.long 0x8BC++0x03 hide.long 0x00 "MPWRCADL,MMDC PHY Write CA Delay Control Register" newline width 8. rgroup.long 0x8C0++0x03 line.long 0x00 "MPDCCR,MMDC PHY Duty Cycle Control Register" bitfld.long 0x00 28.--30. " RD_DQS3_FT_DCC ,Read dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 25.--27. " RD_DQS2_FT_DCC ,Read dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 22.--24. " RD_DQS1_FT_DCC ,Read dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." newline bitfld.long 0x00 19.--21. " RD_DQS0_FT_DCC ,Read dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 16.--18. " CK_FT1_DCC ,Secondary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 12.--14. " CK_FT0_DCC ,Primary duty cycle fine tuning control of DDR clock" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." newline bitfld.long 0x00 9.--11. " WR_DQS3_FT_DCC ,Write dqs3 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 6.--8. " WR_DQS2_FT_DCC ,Write dqs2 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." bitfld.long 0x00 3.--5. " WR_DQS1_FT_DCC ,Write dqs1 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." newline bitfld.long 0x00 0.--2. " WR_DQS0_FT_DCC ,Write dqs0 fine tune duty cycle control" ",48.5% low/51.5% high,50%,,51.5% low/48.5% high,?..." else group.long 0x18++0x03 line.long 0x00 "MDMISC,MMDC Core Miscellaneous Register" bitfld.long 0x00 3.--4. " DDR_TYPE ,DDR TYPE" "DDR3,LPDDR2,?..." endif width 0x0B tree.end tree "OCOTP_CTRL (On-Chip OTP Controller)" base ad:0x021BC000 width 22. group.long 0x00++0x13 line.long 0x00 "OCOTP_CTRL,OTP Controller Control Register" hexmask.long.word 0x00 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable [key: 0x3E77]" bitfld.long 0x00 12. " CRC_FAIL ,Set by controller when CRC value != CRC fuse" "Equal,Not equal" bitfld.long 0x00 11. " CRC_TEST ,Set to calculate CRC" "Not set,Set" newline bitfld.long 0x00 10. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not forced,Forced" bitfld.long 0x00 9. " ERROR ,Accessing to locked region error" "No error,Error" newline rbitfld.long 0x00 8. " BUSY ,OTP controller status bit" "Not busy,Busy" hexmask.long.byte 0x00 0.--6. 1. " ADDR ,OTP write and read access address register" line.long 0x04 "OCOTP_CTRL_SET,OTP Controller Control Set Register" hexmask.long.word 0x04 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable" bitfld.long 0x04 12. " CRC_FAIL ,Set by controller when CRC value != CRC fuse" "Equal,Not equal" bitfld.long 0x04 11. " CRC_TEST ,Set to calculate CRC" "Not set,Set" newline bitfld.long 0x04 10. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not forced,Forced" bitfld.long 0x04 9. " ERROR ,Accessing to locked region error" "No error,Error" newline rbitfld.long 0x04 8. " BUSY ,OTP controller status bit" "Not effect,Set" hexmask.long.byte 0x04 0.--6. 1. " ADDR ,OTP write and read access address register" line.long 0x08 "OCOTP_CTRL_CLR,OTP Controller Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable" bitfld.long 0x08 12. " CRC_FAIL ,Set by controller when CRC value != CRC fuse" "Equal,Not equal" bitfld.long 0x08 11. " CRC_TEST ,Set to calculate CRC" "Not set,Set" newline bitfld.long 0x08 10. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not forced,Forced" bitfld.long 0x08 9. " ERROR ,Accessing to locked region error" "No error,Error" newline rbitfld.long 0x08 8. " BUSY ,OTP controller status bit" "No effect,Clear" hexmask.long.byte 0x08 0.--6. 1. " ADDR ,OTP write and read access address register" line.long 0x0C "OCOTP_CTRL_TOG,OTP Controller Control Toggle Register" hexmask.long.word 0x0C 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable" bitfld.long 0x0C 12. " CRC_FAIL ,Set by controller when CRC value != CRC fuse" "Equal,Not equal" bitfld.long 0x0C 11. " CRC_TEST ,Set to calculate CRC" "Not set,Set" newline bitfld.long 0x0C 10. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not forced,Forced" bitfld.long 0x0C 9. " ERROR ,Accessing to locked region error" "No error,Error" newline rbitfld.long 0x0C 8. " BUSY ,OTP controller status bit" "Not toggle,Toggle" hexmask.long.byte 0x0C 0.--6. 1. " ADDR ,OTP write and read access address register" line.long 0x10 "OCOTP_TIMING,OTP Controller Timing Register" bitfld.long 0x10 22.--27. " WAIT ,Time interval between auto read and write access in one time program" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 16.--21. " STROBE_READ ,Strobe period in one time read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x10 12.--15. " RELAX ,Time to add to all default timing parameters other than the Tpgm and Trd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x10 0.--11. 1. " STROBE_PROG ,Strobe period in one time write OTP" group.long 0x20++0x03 line.long 0x00 "OCOTP_DATA,OTP Controller Write Data Register" group.long 0x30++0x03 line.long 0x00 "OCOTP_READ_CTRL,OTP Controller Write Data Register" bitfld.long 0x00 0. " READ_FUSE ,Initiate a read to OTP" "Not initiated,Initiated" group.long 0x40++0x03 line.long 0x00 "OCOTP_READ_FUSE_DATA,OTP Controller Read Data Register" group.long 0x50++0x03 line.long 0x00 "OCOTP_SW_STICKY,Sticky bit Register" bitfld.long 0x00 2. " FIELD_RETURN_LOCK ,Shadow register write and OTP write lock for FIELD_RETURN region" "Not locked,Locked" bitfld.long 0x00 1. " SRK_REVOKE_LOCK ,Shadow register write and OTP write lock for SRK_REVOKE/MC_ERA/AP_BI_VER region" "Not locked,Locked" group.long 0x60++0x0F line.long 0x00 "OCOTP_SCS,Software Controllable Signals Register" bitfld.long 0x00 31. " LOCK ,HW_OCOTP_SCS register lock" "Not locked,Locked" hexmask.long 0x00 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use" bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG debug enable" "Disabled,Enabled" line.long 0x04 "OCOTP_SCS_SET,Software Controllable Signals Set Register" bitfld.long 0x04 31. " LOCK ,Lock set" "No effect,Set" hexmask.long 0x04 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use" bitfld.long 0x04 0. " HAB_JDE ,HAB JTAG debug enable set" "No effect,Set" line.long 0x08 "OCOTP_SCS_CLR,Software Controllable Signals Clear Register" bitfld.long 0x08 31. " LOCK ,Lock clear" "No effect,Clear" hexmask.long 0x08 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use" bitfld.long 0x08 0. " HAB_JDE ,HAB JTAG debug enable clear" "No effect,Clear" line.long 0x0C "OCOTP_SCS_TOG,Software Controllable Signals Toggle Register" bitfld.long 0x0C 31. " LOCK ,Lock toggle" "Not toggle,Toggle" hexmask.long 0x0C 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use" bitfld.long 0x0C 0. " HAB_JDE ,HAB JTAG debug enable clear" "Not toggle,Toggle" group.long 0x70++0x03 line.long 0x00 "OCOTP_CRC_ADDR,OTP Controller CRC test address" bitfld.long 0x00 19. " OTPMK_CRC ,Enable bit for CRC32 calculation address" "Low,High" hexmask.long.byte 0x00 16.--18. 0x01 " CRC_ADDR ,Address of 32-bit CRC result for comparing" hexmask.long.byte 0x00 8.--15. 0x01 " DATA_END_ADDR ,Start address of fuse location for CRC calculation" hexmask.long.byte 0x00 0.--7. 0x01 " DATA_START_ADDR ,End address of fuse location for CRC calculation" group.long 0x80++0x03 line.long 0x00 "OCOTP_CRC_VALUE,OTP Controller CRC Value Register" bitfld.long 0x00 16.--21. " RELAX_READ ,This count value specifies the time to add to read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--11. 1. " READ_PROG ,This count value specifies the time to add to write OTP" rgroup.long 0x90++0x03 line.long 0x00 "OCOTP_VERSION,OTP Controller Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0x100++0x03 line.long 0x00 "OCOTP_TIMING2,OTP Controller Timing Register 2" group.long 0x400++0x03 line.long 0x00 "OCOTP_LOCK,Value of OTP Bank0 Word0" rbitfld.long 0x00 31. " GP3_RLOCK ,Status of shadow register and OTP read lock for GP3 region" "Low,High" bitfld.long 0x00 30. " GP4_RLOCK ,Status of shadow register and OTP read lock for GP4 region" "Low,High" rbitfld.long 0x00 25. " PIN ,Status of Pin access lock bit" "Low,High" newline rbitfld.long 0x00 23. " GP4 ,Status of shadow register and OTP write lock for GP4 region" "Low,High" rbitfld.long 0x00 22. " MISC_CONF ,Status of shadow register and OTP write lock for misc_conf region" "Low,High" rbitfld.long 0x00 21. " ROM_PATCH ,Status of shadow register and OTP write lock for rom_patch region" "Low,High" newline rbitfld.long 0x00 20. " OTPMK_CRC ,Status of shadow register and OTP write lock for otpmk crc region" "Low,High" rbitfld.long 0x00 18.--19. " ANALOG ,Status of shadow register and OTP write lock for analog region" "0,1,2,3" rbitfld.long 0x00 17. " OTPMK ,Status of shadow register and OTP write lock for OTPMK region" "Low,High" newline rbitfld.long 0x00 16. " SW_GP ,Status of shadow register and OTP write lock for GP3 region" "Low,High" rbitfld.long 0x00 15. " GP3 ,Status of shadow register and OTP write lock for GP3 region" "Low,High" rbitfld.long 0x00 14. " SRK ,Status of shadow register and OTP write lock for srk region" "Low,High" newline rbitfld.long 0x00 12.--13. " GP2 ,Status of shadow register and OTP write lock for gp2 region" "0,1,2,3" rbitfld.long 0x00 10.--11. " GP1 ,Status of shadow register and OTP write lock for gp2 region" "0,1,2,3" rbitfld.long 0x00 8.--9. " MAC_ADDR ,Status of shadow register and OTP write lock for mac_addr region" "0,1,2,3" newline rbitfld.long 0x00 6. " SJC_RESP ,Status of shadow register read and write" "Low,High" rbitfld.long 0x00 4.--5. " MEM_TRIM ,Status of shadow register and OTP write lock for mem_trim region" "0,1,2,3" rbitfld.long 0x00 2.--3. " BOOT_CFG ,Status of shadow register and OTP write lock for boot_cfg region" "0,1,2,3" newline rbitfld.long 0x00 0.--1. " TESTER ,Status of shadow register and OTp write lock for tester region" "0,1,2,3" group.long 0x410++0x03 line.long 0x00 "OCOTP_CFG0,Value of OTP Bank0 Word1" group.long 0x420++0x03 line.long 0x00 "OCOTP_CFG1,Value of OTP Bank0 Word2" group.long 0x430++0x03 line.long 0x00 "OCOTP_CFG2,Value of OTP Bank0 Word3" group.long 0x440++0x03 line.long 0x00 "OCOTP_CFG3,Value of OTP Bank0 Word4" group.long 0x450++0x03 line.long 0x00 "OCOTP_CFG4,Value of OTP Bank0 Word5" group.long 0x460++0x03 line.long 0x00 "OCOTP_CFG5,Value of OTP Bank0 Word6" group.long 0x470++0x03 line.long 0x00 "OCOTP_CFG6,Value of OTP Bank0 Word7" group.long 0x480++0x03 line.long 0x00 "OCOTP_MEM0,Value of OTP Bank1 Word0" group.long 0x490++0x03 line.long 0x00 "OCOTP_MEM1,Value of OTP Bank1 Word1" group.long 0x4A0++0x03 line.long 0x00 "OCOTP_MEM2,Value of OTP Bank1 Word2" group.long 0x4B0++0x03 line.long 0x00 "OCOTP_MEM3,Value of OTP Bank1 Word3" group.long 0x4C0++0x03 line.long 0x00 "OCOTP_MEM4,Value of OTP Bank1 Word4" group.long 0x4D0++0x03 line.long 0x00 "OCOTP_ANA0,Value of OTP Bank1 Word5" group.long 0x4E0++0x03 line.long 0x00 "OCOTP_ANA1,Value of OTP Bank1 Word6" group.long 0x4F0++0x03 line.long 0x00 "OCOTP_ANA2,Value of OTP Bank1 Word7" group.long 0x500++0x03 line.long 0x00 "OCOTP_OTPMK0,Value of OTP Bank2 Word0" group.long 0x510++0x03 line.long 0x00 "OCOTP_OTPMK1,Value of OTP Bank2 Word1" group.long 0x520++0x03 line.long 0x00 "OCOTP_OTPMK2,Value of OTP Bank2 Word2" group.long 0x530++0x03 line.long 0x00 "OCOTP_OTPMK3,Value of OTP Bank2 Word3" group.long 0x540++0x03 line.long 0x00 "OCOTP_OTPMK4,Value of OTP Bank2 Word4" group.long 0x550++0x03 line.long 0x00 "OCOTP_OTPMK5,Value of OTP Bank2 Word5" group.long 0x560++0x03 line.long 0x00 "OCOTP_OTPMK6,Value of OTP Bank2 Word6" group.long 0x570++0x03 line.long 0x00 "OCOTP_OTPMK7,Value of OTP Bank2 Word7" group.long 0x580++0x03 line.long 0x00 "OCOTP_SRK0,Shadow Register for OTP Bank3 Word0" group.long 0x590++0x03 line.long 0x00 "OCOTP_SRK1,Shadow Register for OTP Bank3 Word1" group.long 0x5A0++0x03 line.long 0x00 "OCOTP_SRK2,Shadow Register for OTP Bank3 Word2" group.long 0x5B0++0x03 line.long 0x00 "OCOTP_SRK3,Shadow Register for OTP Bank3 Word3" group.long 0x5C0++0x03 line.long 0x00 "OCOTP_SRK4,Shadow Register for OTP Bank3 Word4" group.long 0x5D0++0x03 line.long 0x00 "OCOTP_SRK5,Shadow Register for OTP Bank3 Word5" group.long 0x5E0++0x03 line.long 0x00 "OCOTP_SRK6,Shadow Register for OTP Bank3 Word6" group.long 0x5F0++0x03 line.long 0x00 "OCOTP_SRK7,Shadow Register for OTP Bank3 Word7" group.long 0x600++0x03 line.long 0x00 "OCOTP_SJC_RESP0,Value of OTP Bank4 Word0" group.long 0x610++0x03 line.long 0x00 "OCOTP_SJC_RESP1,Value of OTP Bank4 Word1" group.long 0x620++0x03 line.long 0x00 "OCOTP_MAC0,Value of OTP Bank4 Word2" group.long 0x630++0x03 line.long 0x00 "OCOTP_MAC1,Value of OTP Bank4 Word3" group.long 0x640++0x03 line.long 0x00 "OCOTP_MAC,Value of OTP Bank4 Word4" group.long 0x650++0x03 line.long 0x00 "OCOTP_CRC,Value of OTP Bank4 Word5" group.long 0x660++0x03 line.long 0x00 "OCOTP_GP1,Value of OTP Bank4 Word6" group.long 0x670++0x03 line.long 0x00 "OCOTP_GP2,Value of OTP Bank4 Word7" group.long 0x680++0x03 line.long 0x00 "OCOTP_SW_GP0,Value of OTP Bank5 Word0" group.long 0x690++0x03 line.long 0x00 "OCOTP_SW_GP1,Value of OTP Bank5 Word1" group.long 0x6A0++0x03 line.long 0x00 "OCOTP_SW_GP2,Value of OTP Bank5 Word2" group.long 0x6B0++0x03 line.long 0x00 "OCOTP_SW_GP3,Value of OTP Bank5 Word3" group.long 0x6C0++0x03 line.long 0x00 "OCOTP_SW_GP4,Value of OTP Bank5 Word4" group.long 0x6D0++0x03 line.long 0x00 "OCOTP_MISC_CONF,Value of OTP Bank5 Word5" group.long 0x6E0++0x03 line.long 0x00 "OCOTP_FIELD_RETURN,Value of OTP Bank5 Word6" group.long 0x6F0++0x03 line.long 0x00 "OCOTP_SRK_REVOKE,Value of OTP Bank5 Word7" group.long 0x800++0x03 line.long 0x00 "OCOTP_ROM_PATCH0,Value of OTP Bank6 Word0" group.long 0x810++0x03 line.long 0x00 "OCOTP_ROM_PATCH1,Value of OTP Bank6 Word1" group.long 0x820++0x03 line.long 0x00 "OCOTP_ROM_PATCH2,Value of OTP Bank6 Word2" group.long 0x830++0x03 line.long 0x00 "OCOTP_ROM_PATCH3,Value of OTP Bank6 Word3" group.long 0x840++0x03 line.long 0x00 "OCOTP_ROM_PATCH4,Value of OTP Bank6 Word4" group.long 0x850++0x03 line.long 0x00 "OCOTP_ROM_PATCH5,Value of OTP Bank6 Word5" group.long 0x860++0x03 line.long 0x00 "OCOTP_ROM_PATCH6,Value of OTP Bank6 Word6" group.long 0x870++0x03 line.long 0x00 "OCOTP_ROM_PATCH7,Value of OTP Bank6 Word7" group.long 0x880++0x03 line.long 0x00 "OCOTP_GP3_0,Value of OTP Bank7 Word0" group.long 0x890++0x03 line.long 0x00 "OCOTP_GP3_1,Value of OTP Bank7 Word1" group.long 0x8A0++0x03 line.long 0x00 "OCOTP_GP3_2,Value of OTP Bank7 Word2" group.long 0x8B0++0x03 line.long 0x00 "OCOTP_GP3_3,Value of OTP Bank7 Word3" group.long 0x8C0++0x03 line.long 0x00 "OCOTP_GP3_4,Value of OTP Bank7 Word4" group.long 0x8D0++0x03 line.long 0x00 "OCOTP_GP4_0,Value of OTP Bank7 Word5" group.long 0x8E0++0x03 line.long 0x00 "OCOTP_GP4_1,Value of OTP Bank7 Word6" group.long 0x8F0++0x03 line.long 0x00 "OCOTP_GP4_2,Value of OTP Bank7 Word7" width 0x0B tree.end tree "PMU (Power Management Unit)" base ad:0x020C8110 width 14. group.long 0x00++0x03 line.long 0x00 "REG_1P1,Regulator 1P1 Register" bitfld.long 0x00 19. " SELREF_WEAK_LINREG ,Select source for reference voltage of 1p1 regulator" "Low-power-bandgap,VDD_SOC_CAP" bitfld.long 0x00 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x00 17. " OK_VDD1P1 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x00 16. " BO_VDD1P1 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x00 8.--12. " OUTPUT_TRG ,Regulator output voltage" ",,,,0.8V,0.825V,0.850V,0.875V,0.9V,0.925V,0.950V,0.975V,1.0V,1.025V,1.050V,1.075V,1.1V,1.125V,1.150V,1.175V,1.2V,1.225V,1.250V,1.275V,1.3V,1.325V,1.350V,1.375V,?..." bitfld.long 0x00 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x00 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" sif cpuis("IMX6SLL")||cpuis("IMX6ULL") group.long 0x04++0x0B line.long 0x00 "REG_1P1_SET,Regulator 1P1 Set Register" bitfld.long 0x00 19. " SELREF_WEAK_LINREG ,Select source for reference voltage of 1p1 regulator" "Low-power-bandgap,VDD_SOC_CAP" bitfld.long 0x00 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x00 17. " OK_VDD1P1 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x00 16. " BO_VDD1P1 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x00 8.--12. " OUTPUT_TRG ,Regulator output voltage" ",,,,0.8V,0.825V,0.850V,0.875V,0.9V,0.925V,0.950V,0.975V,1.0V,1.025V,1.050V,1.075V,1.1V,1.125V,1.150V,1.175V,1.2V,1.225V,1.250V,1.275V,1.3V,1.325V,1.350V,1.375V,?..." bitfld.long 0x00 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x00 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x04 "REG_1P1_CLR,Regulator 1P1 Clear Register" bitfld.long 0x04 19. " SELREF_WEAK_LINREG ,Select source for reference voltage of 1p1 regulator" "Low-power-bandgap,VDD_SOC_CAP" bitfld.long 0x04 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x04 17. " OK_VDD1P1 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x04 16. " BO_VDD1P1 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x04 8.--12. " OUTPUT_TRG ,Regulator output voltage" ",,,,0.8V,0.825V,0.850V,0.875V,0.9V,0.925V,0.950V,0.975V,1.0V,1.025V,1.050V,1.075V,1.1V,1.125V,1.150V,1.175V,1.2V,1.225V,1.250V,1.275V,1.3V,1.325V,1.350V,1.375V,?..." bitfld.long 0x04 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x04 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x04 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x08 "REG_1P1_TOG,Regulator 1P1 Toggle Register" bitfld.long 0x08 19. " SELREF_WEAK_LINREG ,Select source for reference voltage of 1p1 regulator" "Low-power-bandgap,VDD_SOC_CAP" bitfld.long 0x08 18. " ENABLE_WEAK_LINREG ,Enables the weak 1p1 regulator" "Disabled,Enabled" rbitfld.long 0x08 17. " OK_VDD1P1 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x08 16. " BO_VDD1P1 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" newline bitfld.long 0x08 8.--12. " OUTPUT_TRG ,Regulator output voltage" ",,,,0.8V,0.825V,0.850V,0.875V,0.9V,0.925V,0.950V,0.975V,1.0V,1.025V,1.050V,1.075V,1.1V,1.125V,1.150V,1.175V,1.2V,1.225V,1.250V,1.275V,1.3V,1.325V,1.350V,1.375V,?..." bitfld.long 0x08 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x08 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x08 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "REG_3P0,Regulator 3P0 Register" rbitfld.long 0x00 17. " OK_VDD3P0 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x00 16. " BO_VDD3P0 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" bitfld.long 0x00 8.--12. " OUTPUT_TRG ,Regulator output voltage" "2.625V,2.65V,2.675V,2.7V,2.725V,2.75V,2.775V,2.8V,2.825V,2.85V,2.875V,2.9V,2.925V,2.95V,2.975V,3.0V,3.025V,3.05V,3.075V,3.1V,3.125V,3.15V,3.175V,3.2V,3.225V,3.25V,3.275V,3.3V,3.325V,3.35V,3.375V,3.4V" bitfld.long 0x00 7. " VBUS_SEL ,Select input voltage source for LDO_3P0" "USB_OTG1_VBUS,USB_OTG2_VBUS" newline bitfld.long 0x00 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x00 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" sif cpuis("IMX6ULL") group.long 0x14++0x0B line.long 0x00 "REG_3P0_SET,Regulator 3P0 Set Register" rbitfld.long 0x00 17. " OK_VDD3P0 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x00 16. " BO_VDD3P0 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" bitfld.long 0x00 8.--12. " OUTPUT_TRG ,Regulator output voltage" "2.625V,2.65V,2.675V,2.7V,2.725V,2.75V,2.775V,2.8V,2.825V,2.85V,2.875V,2.9V,2.925V,2.95V,2.975V,3.0V,3.025V,3.05V,3.075V,3.1V,3.125V,3.15V,3.175V,3.2V,3.225V,3.25V,3.275V,3.3V,3.325V,3.35V,3.375V,3.4V" bitfld.long 0x00 7. " VBUS_SEL ,Select input voltage source for LDO_3P0" "USB_OTG1_VBUS,USB_OTG2_VBUS" newline bitfld.long 0x00 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x00 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x04 "REG_3P0_CLR,Regulator 3P0 Clear Register" rbitfld.long 0x04 17. " OK_VDD3P0 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x04 16. " BO_VDD3P0 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" bitfld.long 0x04 8.--12. " OUTPUT_TRG ,Regulator output voltage" "2.625V,2.65V,2.675V,2.7V,2.725V,2.75V,2.775V,2.8V,2.825V,2.85V,2.875V,2.9V,2.925V,2.95V,2.975V,3.0V,3.025V,3.05V,3.075V,3.1V,3.125V,3.15V,3.175V,3.2V,3.225V,3.25V,3.275V,3.3V,3.325V,3.35V,3.375V,3.4V" bitfld.long 0x04 7. " VBUS_SEL ,Select input voltage source for LDO_3P0" "USB_OTG1_VBUS,USB_OTG2_VBUS" newline bitfld.long 0x04 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x04 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x08 "REG_3P0_TOG,Regulator 3P0 Toggle Register" rbitfld.long 0x08 17. " OK_VDD3P0 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x08 16. " BO_VDD3P0 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" bitfld.long 0x08 8.--12. " OUTPUT_TRG ,Regulator output voltage" "2.625V,2.65V,2.675V,2.7V,2.725V,2.75V,2.775V,2.8V,2.825V,2.85V,2.875V,2.9V,2.925V,2.95V,2.975V,3.0V,3.025V,3.05V,3.075V,3.1V,3.125V,3.15V,3.175V,3.2V,3.225V,3.25V,3.275V,3.3V,3.325V,3.35V,3.375V,3.4V" bitfld.long 0x08 7. " VBUS_SEL ,Select input voltage source for LDO_3P0" "USB_OTG1_VBUS,USB_OTG2_VBUS" newline bitfld.long 0x08 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x08 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" endif group.long 0x20++0x03 line.long 0x00 "REG_2P5,Regulator 2P5 Register" bitfld.long 0x00 18. " ENABLE_WEAK_LINREG ,Enables the weak 2p5 regulator" "Disabled,Enabled" rbitfld.long 0x00 17. " OK_VDD2P5 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x00 16. " BO_VDD2P5 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" bitfld.long 0x00 8.--12. " OUTPUT_TRG ,Regulator output voltage" "2.1V,2.125V,2.15V,2.175V,2.2V,2.225V,2.25V,2.275V,2.3V,2.325V,2.35V,2.375V,2.4V,2.425V,2.45V,2.475V,2.5V,2.525V,2.55V,2.575V,2.6V,2.625V,2.65V,2.675V,2.7V,2.725V,2.75V,2.775V,2.8V,2.825V,2.85V,2.875V" newline bitfld.long 0x00 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x00 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" sif cpuis("IMX6ULL") group.long 0x24++0x0B line.long 0x00 "REG_2P5_SET,Regulator 2P5 Set Register" bitfld.long 0x00 18. " ENABLE_WEAK_LINREG ,Enables the weak 2p5 regulator" "Disabled,Enabled" rbitfld.long 0x00 17. " OK_VDD2P5 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x00 16. " BO_VDD2P5 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" bitfld.long 0x00 8.--12. " OUTPUT_TRG ,Regulator output voltage" "2.1V,2.125V,2.15V,2.175V,2.2V,2.225V,2.25V,2.275V,2.3V,2.325V,2.35V,2.375V,2.4V,2.425V,2.45V,2.475V,2.5V,2.525V,2.55V,2.575V,2.6V,2.625V,2.65V,2.675V,2.7V,2.725V,2.75V,2.775V,2.8V,2.825V,2.85V,2.875V" newline bitfld.long 0x00 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x00 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x04 "REG_2P5_CLR,Regulator 2P5 Clear Register" bitfld.long 0x04 18. " ENABLE_WEAK_LINREG ,Enables the weak 2p5 regulator" "Disabled,Enabled" rbitfld.long 0x04 17. " OK_VDD2P5 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x04 16. " BO_VDD2P5 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" bitfld.long 0x04 8.--12. " OUTPUT_TRG ,Regulator output voltage" "2.1V,2.125V,2.15V,2.175V,2.2V,2.225V,2.25V,2.275V,2.3V,2.325V,2.35V,2.375V,2.4V,2.425V,2.45V,2.475V,2.5V,2.525V,2.55V,2.575V,2.6V,2.625V,2.65V,2.675V,2.7V,2.725V,2.75V,2.775V,2.8V,2.825V,2.85V,2.875V" newline bitfld.long 0x04 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x04 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x04 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x04 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" line.long 0x08 "REG_2P5_TOG,Regulator 2P5 Toggle Register" bitfld.long 0x08 18. " ENABLE_WEAK_LINREG ,Enables the weak 2p5 regulator" "Disabled,Enabled" rbitfld.long 0x08 17. " OK_VDD2P5 ,Status bit that signals when the regulator output is ok" "Not ok,Ok" rbitfld.long 0x08 16. " BO_VDD2P5 ,Status bit that signals when a brownout is detected on the regulator output" "Not detected,Detected" bitfld.long 0x08 8.--12. " OUTPUT_TRG ,Regulator output voltage" "2.1V,2.125V,2.15V,2.175V,2.2V,2.225V,2.25V,2.275V,2.3V,2.325V,2.35V,2.375V,2.4V,2.425V,2.45V,2.475V,2.5V,2.525V,2.55V,2.575V,2.6V,2.625V,2.65V,2.675V,2.7V,2.725V,2.75V,2.775V,2.8V,2.825V,2.85V,2.875V" newline bitfld.long 0x08 4.--6. " BO_OFFSET ,Regulator brownout offset voltage" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x08 3. " ENABLE_PULLDOWN ,Control bit to enable the pull-down circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 2. " ENABLE_ILIMIT ,Control bit to enable the current-limit circuitry in the regulator" "Disabled,Enabled" bitfld.long 0x08 1. " ENABLE_BO ,Control bit to enable the brownout circuitry in the regulator" "Disabled,Enabled" newline bitfld.long 0x08 0. " ENABLE_LINREG ,Control bit to enable the regulator output" "Disabled,Enabled" endif group.long 0x30++0x03 line.long 0x00 "REG_CORE,Digital Regulator Core Register" bitfld.long 0x00 29. " FET_ODRIVE ,Increases the gate drive on power gating fets to reduce leakage in the off state" "Not set,Set" bitfld.long 0x00 27.--28. " RAMP_RATE ,Regulator voltage ramp rate" "Fast,Medium Fast,Medium Slow,Slow" bitfld.long 0x00 18.--22. " REG2_TARG ,Defines the target voltage for the SOC power domain" "Gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" bitfld.long 0x00 0.--4. " REG0_TARG ,Defines the target voltage for the arm core power domain" "Gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" sif cpuis("IMX6ULL") group.long 0x34++0x0B line.long 0x00 "REG_CORE_SET,Digital Regulator Core Set Register" bitfld.long 0x00 29. " FET_ODRIVE ,Increases the gate drive on power gating fets to reduce leakage in the off state" "Not set,Set" bitfld.long 0x00 27.--28. " RAMP_RATE ,Regulator voltage ramp rate" "Fast,Medium Fast,Medium Slow,Slow" bitfld.long 0x00 18.--22. " REG2_TARG ,Defines the target voltage for the SOC power domain" "Gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" bitfld.long 0x00 0.--4. " REG0_TARG ,Defines the target voltage for the arm core power domain" "Gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" line.long 0x04 "REG_CORE_CLR,Digital Regulator Core Clear Register" bitfld.long 0x04 29. " FET_ODRIVE ,Increases the gate drive on power gating fets to reduce leakage in the off state" "Not set,Set" bitfld.long 0x04 27.--28. " RAMP_RATE ,Regulator voltage ramp rate" "Fast,Medium Fast,Medium Slow,Slow" bitfld.long 0x04 18.--22. " REG2_TARG ,Defines the target voltage for the SOC power domain" "Gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" bitfld.long 0x04 0.--4. " REG0_TARG ,Defines the target voltage for the arm core power domain" "Gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" line.long 0x08 "REG_CORE_TOG,Digital Regulator Core Toggle Register" bitfld.long 0x08 29. " FET_ODRIVE ,Increases the gate drive on power gating fets to reduce leakage in the off state" "Not set,Set" bitfld.long 0x08 27.--28. " RAMP_RATE ,Regulator voltage ramp rate" "Fast,Medium Fast,Medium Slow,Slow" bitfld.long 0x08 18.--22. " REG2_TARG ,Defines the target voltage for the SOC power domain" "Gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" bitfld.long 0x08 0.--4. " REG0_TARG ,Defines the target voltage for the arm core power domain" "Gated off,0.725V,0.75V,0.775V,0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,Full on" endif group.long 0x40++0x03 line.long 0x00 "MISC0,Miscellaneous Register 0" bitfld.long 0x00 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x00 30. " XTAL_24M_PWD ,Power down the 24M crystal oscillator" "No,Yes" bitfld.long 0x00 29. " RTC_XTAL_SOURCE ,Chip source for rtc clock" "Internal,RTC_XTAL" bitfld.long 0x00 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock" "0.5ms,1.oms,2.0ms,3.0ms,4.0ms,5.0ms,6.0ms,7.0ms" newline bitfld.long 0x00 25. " CLKGATE_CTRL ,Allows disabling the clock gate" "Allowed,Not allowed" bitfld.long 0x00 16. " OSC_XTALOK_EN ,Enables the detector that signals when the 24MHz crystal oscillator is stable" "Disabled,Enabled" rbitfld.long 0x00 15. " OSC_XTALOK ,Signals that the output of the 24-MHz crystal oscillator is stable" "Not stable,Stable" bitfld.long 0x00 13.--14. " OSC_I ,Bias current in the 24MHz oscillator" "Nominal,Decrease by 12.5%,Decrease by 25%,Decrease by 37.5%" newline bitfld.long 0x00 12. " DISCON_HIGHI_SNVS ,Switch from VDD_HIGH_IN to VDD_SNVS_IN" "On,Off" bitfld.long 0x00 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode" "SUSPEND(DSM),STANDBY,STOP(low power),STOP(very low power)" bitfld.long 0x00 7. " REFTOP_VBGUP ,Signals that the analog bandgap voltage is up and stable" "Not stable,Stable" bitfld.long 0x00 4.--6. " REFTOP_VBGADJ ,REFTOP_VBGADJ" "Nominal VBG,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG+0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" newline bitfld.long 0x00 3. " REFTOP_SELFBIASOFF ,Disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x00 0. " REFTOP_PWD ,Power-down the analog bandgap reference circuitry" "Powered,Powered down" group.long 0x50++0x0F line.long 0x00 "MISC1,Miscellaneous Register 1" eventfld.long 0x00 31. " IRQ_DIG_BO ,Digital regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " IRQ_ANA_BO ,Analog regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt" "No interrupt,Interrupt" bitfld.long 0x00 17. " PFD_528_AUTOGATE_EN ,Enables clkgate (reset) of all PFD_528 clks anytime PLL_528 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x00 16. " PFD_480_AUTOGATE_EN ,Enables clkgate (reset) of all PFD_480 clks anytime USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x00 12. " LVDSCLK1_IBEN ,Enable the LVDS input buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x00 10. " LVDSCLK1_OBEN ,Enable the LVDS output buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x00 0.--4. " LVDS1_CLK_SEL ,Select clk to be routed to anaclk1/1b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x04 "MISC1_SET,Miscellaneous Register 1" eventfld.long 0x04 31. " IRQ_DIG_BO ,Digital regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x04 30. " IRQ_ANA_BO ,Analog regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x04 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt" "No interrupt,Interrupt" eventfld.long 0x04 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt" "No interrupt,Interrupt" bitfld.long 0x04 17. " PFD_528_AUTOGATE_EN ,Enables clkgate (reset) of all PFD_528 clks anytime PLL_528 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x04 16. " PFD_480_AUTOGATE_EN ,Enables clkgate (reset) of all PFD_480 clks anytime USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x04 12. " LVDSCLK1_IBEN ,Enable the LVDS input buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x04 10. " LVDSCLK1_OBEN ,Enable the LVDS output buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x04 0.--4. " LVDS1_CLK_SEL ,Select clk to be routed to anaclk1/1b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x08 "MISC1_CLR,Miscellaneous Register 1" eventfld.long 0x08 31. " IRQ_DIG_BO ,Digital regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x08 30. " IRQ_ANA_BO ,Analog regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x08 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt" "No interrupt,Interrupt" eventfld.long 0x08 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt" "No interrupt,Interrupt" newline eventfld.long 0x08 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt" "No interrupt,Interrupt" bitfld.long 0x08 17. " PFD_528_AUTOGATE_EN ,Enables clkgate (reset) of all PFD_528 clks anytime PLL_528 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x08 16. " PFD_480_AUTOGATE_EN ,Enables clkgate (reset) of all PFD_480 clks anytime USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x08 12. " LVDSCLK1_IBEN ,Enable the LVDS input buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x08 10. " LVDSCLK1_OBEN ,Enable the LVDS output buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x08 0.--4. " LVDS1_CLK_SEL ,Select clk to be routed to anaclk1/1b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" line.long 0x0C "MISC1_TOG,Miscellaneous Register 1" eventfld.long 0x0C 31. " IRQ_DIG_BO ,Digital regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x0C 30. " IRQ_ANA_BO ,Analog regulator brownout interrupt" "No interrupt,Interrupt" eventfld.long 0x0C 29. " IRQ_TEMPHIGH ,Temperature sensor high interrupt" "No interrupt,Interrupt" eventfld.long 0x0C 28. " IRQ_TEMPLOW ,Temperature sensor low interrupt" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " IRQ_TEMPPANIC ,Temperature sensor panic interrupt" "No interrupt,Interrupt" bitfld.long 0x0C 17. " PFD_528_AUTOGATE_EN ,Enables clkgate (reset) of all PFD_528 clks anytime PLL_528 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x0C 16. " PFD_480_AUTOGATE_EN ,Enables clkgate (reset) of all PFD_480 clks anytime USB1_PLL_480 is unlocked or powered off" "Disabled,Enabled" bitfld.long 0x0C 12. " LVDSCLK1_IBEN ,Enable the LVDS input buffer for anaclk1/1b" "Disabled,Enabled" newline bitfld.long 0x0C 10. " LVDSCLK1_OBEN ,Enable the LVDS output buffer for anaclk1/1b" "Disabled,Enabled" bitfld.long 0x0C 0.--4. " LVDS1_CLK_SEL ,Select clk to be routed to anaclk1/1b" "ARM_PLL,SYS_PLL,PFD4,PFD5,PFD6,PFD7,AUDIO_PLL,VIDEO_PLL,,ETHERNET_REF,,,USB1_PLL,USB2_PLL,PFD0,PFD1,PFD2,PFD3,XTAL,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7,PFD7" group.long 0x60++0x0F line.long 0x00 "MISC2,Miscellaneous Register 2" bitfld.long 0x00 30.--31. " VIDEO_DIV ,Post-divider for video PLL" "/1,/2,/1,/4" bitfld.long 0x00 28.--29. " REG2_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x00 24.--25. " REG0_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x00 23. 15. " AUDIO_DIV_MSB ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" newline rbitfld.long 0x00 22. " REG2_OK ,Signals that the voltage is above the brownout level for the SOC supply" "Below,Above" bitfld.long 0x00 21. " REG2_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" rbitfld.long 0x00 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "No brownout,Brownout" rbitfld.long 0x00 16.--18. " REG2_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" newline bitfld.long 0x00 7. " PLL3_DISABLE ,Turn off the USB-PLL(PLL3) in run mode" "No,Yes" bitfld.long 0x00 5. " REG0_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" rbitfld.long 0x00 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "No brownout,Brownout" rbitfld.long 0x00 0.--2. " REG0_BO_OFFSET ,Defines the brown out voltage offset for the CORE power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" line.long 0x04 "MISC2_SET,Miscellaneous Register 2" bitfld.long 0x04 30.--31. " VIDEO_DIV ,Post-divider for video PLL" "/1,/2,/1,/4" bitfld.long 0x04 28.--29. " REG2_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x04 24.--25. " REG0_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x04 23. 15. " AUDIO_DIV ,Post-divider for Audio PLL" "/1,/2,/1,/4" newline rbitfld.long 0x04 22. " REG2_OK ,Signals that the voltage is above the brownout level for the SOC supply" "Below,Above" bitfld.long 0x04 21. " REG2_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" rbitfld.long 0x04 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "No brownout,Brownout" rbitfld.long 0x04 16.--18. " REG2_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" newline bitfld.long 0x04 7. " PLL3_DISABLE ,Turn off the USB-PLL(PLL3) in run mode" "No,Yes" bitfld.long 0x04 5. " REG0_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" rbitfld.long 0x04 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "No brownout,Brownout" rbitfld.long 0x04 0.--2. " REG0_BO_OFFSET ,Defines the brown out voltage offset for the CORE power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" line.long 0x08 "MISC2_CLR,Miscellaneous Register 2" bitfld.long 0x08 30.--31. " VIDEO_DIV ,Post-divider for video PLL" "/1,/2,/1,/4" bitfld.long 0x08 28.--29. " REG2_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x08 24.--25. " REG0_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x08 23. 15. " AUDIO_DIV_MSB ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" newline rbitfld.long 0x08 22. " REG2_OK ,Signals that the voltage is above the brownout level for the SOC supply" "Below,Above" bitfld.long 0x08 21. " REG2_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" rbitfld.long 0x08 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "No brownout,Brownout" rbitfld.long 0x08 16.--18. " REG2_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" newline bitfld.long 0x08 7. " PLL3_DISABLE ,Turn off the USB-PLL(PLL3) in run mode" "No,Yes" bitfld.long 0x08 5. " REG0_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" rbitfld.long 0x08 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "No brownout,Brownout" rbitfld.long 0x08 0.--2. " REG0_BO_OFFSET ,Defines the brown out voltage offset for the CORE power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" line.long 0x0C "MISC2_TOG,Miscellaneous Register 2" bitfld.long 0x0C 30.--31. " VIDEO_DIV ,Post-divider for video PLL" "/1,/2,/1,/4" bitfld.long 0x0C 28.--29. " REG2_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x0C 24.--25. " REG0_STEP_TIME ,Number of clock periods (24MHz clock)" "64,128,256,512" bitfld.long 0x0C 23. 15. " AUDIO_DIV_MSB ,MSB of Post-divider for Audio PLL" "/1,/2,/1,/4" newline rbitfld.long 0x0C 22. " REG2_OK ,Signals that the voltage is above the brownout level for the SOC supply" "Below,Above" bitfld.long 0x0C 21. " REG2_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" rbitfld.long 0x0C 19. " REG2_BO_STATUS ,Reg2 brownout status bit" "No brownout,Brownout" rbitfld.long 0x0C 16.--18. " REG2_BO_OFFSET ,Defines the brown out voltage offset for the xPU power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" newline bitfld.long 0x0C 7. " PLL3_DISABLE ,Turn off the USB-PLL(PLL3) in run mode" "No,Yes" bitfld.long 0x0C 5. " REG0_ENABLE_BO ,Enables the brownout detection" "Disabled,Enabled" rbitfld.long 0x0C 3. " REG0_BO_STATUS ,Reg0 brownout status bit" "No brownout,Brownout" rbitfld.long 0x0C 0.--2. " REG0_BO_OFFSET ,Defines the brown out voltage offset for the CORE power domain" "0V,0.025V,0.05V,0.075V,0.100V,0.125V,0.15V,0.175V" newline width 17. group.long 0x160++0x0B line.long 0x00 "LOWPWR_CTRL_SET,Low Power Control Register" bitfld.long 0x00 17. " MIX_PWRGATE ,Display power gate control" "Not gated,Gated" rbitfld.long 0x00 16. " XTALOSC_PWRUP_STAT ,Status of the 24MHz xtal oscillator" "Not stable,Stable" bitfld.long 0x00 14.--15. " XTALOSC_PWRUP_DELAY ,Specifies delay between 24MHz xtal power up until stable" "0.25ms,0.5ms,1ms,2ms" bitfld.long 0x00 13. " RCOSC_CG_OVERRIDE ,[Debug] Clock gating of certain digital logic clocked by the 24MHz clk" "0,1" newline bitfld.long 0x00 11. " DISPLAY_PWRGATE ,Display logic power gate control" "Not gated,Gated" bitfld.long 0x00 10. " CPU_PWRGATE ,CPU power gate control" "Not gated,Gated" bitfld.long 0x00 9. " L2_PWRGATE ,L2 power gate control" "Not gated,Gated" bitfld.long 0x00 8. " L1_PWRGATE ,L1 power gate control" "Not gated,Gated" newline bitfld.long 0x00 7. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No,Yes" bitfld.long 0x00 6. " LPBG_TEST ,Low power bandgap test bit" "0,1" bitfld.long 0x00 5. " LPBG_SEL ,Bandgap select" "Normal power,Low power" bitfld.long 0x00 4. " OSC_SEL ,Select the source for the 24MHz clock" "XTAL OSC,RC OSC" newline bitfld.long 0x00 1.--3. " RC_OSC_PROG ,RC osc. tuning values" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " RC_OSC_EN ,RC Osc. enable control" "Disabled,Enabled" line.long 0x04 "LOWPWR_CTRL_CLR,Low Power Control Register" bitfld.long 0x04 17. " MIX_PWRGATE ,Display power gate control" "Not gated,Gated" rbitfld.long 0x04 16. " XTALOSC_PWRUP_STAT ,Status of the 24MHz xtal oscillator" "Not stable,Stable" bitfld.long 0x04 14.--15. " XTALOSC_PWRUP_DELAY ,Specifies delay between 24MHz xtal power up until stable" "0.25ms,0.5ms,1ms,2ms" bitfld.long 0x04 13. " RCOSC_CG_OVERRIDE ,[Debug] Clock gating of certain digital logic clocked by the 24MHz clk" "0,1" newline bitfld.long 0x04 11. " DISPLAY_PWRGATE ,Display logic power gate control" "Not gated,Gated" bitfld.long 0x04 10. " CPU_PWRGATE ,CPU power gate control" "Not gated,Gated" bitfld.long 0x04 9. " L2_PWRGATE ,L2 power gate control" "Not gated,Gated" bitfld.long 0x04 8. " L1_PWRGATE ,L1 power gate control" "Not gated,Gated" newline bitfld.long 0x04 7. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No,Yes" bitfld.long 0x04 6. " LPBG_TEST ,Low power bandgap test bit" "0,1" bitfld.long 0x04 5. " LPBG_SEL ,Bandgap select" "Normal power,Low power" bitfld.long 0x04 4. " OSC_SEL ,Select the source for the 24MHz clock" "XTAL OSC,RC OSC" newline bitfld.long 0x04 1.--3. " RC_OSC_PROG ,RC osc. tuning values" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " RC_OSC_EN ,RC Osc. enable control" "Disabled,Enabled" line.long 0x08 "LOWPWR_CTRL_TGL,Low Power Control Register" bitfld.long 0x08 17. " MIX_PWRGATE ,Display power gate control" "Not gated,Gated" rbitfld.long 0x08 16. " XTALOSC_PWRUP_STAT ,Status of the 24MHz xtal oscillator" "Not stable,Stable" bitfld.long 0x08 14.--15. " XTALOSC_PWRUP_DELAY ,Specifies delay between 24MHz xtal power up until stable" "0.25ms,0.5ms,1ms,2ms" bitfld.long 0x08 13. " RCOSC_CG_OVERRIDE ,[Debug] Clock gating of certain digital logic clocked by the 24MHz clk" "0,1" newline bitfld.long 0x08 11. " DISPLAY_PWRGATE ,Display logic power gate control" "Not gated,Gated" bitfld.long 0x08 10. " CPU_PWRGATE ,CPU power gate control" "Not gated,Gated" bitfld.long 0x08 9. " L2_PWRGATE ,L2 power gate control" "Not gated,Gated" bitfld.long 0x08 8. " L1_PWRGATE ,L1 power gate control" "Not gated,Gated" newline bitfld.long 0x08 7. " REFTOP_IBIAS_OFF ,Low power reftop ibias disable" "No,Yes" bitfld.long 0x08 6. " LPBG_TEST ,Low power bandgap test bit" "0,1" bitfld.long 0x08 5. " LPBG_SEL ,Bandgap select" "Normal power,Low power" bitfld.long 0x08 4. " OSC_SEL ,Select the source for the 24MHz clock" "XTAL OSC,RC OSC" newline bitfld.long 0x08 1.--3. " RC_OSC_PROG ,RC osc. tuning values" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " RC_OSC_EN ,RC Osc. enable control" "Disabled,Enabled" width 0x0B tree.end tree "PWM (Pulse Width Modulation)" tree "PWM 1" base ad:0x02080000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration [rollover/comparison}" "Set/cleared,Cleared/set,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM 2" base ad:0x02084000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration [rollover/comparison}" "Set/cleared,Cleared/set,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM 3" base ad:0x02088000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration [rollover/comparison}" "Set/cleared,Cleared/set,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM 4" base ad:0x0208C000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark" "1 slot,2 slots,3 slots,4 slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration [rollover/comparison}" "Set/cleared,Cleared/set,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Select clock source" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "Not occurred,Occurred" eventfld.long 0x04 5. " CMP ,Compare status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Above mark,Below mark" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree.end tree "PXP (Pixel Pipeline)" base ad:0x020F0000 width 25. group.long 0x00++0x33 line.long 0x00 "CTRL,Control Register 0" bitfld.long 0x00 31. " SFTRST ,Disable clocking with the PXP and hold it in its reset (Lowest power) state" "No,Yes" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Not gated,Gated" bitfld.long 0x00 28. " EN_REPEAT ,Enable the PXP to run continuously" "Disabled,Enabled" newline bitfld.long 0x00 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 25. " ENABLE_LUT ,Enable the LUT engine in the PXP primary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 23. " BLOCK_SIZE ,Select the block size to process" "8x8,16x16" newline bitfld.long 0x00 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP primary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 16. " ENABLE_PS_AS_OUT ,Enable the PS engine and AS engine and OUTBUF in the PXP primary processing flow" "Disabled,Enabled" bitfld.long 0x00 15. " VFLIP1 ,Input buffer flipped vertically" "No,Yes" newline bitfld.long 0x00 14. " HFLIP1 ,Input buffer flipped horizontally" "No,Yes" bitfld.long 0x00 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x00 11. " VFLIP0 ,Output buffer flipped vertically" "No,Yes" newline bitfld.long 0x00 10. " HFLIP0 ,Output buffer flipped horizontally" "No,Yes" bitfld.long 0x00 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x00 5. " HANDSHAKE_ABORT_SKIP ,Skips the asserted abort" "Disabled,Enabled" newline bitfld.long 0x00 4. " ENABLE_LCD0_HANDSHAKE ,Enables handshake with LCD0 controller" "Disabled,Enabled" bitfld.long 0x00 3. " LUT_DMA_IRQ_ENABLE ,LUT DMA interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " IRQ_ENABLE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE ,Enables PXP operation with specified parameters" "Disabled,Enabled" line.long 0x04 "CTRL_SET,Control Register 0" bitfld.long 0x04 31. " SFTRST ,Disable clocking with the PXP and hold it in its reset (Lowest power) state" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" bitfld.long 0x04 28. " EN_REPEAT ,Enable the PXP to run continuously" "No effect,Set" newline bitfld.long 0x04 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 25. " ENABLE_LUT ,Enable the LUT engine in the PXP primary processing flow" "No effect,Set" newline bitfld.long 0x04 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Set" bitfld.long 0x04 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP primary processing flow" "No effect,Set" newline bitfld.long 0x04 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP primary processing flow" "No effect,Set" newline bitfld.long 0x04 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 16. " ENABLE_PS_AS_OUT ,Enable the PS engine and AS engine and OUTBUF in the PXP primary processing flow" "No effect,Set" bitfld.long 0x04 15. " VFLIP1 ,Input buffer flipped vertically" "No effect,Set" newline bitfld.long 0x04 14. " HFLIP1 ,Input buffer flipped horizontally" "No effect,Set" bitfld.long 0x04 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x04 11. " VFLIP0 ,Output buffer flipped vertically" "No effect,Set" newline bitfld.long 0x04 10. " HFLIP0 ,Output buffer flipped horizontally" "No effect,Set" bitfld.long 0x04 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x04 5. " HANDSHAKE_ABORT_SKIP ,Skips the asserted abort" "No effect,Set" newline bitfld.long 0x04 4. " ENABLE_LCD0_HANDSHAKE ,Enables handshake with LCD0 controller" "No effect,Set" bitfld.long 0x04 3. " LUT_DMA_IRQ_ENABLE ,LUT DMA interrupt enable" "No effect,Set" bitfld.long 0x04 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "No effect,Set" newline bitfld.long 0x04 1. " IRQ_ENABLE ,Interrupt enable" "No effect,Set" bitfld.long 0x04 0. " ENABLE ,Enables PXP operation with specified parameters" "No effect,Set" line.long 0x08 "CTRL_CLR,Control Register 0" bitfld.long 0x08 31. " SFTRST ,Disable clocking with the PXP and hold it in its reset (Lowest power) state" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" bitfld.long 0x08 28. " EN_REPEAT ,Enable the PXP to run continuously" "No effect,Clear" newline bitfld.long 0x08 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 25. " ENABLE_LUT ,Enable the LUT engine in the PXP primary processing flow" "No effect,Clear" newline bitfld.long 0x08 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Clear" bitfld.long 0x08 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP primary processing flow" "No effect,Clear" newline bitfld.long 0x08 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP primary processing flow" "No effect,Clear" newline bitfld.long 0x08 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 16. " ENABLE_PS_AS_OUT ,Enable the PS engine and AS engine and OUTBUF in the PXP primary processing flow" "No effect,Clear" bitfld.long 0x08 15. " VFLIP1 ,Input buffer flipped vertically" "No effect,Clear" newline bitfld.long 0x08 14. " HFLIP1 ,Input buffer flipped horizontally" "No effect,Clear" bitfld.long 0x08 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x08 11. " VFLIP0 ,Output buffer flipped vertically" "No effect,Clear" newline bitfld.long 0x08 10. " HFLIP0 ,Output buffer flipped horizontally" "No effect,Clear" bitfld.long 0x08 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x08 5. " HANDSHAKE_ABORT_SKIP ,Skips the asserted abort" "No effect,Clear" newline bitfld.long 0x08 4. " ENABLE_LCD0_HANDSHAKE ,Enables handshake with LCD0 controller" "No effect,Clear" bitfld.long 0x08 3. " LUT_DMA_IRQ_ENABLE ,LUT DMA interrupt enable" "No effect,Clear" bitfld.long 0x08 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "No effect,Clear" newline bitfld.long 0x08 1. " IRQ_ENABLE ,Interrupt enable" "No effect,Clear" bitfld.long 0x08 0. " ENABLE ,Enables PXP operation with specified parameters" "No effect,Clear" line.long 0x0C "CTRL_TOG,Control Register 0" bitfld.long 0x0C 31. " SFTRST ,Disable clocking with the PXP and hold it in its reset (Lowest power) state" "Not toggled,Toggled" bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "Not toggled,Toggled" bitfld.long 0x0C 28. " EN_REPEAT ,Enable the PXP to run continuously" "Not toggled,Toggled" newline bitfld.long 0x0C 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 25. " ENABLE_LUT ,Enable the LUT engine in the PXP primary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 23. " BLOCK_SIZE ,Select the block size to process" "Not toggled,Toggled" bitfld.long 0x0C 21. " ENABLE_ALPHA_B ,Enable the Alpha-B engine in the PXP primary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP primary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 16. " ENABLE_PS_AS_OUT ,Enable the PS engine and AS engine and OUTBUF in the PXP primary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 15. " VFLIP1 ,Input buffer flipped vertically" "Not toggled,Toggled" newline bitfld.long 0x0C 14. " HFLIP1 ,Input buffer flipped horizontally" "Not toggled,Toggled" bitfld.long 0x0C 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x0C 11. " VFLIP0 ,Output buffer flipped vertically" "Not toggled,Toggled" newline bitfld.long 0x0C 10. " HFLIP0 ,Output buffer flipped horizontally" "Not toggled,Toggled" bitfld.long 0x0C 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x0C 5. " HANDSHAKE_ABORT_SKIP ,Skips the asserted abort" "Not toggled,Toggled" newline bitfld.long 0x0C 4. " ENABLE_LCD0_HANDSHAKE ,Enables handshake with LCD0 controller" "Not toggled,Toggled" bitfld.long 0x0C 3. " LUT_DMA_IRQ_ENABLE ,LUT DMA interrupt enable" "Not toggled,Toggled" bitfld.long 0x0C 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "Not toggled,Toggled" newline bitfld.long 0x0C 1. " IRQ_ENABLE ,Interrupt enable" "Not toggled,Toggled" bitfld.long 0x0C 0. " ENABLE ,Enables PXP operation with specified parameters" "Not toggled,Toggled" line.long 0x10 "STAT,Status Register" hexmask.long.byte 0x10 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x10 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" rbitfld.long 0x10 12.--15. " AXI_ERROR_ID_1 ,Indicates the AXI1 ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 10. " AXI_READ_ERROR_1 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No error,Error" bitfld.long 0x10 9. " AXI_WRITE_ERROR_1 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No error,Error" bitfld.long 0x10 8. " LUT_DMA_LOAD_DONE_IRQ ,Indicates that the LUT DMA transfer has completed" "Not completed,Completed" newline rbitfld.long 0x10 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 3. " NEXT_IRQ ,Next command issue" "Not issued,Issued" bitfld.long 0x10 2. " AXI_READ_ERROR_0 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No error,Error" newline bitfld.long 0x10 1. " AXI_WRITE_ERROR_0 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No error,Error" bitfld.long 0x10 0. " IRQ0 ,Indicates current PXP interrupt status" "No interrupt,Interrupt" line.long 0x14 "STAT_SET,Status Register" hexmask.long.byte 0x14 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x14 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" rbitfld.long 0x14 12.--15. " AXI_ERROR_ID_1 ,Indicates the AXI1 ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 10. " AXI_READ_ERROR_1 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No effect,Set" bitfld.long 0x14 9. " AXI_WRITE_ERROR_1 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No effect,Set" bitfld.long 0x14 8. " LUT_DMA_LOAD_DONE_IRQ ,Indicates that the LUT DMA transfer has completed" "No effect,Set" newline rbitfld.long 0x14 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 3. " NEXT_IRQ ,Next command issue" "No effect,Set" bitfld.long 0x14 2. " AXI_READ_ERROR_0 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No effect,Set" newline bitfld.long 0x14 1. " AXI_WRITE_ERROR_0 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No effect,Set" bitfld.long 0x14 0. " IRQ0 ,Indicates current PXP interrupt status" "No effect,Set" line.long 0x18 "STAT_CLR,Status Register" hexmask.long.byte 0x18 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x18 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" rbitfld.long 0x18 12.--15. " AXI_ERROR_ID_1 ,Indicates the AXI1 ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 10. " AXI_READ_ERROR_1 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No effect,Clear" bitfld.long 0x18 9. " AXI_WRITE_ERROR_1 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No effect,Clear" bitfld.long 0x18 8. " LUT_DMA_LOAD_DONE_IRQ ,Indicates that the LUT DMA transfer has completed" "No effect,Clear" newline rbitfld.long 0x18 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 3. " NEXT_IRQ ,Next command issue" "No effect,Clear" bitfld.long 0x18 2. " AXI_READ_ERROR_0 ,Indicates PXP encountered an AXI read error and processing has been terminated" "No effect,Clear" newline bitfld.long 0x18 1. " AXI_WRITE_ERROR_0 ,Indicates PXP encountered an AXI write error and processing has been terminated" "No effect,Clear" bitfld.long 0x18 0. " IRQ0 ,Indicates current PXP interrupt status" "No effect,Clear" line.long 0x1C "STAT_TOG,Status Register" hexmask.long.byte 0x1C 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x1C 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" rbitfld.long 0x1C 12.--15. " AXI_ERROR_ID_1 ,Indicates the AXI1 ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 10. " AXI_READ_ERROR_1 ,Indicates PXP encountered an AXI read error and processing has been terminated" "Not toggled,Toggled" bitfld.long 0x1C 9. " AXI_WRITE_ERROR_1 ,Indicates PXP encountered an AXI write error and processing has been terminated" "Not toggled,Toggled" bitfld.long 0x1C 8. " LUT_DMA_LOAD_DONE_IRQ ,Indicates that the LUT DMA transfer has completed" "Not toggled,Toggled" newline rbitfld.long 0x1C 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 3. " NEXT_IRQ ,Next command issue" "Not toggled,Toggled" bitfld.long 0x1C 2. " AXI_READ_ERROR_0 ,Indicates PXP encountered an AXI read error and processing has been terminated" "Not toggled,Toggled" newline bitfld.long 0x1C 1. " AXI_WRITE_ERROR_0 ,Indicates PXP encountered an AXI write error and processing has been terminated" "Not toggled,Toggled" bitfld.long 0x1C 0. " IRQ0 ,Indicates current PXP interrupt status" "Not toggled,Toggled" line.long 0x20 "OUT_CTRL,Output Buffer Control Register" hexmask.long.byte 0x20 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x20 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "Computed,Overwrited" newline bitfld.long 0x20 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" bitfld.long 0x20 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x24 "OUT_CTRL_SET,Output Buffer Control Set Register" hexmask.long.byte 0x24 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x24 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "No effect,Set" newline bitfld.long 0x24 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" bitfld.long 0x24 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x28 "OUT_CTRL_CLR,Output Buffer Control Clear Register" hexmask.long.byte 0x28 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x28 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "No effect,Clear" newline bitfld.long 0x28 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" bitfld.long 0x28 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x2C "OUT_CTRL_TOG,Output Buffer Control Toggle Register" hexmask.long.byte 0x2C 24.--31. 1. " ALPHA ,Alpha component" bitfld.long 0x2C 23. " ALPHA_OUT ,Overwritten alpha component in output buffer" "Not toggled,Toggled" newline bitfld.long 0x2C 8.--9. " INTERLACED_OUT ,Methods of write output data" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED" bitfld.long 0x2C 0.--4. " FORMAT ,Output framebuffer format" "ARGB8888,,,,RGB888,RGB888P,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,?..." line.long 0x30 "OUT_BUF,Output Frame Buffer Pointer" group.long 0x40++0x03 line.long 0x00 "OUT_BUF2,Output Frame Buffer Pointer 2" group.long 0x50++0x03 line.long 0x00 "OUT_PITCH,Output Buffer Pitch" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Number of bytes in memory between two vertically adjacent pixels" group.long 0x60++0x03 line.long 0x00 "OUT_LRC,Output Surface Lower Right Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Number of horizontal PIXELS in the output surface (Non-rotated)" hexmask.long.word 0x00 0.--13. 1. " Y ,Number of vertical PIXELS in the output surface (Non-rotated)" group.long 0x70++0x03 line.long 0x00 "OUT_PS_ULC,Processed Surface Upper Left Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Upper left X-coordinate (In pixels) of PS in the output buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Upper left Y-coordinate (In pixels) of PS in the output buffer" group.long 0x80++0x03 line.long 0x00 "OUT_PS_LRC,Processed Surface Lower Right Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Lower right X-coordinate (In pixels) of PS in the output frame buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Lower right Y-coordinate (In pixels) of PS in the output frame buffer" group.long 0x90++0x03 line.long 0x00 "OUT_AS_ULC,Alpha Surface Upper Left Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Upper left X-coordinate (In pixels) of AS in the output frame buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Upper left Y-coordinate (In pixels) of AS in the output frame buffer" group.long 0xA0++0x03 line.long 0x00 "OUT_AS_LRC,Alpha Surface Lower Right Coordinate" hexmask.long.word 0x00 16.--29. 1. " X ,Lower right X-coordinate (In pixels) of AS in the output frame buffer" hexmask.long.word 0x00 0.--13. 1. " Y ,Lower right Y-coordinate (In pixels) of AS in the output frame buffer" group.long 0xB0++0x13 line.long 0x00 "PS_CTRL,Processed Surface (Ps) Control Register" bitfld.long 0x00 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x00 8.--9. " DECY ,Vertical pre decimation filter control" "Disabled,By 2,By 4,By 8" newline bitfld.long 0x00 6. " WB_SWAP ,Swap bytes in words" "Not swapped,Swapped" bitfld.long 0x00 0.--5. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420,?..." line.long 0x04 "PS_CTRL_SET,Processed Surface (Ps) Control Set Register" bitfld.long 0x04 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x04 8.--9. " DECY ,Vertical pre decimation filter control" "Disabled,By 2,By 4,By 8" newline bitfld.long 0x04 6. " WB_SWAP ,Swap bytes in words" "Not swapped,Swapped" bitfld.long 0x04 0.--5. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420,?..." line.long 0x08 "PS_CTRL_CLR,Processed Surface (Ps) Control Clear Register" bitfld.long 0x08 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x08 8.--9. " DECY ,Vertical pre decimation filter control" "Disabled,By 2,By 4,By 8" newline bitfld.long 0x08 6. " WB_SWAP ,Swap bytes in words" "Not swapped,Swapped" bitfld.long 0x08 0.--5. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420,?..." line.long 0x0C "PS_CTRL_TOG,Processed Surface (Ps) Control Toggle Register" bitfld.long 0x0C 10.--11. " DECX ,Horizontal pre decimation filter control" "Disabled,By 2,By 4,By 8" bitfld.long 0x0C 8.--9. " DECY ,Vertical pre decimation filter control" "Disabled,By 2,By 4,By 8" newline bitfld.long 0x0C 6. " WB_SWAP ,Swap bytes in words" "Not swapped,Swapped" bitfld.long 0x0C 0.--5. " FORMAT ,PS buffer format" ",,,,RGB888,,,,,,,,RGB555,RGB444,RGB565,,YUV1P444,,UYVY1P422,VYUY1P422,Y8,Y4,,,YUV2P422,YUV2P420,YVU2P422,YVU2P420,,,YUV422,YUV420,?..." line.long 0x10 "PS_BUF,PS Input Buffer Address" group.long 0xD0++0x03 line.long 0x00 "PS_UBUF,PS U/cb Or 2 Plane UV Input Buffer Address" group.long 0xE0++0x03 line.long 0x00 "PS_VBUF,PS V/cr Input Buffer Address" group.long 0xF0++0x03 line.long 0x00 "PS_PITCH,Processed Surface Pitch" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Number of bytes in memory between two vertically adjacent pixels" group.long 0x100++0x03 line.long 0x00 "PS_BACKGROUND_0,PS Background Color" hexmask.long.tbyte 0x00 0.--23. 1. " COLOR ,Background color (In 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC" group.long 0x110++0x03 line.long 0x00 "PS_SCALE,PS Scale Factor Register" hexmask.long.word 0x00 16.--30. 1. " YSCALE ,Two bit integer and 12 bit fractional representation of the Y scaling factor for the PS source buffer" hexmask.long.word 0x00 0.--14. 1. " XSCALE ,Two bit integer and 12 bit fractional representation of the X scaling factor for the PS source buffer" group.long 0x120++0x03 line.long 0x00 "PS_OFFSET,PS Scale Offset Register" hexmask.long.word 0x00 16.--27. 1. " YOFFSET ,12 bit fractional representation of the Y scaling offset" hexmask.long.word 0x00 0.--11. 1. " XOFFSET ,12 bit fractional representation of the X scaling offset" group.long 0x130++0x03 line.long 0x00 "PS_CLRKEYLOW_0,PS Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of color key applied to PS buffer" group.long 0x140++0x03 line.long 0x00 "PS_CLRKEYHIGH_0,PS Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of color key applied to PS buffer" group.long 0x150++0x03 line.long 0x00 "AS_CTRL,Alpha Surface Control" bitfld.long 0x00 21. " ALPHA1_INVERT ,Invert the alpha value and apply (1- alpha) for image composition" "Not inverted,Inverted" bitfld.long 0x00 20. " ALPHA0_INVERT ,Invert the alpha value and apply (1- alpha) for image composition" "Not inverted,Inverted" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform" "AS AND PS,nAS AND PS,AS AND nPS,AS OR PS,nAS OR PS,AS OR nPS,nAS,nPS,AS NAND PS,AS NOR PS,AS XOR PS,AS XNOR PS,?..." newline hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" newline bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for AS" "ARGB8888,RGBA8888,,,RGB888,,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled" bitfld.long 0x00 1.--2. " ALPHA_CTRL ,Methods of construction of alpha value" "Embedded,Override,Multiply,Rops" group.long 0x160++0x03 line.long 0x00 "AS_BUF,Alpha Surface Buffer Pointer" group.long 0x170++0x03 line.long 0x00 "AS_PITCH,Alpha Surface Pitch" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Number of bytes in memory between two vertically adjacent pixels" group.long 0x180++0x03 line.long 0x00 "AS_CLRKEYLOW_0,Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x190++0x03 line.long 0x00 "AS_CLRKEYHIGH_0,Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x1A0++0x03 line.long 0x00 "CSC1_COEF0,Color Space Conversion Coefficient Register 0" bitfld.long 0x00 31. " YCBCR_MODE ,Conversion data type" "YUV to RGB,Ycbcr to RGB" bitfld.long 0x00 30. " BYPASS ,Bypass the CSC unit in the scaling engine" "Not bypassed,Bypassed" newline hexmask.long.word 0x00 18.--28. 1. " C0 ,Two's compliment Y multiplier coefficient" hexmask.long.word 0x00 9.--17. 1. " UV_OFFSET ,Two's compliment phase offset implicit for cbcr data" newline hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two's compliment amplitude offset implicit in the Y data" group.long 0x1B0++0x03 line.long 0x00 "CSC1_COEF1,Color Space Conversion Coefficient Register 1" hexmask.long.word 0x00 16.--26. 1. " C1 ,Two's compliment red v/cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C4 ,Two's compliment blue u/cb multiplier coefficient" group.long 0x1C0++0x03 line.long 0x00 "CSC1_COEF2,Color Space Conversion Coefficient Register 2" hexmask.long.word 0x00 16.--26. 1. " C2 ,Two's complement green v/cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C3 ,Two's complement green u/cb multiplier coefficient" group.long 0x1D0++0x03 line.long 0x00 "CSC2_CTRL,Color Space Conversion Control Register" bitfld.long 0x00 1.--2. " CSC_MODE ,Methods of CSC unit operates on pixels when the CSC is not bypassed (Converted from)" "YUV to RGB,Ycbcr to RGB,RGB to YUV,RGB to ycbcr" bitfld.long 0x00 0. " BYPASS ,Bypass CSC2 unit" "Not bypassed,Bypassed" group.long 0x1E0++0x03 line.long 0x00 "CSC2_COEF0,Color Space Conversion Coefficient Register 0" hexmask.long.word 0x00 16.--26. 1. " A2 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " A1 ,Two's complement coefficient offset" group.long 0x1F0++0x03 line.long 0x00 "CSC2_COEF1,Color Space Conversion Coefficient Register 1" hexmask.long.word 0x00 16.--26. 1. " B1 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " A3 ,Two's complement coefficient offset" group.long 0x200++0x03 line.long 0x00 "CSC2_COEF2,Color Space Conversion Coefficient Register 2" hexmask.long.word 0x00 16.--26. 1. " B3 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " B2 ,Two's complement coefficient offset" group.long 0x210++0x03 line.long 0x00 "CSC2_COEF3,Color Space Conversion Coefficient Register 3" hexmask.long.word 0x00 16.--26. 1. " C2 ,Two's complement coefficient offset" hexmask.long.word 0x00 0.--10. 1. " C1 ,Two's complement coefficient offset" group.long 0x220++0x03 line.long 0x00 "CSC2_COEF4,Color Space Conversion Coefficient Register 4" hexmask.long.word 0x00 16.--26. 1. " D1 ,Two's complement coefficient integer offset to be added" hexmask.long.word 0x00 0.--10. 1. " C3 ,Two's complement coefficient offset" group.long 0x230++0x03 line.long 0x00 "CSC2_COEF5,Color Space Conversion Coefficient Register 5" hexmask.long.word 0x00 16.--24. 1. " D3 ,Two's complement coefficient integer offset to be added" hexmask.long.word 0x00 0.--8. 1. " D2 ,Two's complement D1 coefficient integer offset to be added" group.long 0x240++0x03 line.long 0x00 "LUT_CTRL,Lookup Table Control Register" bitfld.long 0x00 31. " BYPASS ,Bypass the LUT memory resource completely" "Not bypassed,Bypassed" bitfld.long 0x00 24.--25. " LOOKUP_MODE ,Configure the input address for the 16KB" "CACHE_RGB565,DIRECT_Y8,DIRECT_RGB444,DIRECT_RGB454" newline bitfld.long 0x00 16.--17. " OUT_MODE ,Select the output mode of operation for the LUT resource" ",Y8,RGBW4444CFA,RGB888" bitfld.long 0x00 10. " SEL_8KB ,Selects which 8KB bank of memory to use for direct 12bpp lookup modes" "First,Second" newline bitfld.long 0x00 9. " LRU_UPD ,Least recently used policy update control" "All hits,Hit after miss" bitfld.long 0x00 8. " INVALID ,Invalidate the cache LRU and valid bits" "Invalid,Valid" newline bitfld.long 0x00 0. " DMA_START ,Load the PXP LUT memory based on PXP_LUT_ADDR_NUM_BYTES, PXP_LUT_ADDR_ADDR, and PXP_LUT_MEM_ADDR" "Not loaded,Loaded" group.long 0x250++0x03 line.long 0x00 "LUT_ADDR,Lookup Table Control Register" hexmask.long.word 0x00 16.--30. 1. " NUM_BYTES ,Number of bytes to load via a DMA operation" hexmask.long.word 0x00 0.--13. 1. " ADDR ,LUT indexed address pointer" group.long 0x260++0x03 line.long 0x00 "LUT_DATA,Lookup Table Data Register" group.long 0x270++0x03 line.long 0x00 "LUT_EXTMEM,Lookup Table External Memory Address Register" group.long 0x280++0x03 line.long 0x00 "CFA,Color Filter Array Register" group.long 0x290++0x03 line.long 0x00 "ALPHA_A_CTRL,PXP Alpha Engine A Control Register" hexmask.long.byte 0x00 24.--31. 1. " S1_GLOBAL_ALPHA ,S1 global alpha" hexmask.long.byte 0x00 16.--23. 1. " S0_GLOBAL_ALPHA ,S0 global alpha" newline bitfld.long 0x00 13. " S1_COLOR_MODE ,S1 color mode" "Straight mode,Multiply mode" bitfld.long 0x00 12. " S1_ALPHA_MODE ,S1 alpha mode" "Straight mode,Inversed mode" newline bitfld.long 0x00 10.--11. " S1_GLOBAL_ALPHA_MODE ,S1 global alpha mode" "Global alpha,Local alpha,Scaled alpha,Scaled alpha" bitfld.long 0x00 8.--9. " S1_S0_FACTOR_MODE ,S1 to s0 factor mode" "1,0,Straight,Inversed" newline bitfld.long 0x00 6. " S0_COLOR_MODE ,S0 color mode" "Straight mode,Multiply mode" bitfld.long 0x00 5. " S0_ALPHA_MODE ,S0 alpha mode" "Straight mode,Inversed mode" newline bitfld.long 0x00 3.--4. " S0_GLOBAL_ALPHA_MODE ,S0 global alpha mode" "Global alpha,Local alpha,Scaled alpha,Scaled alpha" bitfld.long 0x00 1.--2. " S0_S1_FACTOR_MODE ,S0 to s1 factor mode" "1,0,Straight,Inversed" bitfld.long 0x00 0. " POTER_DUFF_ENABLE ,Porter duff enable" "Disabled,Enabled" group.long 0x2C0++0x03 line.long 0x00 "PS_BACKGROUND_1,PS Background Color 1" hexmask.long.tbyte 0x00 0.--23. 1. " COLOR ,Background color (In 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC" group.long 0x2D0++0x03 line.long 0x00 "PS_CLRKEYLOW_1,PS Color Key Low 1" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of color key applied to PS buffer" group.long 0x2E0++0x03 line.long 0x00 "PS_CLRKEYHIGH_1,PS Color Key High 1" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of color key applied to PS buffer" group.long 0x2F0++0x03 line.long 0x00 "AS_CLRKEYLOW_1,Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x300++0x03 line.long 0x00 "AS_CLRKEYHIGH_1,Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x310++0x13 line.long 0x00 "CTRL2,Control Register 2" bitfld.long 0x00 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 25. " ENABLE_LUT ,Enable the LUT engine in the PXP secondary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 23. " BLOCK_SIZE ,Select the block size to process through the rotate block" "8x8,16x16" bitfld.long 0x00 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP secondary processing flow" "Disabled,Enabled" newline bitfld.long 0x00 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP secondary processing flow" "Disabled,Enabled" bitfld.long 0x00 15. " VFLIP1 ,Input buffer flipped vertically" "No,Yes" bitfld.long 0x00 14. " HFLIP1 ,Input buffer flipped horizontally" "No,Yes" newline bitfld.long 0x00 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x00 11. " VFLIP0 ,Output buffer flipped vertically" "No,Yes" bitfld.long 0x00 10. " HFLIP0 ,Output buffer flipped horizontally" "No,Yes" newline bitfld.long 0x00 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x00 0. " ENABLE ,Enables PXP secondary data processing flow with specified parameters" "Disabled,Enabled" line.long 0x04 "CTRL2_SET,Control Register 2" bitfld.long 0x04 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 25. " ENABLE_LUT ,Enable the LUT engine in the PXP secondary processing flow" "No effect,Set" newline bitfld.long 0x04 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 23. " BLOCK_SIZE ,Select the block size to process through the rotate block" "No effect,Set" bitfld.long 0x04 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP secondary processing flow" "No effect,Set" newline bitfld.long 0x04 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP secondary processing flow" "No effect,Set" newline bitfld.long 0x04 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP secondary processing flow" "No effect,Set" bitfld.long 0x04 15. " VFLIP1 ,Input buffer flipped vertically" "No effect,Set" bitfld.long 0x04 14. " HFLIP1 ,Input buffer flipped horizontally" "No effect,Set" newline bitfld.long 0x04 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x04 11. " VFLIP0 ,Output buffer flipped vertically" "No effect,Set" bitfld.long 0x04 10. " HFLIP0 ,Output buffer flipped horizontally" "No effect,Set" newline bitfld.long 0x04 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x04 0. " ENABLE ,Enables PXP secondary data processing flow with specified parameters" "No effect,Set" line.long 0x08 "CTRL2_CLR,Control Register 2" bitfld.long 0x08 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 25. " ENABLE_LUT ,Enable the LUT engine in the PXP secondary processing flow" "No effect,Clear" newline bitfld.long 0x08 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 23. " BLOCK_SIZE ,Select the block size to process through the rotate block" "No effect,Clear" bitfld.long 0x08 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP secondary processing flow" "No effect,Clear" newline bitfld.long 0x08 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP secondary processing flow" "No effect,Clear" newline bitfld.long 0x08 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP secondary processing flow" "No effect,Clear" bitfld.long 0x08 15. " VFLIP1 ,Input buffer flipped vertically" "No effect,Clear" bitfld.long 0x08 14. " HFLIP1 ,Input buffer flipped horizontally" "No effect,Clear" newline bitfld.long 0x08 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x08 11. " VFLIP0 ,Output buffer flipped vertically" "No effect,Clear" bitfld.long 0x08 10. " HFLIP0 ,Output buffer flipped horizontally" "No effect,Clear" newline bitfld.long 0x08 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x08 0. " ENABLE ,Enables PXP secondary data processing flow with specified parameters" "No effect,Clear" line.long 0x0C "CTRL2_TOG,Control Register 2" bitfld.long 0x0C 27. " ENABLE_ROTATE1 ,Enable the ROTATE1 engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 26. " ENABLE_ROTATE0 ,Enable the ROTATE0 engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 25. " ENABLE_LUT ,Enable the LUT engine in the PXP secondary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 24. " ENABLE_CSC2 ,Enable the CSC2 engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 23. " BLOCK_SIZE ,Select the block size to process through the rotate block" "Not toggled,Toggled" bitfld.long 0x0C 19. " ENABLE_WFE_B ,Enable the WFE-B engine in the PXP secondary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 18. " ENABLE_WFE_A ,Enable the WFE-A engine in the PXP secondary processing flow" "Not toggled,Toggled" newline bitfld.long 0x0C 17. " ENABLE_DITHER ,Enable the dithering engine in the PXP secondary processing flow" "Not toggled,Toggled" bitfld.long 0x0C 15. " VFLIP1 ,Input buffer flipped vertically" "Not toggled,Toggled" bitfld.long 0x0C 14. " HFLIP1 ,Input buffer flipped horizontally" "Not toggled,Toggled" newline bitfld.long 0x0C 12.--13. " ROTATE1 ,Clockwise rotation at the input buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x0C 11. " VFLIP0 ,Output buffer flipped vertically" "Not toggled,Toggled" bitfld.long 0x0C 10. " HFLIP0 ,Output buffer flipped horizontally" "Not toggled,Toggled" newline bitfld.long 0x0C 8.--9. " ROTATE0 ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270" bitfld.long 0x0C 0. " ENABLE ,Enables PXP secondary data processing flow with specified parameters" "Not toggled,Toggled" line.long 0x10 "POWER_REG0,PXP Power Control Register" hexmask.long.tbyte 0x10 12.--31. 1. " CTRL ,This register contains power control for the PXP" bitfld.long 0x10 9.--11. " ROT0_MEM_LP_STATE ,Selects the low power state of the ROT 0 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x10 6.--8. " LUT_LP_STATE_WAY1_BANKN ,Selects the low power state of the lut's WAY1-BANK0,1,2,3 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." newline bitfld.long 0x10 3.--5. " LUT_LP_STATE_WAY0_BANKN ,Selects the low power state of the lut's WAY0-BANK1,2,3 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x10 0.--2. " LUT_LP_STATE_WAY0_BANK0 ,Selects the low power state of the lut's WAY0-BANK0 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." group.long 0x330++0x03 line.long 0x00 "POWER_REG1,PXP Power Control Register 1" bitfld.long 0x00 21.--23. " ALU_B_MEM_LP_STATE ,Selects the low power state of the ALU B memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 18.--20. " ALU_A_MEM_LP_STATE ,Selects the low power state of the ALU A memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 15.--17. " DITH2_LUT_MEM_LP_STATE ,Selects the low power state of the dither2 LUT memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." newline bitfld.long 0x00 12.--14. " DITH1_LUT_MEM_LP_STATE ,Selects the low power state of the dither1 LUT memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 9.--11. " DITH0_ERR1_MEM_LP_STATE ,Selects the low power state of the dither0 ERR1 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 6.--8. " DITH0_ERR0_MEM_LP_STATE ,Selects the low power state of the dither0 ERR0 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." newline bitfld.long 0x00 3.--5. " DITH0_LUT_MEM_LP_STATE ,Selects the low power state of the dither0 LUT memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." bitfld.long 0x00 0.--2. " ROT1_MEM_LP_STATE ,Selects the low power state of the ROT 1 memory" "None,Light sleep mode,Deep sleep mode,,Shut down mode,?..." group.long 0x340++0x0F line.long 0x00 "DATA_PATH_CTRL0,DATA_PATH_CTRL0" bitfld.long 0x00 28.--29. " MUX14_SEL ,Chooses the data path through MUX 14" "ALU A,ALU B,No output,No output" bitfld.long 0x00 24.--25. " MUX12_SEL ,Chooses the data path through MUX 12" "ALU A,ALU B,No output,No output" bitfld.long 0x00 22.--23. " MUX11_SEL ,Chooses the data path through MUX 11" "ALU A,ALU B,No output,No output" newline bitfld.long 0x00 18.--19. " MUX9_SEL ,Chooses the data path through MUX 9" "ALU A,ALU B,No output,No output" bitfld.long 0x00 16.--17. " MUX8_SEL ,Chooses the data path through MUX 8" "ALU A,ALU B,No output,No output" bitfld.long 0x00 6.--7. " MUX3_SEL ,Chooses the data path through MUX 3" "ALU A,ALU B,No output,No output" newline bitfld.long 0x00 2.--3. " MUX1_SEL ,Chooses the data path through MUX 1" "ALU A,ALU B,No output,No output" bitfld.long 0x00 0.--1. " MUX0_SEL ,Chooses the data path through MUX 0" "ALU A,ALU B,No output,No output" line.long 0x04 "DATA_PATH_CTRL0_SET,DATA_PATH_CTRL0_SET" bitfld.long 0x04 28.--29. " MUX14_SEL ,Chooses the data path through MUX 14" "ALU A,ALU B,No output,No output" bitfld.long 0x04 24.--25. " MUX12_SEL ,Chooses the data path through MUX 12" "ALU A,ALU B,No output,No output" bitfld.long 0x04 22.--23. " MUX11_SEL ,Chooses the data path through MUX 11" "ALU A,ALU B,No output,No output" newline bitfld.long 0x04 18.--19. " MUX9_SEL ,Chooses the data path through MUX 9" "ALU A,ALU B,No output,No output" bitfld.long 0x04 16.--17. " MUX8_SEL ,Chooses the data path through MUX 8" "ALU A,ALU B,No output,No output" bitfld.long 0x04 6.--7. " MUX3_SEL ,Chooses the data path through MUX 3" "ALU A,ALU B,No output,No output" newline bitfld.long 0x04 2.--3. " MUX1_SEL ,Chooses the data path through MUX 1" "ALU A,ALU B,No output,No output" bitfld.long 0x04 0.--1. " MUX0_SEL ,Chooses the data path through MUX 0" "ALU A,ALU B,No output,No output" line.long 0x08 "DATA_PATH_CTRL0_CLR,DATA_PATH_CTRL0_CLR" bitfld.long 0x08 28.--29. " MUX14_SEL ,Chooses the data path through MUX 14" "ALU A,ALU B,No output,No output" bitfld.long 0x08 24.--25. " MUX12_SEL ,Chooses the data path through MUX 12" "ALU A,ALU B,No output,No output" bitfld.long 0x08 22.--23. " MUX11_SEL ,Chooses the data path through MUX 11" "ALU A,ALU B,No output,No output" newline bitfld.long 0x08 18.--19. " MUX9_SEL ,Chooses the data path through MUX 9" "ALU A,ALU B,No output,No output" bitfld.long 0x08 16.--17. " MUX8_SEL ,Chooses the data path through MUX 8" "ALU A,ALU B,No output,No output" bitfld.long 0x08 6.--7. " MUX3_SEL ,Chooses the data path through MUX 3" "ALU A,ALU B,No output,No output" newline bitfld.long 0x08 2.--3. " MUX1_SEL ,Chooses the data path through MUX 1" "ALU A,ALU B,No output,No output" bitfld.long 0x08 0.--1. " MUX0_SEL ,Chooses the data path through MUX 0" "ALU A,ALU B,No output,No output" line.long 0x0C "DATA_PATH_CTRL0_TOG,DATA_PATH_CTRL0_TOG" bitfld.long 0x0C 28.--29. " MUX14_SEL ,Chooses the data path through MUX 14" "ALU A,ALU B,No output,No output" bitfld.long 0x0C 24.--25. " MUX12_SEL ,Chooses the data path through MUX 12" "ALU A,ALU B,No output,No output" bitfld.long 0x0C 22.--23. " MUX11_SEL ,Chooses the data path through MUX 11" "ALU A,ALU B,No output,No output" newline bitfld.long 0x0C 18.--19. " MUX9_SEL ,Chooses the data path through MUX 9" "ALU A,ALU B,No output,No output" bitfld.long 0x0C 16.--17. " MUX8_SEL ,Chooses the data path through MUX 8" "ALU A,ALU B,No output,No output" bitfld.long 0x0C 6.--7. " MUX3_SEL ,Chooses the data path through MUX 3" "ALU A,ALU B,No output,No output" newline bitfld.long 0x0C 2.--3. " MUX1_SEL ,Chooses the data path through MUX 1" "ALU A,ALU B,No output,No output" bitfld.long 0x0C 0.--1. " MUX0_SEL ,Chooses the data path through MUX 0" "ALU A,ALU B,No output,No output" group.long 0x350++0x23 line.long 0x00 "DATA_PATH_CTRL1,DATA_PATH_CTRL1" bitfld.long 0x00 2.--3. " MUX17_SEL ,Chooses the data path through MUX 17" "ALU A,ALU B,No output,No output" bitfld.long 0x00 0.--1. " MUX16_SEL ,Chooses the data path through MUX 16" "ALU A engine,HISTOGRAM_PIXEL,ALU B engine,No output" line.long 0x04 "DATA_PATH_CTRL1_SET,DATA_PATH_CTRL1_SET" bitfld.long 0x04 2.--3. " MUX17_SEL ,Chooses the data path through MUX 17" "ALU A,ALU B,No output,No output" bitfld.long 0x04 0.--1. " MUX16_SEL ,Chooses the data path through MUX 16" "ALU A engine,HISTOGRAM_PIXEL,ALU B engine,No output" line.long 0x08 "DATA_PATH_CTRL1_CLR,DATA_PATH_CTRL1_CLR" bitfld.long 0x08 2.--3. " MUX17_SEL ,Chooses the data path through MUX 17" "ALU A,ALU B,No output,No output" bitfld.long 0x08 0.--1. " MUX16_SEL ,Chooses the data path through MUX 16" "ALU A engine,HISTOGRAM_PIXEL,ALU B engine,No output" line.long 0x0C "DATA_PATH_CTRL1_TOG,DATA_PATH_CTRL1_TOG" bitfld.long 0x0C 2.--3. " MUX17_SEL ,Chooses the data path through MUX 17" "ALU A,ALU B,No output,No output" bitfld.long 0x0C 0.--1. " MUX16_SEL ,Chooses the data path through MUX 16" "ALU A engine,HISTOGRAM_PIXEL,ALU B engine,No output" line.long 0x10 "INIT_MEM_CTRL,Initialize Memory Buffer Control Register" bitfld.long 0x10 31. " START ,Enables writing to the memory" "Disabled,Enabled" bitfld.long 0x10 27.--30. " SELECT ,Selects which memory to write" "DITHER0_LUT,DITHER0_ERR0,DITHER0_ERR1,DITHER1_LUT,DITHER2_LUT,ALU_A,ALU_B,WFE_A_FETCH,WFE_B_FETCH,?..." hexmask.long.word 0x10 0.--15. 0x01 " ADDR ,Base address to start writing" line.long 0x14 "INIT_MEM_CTRL_SET,Initialize Memory Buffer Control Register" bitfld.long 0x14 31. " START ,Enables writing to the memory" "No effect,Set" bitfld.long 0x14 27.--30. " SELECT ,Selects which memory to write" "DITHER0_LUT,DITHER0_ERR0,DITHER0_ERR1,DITHER1_LUT,DITHER2_LUT,ALU_A,ALU_B,WFE_A_FETCH,WFE_B_FETCH,?..." hexmask.long.word 0x14 0.--15. 0x01 " ADDR ,Base address to start writing" line.long 0x18 "INIT_MEM_CTRL_CLR,Initialize Memory Buffer Control Register" bitfld.long 0x18 31. " START ,Enables writing to the memory" "No effect,Clear" bitfld.long 0x18 27.--30. " SELECT ,Selects which memory to write" "DITHER0_LUT,DITHER0_ERR0,DITHER0_ERR1,DITHER1_LUT,DITHER2_LUT,ALU_A,ALU_B,WFE_A_FETCH,WFE_B_FETCH,?..." hexmask.long.word 0x18 0.--15. 0x01 " ADDR ,Base address to start writing" line.long 0x1C "INIT_MEM_CTRL_TOG,Initialize Memory Buffer Control Register" bitfld.long 0x1C 31. " START ,Enables writing to the memory" "Not toggled,Toggled" bitfld.long 0x1C 27.--30. " SELECT ,Selects which memory to write" "DITHER0_LUT,DITHER0_ERR0,DITHER0_ERR1,DITHER1_LUT,DITHER2_LUT,ALU_A,ALU_B,WFE_A_FETCH,WFE_B_FETCH,?..." hexmask.long.word 0x1C 0.--15. 0x01 " ADDR ,Base address to start writing" line.long 0x20 "INIT_MEM_DATA,Write Data Register" group.long 0x380++0x03 line.long 0x00 "INIT_MEM_DATA_HIGH,Write Data Register" group.long 0x390++0x1F line.long 0x00 "PXP_IRQ_MAS,PXP IRQ Mask Register" bitfld.long 0x00 15. " WFE_B_STORE_IRQ_EN ,Enables WFE B store engine interrupt detection" "Disabled,Enabled" bitfld.long 0x00 11. " WFE_B_CH1_STORE_IRQ_EN ,Enables WFE B ch1 store engine interrupt detection" "Disabled,Enabled" newline bitfld.long 0x00 10. " WFE_B_CH0_STORE_IRQ_EN ,Enables WFE B ch0 store engine interrupt detection" "Disabled,Enabled" line.long 0x04 "PXP_IRQ_MAS_SET,PXP IRQ Mask Register" bitfld.long 0x04 15. " WFE_B_STORE_IRQ_EN ,Enables WFE B store engine interrupt detection" "No effect,Set" bitfld.long 0x04 11. " WFE_B_CH1_STORE_IRQ_EN ,Enables WFE B ch1 store engine interrupt detection" "No effect,Set" newline bitfld.long 0x04 10. " WFE_B_CH0_STORE_IRQ_EN ,Enables WFE B ch0 store engine interrupt detection" "No effect,Set" line.long 0x08 "PXP_IRQ_MAS_CLR,PXP IRQ Mask Register" bitfld.long 0x08 15. " WFE_B_STORE_IRQ_EN ,Enables WFE B store engine interrupt detection" "No effect,Clear" bitfld.long 0x08 11. " WFE_B_CH1_STORE_IRQ_EN ,Enables WFE B ch1 store engine interrupt detection" "No effect,Clear" newline bitfld.long 0x08 10. " WFE_B_CH0_STORE_IRQ_EN ,Enables WFE B ch0 store engine interrupt detection" "No effect,Clear" line.long 0x0C "PXP_IRQ_MAS_TOG,PXP IRQ Mask Register" bitfld.long 0x0C 15. " WFE_B_STORE_IRQ_EN ,Enables WFE B store engine interrupt detection" "Not toggled,Toggled" bitfld.long 0x0C 11. " WFE_B_CH1_STORE_IRQ_EN ,Enables WFE B ch1 store engine interrupt detection" "Not toggled,Toggled" newline bitfld.long 0x0C 10. " WFE_B_CH0_STORE_IRQ_EN ,Enables WFE B ch0 store engine interrupt detection" "Not toggled,Toggled" line.long 0x10 "HW_PXP_IRQ,HW_PXP_IRQ" bitfld.long 0x10 15. " WFE_B_STORE_IRQ ,WFE B store engine interrupt" "No interrupt,Interrupt" bitfld.long 0x10 11. " WFE_B_CH1_STORE_IRQ ,WFE B ch1 store engine interrupt" "No interrupt,Interrupt" newline bitfld.long 0x10 10. " WFE_B_CH0_STORE_IRQ ,WFE B ch0 store engine interrupt" "No interrupt,Interrupt" line.long 0x14 "HW_PXP_IRQ_SET,HW_PXP_IRQ_SET" bitfld.long 0x14 15. " WFE_B_STORE_IRQ ,WFE B store engine interrupt" "No effect,Set" bitfld.long 0x14 11. " WFE_B_CH1_STORE_IRQ ,WFE B ch1 store engine interrupt" "No effect,Set" newline bitfld.long 0x14 10. " WFE_B_CH0_STORE_IRQ ,WFE B ch0 store engine interrupt" "No effect,Set" line.long 0x18 "HW_PXP_IRQ_CLR,HW_PXP_IRQ_CLR" bitfld.long 0x18 15. " WFE_B_STORE_IRQ ,WFE B store engine interrupt" "No effect,Clear" bitfld.long 0x18 11. " WFE_B_CH1_STORE_IRQ ,WFE B ch1 store engine interrupt" "No effect,Clear" newline bitfld.long 0x18 10. " WFE_B_CH0_STORE_IRQ ,WFE B ch0 store engine interrupt" "No effect,Clear" line.long 0x1C "HW_PXP_IRQ_TOG,HW_PXP_IRQ_TOG" bitfld.long 0x1C 15. " WFE_B_STORE_IRQ ,WFE B store engine interrupt" "Not toggled,Toggled" bitfld.long 0x1C 11. " WFE_B_CH1_STORE_IRQ ,WFE B ch1 store engine interrupt" "Not toggled,Toggled" newline bitfld.long 0x1C 10. " WFE_B_CH0_STORE_IRQ ,WFE B ch0 store engine interrupt" "Not toggled,Toggled" group.long 0x3B0++0x0F line.long 0x00 "NEXT_EN,Next Buffer Enable Select Register" bitfld.long 0x00 1. " WFEB ,WFE B Next Buffer function enable" "Disabled,Enabled" bitfld.long 0x00 0. " LEGACY ,Legacy Next Buffer function enable" "Disabled,Enabled" line.long 0x04 "NEXT_EN_SET,Next Buffer Enable Select Register" bitfld.long 0x04 1. " WFEB ,WFE B Next Buffer function enable" "Disabled,Enabled" bitfld.long 0x04 0. " LEGACY ,Legacy Next Buffer function enable" "Disabled,Enabled" line.long 0x08 "NEXT_EN_CLR,Next Buffer Enable Select Register" bitfld.long 0x08 1. " WFEB ,WFE B Next Buffer function enable" "Disabled,Enabled" bitfld.long 0x08 0. " LEGACY ,Legacy Next Buffer function enable" "Disabled,Enabled" line.long 0x0C "NEXT_EN_TOG,Next Buffer Enable Select Register" bitfld.long 0x0C 1. " WFEB ,WFE B Next Buffer function enable" "Disabled,Enabled" bitfld.long 0x0C 0. " LEGACY ,Legacy Next Buffer function enable" "Disabled,Enabled" group.long 0x400++0x03 line.long 0x00 "NEXT,Next Frame Pointer" hexmask.long 0x00 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" rbitfld.long 0x00 0. " ENABLED ,Indicates that the 'next frame' functionality has been enabled" "Disabled,Enabled" group.long 0x410++0x03 line.long 0x00 "DEBUGCTRL,Debug Control Register" bitfld.long 0x00 11. " LUT_CLR_STAT_CNT[1] ,Clear LUT status counter 1" "0,1" bitfld.long 0x00 10. " [2] ,Clear LUT status counter 2" "0,1" newline bitfld.long 0x00 9. " [3] ,Clear LUT status counter 3" "0,1" bitfld.long 0x00 8. " [4] ,Clear LUT status counter 4" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " SELECT ,Index into one of the PXP debug registers" rgroup.long 0x420++0x03 line.long 0x00 "DEBUG,Debug Register" rgroup.long 0x430++0x03 line.long 0x00 "VERSION,Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" newline hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" newline hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 35. tree "WFB Registers" group.long 0x1100++0x0F line.long 0x00 "FETCH_CTRL,Fetch Engine Control For WFE B Register" bitfld.long 0x00 31. " BUF2_DONE_IRQ_EN ,Buffer2 fetch done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " BUF1_DONE_IRQ_EN ,Buffer1 fetch done interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " BUF2_DONE_IRQ ,Buffer2 fetch done interrupt" "Not occurred,Occurred" bitfld.long 0x00 28. " BUF1_DONE_IRQ ,Buffer1 fetch done interrupt" "Not occurred,Occurred" newline bitfld.long 0x00 22.--23. " BUF2_LINE_MODE ,Indicates the number of lines to be fetched" "0,1,2,3" bitfld.long 0x00 20.--21. " BF2_BYTES_PP ,Indicates the number of bytes in each pixel for the buffer" "0,1,2,3" newline bitfld.long 0x00 18.--19. " BUF1_LINE_MODE ,Indicates the number of lines to be fetched" "0,1,2,3" bitfld.long 0x00 16.--17. " BF1_BYTES_PP ,Indicates the number of bytes in each pixel for the buffer" "0,1,2,3" newline bitfld.long 0x00 13. " BF2_BORDER_MODE ,Indicates buffer2 border pixels select" "0,1" bitfld.long 0x00 12. " BF2_BURST_LEN ,Indicates buffer2 AXI burst length" "0,1" newline bitfld.long 0x00 11. " BF2_BYPASS_MODE ,Indicates buffer2 to bypass pixels" "Not bypassed,Bypassed" bitfld.long 0x00 10. " BF2_HSK_MODE ,Mode of operation" "0,1" newline bitfld.long 0x00 9. " BF2_SRAM_IF ,Fetch source" "0,1" bitfld.long 0x00 8. " BF2_EN ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " BF1_BORDER_MODE ,Indicates buffer1 border pixels select" "0,1" bitfld.long 0x00 4. " BF1_BURST_LEN ,Indicates buffer1 AXI burst length" "0,1" newline bitfld.long 0x00 3. " BF1_BYPASS_MODE ,Indicates buffer1 to bypass pixels" "Not bypassed,Bypassed" bitfld.long 0x00 2. " BF1_HSK_MODE ,Mode of operation" "0,1" newline bitfld.long 0x00 1. " BF1_SRAM_IF ,Fetch source" "0,1" bitfld.long 0x00 0. " BF1_EN ,Buffer1 enable" "Disabled,Enabled" line.long 0x04 "FETCH_CTRL_SET,Fetch Engine Control For WFE B Register" bitfld.long 0x04 31. " BUF2_DONE_IRQ_EN ,Buffer2 fetch done interrupt enable" "Disabled,Enabled" bitfld.long 0x04 30. " BUF1_DONE_IRQ_EN ,Buffer1 fetch done interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 29. " BUF2_DONE_IRQ ,Buffer2 fetch done interrupt" "Not occurred,Occurred" bitfld.long 0x04 28. " BUF1_DONE_IRQ ,Buffer1 fetch done interrupt" "Not occurred,Occurred" newline bitfld.long 0x04 22.--23. " BUF2_LINE_MODE ,Indicates the number of lines to be fetched" "0,1,2,3" bitfld.long 0x04 20.--21. " BF2_BYTES_PP ,Indicates the number of bytes in each pixel for the buffer" "0,1,2,3" newline bitfld.long 0x04 18.--19. " BUF1_LINE_MODE ,Indicates the number of lines to be fetched" "0,1,2,3" bitfld.long 0x04 16.--17. " BF1_BYTES_PP ,Indicates the number of bytes in each pixel for the buffer" "0,1,2,3" newline bitfld.long 0x04 13. " BF2_BORDER_MODE ,Indicates buffer2 border pixels select" "0,1" bitfld.long 0x04 12. " BF2_BURST_LEN ,Indicates buffer2 AXI burst length" "0,1" newline bitfld.long 0x04 11. " BF2_BYPASS_MODE ,Indicates buffer2 to bypass pixels" "Not bypassed,Bypassed" bitfld.long 0x04 10. " BF2_HSK_MODE ,Mode of operation" "0,1" newline bitfld.long 0x04 9. " BF2_SRAM_IF ,Fetch source" "0,1" bitfld.long 0x04 8. " BF2_EN ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " BF1_BORDER_MODE ,Indicates buffer1 border pixels select" "0,1" bitfld.long 0x04 4. " BF1_BURST_LEN ,Indicates buffer1 AXI burst length" "0,1" newline bitfld.long 0x04 3. " BF1_BYPASS_MODE ,Indicates buffer1 to bypass pixels" "Not bypassed,Bypassed" bitfld.long 0x04 2. " BF1_HSK_MODE ,Mode of operation" "0,1" newline bitfld.long 0x04 1. " BF1_SRAM_IF ,Fetch source" "0,1" bitfld.long 0x04 0. " BF1_EN ,Buffer1 enable" "Disabled,Enabled" line.long 0x08 "FETCH_CTRL_CLR,Fetch Engine Control For WFE B Register" bitfld.long 0x08 31. " BUF2_DONE_IRQ_EN ,Buffer2 fetch done interrupt enable" "Disabled,Enabled" bitfld.long 0x08 30. " BUF1_DONE_IRQ_EN ,Buffer1 fetch done interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 29. " BUF2_DONE_IRQ ,Buffer2 fetch done interrupt" "Not occurred,Occurred" bitfld.long 0x08 28. " BUF1_DONE_IRQ ,Buffer1 fetch done interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 22.--23. " BUF2_LINE_MODE ,Indicates the number of lines to be fetched" "0,1,2,3" bitfld.long 0x08 20.--21. " BF2_BYTES_PP ,Indicates the number of bytes in each pixel for the buffer" "0,1,2,3" newline bitfld.long 0x08 18.--19. " BUF1_LINE_MODE ,Indicates the number of lines to be fetched" "0,1,2,3" bitfld.long 0x08 16.--17. " BF1_BYTES_PP ,Indicates the number of bytes in each pixel for the buffer" "0,1,2,3" newline bitfld.long 0x08 13. " BF2_BORDER_MODE ,Indicates buffer2 border pixels select" "0,1" bitfld.long 0x08 12. " BF2_BURST_LEN ,Indicates buffer2 AXI burst length" "0,1" newline bitfld.long 0x08 11. " BF2_BYPASS_MODE ,Indicates buffer2 to bypass pixels" "Not bypassed,Bypassed" bitfld.long 0x08 10. " BF2_HSK_MODE ,Mode of operation" "0,1" newline bitfld.long 0x08 9. " BF2_SRAM_IF ,Fetch source" "0,1" bitfld.long 0x08 8. " BF2_EN ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BF1_BORDER_MODE ,Indicates buffer1 border pixels select" "0,1" bitfld.long 0x08 4. " BF1_BURST_LEN ,Indicates buffer1 AXI burst length" "0,1" newline bitfld.long 0x08 3. " BF1_BYPASS_MODE ,Indicates buffer1 to bypass pixels" "Not bypassed,Bypassed" bitfld.long 0x08 2. " BF1_HSK_MODE ,Mode of operation" "0,1" newline bitfld.long 0x08 1. " BF1_SRAM_IF ,Fetch source" "0,1" bitfld.long 0x08 0. " BF1_EN ,Buffer1 enable" "Disabled,Enabled" line.long 0x0C "FETCH_CTRL_TOG,Fetch Engine Control For WFE B Register" bitfld.long 0x0C 31. " BUF2_DONE_IRQ_EN ,Buffer2 fetch done interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 30. " BUF1_DONE_IRQ_EN ,Buffer1 fetch done interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 29. " BUF2_DONE_IRQ ,Buffer2 fetch done interrupt" "Not occurred,Occurred" bitfld.long 0x0C 28. " BUF1_DONE_IRQ ,Buffer1 fetch done interrupt" "Not occurred,Occurred" newline bitfld.long 0x0C 22.--23. " BUF2_LINE_MODE ,Indicates the number of lines to be fetched" "0,1,2,3" bitfld.long 0x0C 20.--21. " BF2_BYTES_PP ,Indicates the number of bytes in each pixel for the buffer" "0,1,2,3" newline bitfld.long 0x0C 18.--19. " BUF1_LINE_MODE ,Indicates the number of lines to be fetched" "0,1,2,3" bitfld.long 0x0C 16.--17. " BF1_BYTES_PP ,Indicates the number of bytes in each pixel for the buffer" "0,1,2,3" newline bitfld.long 0x0C 13. " BF2_BORDER_MODE ,Indicates buffer2 border pixels select" "0,1" bitfld.long 0x0C 12. " BF2_BURST_LEN ,Indicates buffer2 AXI burst length" "0,1" newline bitfld.long 0x0C 11. " BF2_BYPASS_MODE ,Indicates buffer2 to bypass pixels" "Not bypassed,Bypassed" bitfld.long 0x0C 10. " BF2_HSK_MODE ,Mode of operation" "0,1" newline bitfld.long 0x0C 9. " BF2_SRAM_IF ,Fetch source" "0,1" bitfld.long 0x0C 8. " BF2_EN ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BF1_BORDER_MODE ,Indicates buffer1 border pixels select" "0,1" bitfld.long 0x0C 4. " BF1_BURST_LEN ,Indicates buffer1 AXI burst length" "0,1" newline bitfld.long 0x0C 3. " BF1_BYPASS_MODE ,Indicates buffer1 to bypass pixels" "Not bypassed,Bypassed" bitfld.long 0x0C 2. " BF1_HSK_MODE ,Mode of operation" "0,1" newline bitfld.long 0x0C 1. " BF1_SRAM_IF ,Fetch source" "0,1" bitfld.long 0x0C 0. " BF1_EN ,Buffer1 enable" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "FETCH_BUF1_ADDR,Fetch Engine Buffer1 Base Address Register" group.long 0x20++0x03 line.long 0x00 "FETCH_BUF1_PITCH,Fetch Engine Buffer1 Pitch Register" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Indicates the number of bytes in memory between two vertically adjacent pixels" group.long 0x30++0x03 line.long 0x00 "FETCH_BUF1_SIZE,Fetch Engine Buffer1 Size Register" hexmask.long.word 0x00 16.--31. 1. " BUF_HEIGHT ,Indicates the buffer height in pixels" hexmask.long.word 0x00 0.--15. 1. " BUF_WIDTH ,Indicates the buffer width in pixels" group.long 0x40++0x03 line.long 0x00 "FETCH_BUF2_ADDR,Fetch Engine Buffer2 Base Address Register" group.long 0x50++0x03 line.long 0x00 "FETCH_BUF2_PITCH,Fetch Engine Buffer2 Pitch Register" hexmask.long.word 0x00 0.--15. 1. " PITCH ,Indicates the number of bytes in memory between two vertically adjacent pixels" group.long 0x60++0x03 line.long 0x00 "FETCH_BUF2_SIZE,Fetch Engine Buffer2 Size Register" hexmask.long.word 0x00 16.--31. 1. " BUF_HEIGHT ,Indicates the buffer height in pixels" hexmask.long.word 0x00 0.--15. 1. " BUF_WIDTH ,Indicates the buffer width in pixels" group.long 0x1170++0x03 line.long 0x00 "ARRAY_PIXEL0_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1180++0x03 line.long 0x00 "ARRAY_PIXEL1_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1190++0x03 line.long 0x00 "ARRAY_PIXEL2_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11A0++0x03 line.long 0x00 "ARRAY_PIXEL3_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11B0++0x03 line.long 0x00 "ARRAY_PIXEL4_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11C0++0x03 line.long 0x00 "ARRAY_PIXEL5_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11D0++0x03 line.long 0x00 "ARRAY_PIXEL6_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11E0++0x03 line.long 0x00 "ARRAY_PIXEL7_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11F0++0x03 line.long 0x00 "ARRAY_FLAG0_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 0" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1200++0x03 line.long 0x00 "ARRAY_FLAG1_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 1" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1210++0x03 line.long 0x00 "ARRAY_FLAG2_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 2" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1220++0x03 line.long 0x00 "ARRAY_FLAG3_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 3" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1230++0x03 line.long 0x00 "ARRAY_FLAG4_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 4" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1240++0x03 line.long 0x00 "ARRAY_FLAG5_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 5" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1250++0x03 line.long 0x00 "ARRAY_FLAG6_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 6" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1260++0x03 line.long 0x00 "ARRAY_FLAG7_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 7" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1270++0x03 line.long 0x00 "FETCH_BUF1_CORD,Control Bits For The PXP WFA Fetch Sub-Block" hexmask.long.word 0x00 16.--29. 1. " YCORD ,Indicates Y co-ordinate in pixels" hexmask.long.word 0x00 0.--15. 1. " XCORD ,Indicates X co-ordinate in pixels" group.long 0x1280++0x03 line.long 0x00 "FETCH_BUF2_CORD,Control Bits For The PXP WFA Fetch Sub-Block" hexmask.long.word 0x00 16.--29. 1. " YCORD ,Indicates Y co-ordinate in pixels" hexmask.long.word 0x00 0.--15. 1. " XCORD ,Indicates X co-ordinate in pixels" group.long 0x1290++0x03 line.long 0x00 "ARRAY_FLAG8_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 8" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12A0++0x03 line.long 0x00 "ARRAY_FLAG9_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 9" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12B0++0x03 line.long 0x00 "ARRAY_FLAG10_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 10" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12C0++0x03 line.long 0x00 "ARRAY_FLAG11_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 11" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12D0++0x03 line.long 0x00 "ARRAY_FLAG12_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 12" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12E0++0x03 line.long 0x00 "ARRAY_FLAG13_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 13" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12F0++0x03 line.long 0x00 "ARRAY_FLAG14_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 14" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1300++0x03 line.long 0x00 "ARRAY_FLAG15_MASK,Control Bits For The PXP WFB Fetch Sub-Block Register 15" bitfld.long 0x00 29. " BUF_SEL_BF1 ,Buffer1 enable" "Disabled,Enabled" bitfld.long 0x00 28. " BUF_SEL_BF2 ,Buffer2 enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SIGN_Y ,Offset sign" "0,1" bitfld.long 0x00 24. " SIGN_X ,Offset sign" "0,1" newline bitfld.long 0x00 20.--21. " OFFSET_Y ,Indicates the Y offset position for the pixel" "0,1,2,3" bitfld.long 0x00 16.--17. " OFFSET_X ,Indicates the X offset position for the pixel" "0,1,2,3" newline bitfld.long 0x00 8.--12. " H_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " L_OFS ,Indicates the right bit position on the original pixel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1310++0x03 line.long 0x00 "ARRAY_REG0,Software Define Pixels For WFB Fetch Sub-Block Register 0" hexmask.long.byte 0x00 24.--31. 1. " SW_PIXLE3 ,Software define pixel3" hexmask.long.byte 0x00 16.--23. 1. " SW_PIXLE2 ,Software define pixel2" newline hexmask.long.byte 0x00 8.--15. 1. " SW_PIXLE1 ,Software define pixel1" hexmask.long.byte 0x00 0.--7. 1. " SW_PIXLE0 ,Software define pixel0" group.long 0x1320++0x03 line.long 0x00 "ARRAY_REG1,Software Define Pixels For WFB Fetch Sub-Block Register 1" hexmask.long.byte 0x00 24.--31. 1. " SW_PIXLE7 ,Software define pixel7" hexmask.long.byte 0x00 16.--23. 1. " SW_PIXLE6 ,Software define pixel6" newline hexmask.long.byte 0x00 8.--15. 1. " SW_PIXLE5 ,Software define pixel5" hexmask.long.byte 0x00 0.--7. 1. " SW_PIXLE4 ,Software define pixel4" group.long 0x1330++0x03 line.long 0x00 "ARRAY_REG2,Software Define Pixels For WFB Fetch Sub-Block Register 2" bitfld.long 0x00 15. " SW_FLAG15 ,Software define flag15" "Not occurred,Occurred" bitfld.long 0x00 14. " SW_FLAG14 ,Software define flag14" "Not occurred,Occurred" bitfld.long 0x00 13. " SW_FLAG13 ,Software define flag13" "Not occurred,Occurred" newline bitfld.long 0x00 12. " SW_FLAG12 ,Software define flag12" "Not occurred,Occurred" bitfld.long 0x00 11. " SW_FLAG11 ,Software define flag11" "Not occurred,Occurred" bitfld.long 0x00 10. " SW_FLAG10 ,Software define flag10" "Not occurred,Occurred" newline bitfld.long 0x00 9. " SW_FLAG9 ,Software define flag9" "Not occurred,Occurred" bitfld.long 0x00 8. " SW_FLAG8 ,Software define flag8" "Not occurred,Occurred" bitfld.long 0x00 7. " SW_FLAG7 ,Software define flag7" "Not occurred,Occurred" newline bitfld.long 0x00 6. " SW_FLAG6 ,Software define flag6" "Not occurred,Occurred" bitfld.long 0x00 5. " SW_FLAG5 ,Software define flag5" "Not occurred,Occurred" bitfld.long 0x00 4. " SW_FLAG4 ,Software define flag4" "Not occurred,Occurred" newline bitfld.long 0x00 3. " SW_FLAG3 ,Software define flag3" "Not occurred,Occurred" bitfld.long 0x00 2. " SW_FLAG2 ,Software define flag2" "Not occurred,Occurred" newline bitfld.long 0x00 1. " SW_FLAG1 ,Software define flag1" "Not occurred,Occurred" bitfld.long 0x00 0. " SW_FLAG0 ,Software define flag0" "Not occurred,Occurred" tree.end width 20. tree "WFE_B_STORE Registers" group.long 0x1340++0x0F line.long 0x00 "CTRL_CH0,Store Engine Control Channel 0 Register" bitfld.long 0x00 31. " ARBIT_EN ,Arbitration enable" "Disabled,Enabled" bitfld.long 0x00 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "0,1,2,3" bitfld.long 0x00 11. " FILL_DATA_EN ,Bit for fill data enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " PACK_IN_SEL ,Pack_in_sel" "0,1" bitfld.long 0x00 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " STORE_BYPASS_EN ,Bit for store bypass enable " "Disabled,Enabled" bitfld.long 0x00 5.--6. " ARRAY_LINE_NUM ,Array size" "0,1,2,3" newline bitfld.long 0x00 4. " ARRAY_EN ,Array enable" "Disabled,Enabled" bitfld.long 0x00 3. " HANDSHAKE_EN ,Handshake with the store engine enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " BLOCK_16 ,Block size" "0,1" bitfld.long 0x00 1. " BLOCK_EN ,Store mode" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x04 "CTRL_CH0_SET,Store Engine Control Channel 0 Set Register" bitfld.long 0x04 31. " ARBIT_EN ,Arbitration enable" "Disabled,Enabled" bitfld.long 0x04 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "Disabled,Enabled" newline bitfld.long 0x04 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "0,1,2,3" bitfld.long 0x04 11. " FILL_DATA_EN ,Bit for fill data enable" "Disabled,Enabled" newline bitfld.long 0x04 10. " PACK_IN_SEL ,Pack_in_sel" "0,1" bitfld.long 0x04 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " STORE_BYPASS_EN ,Bit for store bypass enable " "Disabled,Enabled" bitfld.long 0x04 5.--6. " ARRAY_LINE_NUM ,Array size" "0,1,2,3" newline bitfld.long 0x04 4. " ARRAY_EN ,Array enable" "Disabled,Enabled" bitfld.long 0x04 3. " HANDSHAKE_EN ,Handshake with the store engine enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " BLOCK_16 ,Block size" "0,1" bitfld.long 0x04 1. " BLOCK_EN ,Store mode" "Disabled,Enabled" newline bitfld.long 0x04 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x08 "CTRL_CH0_CLR,Store Engine Control Channel 0 Clear Register" bitfld.long 0x08 31. " ARBIT_EN ,Arbitration enable" "Disabled,Enabled" bitfld.long 0x08 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "Disabled,Enabled" newline bitfld.long 0x08 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "0,1,2,3" bitfld.long 0x08 11. " FILL_DATA_EN ,Bit for fill data enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " PACK_IN_SEL ,Pack_in_sel" "0,1" bitfld.long 0x08 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " STORE_BYPASS_EN ,Bit for store bypass enable " "Disabled,Enabled" bitfld.long 0x08 5.--6. " ARRAY_LINE_NUM ,Array size" "0,1,2,3" newline bitfld.long 0x08 4. " ARRAY_EN ,Array enable" "Disabled,Enabled" bitfld.long 0x08 3. " HANDSHAKE_EN ,Handshake with the store engine enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BLOCK_16 ,Block size" "0,1" bitfld.long 0x08 1. " BLOCK_EN ,Store mode" "Disabled,Enabled" newline bitfld.long 0x08 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x0C "CTRL_CH0_TOG,Store Engine Control Channel 0 Toggle Register" bitfld.long 0x0C 31. " ARBIT_EN ,Arbitration enable" "Disabled,Enabled" bitfld.long 0x0C 24. " COMBINE_2CHANNEL ,Combine 2 channel enable" "Disabled,Enabled" newline bitfld.long 0x0C 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "0,1,2,3" bitfld.long 0x0C 11. " FILL_DATA_EN ,Bit for fill data enable" "Disabled,Enabled" newline bitfld.long 0x0C 10. " PACK_IN_SEL ,Pack_in_sel" "0,1" bitfld.long 0x0C 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " STORE_BYPASS_EN ,Bit for store bypass enable " "Disabled,Enabled" bitfld.long 0x0C 5.--6. " ARRAY_LINE_NUM ,Array size" "0,1,2,3" newline bitfld.long 0x0C 4. " ARRAY_EN ,Array enable" "Disabled,Enabled" bitfld.long 0x0C 3. " HANDSHAKE_EN ,Handshake with the store engine enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BLOCK_16 ,Block size" "0,1" bitfld.long 0x0C 1. " BLOCK_EN ,Store mode" "Disabled,Enabled" newline bitfld.long 0x0C 0. " CH_EN ,Channel enable" "Disabled,Enabled" group.long 0x1350++0x0F line.long 0x00 "CTRL_CH1,Store Engine Control Channel 1 Register" bitfld.long 0x00 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "0,1,2,3" bitfld.long 0x00 10. " PACK_IN_SEL ,Pack_in_sel" "0,1" newline bitfld.long 0x00 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" bitfld.long 0x00 8. " STORE_BYPASS_EN ,Bit for store bypass enable" "Disabled,Enabled" newline bitfld.long 0x00 5.--6. " ARRAY_LINE_NUM ,Array size" "0,1,2,3" bitfld.long 0x00 4. " ARRAY_EN ,Array enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " HANDSHAKE_EN ,Handshake with the fetch engine enable" "Disabled,Enabled" bitfld.long 0x00 2. " BLOCK_16 ,Determines the block size" "0,1" newline bitfld.long 0x00 1. " BLOCK_EN ,Store mode" "Disabled,Enabled" bitfld.long 0x00 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x04 "CTRL_CH1_SET,Store Engine Control Channel 1 Register" bitfld.long 0x04 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "0,1,2,3" bitfld.long 0x04 10. " PACK_IN_SEL ,Pack_in_sel" "0,1" newline bitfld.long 0x04 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" bitfld.long 0x04 8. " STORE_BYPASS_EN ,Bit for store bypass enable" "Disabled,Enabled" newline bitfld.long 0x04 5.--6. " ARRAY_LINE_NUM ,Array size" "0,1,2,3" bitfld.long 0x04 4. " ARRAY_EN ,Array enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " HANDSHAKE_EN ,Handshake with the fetch engine enable" "Disabled,Enabled" bitfld.long 0x04 2. " BLOCK_16 ,Determines the block size" "0,1" newline bitfld.long 0x04 1. " BLOCK_EN ,Store mode" "Disabled,Enabled" bitfld.long 0x04 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x08 "CTRL_CH1_CLR,Store Engine Control Channel 1 Register" bitfld.long 0x08 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "0,1,2,3" bitfld.long 0x08 10. " PACK_IN_SEL ,Pack_in_sel" "0,1" newline bitfld.long 0x08 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" bitfld.long 0x08 8. " STORE_BYPASS_EN ,Bit for store bypass enable" "Disabled,Enabled" newline bitfld.long 0x08 5.--6. " ARRAY_LINE_NUM ,Array size" "0,1,2,3" bitfld.long 0x08 4. " ARRAY_EN ,Array enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " HANDSHAKE_EN ,Handshake with the fetch engine enable" "Disabled,Enabled" bitfld.long 0x08 2. " BLOCK_16 ,Determines the block size" "0,1" newline bitfld.long 0x08 1. " BLOCK_EN ,Store mode" "Disabled,Enabled" bitfld.long 0x08 0. " CH_EN ,Channel enable" "Disabled,Enabled" line.long 0x0C "CTRL_CH1_TOG,Store Engine Control Channel 1 Register" bitfld.long 0x0C 16.--17. " WR_NUM_BYTES ,Bytes in a write burst" "0,1,2,3" bitfld.long 0x0C 10. " PACK_IN_SEL ,Pack_in_sel" "0,1" newline bitfld.long 0x0C 9. " STORE_MEMORY_EN ,Store memory enable" "Disabled,Enabled" bitfld.long 0x0C 8. " STORE_BYPASS_EN ,Bit for store bypass enable" "Disabled,Enabled" newline bitfld.long 0x0C 5.--6. " ARRAY_LINE_NUM ,Array size" "0,1,2,3" bitfld.long 0x0C 4. " ARRAY_EN ,Array enable" "Disabled,Enabled" newline bitfld.long 0x0C 3. " HANDSHAKE_EN ,Handshake with the fetch engine enable" "Disabled,Enabled" bitfld.long 0x0C 2. " BLOCK_16 ,Determines the block size" "0,1" newline bitfld.long 0x0C 1. " BLOCK_EN ,Store mode" "Disabled,Enabled" bitfld.long 0x0C 0. " CH_EN ,Channel enable" "Disabled,Enabled" rgroup.long 0x1360++0x03 line.long 0x00 "STATUS_CH0,Store Engine Status Channel 0 Register" hexmask.long.word 0x00 16.--31. 1. " STORE_BLOCK_Y ,Current Y co-ordinate" hexmask.long.word 0x00 0.--15. 1. " STORE_BLOCK_X ,Current X co-ordinate" rgroup.long 0x1370++0x03 line.long 0x00 " STATUS_CH1,Store Engine Status Channel 1 Register" hexmask.long.word 0x00 16.--31. 1. " STORE_BLOCK_Y ,Current Y co-ordinate" hexmask.long.word 0x00 0.--15. 1. " STORE_BLOCK_X ,Current X co-ordinate" group.long 0x1380++0x03 line.long 0x00 "SIZE_CH0,Control Bits For The PXP Store Engine Sub-Block" hexmask.long.word 0x00 16.--31. 1. " OUT_HEIGH ,Actual output height -1" hexmask.long.word 0x00 0.--15. 1. " OUT_WIDTH ,Actual output width -1" group.long 0x1390++0x03 line.long 0x00 "SIZE_CH1,Control Bits For The PXP Store Engine Sub-Block" hexmask.long.word 0x00 16.--31. 1. " OUT_HEIGH ,Actual output height -1" hexmask.long.word 0x00 0.--15. 1. " OUT_WIDTH ,Actual output width -1" group.long 0x13A0++0x03 line.long 0x00 "PITCH,Control Bits For The PXP Store Engine Sub-Block Pitch" hexmask.long.word 0x00 16.--31. 1. " CH1_OUT_PITCH ,Indicates the channel 1 input pitch" hexmask.long.word 0x00 0.--15. 1. " CH0_OUT_PITCH ,Indicates the channel 0 input pitch" group.long 0x13B0++0x0F line.long 0x00 "SHIFT_CTRL_CH0,Shift Control Bits For The PXP Store Engine Sub-Block" bitfld.long 0x00 7. " SHIFT_BYPASS ,Channel 0 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x00 5. " OUT_YUV422_2P_EN ,Enable for YUV422 2 plane" "Disabled,Enabled" newline bitfld.long 0x00 4. " OUT_YUV422_1P_EN ,Enable for YUV422 1 plane" "Disabled,Enabled" bitfld.long 0x00 3. " OUTPUT_ACTIVE_BPP[1] ,Output active BBP" "Inactive,Active" bitfld.long 0x00 2. " [0] ,Output active BBP" "Inactive,Active" line.long 0x04 "SHIFT_CTRL_CH0_SET,Shift Control Bits For The PXP Store Engine Sub-Block" bitfld.long 0x04 7. " SHIFT_BYPASS ,Channel 0 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x04 5. " OUT_YUV422_2P_EN ,Enable for YUV422 2 plane" "Disabled,Enabled" newline bitfld.long 0x04 4. " OUT_YUV422_1P_EN ,Enable for YUV422 1 plane" "Disabled,Enabled" bitfld.long 0x04 3. " OUTPUT_ACTIVE_BPP[1] ,Output active BBP" "Inactive,Active" bitfld.long 0x04 2. " [0] ,Output active BBP" "Inactive,Active" line.long 0x08 "SHIFT_CTRL_CH0_CLR,Shift Control Bits For The PXP Store Engine Sub-Block" bitfld.long 0x08 7. " SHIFT_BYPASS ,Channel 0 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x08 5. " OUT_YUV422_2P_EN ,Enable for YUV422 2 plane" "Disabled,Enabled" newline bitfld.long 0x08 4. " OUT_YUV422_1P_EN ,Enable for YUV422 1 plane" "Disabled,Enabled" bitfld.long 0x08 3. " OUTPUT_ACTIVE_BPP[1] ,Output active BBP" "Inactive,Active" bitfld.long 0x08 2. " [0] ,Output active BBP" "Inactive,Active" line.long 0x0C "SHIFT_CTRL_CH0_TOG,Shift Control Bits For The PXP Store Engine Sub-Block" bitfld.long 0x0C 7. " SHIFT_BYPASS ,Channel 0 shift bypass" "Not bypassed,Bypassed" bitfld.long 0x0C 5. " OUT_YUV422_2P_EN ,Enable for YUV422 2 plane" "Disabled,Enabled" newline bitfld.long 0x0C 4. " OUT_YUV422_1P_EN ,Enable for YUV422 1 plane" "Disabled,Enabled" bitfld.long 0x0C 3. " OUTPUT_ACTIVE_BPP[1] ,Output active BBP" "Inactive,Active" bitfld.long 0x0C 2. " [0] ,Output active BBP" "Inactive,Active" group.long 0x13B0++0x0F line.long 0x00 "SHIFT_CTRL_CH0,Shift Control Bits For The PXP Store Engine Sub-Block" bitfld.long 0x00 5. " OUT_YUV422_2P_EN ,Enable for YUV422 2 plane" "Disabled,Enabled" bitfld.long 0x00 4. " OUT_YUV422_1P_EN ,Enable for YUV422 1 plane" "Disabled,Enabled" newline bitfld.long 0x00 3. " OUTPUT_ACTIVE_BPP[1] ,Output active BBP" "Inactive,Active" bitfld.long 0x00 2. " [0] ,Output active BBP" "Inactive,Active" line.long 0x04 "SHIFT_CTRL_CH0_SET,Shift Control Bits For The PXP Store Engine Sub-Block" bitfld.long 0x04 5. " OUT_YUV422_2P_EN ,Enable for YUV422 2 plane" "Disabled,Enabled" bitfld.long 0x04 4. " OUT_YUV422_1P_EN ,Enable for YUV422 1 plane" "Disabled,Enabled" newline bitfld.long 0x04 3. " OUTPUT_ACTIVE_BPP[1] ,Output active BBP" "Inactive,Active" bitfld.long 0x04 2. " [0] ,Output active BBP" "Inactive,Active" line.long 0x08 "SHIFT_CTRL_CH0_CLR,Shift Control Bits For The PXP Store Engine Sub-Block" bitfld.long 0x08 5. " OUT_YUV422_2P_EN ,Enable for YUV422 2 plane" "Disabled,Enabled" bitfld.long 0x08 4. " OUT_YUV422_1P_EN ,Enable for YUV422 1 plane" "Disabled,Enabled" newline bitfld.long 0x08 3. " OUTPUT_ACTIVE_BPP[1] ,Output active BBP" "Inactive,Active" bitfld.long 0x08 2. " [0] ,Output active BBP" "Inactive,Active" line.long 0x0C "SHIFT_CTRL_CH0_TOG,Shift Control Bits For The PXP Store Engine Sub-Block" bitfld.long 0x0C 5. " OUT_YUV422_2P_EN ,Enable for YUV422 2 plane" "Disabled,Enabled" bitfld.long 0x0C 4. " OUT_YUV422_1P_EN ,Enable for YUV422 1 plane" "Disabled,Enabled" newline bitfld.long 0x0C 3. " OUTPUT_ACTIVE_BPP[1] ,Output active BBP" "Inactive,Active" bitfld.long 0x0C 2. " [0] ,Output active BBP" "Inactive,Active" group.long 0x1410++0x03 line.long 0x00 "ADDR_0_CH0,Address 0 Channel 0 Register" group.long 0x1420++0x03 line.long 0x00 "ADDR_1_CH0,Address 1 Channel 0 Register" group.long 0x1430++0x03 line.long 0x00 "FILL_DATA_CH0,Fill Data Mode Register" group.long 0x1440++0x03 line.long 0x00 "ADDR_0_CH1,Address 0 Channel 1 Register" group.long 0x1450++0x03 line.long 0x00 "ADDR_1_CH1,Address 1 Channel 1 Register" group.long 0x1460++0x03 line.long 0x00 "D_MASK0_H_CH0,Data Mask0 High Byte Register" group.long (0x1460+0x10)++0x03 line.long 0x00 "D_MASK0_L_CH0,Data Mask0 Low Byte Register" group.long 0x1470++0x03 line.long 0x00 "D_MASK1_H_CH0,Data Mask0 High Byte Register" group.long (0x1470+0x10)++0x03 line.long 0x00 "D_MASK1_L_CH0,Data Mask0 Low Byte Register" group.long 0x1480++0x03 line.long 0x00 "D_MASK2_H_CH0,Data Mask0 High Byte Register" group.long (0x1480+0x10)++0x03 line.long 0x00 "D_MASK2_L_CH0,Data Mask0 Low Byte Register" group.long 0x1490++0x03 line.long 0x00 "D_MASK3_H_CH0,Data Mask0 High Byte Register" group.long (0x1490+0x10)++0x03 line.long 0x00 "D_MASK3_L_CH0,Data Mask0 Low Byte Register" group.long 0x14A0++0x03 line.long 0x00 "D_MASK4_H_CH0,Data Mask0 High Byte Register" group.long (0x14A0+0x10)++0x03 line.long 0x00 "D_MASK4_L_CH0,Data Mask0 Low Byte Register" group.long 0x14B0++0x03 line.long 0x00 "D_MASK5_H_CH0,Data Mask0 High Byte Register" group.long (0x14B0+0x10)++0x03 line.long 0x00 "D_MASK5_L_CH0,Data Mask0 Low Byte Register" group.long 0x14C0++0x03 line.long 0x00 "D_MASK6_H_CH0,Data Mask0 High Byte Register" group.long (0x14C0+0x10)++0x03 line.long 0x00 "D_MASK6_L_CH0,Data Mask0 Low Byte Register" group.long 0x14D0++0x03 line.long 0x00 "D_MASK7_H_CH0,Data Mask0 High Byte Register" group.long (0x14D0+0x10)++0x03 line.long 0x00 "D_MASK7_L_CH0,Data Mask0 Low Byte Register" group.long 0x1560++0x03 line.long 0x00 "D_SHIFT_L_CH0,Data Shift Flag Channel 0 Low Register" bitfld.long 0x00 31. " D_SHIFT_FLAG3 ,Data shift flag 3" "Not occurred,Occurred" bitfld.long 0x00 24.--29. " D_SHIFT_WIDTH3 ,Data shift width 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " D_SHIFT_FLAG2 ,Data shift flag 2" "Not occurred,Occurred" bitfld.long 0x00 16.--21. " D_SHIFT_WIDTH2 ,Data shift width 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15. " D_SHIFT_FLAG1 ,Data shift flag 1" "Not occurred,Occurred" bitfld.long 0x00 8.--13. " D_SHIFT_WIDTH1 ,Data shift width 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " D_SHIFT_FLAG0 ,Data shift flag 0" "Not occurred,Occurred" bitfld.long 0x00 0.--5. " D_SHIFT_WIDTH0 ,Data shift width 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1570++0x03 line.long 0x00 "D_SHIFT_H_CH0,Data Shift Flag Channel 0 High Register" bitfld.long 0x00 31. " D_SHIFT_FLAG3 ,Data shift flag 3" "Not occurred,Occurred" bitfld.long 0x00 24.--29. " D_SHIFT_WIDTH3 ,Data shift width 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " D_SHIFT_FLAG2 ,Data shift flag 2" "Not occurred,Occurred" bitfld.long 0x00 16.--21. " D_SHIFT_WIDTH2 ,Data shift width 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15. " D_SHIFT_FLAG1 ,Data shift flag 1" "Not occurred,Occurred" bitfld.long 0x00 8.--13. " D_SHIFT_WIDTH1 ,Data shift width 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " D_SHIFT_FLAG0 ,Data shift flag 0" "Not occurred,Occurred" bitfld.long 0x00 0.--5. " D_SHIFT_WIDTH0 ,Data shift width 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1580++0x03 line.long 0x00 "F_SHIFT_L_CH0,Flag Shift Flag Channel 0 Low Register" bitfld.long 0x00 30. " D_SHIFT_FLAG3 ,Data shift flag 3" "Not occurred,Occurred" bitfld.long 0x00 24.--29. " D_SHIFT_WIDTH3 ,Data shift width 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " D_SHIFT_FLAG2 ,Data shift flag 2" "Not occurred,Occurred" bitfld.long 0x00 16.--21. " D_SHIFT_WIDTH2 ,Data shift width 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15. " D_SHIFT_FLAG1 ,Data shift flag 1" "Not occurred,Occurred" bitfld.long 0x00 8.--13. " D_SHIFT_WIDTH1 ,Data shift width 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " D_SHIFT_FLAG0 ,Data shift flag 0" "Not occurred,Occurred" bitfld.long 0x00 0.--5. " D_SHIFT_WIDTH0 ,Data shift width 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1590++0x03 line.long 0x00 "F_SHIFT_H_CH0,Flag Shift Flag Channel 0 High Register" bitfld.long 0x00 30. " D_SHIFT_FLAG7 ,Data shift flag 3" "Not occurred,Occurred" bitfld.long 0x00 24.--29. " D_SHIFT_WIDTH7 ,Data shift width 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " D_SHIFT_FLAG6 ,Data shift flag 2" "Not occurred,Occurred" bitfld.long 0x00 16.--21. " D_SHIFT_WIDTH6 ,Data shift width 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15. " D_SHIFT_FLAG5 ,Data shift flag 1" "Not occurred,Occurred" bitfld.long 0x00 8.--13. " D_SHIFT_WIDTH5 ,Data shift width 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " D_SHIFT_FLAG4 ,Data shift flag 0" "Not occurred,Occurred" bitfld.long 0x00 0.--5. " D_SHIFT_WIDTH4 ,Data shift width 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x15A0++0x03 line.long 0x00 "F_MASK_L_CH0,Flag Mask Channel 0 Low Register" hexmask.long.byte 0x00 24.--31. 1. " F_MASK3 ,Flag mask3" hexmask.long.byte 0x00 16.--23. 1. " F_MASK2 ,Flag mask2" newline hexmask.long.byte 0x00 8.--15. 1. " F_MASK1 ,Flag mask1" hexmask.long.byte 0x00 0.--7. 1. " F_MASK0 ,Flag mask0" group.long 0x15B0++0x03 line.long 0x00 "F_MASK_H_CH0,Flag Mask Channel 0 High Register" hexmask.long.byte 0x00 24.--31. 1. " F_MASK7 ,Flag mask7" hexmask.long.byte 0x00 16.--23. 1. " F_MASK6 ,Flag mask6" newline hexmask.long.byte 0x00 8.--15. 1. " F_MASK5 ,Flag mask5" hexmask.long.byte 0x00 0.--7. 1. " F_MASK4 ,Flag mask4" newline tree.end width 21. group.long 0x15D0++0x03 line.long 0x00 "FETCH_WFE_B_DEBUG,Fetch Block Debug Information Register" bitfld.long 0x00 28. " BUF_SEL ,Index into WFE a BUFFER" "0,1" bitfld.long 0x00 24.--27. " ITEM_SEL ,Index into one of the PXP debug registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--23. 1. " DEBUG_VALUE ,Debug information for array fetch" group.long 0x1670++0x0F line.long 0x00 "DITHER_CTRL,Dither Engine Control Register" rbitfld.long 0x00 31. " BUSY0 ,Dither engine 0 busy" "Not busy,Busy" rbitfld.long 0x00 30. " BUSY1 ,Dither engine 1 busy" "Not busy,Busy" newline rbitfld.long 0x00 29. " BUSY2 ,Dither engine 2 busy" "Not busy,Busy" newline bitfld.long 0x00 24. " ORDERED_ROUND_MODE ,Rounding or truncation mode" "Rounding,Truncation" bitfld.long 0x00 23. " FINAL_LUT_ENABLE ,Final stage enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " IDX_MATRIX2_SIZE ,Index matrix 2 dimension" "0,1,2,3" bitfld.long 0x00 19.--20. " IDX_MATRIX1_SIZE ,Index matrix 1 dimension" "0,1,2,3" newline bitfld.long 0x00 17.--18. " IDX_MATRIX0_SIZE ,Index matrix 0 dimension" "0,1,2,3" bitfld.long 0x00 15.--16. " LUT_MODE ,Specify to use memory lut to transform pixel" "0,1,2,3" newline bitfld.long 0x00 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " DITHER_MODE_2 ,Dither mode 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--8. " DITHER_MODE_1 ,Dither mode 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " DITHER_MODE_0 ,Dither mode 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " ENABLE2 ,Dither engine 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLE1 ,Dither engine 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENABLE0 ,Dither engine 0 enable" "Disabled,Enabled" line.long 0x04 "DITHER_CTRL_SET,Dither Control Set Register" rbitfld.long 0x04 31. " BUSY0 ,Dither engine 0 busy" "Not busy,Busy" rbitfld.long 0x04 30. " BUSY1 ,Dither engine 1 busy" "Not busy,Busy" newline rbitfld.long 0x04 29. " BUSY2 ,Dither engine 2 busy" "Not busy,Busy" newline bitfld.long 0x04 24. " ORDERED_ROUND_MODE ,Rounding or truncation mode" "Rounding,Truncation" bitfld.long 0x04 23. " FINAL_LUT_ENABLE ,Final stage enable" "Disabled,Enabled" newline bitfld.long 0x04 21.--22. " IDX_MATRIX2_SIZE ,Index matrix 2 dimension" "0,1,2,3" bitfld.long 0x04 19.--20. " IDX_MATRIX1_SIZE ,Index matrix 1 dimension" "0,1,2,3" newline bitfld.long 0x04 17.--18. " IDX_MATRIX0_SIZE ,Index matrix 0 dimension" "0,1,2,3" bitfld.long 0x04 15.--16. " LUT_MODE ,Specify to use memory lut to transform pixel" "0,1,2,3" newline bitfld.long 0x04 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" "0,1,2,3,4,5,6,7" bitfld.long 0x04 9.--11. " DITHER_MODE_2 ,Dither mode 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 6.--8. " DITHER_MODE_1 ,Dither mode 1" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--5. " DITHER_MODE_0 ,Dither mode 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 2. " ENABLE2 ,Dither engine 2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " ENABLE1 ,Dither engine 1 enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " ENABLE0 ,Dither engine 0 enable" "Disabled,Enabled" line.long 0x08 "DITHER_CTRL_CLR,Dither Control Clear Register" rbitfld.long 0x08 31. " BUSY0 ,Dither engine 0 busy" "Not busy,Busy" rbitfld.long 0x08 30. " BUSY1 ,Dither engine 1 busy" "Not busy,Busy" newline rbitfld.long 0x08 29. " BUSY2 ,Dither engine 2 busy" "Not busy,Busy" newline bitfld.long 0x08 24. " ORDERED_ROUND_MODE ,Rounding or truncation mode" "Rounding,Truncation" bitfld.long 0x08 23. " FINAL_LUT_ENABLE ,Final stage enable" "Disabled,Enabled" newline bitfld.long 0x08 21.--22. " IDX_MATRIX2_SIZE ,Index matrix 2 dimension" "0,1,2,3" bitfld.long 0x08 19.--20. " IDX_MATRIX1_SIZE ,Index matrix 1 dimension" "0,1,2,3" newline bitfld.long 0x08 17.--18. " IDX_MATRIX0_SIZE ,Index matrix 0 dimension" "0,1,2,3" bitfld.long 0x08 15.--16. " LUT_MODE ,Specify to use memory lut to transform pixel" "0,1,2,3" newline bitfld.long 0x08 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" "0,1,2,3,4,5,6,7" bitfld.long 0x08 9.--11. " DITHER_MODE_2 ,Dither mode 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 6.--8. " DITHER_MODE_1 ,Dither mode 1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 3.--5. " DITHER_MODE_0 ,Dither mode 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 2. " ENABLE2 ,Dither engine 2 enable" "Disabled,Enabled" bitfld.long 0x08 1. " ENABLE1 ,Dither engine 1 enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " ENABLE0 ,Dither engine 0 enable" "Disabled,Enabled" line.long 0x0C "DITHER_CTRL_TOG,Dither Control Toggle Register" rbitfld.long 0x0C 31. " BUSY0 ,Dither engine 0 busy" "Not busy,Busy" rbitfld.long 0x0C 30. " BUSY1 ,Dither engine 1 busy" "Not busy,Busy" newline rbitfld.long 0x0C 29. " BUSY2 ,Dither engine 2 busy" "Not busy,Busy" newline bitfld.long 0x0C 24. " ORDERED_ROUND_MODE ,Rounding or truncation mode" "Rounding,Truncation" bitfld.long 0x0C 23. " FINAL_LUT_ENABLE ,Final stage enable" "Disabled,Enabled" newline bitfld.long 0x0C 21.--22. " IDX_MATRIX2_SIZE ,Index matrix 2 dimension" "0,1,2,3" bitfld.long 0x0C 19.--20. " IDX_MATRIX1_SIZE ,Index matrix 1 dimension" "0,1,2,3" newline bitfld.long 0x0C 17.--18. " IDX_MATRIX0_SIZE ,Index matrix 0 dimension" "0,1,2,3" bitfld.long 0x0C 15.--16. " LUT_MODE ,Specify to use memory lut to transform pixel" "0,1,2,3" newline bitfld.long 0x0C 12.--14. " NUM_QUANT_BIT ,Number of bits to quantize down to" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. " DITHER_MODE_2 ,Dither mode 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 6.--8. " DITHER_MODE_1 ,Dither mode 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 3.--5. " DITHER_MODE_0 ,Dither mode 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 2. " ENABLE2 ,Dither engine 2 enable" "Disabled,Enabled" bitfld.long 0x0C 1. " ENABLE1 ,Dither engine 1 enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " ENABLE0 ,Dither engine 0 enable" "Disabled,Enabled" group.long 0x1680++0x0F line.long 0x00 "FINAL_LUT_DATA0,Final LUT Data0 Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Final stage LUT data 3 value" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Final stage LUT data 2 value" newline hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Final stage LUT data 1 value" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Final stage LUT data 0 value" line.long 0x04 "FINAL_LUT_DATA0_SET,Final LUT Data0 Set Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Final stage LUT data 3 value" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Final stage LUT data 2 value" newline hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Final stage LUT data 1 value" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Final stage LUT data 0 value" line.long 0x08 "FINAL_LUT_DATA0_CLR,Final LUT Data0 Clear Register" hexmask.long.byte 0x08 24.--31. 1. " DATA3 ,Final stage LUT data 3 value" hexmask.long.byte 0x08 16.--23. 1. " DATA2 ,Final stage LUT data 2 value" newline hexmask.long.byte 0x08 8.--15. 1. " DATA1 ,Final stage LUT data 1 value" hexmask.long.byte 0x08 0.--7. 1. " DATA0 ,Final stage LUT data 0 value" line.long 0x0C "FINAL_LUT_DATA0_TOG,Final LUT Data0 Toggle Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA3 ,Final stage LUT data 3 value" hexmask.long.byte 0x0C 16.--23. 1. " DATA2 ,Final stage LUT data 2 value" newline hexmask.long.byte 0x0C 8.--15. 1. " DATA1 ,Final stage LUT data 1 value" hexmask.long.byte 0x0C 0.--7. 1. " DATA0 ,Final stage LUT data 0 value" group.long 0x1690++0x0F line.long 0x00 "FINAL_LUT_DATA1,Final LUT Data1 Register" hexmask.long.byte 0x00 24.--31. 1. " DATA7 ,Final stage LUT data 7 value" hexmask.long.byte 0x00 16.--23. 1. " DATA6 ,Final stage LUT data 6 value" newline hexmask.long.byte 0x00 8.--15. 1. " DATA5 ,Final stage LUT data 5 value" hexmask.long.byte 0x00 0.--7. 1. " DATA4 ,Final stage LUT data 4 value" line.long 0x04 "FINAL_LUT_DATA1_SET,Final LUT Data1 Set Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Final stage LUT data 7 value" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Final stage LUT data 6 value" newline hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Final stage LUT data 5 value" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Final stage LUT data 4 value" line.long 0x08 "FINAL_LUT_DATA1_CLR,Final LUT Data1 Clear Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Final stage LUT data 7 value" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Final stage LUT data 6 value" newline hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Final stage LUT data 5 value" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Final stage LUT data 4 value" line.long 0x0C "FINAL_LUT_DATA1_TOG,Final LUT Data1 Toggle Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA7 ,Final stage LUT data 7 value" hexmask.long.byte 0x0C 16.--23. 1. " DATA6 ,Final stage LUT data 6 value" newline hexmask.long.byte 0x0C 8.--15. 1. " DATA5 ,Final stage LUT data 5 value" hexmask.long.byte 0x0C 0.--7. 1. " DATA4 ,Final stage LUT data 4 value" group.long 0x16A0++0x0F line.long 0x00 "FINAL_LUT_DATA2,Final LUT Data2 Register" hexmask.long.byte 0x00 24.--31. 1. " DATA11 ,Final stage LUT data 11 value" hexmask.long.byte 0x00 16.--23. 1. " DATA10 ,Final stage LUT data 10 value" newline hexmask.long.byte 0x00 8.--15. 1. " DATA9 ,Final stage LUT data 9 value" hexmask.long.byte 0x00 0.--7. 1. " DATA8 ,Final stage LUT data 8 value" line.long 0x04 "FINAL_LUT_DATA2_SET,Final LUT Data2 Set Register" hexmask.long.byte 0x04 24.--31. 1. " DATA11 ,Final stage LUT data 11 value" hexmask.long.byte 0x04 16.--23. 1. " DATA10 ,Final stage LUT data 10 value" newline hexmask.long.byte 0x04 8.--15. 1. " DATA9 ,Final stage LUT data 9 value" hexmask.long.byte 0x04 0.--7. 1. " DATA8 ,Final stage LUT data 8 value" line.long 0x08 "FINAL_LUT_DATA2_CLR,Final LUT Data2 Clear Register" hexmask.long.byte 0x08 24.--31. 1. " DATA11 ,Final stage LUT data 11 value" hexmask.long.byte 0x08 16.--23. 1. " DATA10 ,Final stage LUT data 10 value" newline hexmask.long.byte 0x08 8.--15. 1. " DATA9 ,Final stage LUT data 9 value" hexmask.long.byte 0x08 0.--7. 1. " DATA8 ,Final stage LUT data 8 value" line.long 0x0C "FINAL_LUT_DATA2_TOG,Final LUT Data2 Toggle Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA11 ,Final stage LUT data 11 value" hexmask.long.byte 0x0C 16.--23. 1. " DATA10 ,Final stage LUT data 10 value" newline hexmask.long.byte 0x0C 8.--15. 1. " DATA9 ,Final stage LUT data 9 value" hexmask.long.byte 0x0C 0.--7. 1. " DATA8 ,Final stage LUT data 8 value" group.long 0x16B0++0x0F line.long 0x00 "FINAL_LUT_DATA3,Final LUT Data3 Register" hexmask.long.byte 0x00 24.--31. 1. " DATA15 ,Final stage LUT data 15 value" hexmask.long.byte 0x00 16.--23. 1. " DATA14 ,Final stage LUT data 14 value" newline hexmask.long.byte 0x00 8.--15. 1. " DATA13 ,Final stage LUT data 13 value" hexmask.long.byte 0x00 0.--7. 1. " DATA12 ,Final stage LUT data 12 value" line.long 0x04 "FINAL_LUT_DATA3_SET,Final LUT Data3 Set Register" hexmask.long.byte 0x04 24.--31. 1. " DATA15 ,Final stage LUT data 15 value" hexmask.long.byte 0x04 16.--23. 1. " DATA14 ,Final stage LUT data 14 value" newline hexmask.long.byte 0x04 8.--15. 1. " DATA13 ,Final stage LUT data 13 value" hexmask.long.byte 0x04 0.--7. 1. " DATA12 ,Final stage LUT data 12 value" line.long 0x08 "FINAL_LUT_DATA3_CLR,Final LUT Data3 Clear Register" hexmask.long.byte 0x08 24.--31. 1. " DATA15 ,Final stage LUT data 15 value" hexmask.long.byte 0x08 16.--23. 1. " DATA14 ,Final stage LUT data 14 value" newline hexmask.long.byte 0x08 8.--15. 1. " DATA13 ,Final stage LUT data 13 value" hexmask.long.byte 0x08 0.--7. 1. " DATA12 ,Final stage LUT data 12 value" line.long 0x0C "FINAL_LUT_DATA3_TOG,Final LUT Data3 Toggle Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA15 ,Final stage LUT data 15 value" hexmask.long.byte 0x0C 16.--23. 1. " DATA14 ,Final stage LUT data 14 value" newline hexmask.long.byte 0x0C 8.--15. 1. " DATA13 ,Final stage LUT data 13 value" hexmask.long.byte 0x0C 0.--7. 1. " DATA12 ,Final stage LUT data 12 value" tree "WFE_B Registers" width 22. group.long 0x1D00++0x13 line.long 0x00 "CTRL,Control Register to Control Bits For The PXP WFE Sub-Block" rbitfld.long 0x00 31. " DONE ,Indicates that the WFE B has completed processing the update memory region" "Not done,Done" bitfld.long 0x00 2. " SW_RESET ,Reset WFE B state" "No reset,Reset" newline bitfld.long 0x00 0. " ENABLE ,WFE B block enable" "Disabled,Enabled" line.long 0x04 "CTRL,Control Register to Control Bits For The PXP WFE Sub-Block" rbitfld.long 0x04 31. " DONE ,Indicates that the WFE B has completed processing the update memory region" "Not done,Done" bitfld.long 0x04 2. " SW_RESET ,Reset WFE B state" "No reset,Reset" newline bitfld.long 0x04 0. " ENABLE ,WFE B block enable" "Disabled,Enabled" line.long 0x08 "CTRL,Control Register to Control Bits For The PXP WFE Sub-Block" rbitfld.long 0x08 31. " DONE ,Indicates that the WFE B has completed processing the update memory region" "Not done,Done" bitfld.long 0x08 2. " SW_RESET ,Reset WFE B state" "No reset,Reset" newline bitfld.long 0x08 0. " ENABLE ,WFE B block enable" "Disabled,Enabled" line.long 0x0C "CTRL,Control Register to Control Bits For The PXP WFE Sub-Block" rbitfld.long 0x0C 31. " DONE ,Indicates that the WFE B has completed processing the update memory region" "Not done,Done" bitfld.long 0x0C 2. " SW_RESET ,Reset WFE B state" "No reset,Reset" newline bitfld.long 0x0C 0. " ENABLE ,WFE B block enable" "Disabled,Enabled" line.long 0x10 "DIMENSIONS,PXP WFE Sub-Block Dimensions" hexmask.long.word 0x10 16.--27. 1. " HEIGHT ,Height in pixels of the update region" newline hexmask.long.word 0x10 0.--11. 1. " WIDTH ,Width in pixels of the update region" group.long 0x1D20++0x03 line.long 0x00 "OFFSET,PXP WFE Sub-Block Offset" hexmask.long.word 0x00 16.--27. 1. " Y_OFFSET ,Distance from the frame origin to the update region origin in the Y direction" newline hexmask.long.word 0x00 0.--11. 1. " X_OFFSET ,Distance from the frame origin to the update region origin in the X direction" group.long 0x1D30++0x03 line.long 0x00 "SW_DATA_REGS,SW Data Value Register" hexmask.long.byte 0x00 24.--31. 1. " VAL3 ,Holds programmable data value" hexmask.long.byte 0x00 16.--23. 1. " VAL2 ,Holds programmable data value" newline hexmask.long.byte 0x00 8.--15. 1. " VAL1 ,Holds programmable data value" hexmask.long.byte 0x00 0.--7. 1. " VAL0 ,Holds programmable data value" group.long 0x1D40++0x03 line.long 0x00 "SW_FLAG_REGS,SW Flag Register" bitfld.long 0x00 3. " VAL3 ,Holds programmable flag value" "Not occurred,Occurred" bitfld.long 0x00 2. " VAL2 ,Holds programmable flag value" "Not occurred,Occurred" newline bitfld.long 0x00 1. " VAL1 ,Holds programmable flag value" "Not occurred,Occurred" bitfld.long 0x00 0. " VAL0 ,Holds programmable flag value" "Not occurred,Occurred" group.long 0x1D50++0x0F line.long 0x00 "STAGE1_MUX0,Stage 1 Mux 0 Register" bitfld.long 0x00 24.--29. " MUX3 ,Input 4 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX2 ,Input 3 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX1 ,Input 2 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX0 ,Input 1 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE1_MUX0_SET,Stage 1 Mux 0 Set Register" bitfld.long 0x04 24.--29. " MUX3 ,Input 4 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX2 ,Input 3 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX1 ,Input 2 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX0 ,Input 1 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE1_MUX0_CLR,Stage 1 Mux 0 Clear Register" bitfld.long 0x08 24.--29. " MUX3 ,Input 4 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX2 ,Input 3 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX1 ,Input 2 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX0 ,Input 1 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE1_MUX0_TOG,Stage 1 Mux 0 Toggle Register" bitfld.long 0x0C 24.--29. " MUX3 ,Input 4 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX2 ,Input 3 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX1 ,Input 2 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX0 ,Input 1 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D60++0x0F line.long 0x00 "STAGE1_MUX1,Stage 1 Mux 1 Register" bitfld.long 0x00 24.--29. " MUX7 ,Input 3 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX6 ,Input 2 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX5 ,Input 1 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX4 ,Input 5 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE1_MUX1_SET,Stage 1 Mux 1 Set Register" bitfld.long 0x04 24.--29. " MUX7 ,Input 3 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX6 ,Input 2 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX5 ,Input 1 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX4 ,Input 5 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE1_MUX1_CLR,Stage 1 Mux 1 Clear Register" bitfld.long 0x08 24.--29. " MUX7 ,Input 3 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX6 ,Input 2 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX5 ,Input 1 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX4 ,Input 5 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE1_MUX1_TOG,Stage 1 Mux 1 Toggle Register" bitfld.long 0x0C 24.--29. " MUX7 ,Input 3 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX6 ,Input 2 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX5 ,Input 1 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX4 ,Input 5 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D70++0x0F line.long 0x00 "STAGE1_MUX2,Stage 1 Mux 2 Register" bitfld.long 0x00 24.--29. " MUX11 ,Input 2 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX10 ,Input 1 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX9 ,Input 5 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX8 ,Input 4 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE1_MUX2_SET,Stage 1 Mux 2 Set Register" bitfld.long 0x04 24.--29. " MUX11 ,Input 2 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX10 ,Input 1 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX9 ,Input 5 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX8 ,Input 4 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE1_MUX2_CLR,Stage 1 Mux 2 Clear Register" bitfld.long 0x08 24.--29. " MUX11 ,Input 2 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX10 ,Input 1 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX9 ,Input 5 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX8 ,Input 4 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE1_MUX2_TOG,Stage 1 Mux 2 Toggle Register" bitfld.long 0x0C 24.--29. " MUX11 ,Input 2 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX10 ,Input 1 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX9 ,Input 5 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX8 ,Input 4 data select bits for 5x8 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D80++0x0F line.long 0x00 "STAGE1_MUX3,Stage 1 Mux 3 Register" bitfld.long 0x00 24.--29. " MUX15 ,Data select bits for D8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX14 ,Input 5 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX13 ,Input 4 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX12 ,Input 3 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE1_MUX3_SET,Stage 1 Mux 3 Set Register" bitfld.long 0x04 24.--29. " MUX15 ,Data select bits for D8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX14 ,Input 5 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX13 ,Input 4 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX12 ,Input 3 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE1_MUX3_CLR,Stage 1 Mux 3 Clear Register" bitfld.long 0x08 24.--29. " MUX15 ,Data select bits for D8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX14 ,Input 5 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX13 ,Input 4 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX12 ,Input 3 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE1_MUX3_TOG,Stage 1 Mux 3 Toggle Register" bitfld.long 0x0C 24.--29. " MUX15 ,Data select bits for D8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX14 ,Input 5 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX13 ,Input 4 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX12 ,Input 3 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D90++0x0F line.long 0x00 "STAGE1_MUX4,Stage 1 Mux 4 Register" bitfld.long 0x00 24.--29. " MUX19 ,Data select bits for D8x1 LUT 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX18 ,Data select bits for D8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX17 ,Data select bits for D8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX16 ,Data select bits for D8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE1_MUX4_SET,Stage 1 Mux 4 Set Register" bitfld.long 0x04 24.--29. " MUX19 ,Data select bits for D8x1 LUT 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX18 ,Data select bits for D8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX17 ,Data select bits for D8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX16 ,Data select bits for D8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE1_MUX4_CLR,Stage 1 Mux 4 Clear Register" bitfld.long 0x08 24.--29. " MUX19 ,Data select bits for D8x1 LUT 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX18 ,Data select bits for D8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX17 ,Data select bits for D8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX16 ,Data select bits for D8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE1_MUX4_TOG,Stage 1 Mux 4 Toggle Register" bitfld.long 0x0C 24.--29. " MUX19 ,Data select bits for D8x1 LUT 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX18 ,Data select bits for D8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX17 ,Data select bits for D8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX16 ,Data select bits for D8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1DA0++0x0F line.long 0x00 "STAGE1_MUX5,Stage 1 Mux 5 Register" bitfld.long 0x00 24.--29. " MUX23 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX22 ,Input data select bits or ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX21 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX20 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE1_MUX5_SET,Stage 1 Mux 5 Set Register" bitfld.long 0x04 24.--29. " MUX23 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX22 ,Input data select bits or ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX21 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX20 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE1_MUX5_CLR,Stage 1 Mux 5 Clear Register" bitfld.long 0x08 24.--29. " MUX23 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX22 ,Input data select bits or ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX21 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX20 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE1_MUX5_TOG,Stage 1 Mux 5 Toggle Register" bitfld.long 0x0C 24.--29. " MUX23 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX22 ,Input data select bits or ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX21 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX20 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1DB0++0x0F line.long 0x00 "STAGE1_MUX6,Stage 1 Mux 6 Register" bitfld.long 0x00 24.--29. " MUX27 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX26 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX25 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX24 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE1_MUX6_SET,Stage 1 Mux 6 Set Register" bitfld.long 0x04 24.--29. " MUX27 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX26 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX25 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX24 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE1_MUX6_CLR,Stage 1 Mux 6 Clear Register" bitfld.long 0x08 24.--29. " MUX27 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX26 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX25 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX24 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE1_MUX6_TOG,Stage 1 Mux 6 Toggle Register" bitfld.long 0x0C 24.--29. " MUX27 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX26 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX25 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX24 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1DC0++0x0F line.long 0x00 "STAGE1_MUX7,Stage 1 Mux 7 Register" bitfld.long 0x00 24.--29. " MUX31 ,Input data select bits for Comparator 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX30 ,Input data select bits for Comparator 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX29 ,Input data select bits for Comparator 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX28 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE1_MUX7_SET,Stage 1 Mux 7 Set Register" bitfld.long 0x04 24.--29. " MUX31 ,Input data select bits for Comparator 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX30 ,Input data select bits for Comparator 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX29 ,Input data select bits for Comparator 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX28 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE1_MUX7_CLR,Stage 1 Mux 7 Clear Register" bitfld.long 0x08 24.--29. " MUX31 ,Input data select bits for Comparator 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX30 ,Input data select bits for Comparator 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX29 ,Input data select bits for Comparator 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX28 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE1_MUX7_TOG,Stage 1 Mux 7 Toggle Register" bitfld.long 0x0C 24.--29. " MUX31 ,Input data select bits for Comparator 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX30 ,Input data select bits for Comparator 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX29 ,Input data select bits for Comparator 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX28 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1DD0++0x0F line.long 0x00 "STAGE1_MUX8,Stage 1 Mux 8 Register" bitfld.long 0x00 0.--5. " MUX32 ,Input data select bits for Comparator 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE1_MUX8_SET,Stage 1 Mux 8 Set Register" bitfld.long 0x04 0.--5. " MUX32 ,Input data select bits for Comparator 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE1_MUX8_CLR,Stage 1 Mux 8 Clear Register" bitfld.long 0x08 0.--5. " MUX32 ,Input data select bits for Comparator 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE1_MUX8_TOG,Stage 1 Mux 8 Toggle Register" bitfld.long 0x0C 0.--5. " MUX32 ,Input data select bits for Comparator 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline group.long 0x1DE0++0x0F line.long 0x00 "STAGE2_MUX0,Stage 2 Mux 0 Register" bitfld.long 0x00 24.--29. " MUX3 ,Input 4 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX2 ,Input 3 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX1 ,Input 2 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX0 ,Input 1 data select bits for 5x6 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX0_SET,Stage 2 Mux 0 Set Register" bitfld.long 0x04 24.--29. " MUX3 ,Input 4 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX2 ,Input 3 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX1 ,Input 2 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX0 ,Input 1 data select bits for 5x6 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX0_CLR,Stage 2 Mux 0 Clear Register" bitfld.long 0x08 24.--29. " MUX3 ,Input 4 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX2 ,Input 3 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX1 ,Input 2 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX0 ,Input 1 data select bits for 5x6 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX0_TOG,Stage 2 Mux 0 Toggle Register" bitfld.long 0x0C 24.--29. " MUX3 ,Input 4 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX2 ,Input 3 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX1 ,Input 2 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX0 ,Input 1 data select bits for 5x6 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1DF0++0x0F line.long 0x00 "STAGE2_MUX1,Stage 2 Mux 1 Register" bitfld.long 0x00 24.--29. " MUX7 ,Input 3 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX6 ,Input 2 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX5 ,Input 1 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX4 ,Input 5 data select bits for 5x6 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX1_SET,Stage 2 Mux 1 Set Register" bitfld.long 0x04 24.--29. " MUX7 ,Input 3 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX6 ,Input 2 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX5 ,Input 1 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX4 ,Input 5 data select bits for 5x6 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX1_CLR,Stage 2 Mux 1 Clear Register" bitfld.long 0x08 24.--29. " MUX7 ,Input 3 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX6 ,Input 2 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX5 ,Input 1 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX4 ,Input 5 data select bits for 5x6 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX1_TOG,Stage 2 Mux 1 Toggle Register" bitfld.long 0x0C 24.--29. " MUX7 ,Input 3 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX6 ,Input 2 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX5 ,Input 1 data select bits for 5x6 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX4 ,Input 5 data select bits for 5x6 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E00++0x0F line.long 0x00 "STAGE2_MUX2,Stage 2 Mux 2 Register" bitfld.long 0x00 24.--29. " MUX11 ,Input 2 data select bits for 5x6 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX10 ,Input 1 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX9 ,Input 5 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX8 ,Input 4 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX2_SET,Stage 2 Mux 2 Set Register" bitfld.long 0x04 24.--29. " MUX11 ,Input 2 data select bits for 5x6 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX10 ,Input 1 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX9 ,Input 5 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX8 ,Input 4 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX2_CLR,Stage 2 Mux 2 Clear Register" bitfld.long 0x08 24.--29. " MUX11 ,Input 2 data select bits for 5x6 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX10 ,Input 1 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX9 ,Input 5 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX8 ,Input 4 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX2_TOG,Stage 2 Mux 2 Toggle Register" bitfld.long 0x0C 24.--29. " MUX11 ,Input 2 data select bits for 5x6 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX10 ,Input 1 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX9 ,Input 5 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX8 ,Input 4 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E10++0x0F line.long 0x00 "STAGE2_MUX3,Stage 2 Mux 3 Register" bitfld.long 0x00 24.--29. " MUX15 ,Input 1 data select bits for 5x6 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX14 ,Input 5 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX13 ,Input 4 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX12 ,Input 3 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX3_SET,Stage 2 Mux 3 Set Register" bitfld.long 0x04 24.--29. " MUX15 ,Input 1 data select bits for 5x6 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX14 ,Input 5 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX13 ,Input 4 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX12 ,Input 3 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX3_CLR,Stage 2 Mux 3 Clear Register" bitfld.long 0x08 24.--29. " MUX15 ,Input 1 data select bits for 5x6 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX14 ,Input 5 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX13 ,Input 4 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX12 ,Input 3 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX3_TOG,Stage 2 Mux 3 Toggle Register" bitfld.long 0x0C 24.--29. " MUX15 ,Input 1 data select bits for 5x6 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX14 ,Input 5 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX13 ,Input 4 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX12 ,Input 3 data select bits for 5x6 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E20++0x0F line.long 0x00 "STAGE2_MUX4,Stage 2 Mux 4 Register" bitfld.long 0x00 24.--29. " MUX19 ,Input 5 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX18 ,Input 4 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX17 ,Input 3 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX16 ,Input 2 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX4_SET,Stage 2 Mux 4 Set Register" bitfld.long 0x04 24.--29. " MUX19 ,Input 5 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX18 ,Input 4 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX17 ,Input 3 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX16 ,Input 2 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX4_CLR,Stage 2 Mux 4 Clear Register" bitfld.long 0x08 24.--29. " MUX19 ,Input 5 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX18 ,Input 4 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX17 ,Input 3 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX16 ,Input 2 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX4_TOG,Stage 2 Mux 4 Toggle Register" bitfld.long 0x0C 24.--29. " MUX19 ,Input 5 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX18 ,Input 4 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX17 ,Input 3 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX16 ,Input 2 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E30++0x0F line.long 0x00 "STAGE2_MUX5,Stage 2 Mux 5 Register" bitfld.long 0x00 24.--29. " MUX23 ,Input 4 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX22 ,Input 3 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX21 ,Input 2 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX20 ,Input 1 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX5_SET,Stage 2 Mux 5 Set Register" bitfld.long 0x04 24.--29. " MUX23 ,Input 4 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX22 ,Input 3 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX21 ,Input 2 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX20 ,Input 1 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX5_CLR,Stage 2 Mux 5 Clear Register" bitfld.long 0x08 24.--29. " MUX23 ,Input 4 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX22 ,Input 3 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX21 ,Input 2 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX20 ,Input 1 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX5_TOG,Stage 2 Mux 5 Toggle Register" bitfld.long 0x0C 24.--29. " MUX23 ,Input 4 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX22 ,Input 3 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX21 ,Input 2 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX20 ,Input 1 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E40++0x0F line.long 0x00 "STAGE2_MUX6,Stage 2 Mux 6 Register" bitfld.long 0x00 24.--29. " MUX27 ,Input 3 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX26 ,Input 2 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX25 ,Input 1 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX24 ,Input 5 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX6_SET,Stage 2 Mux 6 Set Register" bitfld.long 0x04 24.--29. " MUX27 ,Input 3 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX26 ,Input 2 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX25 ,Input 1 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX24 ,Input 5 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX6_CLR,Stage 2 Mux 6 Clear Register" bitfld.long 0x08 24.--29. " MUX27 ,Input 3 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX26 ,Input 2 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX25 ,Input 1 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX24 ,Input 5 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX6_TOG,Stage 2 Mux 6 Toggle Register" bitfld.long 0x0C 24.--29. " MUX27 ,Input 3 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX26 ,Input 2 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX25 ,Input 1 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX24 ,Input 5 data select bits for 5x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E50++0x0F line.long 0x00 "STAGE2_MUX7,Stage 2 Mux 7 Register" bitfld.long 0x00 24.--29. " MUX31 ,Input 2 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX30 ,Input 1 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX29 ,Input 5 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX28 ,Input 4 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX7_SET,Stage 2 Mux 7 Set Register" bitfld.long 0x04 24.--29. " MUX31 ,Input 2 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX30 ,Input 1 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX29 ,Input 5 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX28 ,Input 4 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX7_CLR,Stage 2 Mux 7 Clear Register" bitfld.long 0x08 24.--29. " MUX31 ,Input 2 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX30 ,Input 1 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX29 ,Input 5 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX28 ,Input 4 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX7_TOG,Stage 2 Mux 7 Toggle Register" bitfld.long 0x0C 24.--29. " MUX31 ,Input 2 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX30 ,Input 1 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX29 ,Input 5 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX28 ,Input 4 data select bits for 5x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E60++0x0F line.long 0x00 "STAGE2_MUX8,Stage 2 Mux 8 Register" bitfld.long 0x00 24.--29. " MUX31 ,Input 1 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX30 ,Input 5 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX29 ,Input 4 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX28 ,Input 3 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX8_SET,Stage 2 Mux 8 Set Register" bitfld.long 0x04 24.--29. " MUX31 ,Input 1 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX30 ,Input 5 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX29 ,Input 4 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX28 ,Input 3 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX8_CLR,Stage 2 Mux 8 Clear Register" bitfld.long 0x08 24.--29. " MUX31 ,Input 1 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX30 ,Input 5 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX29 ,Input 4 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX28 ,Input 3 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX8_TOG,Stage 2 Mux 8 Toggle Register" bitfld.long 0x0C 24.--29. " MUX31 ,Input 1 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX30 ,Input 5 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX29 ,Input 4 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX28 ,Input 3 data select bits for 5x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E70++0x0F line.long 0x00 "STAGE2_MUX9,Stage 2 Mux 9 Register" bitfld.long 0x00 24.--29. " MUX39 ,Input 5 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX38 ,Input 4 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX37 ,Input 3 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX36 ,Input 2 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX9_SET,Stage 2 Mux 9 Set Register" bitfld.long 0x04 24.--29. " MUX39 ,Input 5 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX38 ,Input 4 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX37 ,Input 3 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX36 ,Input 2 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX9_CLR,Stage 2 Mux 9 Clear Register" bitfld.long 0x08 24.--29. " MUX39 ,Input 5 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX38 ,Input 4 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX37 ,Input 3 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX36 ,Input 2 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX9_TOG,Stage 2 Mux 9 Toggle Register" bitfld.long 0x0C 24.--29. " MUX39 ,Input 5 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX38 ,Input 4 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX37 ,Input 3 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX36 ,Input 2 data select bits for 5x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E80++0x0F line.long 0x00 "STAGE2_MUX10,Stage 2 Mux 10 Register" bitfld.long 0x00 24.--29. " MUX43 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX42 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX41 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX40 ,Input 2 data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX10_SET,Stage 2 Mux 10 Set Register" bitfld.long 0x04 24.--29. " MUX43 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX42 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX41 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX40 ,Input 2 data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX10_CLR,Stage 2 Mux 10 Clear Register" bitfld.long 0x08 24.--29. " MUX43 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX42 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX41 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX40 ,Input 2 data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX10_TOG,Stage 2 Mux 10 Toggle Register" bitfld.long 0x0C 24.--29. " MUX43 ,Input data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX42 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX41 ,Input data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX40 ,Input 2 data select bits for ALU 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E90++0x0F line.long 0x00 "STAGE2_MUX11,Stage 2 Mux 11 Register" bitfld.long 0x00 24.--29. " MUX47 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX46 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX45 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX44 ,Input 2 data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX11_SET,Stage 2 Mux 11 Set Register" bitfld.long 0x04 24.--29. " MUX47 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX46 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX45 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX44 ,Input 2 data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX11_CLR,Stage 2 Mux 11 Clear Register" bitfld.long 0x08 24.--29. " MUX47 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX46 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX45 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX44 ,Input 2 data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX11_TOG,Stage 2 Mux 11 Toggle Register" bitfld.long 0x0C 24.--29. " MUX47 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX46 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX45 ,Input data select bits for Comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX44 ,Input 2 data select bits for Comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1EA0++0x0F line.long 0x00 "STAGE2_MUX12,Stage 2 Mux 12 Register" bitfld.long 0x00 0.--5. " MUX48 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE2_MUX12_SET,Stage 2 Mux 12 Set Register" bitfld.long 0x04 0.--5. " MUX48 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE2_MUX12_CLR,Stage 2 Mux 12 Clear Register" bitfld.long 0x08 0.--5. " MUX48 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE2_MUX12_TOG,Stage 2 Mux 12 Toggle Register" bitfld.long 0x0C 0.--5. " MUX48 ,Input data select bits for Comparator 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline group.long 0x1EB0++0x0F line.long 0x00 "STAGE3_MUX0,Stage 3 Mux 0 Register" bitfld.long 0x00 24.--29. " MUX3 ,Input 4 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX2 ,Input 3 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX1 ,Input 2 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX0 ,Input 1 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX0_SET,Stage 3 Mux 0 Set Register" bitfld.long 0x04 24.--29. " MUX3 ,Input 4 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX2 ,Input 3 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX1 ,Input 2 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX0 ,Input 1 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX0_CLR,Stage 3 Mux 0 Clear Register" bitfld.long 0x08 24.--29. " MUX3 ,Input 4 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX2 ,Input 3 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX1 ,Input 2 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX0 ,Input 1 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX0_TOG,Stage 3 Mux 0 Toggle Register" bitfld.long 0x0C 24.--29. " MUX3 ,Input 4 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX2 ,Input 3 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX1 ,Input 2 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX0 ,Input 1 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1EC0++0x0F line.long 0x00 "STAGE3_MUX1,Stage 3 Mux 1 Register" bitfld.long 0x00 24.--29. " MUX7 ,Input 8 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX6 ,Input 7 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX5 ,Input 6 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX4 ,Input 5 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX1_SET,Stage 3 Mux 1 Set Register" bitfld.long 0x04 24.--29. " MUX7 ,Input 8 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX6 ,Input 7 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX5 ,Input 6 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX4 ,Input 5 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX1_CLR,Stage 3 Mux 1 Clear Register" bitfld.long 0x08 24.--29. " MUX7 ,Input 8 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX6 ,Input 7 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX5 ,Input 6 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX4 ,Input 5 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX1_TOG,Stage 3 Mux 1 Toggle Register" bitfld.long 0x0C 24.--29. " MUX7 ,Input 8 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX6 ,Input 7 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX5 ,Input 6 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX4 ,Input 5 flag select bits for F8x1 LUT 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1ED0++0x0F line.long 0x00 "STAGE3_MUX2,Stage 3 Mux 2 Register" bitfld.long 0x00 24.--29. " MUX11 ,Input 4 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX10 ,Input 3 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX9 ,Input 2 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX8 ,Input 1 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX2_SET,Stage 3 Mux 2 Set Register" bitfld.long 0x04 24.--29. " MUX11 ,Input 4 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX10 ,Input 3 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX9 ,Input 2 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX8 ,Input 1 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX2_CLR,Stage 3 Mux 2 Clear Register" bitfld.long 0x08 24.--29. " MUX11 ,Input 4 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX10 ,Input 3 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX9 ,Input 2 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX8 ,Input 1 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX2_TOG,Stage 3 Mux 2 Toggle Register" bitfld.long 0x0C 24.--29. " MUX11 ,Input 4 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX10 ,Input 3 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX9 ,Input 2 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX8 ,Input 1 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1EE0++0x0F line.long 0x00 "STAGE3_MUX3,Stage 3 Mux 3 Register" bitfld.long 0x00 24.--29. " MUX15 ,Input 8 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX14 ,Input 7 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX13 ,Input 6 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX12 ,Input 5 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX3_SET,Stage 3 Mux 3 Set Register" bitfld.long 0x04 24.--29. " MUX15 ,Input 8 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX14 ,Input 7 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX13 ,Input 6 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX12 ,Input 5 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX3_CLR,Stage 3 Mux 3 Clear Register" bitfld.long 0x08 24.--29. " MUX15 ,Input 8 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX14 ,Input 7 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX13 ,Input 6 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX12 ,Input 5 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX3_TOG,Stage 3 Mux 3 Toggle Register" bitfld.long 0x0C 24.--29. " MUX15 ,Input 8 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX14 ,Input 7 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX13 ,Input 6 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX12 ,Input 5 flag select bits for F8x1 LUT 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1EF0++0x0F line.long 0x00 "STAGE3_MUX4,Stage 3 Mux 4 Register" bitfld.long 0x00 24.--29. " MUX19 ,Input 4 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX18 ,Input 3 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX17 ,Input 2 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX16 ,Input 1 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX4_SET,Stage 3 Mux 4 Set Register" bitfld.long 0x04 24.--29. " MUX19 ,Input 4 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX18 ,Input 3 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX17 ,Input 2 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX16 ,Input 1 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX4_CLR,Stage 3 Mux 4 Clear Register" bitfld.long 0x08 24.--29. " MUX19 ,Input 4 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX18 ,Input 3 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX17 ,Input 2 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX16 ,Input 1 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX4_TOG,Stage 3 Mux 4 Toggle Register" bitfld.long 0x0C 24.--29. " MUX19 ,Input 4 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX18 ,Input 3 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX17 ,Input 2 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX16 ,Input 1 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F00++0x0F line.long 0x00 "STAGE3_MUX5,Stage 3 Mux 5 Register" bitfld.long 0x00 24.--29. " MUX23 ,Input 8 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX22 ,Input 7 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX21 ,Input 6 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX20 ,Input 5 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX5_SET,Stage 3 Mux 5 Set Register" bitfld.long 0x04 24.--29. " MUX23 ,Input 8 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX22 ,Input 7 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX21 ,Input 6 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX20 ,Input 5 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX5_CLR,Stage 3 Mux 5 Clear Register" bitfld.long 0x08 24.--29. " MUX23 ,Input 8 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX22 ,Input 7 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX21 ,Input 6 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX20 ,Input 5 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX5_TOG,Stage 3 Mux 5 Toggle Register" bitfld.long 0x0C 24.--29. " MUX23 ,Input 8 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX22 ,Input 7 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX21 ,Input 6 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX20 ,Input 5 flag select bits for F8x1 LUT 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F10++0x0F line.long 0x00 "STAGE3_MUX6,Stage 3 Mux 6 Register" bitfld.long 0x00 24.--29. " MUX27 ,Input 4 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX26 ,Input 3 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX25 ,Input 2 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX24 ,Input 1 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX6_SET,Stage 3 Mux 6 Set Register" bitfld.long 0x04 24.--29. " MUX27 ,Input 4 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX26 ,Input 3 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX25 ,Input 2 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX24 ,Input 1 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX6_CLR,Stage 3 Mux 6 Clear Register" bitfld.long 0x08 24.--29. " MUX27 ,Input 4 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX26 ,Input 3 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX25 ,Input 2 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX24 ,Input 1 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX6_TOG,Stage 3 Mux 6 Toggle Register" bitfld.long 0x0C 24.--29. " MUX27 ,Input 4 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX26 ,Input 3 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX25 ,Input 2 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX24 ,Input 1 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F20++0x0F line.long 0x00 "STAGE3_MUX7,Stage 3 Mux 7 Register" bitfld.long 0x00 24.--29. " MUX31 ,Input 8 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX30 ,Input 7 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX29 ,Input 6 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX28 ,Input 5 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX7_SET,Stage 3 Mux 7 Set Register" bitfld.long 0x04 24.--29. " MUX31 ,Input 8 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX30 ,Input 7 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX29 ,Input 6 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX28 ,Input 5 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX7_CLR,Stage 3 Mux 7 Clear Register" bitfld.long 0x08 24.--29. " MUX31 ,Input 8 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX30 ,Input 7 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX29 ,Input 6 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX28 ,Input 5 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX7_TOG,Stage 3 Mux 7 Toggle Register" bitfld.long 0x0C 24.--29. " MUX31 ,Input 8 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX30 ,Input 7 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX29 ,Input 6 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX28 ,Input 5 flag select bits for F8x1 LUT 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F30++0x0F line.long 0x00 "STAGE3_MUX8,Stage 3 Mux 8 Register" bitfld.long 0x00 24.--29. " MUX31 ,Input data select bits for DMUX 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX30 ,Input data select bits for DMUX 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX29 ,Input data select bits for DMUX 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX28 ,Input data select bits for DMUX 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX8_SET,Stage 3 Mux 8 Set Register" bitfld.long 0x04 24.--29. " MUX31 ,Input data select bits for DMUX 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX30 ,Input data select bits for DMUX 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX29 ,Input data select bits for DMUX 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX28 ,Input data select bits for DMUX 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX8_CLR,Stage 3 Mux 8 Clear Register" bitfld.long 0x08 24.--29. " MUX31 ,Input data select bits for DMUX 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX30 ,Input data select bits for DMUX 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX29 ,Input data select bits for DMUX 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX28 ,Input data select bits for DMUX 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX8_TOG,Stage 3 Mux 8 Toggle Register" bitfld.long 0x0C 24.--29. " MUX31 ,Input data select bits for DMUX 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX30 ,Input data select bits for DMUX 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX29 ,Input data select bits for DMUX 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX28 ,Input data select bits for DMUX 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F40++0x0F line.long 0x00 "STAGE3_MUX9,Stage 3 Mux 9 Register" bitfld.long 0x00 24.--29. " MUX39 ,Input data select bits for DMUX 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX38 ,Input data select bits for DMUX 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX37 ,Input data select bits for DMUX 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX36 ,Input data select bits for DMUX 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX9_SET,Stage 3 Mux 9 Set Register" bitfld.long 0x04 24.--29. " MUX39 ,Input data select bits for DMUX 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX38 ,Input data select bits for DMUX 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX37 ,Input data select bits for DMUX 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX36 ,Input data select bits for DMUX 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX9_CLR,Stage 3 Mux 9 Clear Register" bitfld.long 0x08 24.--29. " MUX39 ,Input data select bits for DMUX 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX38 ,Input data select bits for DMUX 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX37 ,Input data select bits for DMUX 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX36 ,Input data select bits for DMUX 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX9_TOG,Stage 3 Mux 9 Toggle Register" bitfld.long 0x0C 24.--29. " MUX39 ,Input data select bits for DMUX 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX38 ,Input data select bits for DMUX 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX37 ,Input data select bits for DMUX 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX36 ,Input data select bits for DMUX 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1F50++0x0F line.long 0x00 "STAGE3_MUX10,Stage 3 Mux 10 Register" bitfld.long 0x00 24.--29. " MUX43 ,Input data select bits for FMUX 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " MUX42 ,Input data select bits for FMUX 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " MUX41 ,Input data select bits for FMUX 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " MUX40 ,Input data select bits for FMUX 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "STAGE3_MUX10_SET,Stage 3 Mux 10 Set Register" bitfld.long 0x04 24.--29. " MUX43 ,Input data select bits for FMUX 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " MUX42 ,Input data select bits for FMUX 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 8.--13. " MUX41 ,Input data select bits for FMUX 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " MUX40 ,Input data select bits for FMUX 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "STAGE3_MUX10_CLR,Stage 3 Mux 10 Clear Register" bitfld.long 0x08 24.--29. " MUX43 ,Input data select bits for FMUX 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " MUX42 ,Input data select bits for FMUX 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " MUX41 ,Input data select bits for FMUX 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " MUX40 ,Input data select bits for FMUX 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "STAGE3_MUX10_TOG,Stage 3 Mux 10 Toggle Register" bitfld.long 0x0C 24.--29. " MUX43 ,Input data select bits for FMUX 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " MUX42 ,Input data select bits for FMUX 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 8.--13. " MUX41 ,Input data select bits for FMUX 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " MUX40 ,Input data select bits for FMUX 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 11. tree "STAGE1 Registers" tree "5X8" group.long 0x1F60++0x03 line.long 0x00 "OUT0_0 ,5x8 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT3 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT2 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT1 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT0 ,LUT output value 0" group.long 0x1F70++0x03 line.long 0x00 "OUT0_1 ,5x8 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT7 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT6 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT5 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT4 ,LUT output value 0" group.long 0x1F80++0x03 line.long 0x00 "OUT0_2 ,5x8 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT11 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT10 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT9 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT8 ,LUT output value 0" group.long 0x1F90++0x03 line.long 0x00 "OUT0_3 ,5x8 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT15 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT14 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT13 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT12 ,LUT output value 0" group.long 0x1FA0++0x03 line.long 0x00 "OUT0_4 ,5x8 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT19 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT18 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT17 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT16 ,LUT output value 0" group.long 0x1FB0++0x03 line.long 0x00 "OUT0_5 ,5x8 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT23 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT22 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT21 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT20 ,LUT output value 0" group.long 0x1FC0++0x03 line.long 0x00 "OUT0_6 ,5x8 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT27 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT26 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT25 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT24 ,LUT output value 0" group.long 0x1FD0++0x03 line.long 0x00 "OUT0_7 ,5x8 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT31 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT30 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT29 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT28 ,LUT output value 0" group.long 0x1FE0++0x03 line.long 0x00 "OUT1_0 ,5x8 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT3 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT2 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT1 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT0 ,LUT output value 0" group.long 0x1FF0++0x03 line.long 0x00 "OUT1_1 ,5x8 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT7 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT6 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT5 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT4 ,LUT output value 0" group.long 0x2000++0x03 line.long 0x00 "OUT1_2 ,5x8 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT11 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT10 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT9 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT8 ,LUT output value 0" group.long 0x2010++0x03 line.long 0x00 "OUT1_3 ,5x8 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT15 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT14 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT13 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT12 ,LUT output value 0" group.long 0x2020++0x03 line.long 0x00 "OUT1_4 ,5x8 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT19 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT18 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT17 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT16 ,LUT output value 0" group.long 0x2030++0x03 line.long 0x00 "OUT1_5 ,5x8 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT23 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT22 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT21 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT20 ,LUT output value 0" group.long 0x2040++0x03 line.long 0x00 "OUT1_6 ,5x8 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT27 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT26 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT25 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT24 ,LUT output value 0" group.long 0x2050++0x03 line.long 0x00 "OUT1_7 ,5x8 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--31. 1. " LUTOUT31 ,LUT output value 3" hexmask.long.byte 0x00 16.--23. 1. " LUTOUT30 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--15. 1. " LUTOUT29 ,LUT output value 1" hexmask.long.byte 0x00 0.--7. 1. " LUTOUT28 ,LUT output value 0" group.long 0x2060++0x03 line.long 0x00 "MASK_0,Corresponding Flag Input Bits Mask Register" bitfld.long 0x00 12. " MASK1_[5] ,Input 5 mask 1" "Not masked,Masked" bitfld.long 0x00 11. " [4] ,Input 4 mask 1" "Not masked,Masked" newline bitfld.long 0x00 10. " [3] ,Input 3 mask 1" "Not masked,Masked" bitfld.long 0x00 9. " [2] ,Input 2 mask 1" "Not masked,Masked" newline bitfld.long 0x00 8. " [1] ,Input 1 mask 1" "Not masked,Masked" newline bitfld.long 0x00 4. " MASK0_[5] ,Input 5 mask 0" "Not masked,Masked" bitfld.long 0x00 3. " [4] ,Input 4 mask 0" "Not masked,Masked" newline bitfld.long 0x00 2. " [3] ,Input 3 mask 0" "Not masked,Masked" bitfld.long 0x00 1. " [2] ,Input 2 mask 0" "Not masked,Masked" newline bitfld.long 0x00 0. " [1] ,Input 1 mask 0" "Not masked,Masked" newline tree.end group.long 0x2070++0x03 line.long 0x00 "5X1_OUT0,5x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2080++0x03 line.long 0x00 "5X1_MASKS,Corresponding Flag Input Bits Mask Register" bitfld.long 0x00 4. " MASK0[5] ,Input 5 mask 0" "Not masked,Masked" bitfld.long 0x00 3. " [4] ,Input 4 mask 0" "Not masked,Masked" newline bitfld.long 0x00 2. " [3] ,Input 3 mask 0" "Not masked,Masked" bitfld.long 0x00 1. " [2] ,Input 2 mask 0" "Not masked,Masked" newline bitfld.long 0x00 0. " [1] ,Input 1 mask 0" "Not masked,Masked" tree "8X1 Registers" group.long 0x2090++0x03 line.long 0x00 "OUT0_0 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x20A0++0x03 line.long 0x00 "OUT0_1 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x20B0++0x03 line.long 0x00 "OUT0_2 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x20C0++0x03 line.long 0x00 "OUT0_3 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x20D0++0x03 line.long 0x00 "OUT0_4 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x20E0++0x03 line.long 0x00 "OUT0_5 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x20F0++0x03 line.long 0x00 "OUT0_6 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2100++0x03 line.long 0x00 "OUT0_7 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2110++0x03 line.long 0x00 "OUT1_0 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2120++0x03 line.long 0x00 "OUT1_1 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2130++0x03 line.long 0x00 "OUT1_2 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2140++0x03 line.long 0x00 "OUT1_3 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2150++0x03 line.long 0x00 "OUT1_4 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2160++0x03 line.long 0x00 "OUT1_5 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2170++0x03 line.long 0x00 "OUT1_6 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2180++0x03 line.long 0x00 "OUT1_7 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2190+0x100)++0x03 line.long 0x00 "OUT2_0 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x21A0+0x100)++0x03 line.long 0x00 "OUT2_1 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x21B0+0x100)++0x03 line.long 0x00 "OUT2_2 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x21C0+0x100)++0x03 line.long 0x00 "OUT2_3 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x21D0+0x100)++0x03 line.long 0x00 "OUT2_4 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x21E0+0x100)++0x03 line.long 0x00 "OUT2_5 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x21F0+0x100)++0x03 line.long 0x00 "OUT2_6 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2200+0x100)++0x03 line.long 0x00 "OUT2_7 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2210+0x180)++0x03 line.long 0x00 "OUT3_0 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2220+0x180)++0x03 line.long 0x00 "OUT3_1 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2230+0x180)++0x03 line.long 0x00 "OUT3_2 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2240+0x180)++0x03 line.long 0x00 "OUT3_3 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2250+0x180)++0x03 line.long 0x00 "OUT3_4 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2260+0x180)++0x03 line.long 0x00 "OUT3_5 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2270+0x180)++0x03 line.long 0x00 "OUT3_6 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2280+0x180)++0x03 line.long 0x00 "OUT3_7 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2290+0x200)++0x03 line.long 0x00 "OUT4_0 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x22A0+0x200)++0x03 line.long 0x00 "OUT4_1 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x22B0+0x200)++0x03 line.long 0x00 "OUT4_2 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x22C0+0x200)++0x03 line.long 0x00 "OUT4_3 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x22D0+0x200)++0x03 line.long 0x00 "OUT4_4 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x22E0+0x200)++0x03 line.long 0x00 "OUT4_5 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x22F0+0x200)++0x03 line.long 0x00 "OUT4_6 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long (0x2300+0x200)++0x03 line.long 0x00 "OUT4_7 ,8x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" tree.end tree.end width 10. tree "STAGE2 Registers" tree "5X6 Registers" group.long 0x2310++0x03 line.long 0x00 "OUT0_0 ,5x6 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT3 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT2 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT1 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT0 ,LUT output value 0" group.long 0x2320++0x03 line.long 0x00 "OUT0_1 ,5x6 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT7 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT6 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT5 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT4 ,LUT output value 0" group.long 0x2330++0x03 line.long 0x00 "OUT0_2 ,5x6 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT11 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT10 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT9 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT8 ,LUT output value 0" group.long 0x2340++0x03 line.long 0x00 "OUT0_3 ,5x6 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT15 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT14 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT13 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT12 ,LUT output value 0" group.long 0x2350++0x03 line.long 0x00 "OUT0_4 ,5x6 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT19 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT18 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT17 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT16 ,LUT output value 0" group.long 0x2360++0x03 line.long 0x00 "OUT0_5 ,5x6 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT23 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT22 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT21 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT20 ,LUT output value 0" group.long 0x2370++0x03 line.long 0x00 "OUT0_6 ,5x6 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT27 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT26 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT25 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT24 ,LUT output value 0" group.long 0x2380++0x03 line.long 0x00 "OUT0_7 ,5x6 LUT Output 0 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT31 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT30 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT29 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT28 ,LUT output value 0" group.long 0x2390++0x03 line.long 0x00 "OUT1_0 ,5x6 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT3 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT2 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT1 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT0 ,LUT output value 0" group.long 0x23A0++0x03 line.long 0x00 "OUT1_1 ,5x6 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT7 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT6 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT5 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT4 ,LUT output value 0" group.long 0x23B0++0x03 line.long 0x00 "OUT1_2 ,5x6 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT11 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT10 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT9 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT8 ,LUT output value 0" group.long 0x23C0++0x03 line.long 0x00 "OUT1_3 ,5x6 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT15 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT14 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT13 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT12 ,LUT output value 0" group.long 0x23D0++0x03 line.long 0x00 "OUT1_4 ,5x6 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT19 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT18 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT17 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT16 ,LUT output value 0" group.long 0x23E0++0x03 line.long 0x00 "OUT1_5 ,5x6 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT23 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT22 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT21 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT20 ,LUT output value 0" group.long 0x23F0++0x03 line.long 0x00 "OUT1_6 ,5x6 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT27 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT26 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT25 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT24 ,LUT output value 0" group.long 0x2400++0x03 line.long 0x00 "OUT1_7 ,5x6 LUT Output 1 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT31 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT30 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT29 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT28 ,LUT output value 0" group.long 0x2410++0x03 line.long 0x00 "OUT2_0 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT3 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT2 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT1 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT0 ,LUT output value 0" group.long 0x2420++0x03 line.long 0x00 "OUT2_1 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT7 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT6 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT5 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT4 ,LUT output value 0" group.long 0x2430++0x03 line.long 0x00 "OUT2_2 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT11 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT10 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT9 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT8 ,LUT output value 0" group.long 0x2440++0x03 line.long 0x00 "OUT2_3 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT15 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT14 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT13 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT12 ,LUT output value 0" group.long 0x2450++0x03 line.long 0x00 "OUT2_4 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT19 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT18 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT17 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT16 ,LUT output value 0" group.long 0x2460++0x03 line.long 0x00 "OUT2_5 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT23 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT22 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT21 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT20 ,LUT output value 0" group.long 0x2470++0x03 line.long 0x00 "OUT2_6 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT27 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT26 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT25 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT24 ,LUT output value 0" group.long 0x2480++0x03 line.long 0x00 "OUT2_7 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT31 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT30 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT29 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT28 ,LUT output value 0" group.long 0x2490++0x03 line.long 0x00 "OUT2_0 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT3 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT2 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT1 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT0 ,LUT output value 0" group.long 0x24A0++0x03 line.long 0x00 "OUT2_1 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT7 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT6 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT5 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT4 ,LUT output value 0" group.long 0x24B0++0x03 line.long 0x00 "OUT2_2 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT11 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT10 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT9 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT8 ,LUT output value 0" group.long 0x24C0++0x03 line.long 0x00 "OUT2_3 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT15 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT14 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT13 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT12 ,LUT output value 0" group.long 0x24D0++0x03 line.long 0x00 "OUT2_4 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT19 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT18 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT17 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT16 ,LUT output value 0" group.long 0x24E0++0x03 line.long 0x00 "OUT2_5 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT23 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT22 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT21 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT20 ,LUT output value 0" group.long 0x24F0++0x03 line.long 0x00 "OUT2_6 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT27 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT26 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT25 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT24 ,LUT output value 0" group.long 0x2500++0x03 line.long 0x00 "OUT2_7 ,5x6 LUT Output 2 Value For Input Value N" hexmask.long.byte 0x00 24.--29. 1. " LUTOUT31 ,LUT output value 3" hexmask.long.byte 0x00 16.--21. 1. " LUTOUT30 ,LUT output value 2" newline hexmask.long.byte 0x00 8.--13. 1. " LUTOUT29 ,LUT output value 1" hexmask.long.byte 0x00 0.--5. 1. " LUTOUT28 ,LUT output value 0" group.long 0x2520++0x03 line.long 0x00 "MASKS_0,Corresponding Flag Input Masks Bits Register" bitfld.long 0x00 28. " MASK3[5] ,Input 5 mask 3" "Not masked,Masked" bitfld.long 0x00 27. " [4] ,Input 4 mask 3" "Not masked,Masked" newline bitfld.long 0x00 26. " [3] ,Input 3 mask 3" "Not masked,Masked" bitfld.long 0x00 25. " [2] ,Input 2 mask 3" "Not masked,Masked" newline bitfld.long 0x00 24. " [1] ,Input 1 mask 3" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK2[5] ,Input 5 mask 2" "Not masked,Masked" bitfld.long 0x00 19. " [4] ,Input 4 mask 2" "Not masked,Masked" newline bitfld.long 0x00 18. " [3] ,Input 3 mask 2" "Not masked,Masked" bitfld.long 0x00 17. " [2] ,Input 2 mask 2" "Not masked,Masked" newline bitfld.long 0x00 16. " [1] ,Input 1 mask 2" "Not masked,Masked" newline bitfld.long 0x00 12. " MASK1[5] ,Input 5 mask 1" "Not masked,Masked" bitfld.long 0x00 11. " [4] ,Input 4 mask 1" "Not masked,Masked" newline bitfld.long 0x00 10. " [3] ,Input 3 mask 1" "Not masked,Masked" bitfld.long 0x00 9. " [2] ,Input 2 mask 1" "Not masked,Masked" newline bitfld.long 0x00 8. " [1] ,Input 1 mask 1" "Not masked,Masked" newline bitfld.long 0x00 4. " MASK0[5] ,Input 5 mask 0" "Not masked,Masked" bitfld.long 0x00 3. " [4] ,Input 4 mask 0" "Not masked,Masked" newline bitfld.long 0x00 2. " [3] ,Input 3 mask 0" "Not masked,Masked" bitfld.long 0x00 1. " [2] ,Input 2 mask 0" "Not masked,Masked" newline bitfld.long 0x00 0. " [1] ,Input 1 mask 0" "Not masked,Masked" group.long 0x2530++0x03 line.long 0x00 "ADDR_0,MUX Position In The Mux Array" hexmask.long.byte 0x00 24.--29. 1. " MUXADDDR3 ,Reflects the address of the next stage element" hexmask.long.byte 0x00 16.--21. 1. " MUXADDDR2 ,Reflects the address of the next stage element" newline hexmask.long.byte 0x00 8.--13. 1. " MUXADDDR1 ,Reflects the address of the next stage element" hexmask.long.byte 0x00 0.--5. 1. " MUXADDDR0 ,Reflects the address of the next stage element" newline tree.end group.long 0x2540++0x03 line.long 0x00 "5X1_OUT0 ,5x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2550++0x03 line.long 0x00 "5X1_OUT1 ,5x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2560++0x03 line.long 0x00 "5X1_OUT2 ,5x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2570++0x03 line.long 0x00 "5X1_OUT3 ,5x1 LUT Output Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2580++0x03 line.long 0x00 "MASKS,Corresponding Flag Input Bits Mask Register" bitfld.long 0x00 28. " MASK3_[5] ,Input 5 mask 3" "Not masked,Masked" bitfld.long 0x00 27. " [4] ,Input 4 mask 3" "Not masked,Masked" newline bitfld.long 0x00 26. " [3] ,Input 3 mask 3" "Not masked,Masked" bitfld.long 0x00 25. " [2] ,Input 2 mask 3" "Not masked,Masked" newline bitfld.long 0x00 24. " [1] ,Input 1 mask 3" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK2_[5] ,Input 5 mask 2" "Not masked,Masked" bitfld.long 0x00 19. " [4] ,Input 4 mask 2" "Not masked,Masked" newline bitfld.long 0x00 18. " [3] ,Input 3 mask 2" "Not masked,Masked" bitfld.long 0x00 17. " [2] ,Input 2 mask 2" "Not masked,Masked" newline bitfld.long 0x00 16. " [1] ,Input 1 mask 2" "Not masked,Masked" newline bitfld.long 0x00 12. " MASK1_[5] ,Input 5 mask 1" "Not masked,Masked" bitfld.long 0x00 11. " [4] ,Input 4 mask 1" "Not masked,Masked" newline bitfld.long 0x00 10. " [3] ,Input 3 mask 1" "Not masked,Masked" bitfld.long 0x00 9. " [2] ,Input 2 mask 1" "Not masked,Masked" newline bitfld.long 0x00 8. " [1] ,Input 1 mask 1" "Not masked,Masked" newline bitfld.long 0x00 4. " MASK0_[5] ,Input 5 mask 0" "Not masked,Masked" bitfld.long 0x00 3. " [4] ,Input 4 mask 0" "Not masked,Masked" newline bitfld.long 0x00 2. " [3] ,Input 3 mask 0" "Not masked,Masked" bitfld.long 0x00 1. " [2] ,Input 2 mask 0" "Not masked,Masked" newline bitfld.long 0x00 0. " [1] ,Input 1 mask 0" "Not masked,Masked" tree.end tree "STAGE3 F8x1 Registers" group.long 0x2590++0x03 line.long 0x00 "OUT0_0 ,5x1 LUT Output 0 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x25A0++0x03 line.long 0x00 "OUT0_1 ,5x1 LUT Output 0 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x25B0++0x03 line.long 0x00 "OUT0_2 ,5x1 LUT Output 0 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x25C0++0x03 line.long 0x00 "OUT0_3 ,5x1 LUT Output 0 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2610++0x03 line.long 0x00 "OUT1_0 ,5x1 LUT Output 1 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2620++0x03 line.long 0x00 "OUT1_1 ,5x1 LUT Output 1 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2630++0x03 line.long 0x00 "OUT1_2 ,5x1 LUT Output 1 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2640++0x03 line.long 0x00 "OUT1_3 ,5x1 LUT Output 1 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2690++0x03 line.long 0x00 "OUT2_0 ,5x1 LUT Output 2 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x26A0++0x03 line.long 0x00 "OUT2_1 ,5x1 LUT Output 2 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x26B0++0x03 line.long 0x00 "OUT2_2 ,5x1 LUT Output 2 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x26C0++0x03 line.long 0x00 "OUT2_3 ,5x1 LUT Output 2 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2710++0x03 line.long 0x00 "OUT3_0 ,5x1 LUT Output 3 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2720++0x03 line.long 0x00 "OUT3_1 ,5x1 LUT Output 3 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2730++0x03 line.long 0x00 "OUT3_2 ,5x1 LUT Output 3 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2740++0x03 line.long 0x00 "OUT3_3 ,5x1 LUT Output 3 Value For Input Value N" bitfld.long 0x00 31. " LUTOUT31 ,LUT out value 31" "0,1" bitfld.long 0x00 30. " [30] ,LUT out value 30" "0,1" bitfld.long 0x00 29. " [29] ,LUT out value 29" "0,1" newline bitfld.long 0x00 28. " [28] ,LUT out value 28" "0,1" bitfld.long 0x00 27. " [27] ,LUT out value 27" "0,1" bitfld.long 0x00 26. " [26] ,LUT out value 26" "0,1" newline bitfld.long 0x00 25. " [25] ,LUT out value 25" "0,1" bitfld.long 0x00 24. " [24] ,LUT out value 24" "0,1" bitfld.long 0x00 23. " [23] ,LUT out value 23" "0,1" newline bitfld.long 0x00 22. " [22] ,LUT out value 22" "0,1" bitfld.long 0x00 21. " [21] ,LUT out value 21" "0,1" bitfld.long 0x00 20. " [20] ,LUT out value 20" "0,1" newline bitfld.long 0x00 19. " [19] ,LUT out value 19" "0,1" bitfld.long 0x00 18. " [18] ,LUT out value 18" "0,1" bitfld.long 0x00 17. " [17] ,LUT out value 17" "0,1" newline bitfld.long 0x00 16. " [16] ,LUT out value 16" "0,1" bitfld.long 0x00 15. " [15] ,LUT out value 15" "0,1" bitfld.long 0x00 14. " [14] ,LUT out value 14" "0,1" newline bitfld.long 0x00 13. " [13] ,LUT out value 13" "0,1" bitfld.long 0x00 12. " [12] ,LUT out value 12" "0,1" bitfld.long 0x00 11. " [11] ,LUT out value 11" "0,1" newline bitfld.long 0x00 10. " [10] ,LUT out value 10" "0,1" bitfld.long 0x00 9. " [9] ,LUT out value 9" "0,1" bitfld.long 0x00 8. " [8] ,LUT out value 8" "0,1" newline bitfld.long 0x00 7. " [7] ,LUT out value 7" "0,1" bitfld.long 0x00 6. " [6] ,LUT out value 6" "0,1" bitfld.long 0x00 5. " [5] ,LUT out value 5" "0,1" newline bitfld.long 0x00 4. " [4] ,LUT out value 4" "0,1" bitfld.long 0x00 3. " [3] ,LUT out value 3" "0,1" bitfld.long 0x00 2. " [2] ,LUT out value 2" "0,1" newline bitfld.long 0x00 1. " [1] ,LUT out value 1" "0,1" bitfld.long 0x00 0. " [0] ,LUT out value 0" "0,1" group.long 0x2790++0x03 line.long 0x00 "MASKS_0,Corresponding Flag Input Masks Bits Register" bitfld.long 0x00 31. " MASK3[8] ,Input 8 mask 3" "Not masked,Masked" bitfld.long 0x00 30. " [7] ,Input 7 mask 3" "Not masked,Masked" newline bitfld.long 0x00 29. " [6] ,Input 6 mask 3" "Not masked,Masked" bitfld.long 0x00 28. " [5] ,Input 5 mask 3" "Not masked,Masked" newline bitfld.long 0x00 27. " [4] ,Input 4 mask 3" "Not masked,Masked" bitfld.long 0x00 26. " [3] ,Input 3 mask 3" "Not masked,Masked" newline bitfld.long 0x00 25. " [2] ,Input 2 mask 3" "Not masked,Masked" bitfld.long 0x00 24. " [1] ,Input 1 mask 3" "Not masked,Masked" newline bitfld.long 0x00 23. " MASK2[8] ,Input 8 mask 2" "Not masked,Masked" bitfld.long 0x00 22. " [7] ,Input 7 mask 2" "Not masked,Masked" newline bitfld.long 0x00 21. " [6] ,Input 6 mask 2" "Not masked,Masked" bitfld.long 0x00 20. " [5] ,Input 5 mask 2" "Not masked,Masked" newline bitfld.long 0x00 19. " [4] ,Input 4 mask 2" "Not masked,Masked" bitfld.long 0x00 18. " [3] ,Input 3 mask 2" "Not masked,Masked" newline bitfld.long 0x00 17. " [2] ,Input 2 mask 2" "Not masked,Masked" bitfld.long 0x00 16. " [1] ,Input 1 mask 2" "Not masked,Masked" newline bitfld.long 0x00 15. " MASK1[8] ,Input 8 mask 1" "Not masked,Masked" bitfld.long 0x00 14. " [7] ,Input 7 mask 1" "Not masked,Masked" newline bitfld.long 0x00 13. " [6] ,Input 6 mask 1" "Not masked,Masked" bitfld.long 0x00 12. " [5] ,Input 5 mask 1" "Not masked,Masked" newline bitfld.long 0x00 11. " [4] ,Input 4 mask 1" "Not masked,Masked" bitfld.long 0x00 10. " [3] ,Input 3 mask 1" "Not masked,Masked" newline bitfld.long 0x00 9. " [2] ,Input 2 mask 1" "Not masked,Masked" bitfld.long 0x00 8. " [1] ,Input 1 mask 1" "Not masked,Masked" newline bitfld.long 0x00 7. " MASK0[8] ,Input 8 mask 0" "Not masked,Masked" bitfld.long 0x00 6. " [7] ,Input 8 mask 0" "Not masked,Masked" newline bitfld.long 0x00 5. " [6] ,Input 6 mask 0" "Not masked,Masked" bitfld.long 0x00 4. " [5] ,Input 5 mask 0" "Not masked,Masked" newline bitfld.long 0x00 3. " [4] ,Input 4 mask 0" "Not masked,Masked" bitfld.long 0x00 2. " [3] ,Input 3 mask 0" "Not masked,Masked" newline bitfld.long 0x00 1. " [2] ,Input 2 mask 0" "Not masked,Masked" bitfld.long 0x00 0. " [1] ,Input 1 mask 0" "Not masked,Masked" newline tree.end tree.end width 25. group.long 0x28A0++0x0F line.long 0x00 "ALU_B_CTRL,Control Bits For The PXP ALU Sub-Block" rbitfld.long 0x00 28. " DONE ,Processing for a frame done" "Not done,Done" bitfld.long 0x00 20. " DONE_IRQ_EN ,Done IRQ enable" "Disabled,Enabled" newline eventfld.long 0x00 16. " DONE_IRQ_FLAG ,Done IRQ flag" "Not occurred,Occurred" bitfld.long 0x00 12. " BYPASS ,Bypass bit" "Not bypassed,Bypassed" newline eventfld.long 0x00 8. " SW_RESET ,Software reset to the ALU" "No reset,Reset" eventfld.long 0x00 4. " START ,Start operation" "Not started,Started" newline bitfld.long 0x00 0. " ENABLE ,Enable bit" "Disabled,Enabled" line.long 0x04 "ALU_B_CTRL_SET,Control Set Bits For The PXP ALU Sub-Block" rbitfld.long 0x04 28. " DONE ,Processing for a frame done" "Not done,Done" bitfld.long 0x04 20. " DONE_IRQ_EN ,Done IRQ enable" "Disabled,Enabled" newline eventfld.long 0x04 16. " DONE_IRQ_FLAG ,Done IRQ flag" "Not occurred,Occurred" bitfld.long 0x04 12. " BYPASS ,Bypass bit" "Not bypassed,Bypassed" newline eventfld.long 0x04 8. " SW_RESET ,Software reset to the ALU" "No reset,Reset" eventfld.long 0x04 4. " START ,Start operation" "Not started,Started" newline bitfld.long 0x04 0. " ENABLE ,Enable bit" "Disabled,Enabled" line.long 0x08 "ALU_B_CTRL_CLR,Control Clear Bits For The PXP ALU Sub-Block" rbitfld.long 0x08 28. " DONE ,Processing for a frame done" "Not done,Done" bitfld.long 0x08 20. " DONE_IRQ_EN ,Done IRQ enable" "Disabled,Enabled" newline eventfld.long 0x08 16. " DONE_IRQ_FLAG ,Done IRQ flag" "Not occurred,Occurred" bitfld.long 0x08 12. " BYPASS ,Bypass bit" "Not bypassed,Bypassed" newline eventfld.long 0x08 8. " SW_RESET ,Software reset to the ALU" "No reset,Reset" eventfld.long 0x08 4. " START ,Start operation" "Not started,Started" newline bitfld.long 0x08 0. " ENABLE ,Enable bit" "Disabled,Enabled" line.long 0x0C "ALU_B_CTRL_TOG,Control Toggle Bits For The PXP ALU Sub-Block" rbitfld.long 0x0C 28. " DONE ,Processing for a frame done" "Not done,Done" bitfld.long 0x0C 20. " DONE_IRQ_EN ,Done IRQ enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " DONE_IRQ_FLAG ,Done IRQ flag" "Not occurred,Occurred" bitfld.long 0x0C 12. " BYPASS ,Bypass bit" "Not bypassed,Bypassed" newline bitfld.long 0x0C 8. " SW_RESET ,Software reset to the ALU" "No reset,Reset" bitfld.long 0x0C 4. " START ,Start operation" "Not started,Started" newline bitfld.long 0x0C 0. " ENABLE ,Enable bit" "Disabled,Enabled" group.long 0x28B0++0x03 line.long 0x00 "ALU_B_BUF_SIZE,Size Of The Buffer To Be Processed By The ALU Engine Register" hexmask.long.word 0x00 16.--27. 1. " BUF_HEIGHT ,Buffer height in pixels" newline hexmask.long.word 0x00 0.--11. 1. " BUF_WIDTH ,Buffer width in pixels" group.long 0x28C0++0x03 line.long 0x00 "ALU_B_INST_ENTRY,Entry Address For The Instruction Memory Of The ALU" hexmask.long.word 0x00 0.--15. 0x01 " ENTRY_ADDR ,Entry address for the instruction memory of ALU" group.long 0x28D0++0x03 line.long 0x00 "ALU_B_PARAM,Parameter Used By SW Running On ALU" hexmask.long.byte 0x00 8.--15. 1. " PARAM1 ,Parameter1 used for the SW running on ALU" newline hexmask.long.byte 0x00 0.--7. 1. " PARAM0 ,Parameter0 used for the SW running on ALU" group.long 0x28E0++0x03 line.long 0x00 "ALU_B_CONFIG,HW Configuration Options For The ALU Core" group.long 0x28F0++0x0F line.long 0x00 "ALU_B_LUT_CONFIG,HW Configuration Options For The LUT" bitfld.long 0x00 4.--5. " MODE ,LUT operation mode setting" "0,1,2,3" bitfld.long 0x00 0. " EN ,Enable LUT function" "Disabled,Enabled" line.long 0x04 "ALU_B_LUT_CONFIG_SET,HW Configuration Options For The LUT Set" bitfld.long 0x04 4.--5. " MODE ,LUT operation mode setting" "0,1,2,3" bitfld.long 0x04 0. " EN ,Enable LUT function" "Disabled,Enabled" line.long 0x08 "ALU_B_LUT_CONFIG_CLR,HW Configuration Options For The LUT Clear" bitfld.long 0x08 4.--5. " MODE ,LUT operation mode setting" "0,1,2,3" bitfld.long 0x08 0. " EN ,Enable LUT function" "Disabled,Enabled" line.long 0x0C "ALU_B_LUT_CONFIG_TOG,HW Configuration Options For The LUT Toggle" bitfld.long 0x0C 4.--5. " MODE ,LUT operation mode setting" "0,1,2,3" bitfld.long 0x0C 0. " EN ,Enable LUT function" "Disabled,Enabled" group.long 0x2900++0x03 line.long 0x00 "ALU_B_LUT_DATA0,Lower 32-bit Data For The LUT" group.long 0x2910++0x03 line.long 0x00 "ALU_B_LUT_DATA1,Higher 32-bit Data For The LUT" group.long 0x2920++0x03 line.long 0x00 "ALU_B_DBG,ALU Block Debugging Register" hexmask.long.byte 0x00 24.--31. 1. " DEBUG_SEL ,Select the signal to be monitored" newline hexmask.long.tbyte 0x00 0.--23. 1. " DEBUG_VALUE ,Value of the signals to be monitored" group.long 0x2A00++0x03 line.long 0x00 "HIST_A_CTRL,Histogram Control Register" bitfld.long 0x00 24.--26. " PIXEL_WIDTH ,The width of the pixel to be used for histogram calculation" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--22. 1. " PIXEL_OFFSET ,The offset of the pixel to be used for histogram calculation" newline rbitfld.long 0x00 12. " STATUS[12] ,Indicates that the bitmap pixels were fully contained within the HIST32 (5-bit grayscale) histogram" "Not full,Full" rbitfld.long 0x00 11. " [11] ,Indicates that the bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "Not full,Full" newline rbitfld.long 0x00 10. " [10] ,Indicates that the bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "Not full,Full" rbitfld.long 0x00 9. " 9] ,Indicates that the bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "Not full,Full" newline rbitfld.long 0x00 8. " [8] ,Indicates that the bitmap pixels were fully contained within the HIST2 (Black / white) histogram" "Not full,Full" newline eventfld.long 0x00 4. " CLEAR ,Clears the histogram result" "No effect,Clear" bitfld.long 0x00 0. " ENABLE ,Enables the histogram engine" "Disabled,Enabled" group.long 0x2A10++0x03 line.long 0x00 "HIST_A_MASK,Histogram Pixel Mask Register" hexmask.long.byte 0x00 24.--31. 1. " MASK_VALUE1 ,The value1 for mask condition checking" hexmask.long.byte 0x00 16.--23. 1. " MASK_VALUE0 ,The value0 for mask condition checking" newline bitfld.long 0x00 13.--15. " MASK_WIDTH ,The width of the field to be checked against mask condition" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 6.--12. 1. " MASK_OFFSET ,The offset of the field to be checked against mask condition" newline bitfld.long 0x00 4.--5. " MASK_MODE ,Operation mode of pixel mask function" "EQUAL,NOT_EQUAL,INSIDE,OUTSIDE" bitfld.long 0x00 0. " MASK_EN ,Enables the pixel mask function in histogram" "Disabled,Enabled" group.long 0x2A20++0x03 line.long 0x00 "HIST_A_BUF_SIZE,Histogram Pixel Buffer Size Register" hexmask.long.word 0x00 16.--27. 1. " HEIGHT ,Indicates the buffer height in pixels" hexmask.long.word 0x00 0.--11. 1. " WIDTH ,Indicates the buffer width in pixels" rgroup.long 0x2A30++0x03 line.long 0x00 "HIST_A_TOTAL_PIXEL,Total Number Of Pixels Used By Histogram Engine" hexmask.long.tbyte 0x00 0.--23. 1. " TOTAL_PIXEL ,Total number of pixels used by histogram engine, the pixels got masked will be skipped" rgroup.long 0x2A40++0x03 line.long 0x00 "HIST_A_ACTIVE_AREA_X,The X Coordinate Offset For Active Area" hexmask.long.word 0x00 16.--27. 1. " MAX_X_OFFSET ,Maximum X coordinate offset for the active area in histogram processing" hexmask.long.word 0x00 0.--11. 1. " MIN_X_OFFSET ,Minimul X coordinate offset for the active area in histogram processing" rgroup.long 0x2A50++0x03 line.long 0x00 "HIST_A_ACTIVE_AREA_Y,The Y Coordinate Offset For Active Area" hexmask.long.word 0x00 16.--27. 1. " MAX_Y_OFFSET ,Maximum Y coordinate offset for the active area in histogram processing" hexmask.long.word 0x00 0.--11. 1. " MIN_Y_OFFSET ,Minimul Y coordinate offset for the active area in histogram processing" rgroup.long 0x2A60++0x03 line.long 0x00 "HIST_A_RAW_STAT0,Histogram Result Based On RAW Pixel Value" rgroup.long 0x2A70++0x03 line.long 0x00 "HIST_A_RAW_STAT1,Histogram Result Based On RAW Pixel Value" group.long 0x2A80++0x03 line.long 0x00 "HIST_B_CTRL,Histogram Control Register" bitfld.long 0x00 24.--26. " PIXEL_WIDTH ,The width of the pixel to be used for histogram calculation" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--22. 1. " PIXEL_OFFSET ,The offset of the pixel to be used for histogram calculation" newline rbitfld.long 0x00 12. " STATUS[12] ,Indicates that the bitmap pixels were fully contained within the HIST32 (5-bit grayscale) histogram" "Not full,Full" rbitfld.long 0x00 11. " [11] ,Indicates that the bitmap pixels were fully contained within the HIST16 (4-bit grayscale) histogram" "Not full,Full" newline rbitfld.long 0x00 10. " [10] ,Indicates that the bitmap pixels were fully contained within the HIST8 (3-bit grayscale) histogram" "Not full,Full" rbitfld.long 0x00 9. " [9] ,Indicates that the bitmap pixels were fully contained within the HIST4 (2-bit grayscale) histogram" "Not full,Full" newline rbitfld.long 0x00 8. " [8] ,Indicates that the bitmap pixels were fully contained within the HIST2 (Black / white) histogram" "Not full,Full" newline eventfld.long 0x00 4. " CLEAR ,Clears the histogram result" "No effect,Clear" bitfld.long 0x00 0. " ENABLE ,Enables the histogram engine" "Disabled,Enabled" group.long 0x2A90++0x03 line.long 0x00 "HIST_B_MASK,Histogram Pixel Mask Register" hexmask.long.byte 0x00 24.--31. 1. " MASK_VALUE1 ,The value1 for mask condition checking" hexmask.long.byte 0x00 16.--23. 1. " MASK_VALUE0 ,The value0 for mask condition checking" newline bitfld.long 0x00 13.--15. " MASK_WIDTH ,The width of the field to be checked against mask condition" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 6.--12. 1. " MASK_OFFSET ,The offset of the field to be checked against mask condition" newline bitfld.long 0x00 4.--5. " MASK_MODE ,Operation mode of pixel mask function" "EQUAL,NOT_EQUAL,INSIDE,OUTSIDE" bitfld.long 0x00 0. " MASK_EN ,Enables the pixel mask function in histogram" "Disabled,Enabled" group.long 0x2AA0++0x03 line.long 0x00 "HIST_B_BUF_SIZE,Histogram Pixel Buffer Size Register" hexmask.long.word 0x00 16.--27. 1. " HEIGHT ,Indicates the buffer height in pixels" hexmask.long.word 0x00 0.--11. 1. " WIDTH ,Indicates the buffer width in pixels" rgroup.long 0x2AB0++0x03 line.long 0x00 "HIST_B_TOTAL_PIXEL,Total Number Of Pixels Used By Histogram Engine" hexmask.long.tbyte 0x00 0.--23. 1. " TOTAL_PIXEL ,Total number of pixels used by histogram engine, the pixels got masked will be skipped" rgroup.long 0x2AC0++0x03 line.long 0x00 "HIST_B_ACTIVE_AREA_X,The X Coordinate Offset For Active Area" hexmask.long.word 0x00 16.--27. 1. " MAX_X_OFFSET ,Maximum X coordinate offset for the active area in histogram processing" hexmask.long.word 0x00 0.--11. 1. " MIN_X_OFFSET ,Minimal X coordinate offset for the active area in histogram processing" rgroup.long 0x2AD0++0x03 line.long 0x00 "HIST_B_ACTIVE_AREA_Y,The Y Coordinate Offset For Active Area" hexmask.long.word 0x00 16.--27. 1. " MAX_Y_OFFSET ,Maximum Y coordinate offset for the active area in histogram processing" hexmask.long.word 0x00 0.--11. 1. " MIN_Y_OFFSET ,Minimal Y coordinate offset for the active area in histogram processing" rgroup.long 0x2AE0++0x03 line.long 0x00 "HIST_B_RAW_STAT0,Histogram Result Based On RAW Pixel Value" rgroup.long 0x2AF0++0x03 line.long 0x00 "HIST_B_RAW_STAT1,Histogram Result Based On RAW Pixel Value" newline width 15. group.long 0x2B00++0x03 line.long 0x00 "HIST2_PARAM,2-level Histogram Parameter Register" bitfld.long 0x00 8.--13. " VALUE1 ,White value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,Black value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B10++0x03 line.long 0x00 "HIST4_PARAM,4-level Histogram Parameter Register" bitfld.long 0x00 24.--29. " VALUE3 ,GRAY3 (White) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE2 ,GRAY2 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE1 ,GRAY1 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,GRAY0 (Black) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B20++0x03 line.long 0x00 "HIST8_PARAM0,8-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--29. " VALUE3 ,GRAY3 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE2 ,GRAY2 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE1 ,GRAY1 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,GRAY0 (Black) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B30++0x03 line.long 0x00 "HIST8_PARAM1,8-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--29. " VALUE7 ,GRAY7 (White) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE6 ,GRAY6 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE5 ,GRAY5 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE4 ,GRAY4 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B40++0x03 line.long 0x00 "HIST16_PARAM0,16-level Histogram Parameter Register" bitfld.long 0x00 24.--29. " VALUE3 ,GRAY3 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE2 ,GRAY2 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE1 ,GRAY1 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,GRAY0 (Black) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B50++0x03 line.long 0x00 "HIST16_PARAM1,16-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--29. " VALUE7 ,GRAY7 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE6 ,GRAY6 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE5 ,GRAY5 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE4 ,GRAY4 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B60++0x03 line.long 0x00 "HIST16_PARAM2,16-level Histogram Parameter 2 Register" bitfld.long 0x00 24.--29. " VALUE11 ,GRAY11 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE10 ,GRAY10 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE9 ,GRAY9 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE8 ,GRAY8 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B70++0x03 line.long 0x00 "HIST16_PARAM3,16-level Histogram Parameter 3 Register" bitfld.long 0x00 24.--29. " VALUE15 ,GRAY15 (White) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE14 ,GRAY14 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE13 ,GRAY13 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE12 ,GRAY12 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B80++0x03 line.long 0x00 "HIST32_PARAM0,32-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--29. " VALUE3 ,GRAY3 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE2 ,GRAY2 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE1 ,GRAY1 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE0 ,GRAY0 (Black) value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2B90++0x03 line.long 0x00 "HIST32_PARAM1,32-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--29. " VALUE7 ,GRAY7 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE6 ,GRAY6 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE5 ,GRAY5 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE4 ,GRAY4 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BA0++0x03 line.long 0x00 "HIST32_PARAM2,32-level Histogram Parameter 2 Register" bitfld.long 0x00 24.--29. " VALUE11 ,GRAY11 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE10 ,GRAY10 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE9 ,GRAY9 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE8 ,GRAY8 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BB0++0x03 line.long 0x00 "HIST32_PARAM3,32-level Histogram Parameter 3 Register" bitfld.long 0x00 24.--29. " VALUE15 ,GRAY15 (White) value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE14 ,GRAY14 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE13 ,GRAY13 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE12 ,GRAY12 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BC0++0x03 line.long 0x00 "HIST32_PARAM4,32-level Histogram Parameter 0 Register" bitfld.long 0x00 24.--29. " VALUE19 ,GRAY19 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE18 ,GRAY18 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE17 ,GRAY17 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE16 ,GRAY16 (Black) value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BD0++0x03 line.long 0x00 "HIST32_PARAM5,32-level Histogram Parameter 1 Register" bitfld.long 0x00 24.--29. " VALUE23 ,GRAY23 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE22 ,GRAY22 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE21 ,GRAY21 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE20 ,GRAY20 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BE0++0x03 line.long 0x00 "HIST32_PARAM6,32-level Histogram Parameter 2 Register" bitfld.long 0x00 24.--29. " VALUE27 ,GRAY27 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE26 ,GRAY26 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE25 ,GRAY25 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE24 ,GRAY24 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2BF0++0x03 line.long 0x00 "HIST32_PARAM7,32-level Histogram Parameter 3 Register" bitfld.long 0x00 24.--29. " VALUE31 ,GRAY31 (White) value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " VALUE30 ,GRAY30 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " VALUE29 ,GRAY29 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " VALUE28 ,GRAY28 value for 32-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline width 22. group.long 0x2CF0++0x03 line.long 0x00 "HANDSHAKE_READY_MUX0,HANDSHAKE_READY_MUX0" bitfld.long 0x00 28.--31. " HSK7 ,Sub-blocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 24.--27. " HSK6 ,Sub-blocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 20.--23. " HSK5 ,Sub-blocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." newline bitfld.long 0x00 16.--19. " HSK4 ,Sub-blocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 12.--15. " HSK3 ,Sub-blocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 8.--11. " HSK2 ,Sub-blocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." newline bitfld.long 0x00 4.--7. " HSK1 ,Sub-blocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." bitfld.long 0x00 0.--3. " HSK0 ,Sub-blocks double buffer handshake signals MUX" "PXP_CONTROL,PXP_STORE_WFE_B CH0,PXP_STORE_WFE_B CH1,PXP_STORE_PRE_DITERING CH0,PXP_STORE_PRE_DITERING CH1,PXP_STORE_DITHERING CH0,PXP_STORE_DITHERING CH1,PXP_STORE_WFE_A CH0,PXP_STORE_WFE_A CH1,CPU_FETCH_SW0_READY,CPU_FETCH_SW1_READY,CPU_STORE_SW0_READY,CPU_STORE_SW1_READY,?..." group.long 0x2D10++0x03 line.long 0x00 "HANDSHAKE_DONE_MUX0,HANDSHAKE_DONE_MUX0" bitfld.long 0x00 28.--31. " HSK7 ,Sub-blocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 24.--27. " HSK6 ,Sub-blocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 20.--23. " HSK5 ,Sub-blocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." newline bitfld.long 0x00 16.--19. " HSK4 ,Sub-blocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 12.--15. " HSK3 ,Sub-blocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 8.--11. " HSK2 ,Sub-blocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." newline bitfld.long 0x00 4.--7. " HSK1 ,Sub-blocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." bitfld.long 0x00 0.--3. " HSK0 ,Sub-blocks double buffer handshake signals MUX" "LCDIF,PXP_FETCH_INPUT CH0,PXP_FETCH_INPUT CH1,PXP_FETCH_DITHERING CH0,PXP_FETCH_DITHERING CH1,PXP_FETCH_WFE_A CH0,PXP_FETCH_WFE_A CH1,PXP_FETCH_WFE_B CH0,PXP_FETCH_WFE_B CH1,CPU_FETCH_SW0_DONE,CPU_FETCH_SW1_DONE,CPU_STORE_SW0_DONE,CPU_STORE_SW1_DONE,?..." width 0x0B tree.end tree "RNGB (Random Number Generator)" base ad:0x021B4000 width 14. rgroup.long 0x00++0x03 line.long 0x00 "VER,Version ID Register" bitfld.long 0x00 28.--31. " TYPE ,Random number generator type" "RNGA,RNGB,RNGC,?..." hexmask.long.byte 0x00 8.--15. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 0.--7. 1. " MINOR ,Minor version number" group.long 0x04++0x07 line.long 0x00 "CMD,Command Register" bitfld.long 0x00 6. " SR ,Software reset" "No reset,Reset" bitfld.long 0x00 5. " CE ,Clear error" "No effect,Clear" bitfld.long 0x00 4. " CI ,Clear interrupt" "No effect,Clear" newline bitfld.long 0x00 1. " GS ,Generate seed" "Not generated,Generated" bitfld.long 0x00 0. " ST ,Self test" "Not initiated,Initiated" line.long 0x04 "CR,Control Register" bitfld.long 0x04 6. " MASKERR ,Mask error interrupt" "Not masked,Masked" bitfld.long 0x04 5. " MASKDONE ,Mask done interrupt" "Not masked,Masked" bitfld.long 0x04 4. " AR ,Auto-reseed" "Disabled,Enabled" newline sif cpuis("IMX6SLL") bitfld.long 0x04 0.--1. " FUFMOD ,FIFO underflow response mode" "All zeros and ESR[FUFE] set,All zeros and ESR[FUFE] set,Bus transfer error,Interrupt and all zeros" else bitfld.long 0x04 0.--1. " FUFMOD ,FIFO underflow response mode" "All zeros/ESR[FUFE] set,All zeros/ESR[FUFE] set,Bus tx error,INT and all zeros" endif rgroup.long 0x0C++0x0B line.long 0x00 "SR,Status Register" bitfld.long 0x00 31. " STATPF[7] ,Statistics test pass fail (Long run test (>34))" "Passed,Failed" bitfld.long 0x00 30. " [6] ,Statistics test pass fail (Length 6+ run test)" "Passed,Failed" bitfld.long 0x00 29. " [5] ,Statistics test pass fail (Length 5 run test)" "Passed,Failed" newline bitfld.long 0x00 28. " [4] ,Statistics test pass fail (Length 4 run test)" "Passed,Failed" bitfld.long 0x00 27. " [3] ,Statistics test pass fail (Length 3 run test)" "Passed,Failed" bitfld.long 0x00 26. " [2] ,Statistics test pass fail (Length 2 run test)" "Passed,Failed" newline bitfld.long 0x00 25. " [1] ,Statistics test pass fail (Length 1 run test)" "Passed,Failed" bitfld.long 0x00 24. " [0] ,Statistics test pass fail (Monobit test)" "Passed,Failed" newline bitfld.long 0x00 23. " ST_PF[2] ,TRNG self test pass/fail" "Passed,Failed" bitfld.long 0x00 22. " [1] ,PRNG self test pass/fail" "Passed,Failed" newline bitfld.long 0x00 21. " [0] ,RESEED self test pass/fail" "Passed,Failed" bitfld.long 0x00 16. " ERR ,Indicates an error was detected in the RNGB" "No error,Error" newline bitfld.long 0x00 12.--15. " FIFO_SIZE ,FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " FIFO_LVL ,FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " NSDN ,New seed done" "Not completed,Completed" newline bitfld.long 0x00 5. " SDN ,Seed done" "Not completed,Completed" bitfld.long 0x00 4. " STDN ,Self test done" "Not completed,Completed" bitfld.long 0x00 3. " RS ,Reseed needed" "Not needed,Needed" newline bitfld.long 0x00 2. " SLP ,Indicates if the RNGB is in sleep mode" "Not sleep,Sleep" bitfld.long 0x00 1. " BUSY ,Reflects the current state of RNGB" "Not busy,Busy" line.long 0x04 "ESR,Error Status Register" bitfld.long 0x04 4. " FUFE ,FIFO underflow error" "Not occurred,Occurred" bitfld.long 0x04 3. " SATE ,Statistical test error" "Passed,Failed" bitfld.long 0x04 2. " STE ,Self test error" "Passed,Failed" newline bitfld.long 0x04 1. " OSCE ,Oscillator error" "No error,Error" line.long 0x08 "OUT,Output FIFO" if (((per.l(ad:0x021B4000+0x0C))&0x02)==0x00) wgroup.long 0x18++0x03 line.long 0x00 "ER,Entropy Register" else hgroup.long 0x18++0x03 hide.long 0x00 "ER,Entropy Register" in endif sif cpuis("IMX6SLL") group.long 0x20++0x03 line.long 0x00 "VCR,Verification Control Register" bitfld.long 0x00 9. " RST_XKEY ,Reset XKEY Register" "No reset,Reset" bitfld.long 0x00 8. " RST_SHREG ,Reset Shift Registers" "Not reset,Reset" bitfld.long 0x00 3. " FAKE_SEED ,Fake Seed" "No,Yes" newline bitfld.long 0x00 2. " OSC_TEST ,Oscillator Frequency Test" "Disabled,Enabled" bitfld.long 0x00 1. " FRC_SYS_CLK ,Force System Clock" "Not forced,Forced" bitfld.long 0x00 0. " SH_CLK_OFF ,Shift Clocks Off" "No effect,Shut off" else rgroup.long 0x20++0x03 line.long 0x00 "VCR,Verification Control Register" bitfld.long 0x00 9. " RST_XKEY ,Reset XKEY Register" "No reset,Reset" bitfld.long 0x00 8. " RST_SHREG ,Reset Shift Registers" "Not reset,Reset" bitfld.long 0x00 3. " FAKE_SEED ,Fake Seed" "No,Yes" newline bitfld.long 0x00 2. " OSC_TEST ,Oscillator Frequency Test" "Disabled,Enabled" bitfld.long 0x00 1. " FRC_SYS_CLK ,Force System Clock" "Not forced,Forced" bitfld.long 0x00 0. " SH_CLK_OFF ,Shift Clocks Off" ",Shut off" endif rgroup.long 0x24++0x03 line.long 0x00 "XKEY,XKEY Data" sif cpuis("IMX6SLL") group.long 0x28++0x03 line.long 0x00 "OCCR,Oscillator Counter Control Register" hexmask.long.tbyte 0x00 0.--17. 1. " OCCR ,Number of clock cycles remaining" else rgroup.long 0x28++0x03 line.long 0x00 "OCCR,Oscillator Counter Control Register" hexmask.long.tbyte 0x00 0.--17. 1. " OCCR ,Number of clock cycles remaining" endif rgroup.long 0x2C++0x08 line.long 0x00 "OSC_CNT,Oscillator Counter" hexmask.long.tbyte 0x00 0.--19. 1. " CLOCK_PULSES ,CLOCK PULSES" line.long 0x04 "OSC_CNT_STAT,Oscillator Counter Status" bitfld.long 0x04 0. " OS ,Oscillator Status" "Not toggled,Toggled" width 0x0B tree.end tree "ROMC (ROM Controller With Patch)" base ad:0x021AC0D4 width 14. group.long 0xD4++0x03 line.long 0x00 "ROMPATCH7D,ROMC Data Registers" group.long 0xD8++0x03 line.long 0x00 "ROMPATCH6D,ROMC Data Registers" group.long 0xDC++0x03 line.long 0x00 "ROMPATCH5D,ROMC Data Registers" group.long 0xE0++0x03 line.long 0x00 "ROMPATCH4D,ROMC Data Registers" group.long 0xE4++0x03 line.long 0x00 "ROMPATCH3D,ROMC Data Registers" group.long 0xE8++0x03 line.long 0x00 "ROMPATCH2D,ROMC Data Registers" group.long 0xEC++0x03 line.long 0x00 "ROMPATCH1D,ROMC Data Registers" group.long 0xF0++0x03 line.long 0x00 "ROMPATCH0D,ROMC Data Registers" group.long 0xF4++0x0B line.long 0x00 "ROMPATCHCNTL,ROMC Control Register" bitfld.long 0x00 29. " DIS ,ROMC disable" "No,Yes" newline bitfld.long 0x00 7. " DATAFIX[7] ,Data fix enable 7" "Opcode patch,Data fix" bitfld.long 0x00 6. " [6] ,Data fix enable 6" "Opcode patch,Data fix" bitfld.long 0x00 5. " [5] ,Data fix enable 5" "Opcode patch,Data fix" bitfld.long 0x00 4. " [4] ,Data fix enable 4" "Opcode patch,Data fix" newline bitfld.long 0x00 3. " [3] ,Data fix enable 3" "Opcode patch,Data fix" bitfld.long 0x00 2. " [2] ,Data fix enable 2" "Opcode patch,Data fix" bitfld.long 0x00 1. " [1] ,Data fix enable 1" "Opcode patch,Data fix" bitfld.long 0x00 0. " [0] ,Data fix enable 0" "Opcode patch,Data fix" line.long 0x04 "ROMPATCHENH,ROMC Enable Register High" line.long 0x08 "ROMPATCHENL,ROMC Enable Register Low" bitfld.long 0x08 15. " ENABLE[15] ,Enable address comparator 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Enable address comparator 14" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Enable address comparator 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Enable address comparator 12" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Enable address comparator 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Enable address comparator 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Enable address comparator 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Enable address comparator 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Enable address comparator 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Enable address comparator 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Enable address comparator 5" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Enable address comparator 4" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Enable address comparator 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Enable address comparator 2" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Enable address comparator 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Enable address comparator 0" "Disabled,Enabled" group.long 0x100++0x03 line.long 0x00 "ROMPATCH0A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x104++0x03 line.long 0x00 "ROMPATCH1A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x108++0x03 line.long 0x00 "ROMPATCH2A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x10C++0x03 line.long 0x00 "ROMPATCH3A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x110++0x03 line.long 0x00 "ROMPATCH4A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x114++0x03 line.long 0x00 "ROMPATCH5A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x118++0x03 line.long 0x00 "ROMPATCH6A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x11C++0x03 line.long 0x00 "ROMPATCH7A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x120++0x03 line.long 0x00 "ROMPATCH8A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x124++0x03 line.long 0x00 "ROMPATCH9A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x128++0x03 line.long 0x00 "ROMPATCH10A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x12C++0x03 line.long 0x00 "ROMPATCH11A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x130++0x03 line.long 0x00 "ROMPATCH12A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x134++0x03 line.long 0x00 "ROMPATCH13A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x138++0x03 line.long 0x00 "ROMPATCH14A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x13C++0x03 line.long 0x00 "ROMPATCH15A,ROMC Address Registers" hexmask.long.tbyte 0x00 1.--22. 0x02 " ADDRX ,Address comparator registers" bitfld.long 0x00 0. " THUMBX ,THUMB comparator select" "ARM patch,THUMB patch" group.long 0x208++0x03 line.long 0x00 "ROMPATCHSR,ROMC Status Register" eventfld.long 0x00 17. " SW ,ROMC AHB multiple address comparator matches indicator" "No collision,Collision" rbitfld.long 0x00 0.--5. " SOURCE ,ROMC source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." width 0x0B tree.end tree "SDMA (Smart Direct Memory Access Controller)" base ad:0x020EC000 width 12. group.long 0x00++0x03 line.long 0x00 "MC0PTR,ARM Platform Channel 0 Pointer" group.long 0x08++0x38 line.long 0x00 "CCPTR,Current Channel Pointer Register" hexmask.long.word 0x00 0.--15. 0x01 " CCPTR ,Contains the start address of the context data for the current channel" line.long 0x04 "CCR,Current Channel Register" bitfld.long 0x04 0.--4. " CCR ,Contains the number of the current running channel whose context is installed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "NCR,Highest Pending Channel Register" bitfld.long 0x08 0.--4. " NCR ,Contains the number of the pending channel that the scheduler has selected to run next" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "EVENTS,External DMA Requests Mirror" line.long 0x10 "CCPRI,Current Channel Priority" bitfld.long 0x10 0.--2. " CCPRI ,Contains the 3-bit priority of the channel whose context is installed" "None,0,1,2,3,4,5,6" line.long 0x14 "NCPRI,Next Channel Priority" bitfld.long 0x14 0.--2. " NCPRI ,Contains the 3-bit priority of the channel the scheduler has selected to run next" "None,0,1,2,3,4,5,6" line.long 0x18 "ECOUNT,OnCE Event Cell Counter" hexmask.long.word 0x18 0.--15. 1. " ECOUNT ,The event cell counter contains the number of times minus one that an event detection must occur before generating a debug request" line.long 0x1C "ECTL,OnCE Event Cell Control Register" bitfld.long 0x1C 13. " EN ,Event cell enable" "Disabled,Enabled" bitfld.long 0x1C 12. " CNT ,Event counter enable" "Disabled,Enabled" bitfld.long 0x1C 10.--11. " ECTC ,Event cell trigger condition bits select" "Address only,Data only,Addr and Data,Addr or Data" newline bitfld.long 0x1C 8.--9. " DTC ,Data trigger condition bits select" "Equal,Not equal,Greater,Less" bitfld.long 0x1C 6.--7. " ATC ,Address trigger condition bits select" "AddrA only,AddrA and AddrB,AddrA or AddrB,?..." bitfld.long 0x1C 4.--5. " ABTC ,Address B trigger condition" "Equal,Not equal,Greater,Less" newline bitfld.long 0x1C 2.--3. " AATC ,Address A trigger condition" "Equal,Not equal,Greater,Less" bitfld.long 0x1C 0.--1. " ATS ,Access type select bits" "Read,Write,Read/Write,?..." line.long 0x20 "EAA,OnCE Event Address Register A" hexmask.long.word 0x20 0.--15. 0x01 " EAA ,Event cell address register A" line.long 0x24 "EAB,OnCE Event Address Register B" hexmask.long.word 0x24 0.--15. 0x01 " EAB ,Event cell address register B" line.long 0x28 "EAM,OnCE Event Cell Address Mask" hexmask.long.word 0x28 0.--15. 0x01 " EAM ,Event cell address mask" line.long 0x2C "ED,OnCE Event Cell Data Register" line.long 0x30 "EDM,OnCE Event Cell Data Mask" line.long 0x34 "RTB,OnCE Real-Time Buffer" rgroup.long 0x40++0x18 line.long 0x00 "TB,OnCE Trace Buffer" bitfld.long 0x00 28. " TBF ,Trace buffer flag" "Invalid,Valid" newline hexmask.long.word 0x00 14.--23. 0x40 " TADDR ,Target address is the address taken after the execution of the change of flow instruction" newline hexmask.long.word 0x00 0.--13. 0x01 " CHFADDR ,Change of flow address is the address where the change of flow is taken when executing a change of flow instruction" line.long 0x04 "OSTAT,OnCE Status" bitfld.long 0x04 12.--15. " PST ,Processor status bits" "Program,Data,Change of flow,Change of flow in loop,Debug,Functional unit,Sleep,Save,Program in sleep,Data in sleep,Change of flow in sleep,Change flow loop sleep,Debug in sleep,Functional unit in sleep,Sleep after reset,Restore" newline bitfld.long 0x04 11. " RCV ,After each write access to the real time buffer this bit is set" "0,1" bitfld.long 0x04 10. " EDR ,Debug mode after an external debug request flag" "Not occurred,Occurred" newline bitfld.long 0x04 9. " ODR ,Debug mode after a OnCE debug request flag" "Not occurred,Occurred" bitfld.long 0x04 8. " SWB ,Debug mode after a software breakpoint flag" "Not occurred,Occurred" newline bitfld.long 0x04 7. " MST ,ARM platform peripheral interface control the OnCE" "Not set,Set" bitfld.long 0x04 0.--2. " ECDR ,Event cell debug request" "Address A,Address B,Data,?..." line.long 0x08 "MCHN0ADDR,Channel 0 Boot Address" bitfld.long 0x08 14. " SMSZ ,Scratch memory size" "24,32" hexmask.long.word 0x08 0.--13. 0x01 " CHN0ADDR ,Contains the address of the channel 0 routine programmed by the ARM platform" line.long 0x0C "ENDIANNESS,Endian Status Register" bitfld.long 0x0C 0. " APEND ,Indicates the endian mode of the Peripheral and Burst DMA interfaces" "Big,Little" line.long 0x10 "SDMA_LOCK,Lock Status Register" bitfld.long 0x10 0. " LOCK ,Determines LOCK value used by SDMA software" "Not locked,Locked" line.long 0x14 "EVENTS2,External DMA Requests Mirror 2" hexmask.long.word 0x14 0.--15. 1. " EVENTS ,Reflects the status of the SDMA's external DMA requests" width 0x0B tree.end tree "SNVS (Secure Non-Volatile Storage)" base ad:0x020CC000 width 9. group.long 0x00++0x0B line.long 0x00 "HPLR,HP Lock Register" bitfld.long 0x00 5. " GPR_SL ,General purpose register soft lock" "Not locked,Locked" bitfld.long 0x00 4. " MC_SL ,Monotonic counter soft lock" "Not locked,Locked" line.long 0x04 "HPCOMR,HP Command Register" bitfld.long 0x04 31. " NPSWA_EN ,Non-privileged software access enable" "Disabled,Enabled" bitfld.long 0x04 5. " LP_SWR_DIS ,LP software reset disable" "No,Yes" bitfld.long 0x04 4. " LP_SWR ,LP software reset" "No effect,Reset" line.long 0x08 "HPCR,HP Control Register" bitfld.long 0x08 27. " BTN_MASK ,Button interrupt mask" "Disabled,Enabled" bitfld.long 0x08 24.--26. " BTN_CONFIG ,Button configuration" "Low,High,Rising edge,Falling edge,Any edge,?..." bitfld.long 0x08 10.--14. " HPCALB_VAL ,HP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x08 8. " HPCALB_EN ,HP real time counter calibration enabled" "Disabled,Enabled" newline bitfld.long 0x08 4.--7. " PI_FREQ ,Periodic interrupt frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3. " PI_EN ,HP periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " HPTA_EN ,HP time alarm interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " RTC_EN ,HP real time counter enable" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "HPSR,HP Status Register" eventfld.long 0x00 7. " BI ,Button interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 6. " BTN ,BTN input state" "Not pressed,Pressed" if (((per.l(ad:0x020CC000+0x08)&0x01)==0x01)) rgroup.long 0x24++0x07 line.long 0x00 "HPRTCMR,HP Real Time Counter MSB Register" line.long 0x04 "HPRTCLR,HP Real Time Counter LSB Register" else group.long 0x24++0x07 line.long 0x00 "HPRTCMR,HP Real Time Counter MSB Register" line.long 0x04 "HPRTCLR,HP Real Time Counter LSB Register" endif if (((per.l(ad:0x020CC000+0x08)&0x02)==0x02)) rgroup.long 0x2C++0x07 line.long 0x00 "HPTAMR,HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP time alarm" line.long 0x04 "HPTALR,HP Time Alarm LSB Register" else group.long 0x2C++0x07 line.long 0x00 "HPTAMR,HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP time alarm" line.long 0x04 "HPTALR,HP Time Alarm LSB Register" endif group.long 0x34++0x03 line.long 0x00 "LPLR,LP Lock Register" bitfld.long 0x00 5. " GPR_HL ,General purpose register hard lock" "Not locked,Locked" bitfld.long 0x00 4. " MC_HL ,Monotonic counter hard lock" "Not locked,Locked" if ((per.l(ad:0x020CC000+0x38)&0x20)==0x20) group.long 0x38++0x03 line.long 0x00 "LPCR,LP Control Register" bitfld.long 0x00 23. " PK_OVERRIDE ,PMIC on request override" "Not overridden,Overridden" bitfld.long 0x00 22. " PK_EN ,PMIC on request enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ON_TIME ,Period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoCpower" "500 ms,50 ms,100 ms,0 ms" bitfld.long 0x00 18.--19. " DEBOUNCE ,Amount of debounce time for the BTN input signal" "50 ms,100 ms,500 ms,0 ms" newline bitfld.long 0x00 16.--17. " BTN_PRESS_TIME ,Button press time out values for PMIC logic" "5 s,10 s,15 s,Disabled" bitfld.long 0x00 10.--14. " LPCALB_VAL ,LP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x00 7. " PWR_GLITCH_EN ,Power glitch enable" "Disabled,Enabled" bitfld.long 0x00 6. " TOP ,Turn off system power" "Power on,Power off" newline bitfld.long 0x00 5. " DP_EN ,Decides whether dumb or smart PMIC is enabled" "Disabled,Enabled" bitfld.long 0x00 2. " MC_ENV ,Monotonic counter enable and valid" "Disabled/invalid,Enabled/valid" else group.long 0x38++0x03 line.long 0x00 "LPCR,LP Control Register" bitfld.long 0x00 23. " PK_OVERRIDE ,PMIC on request override" "Not overridden,Overridden" bitfld.long 0x00 22. " PK_EN ,PMIC on request enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ON_TIME ,Period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoCpower" "500 ms,50 ms,100 ms,0 ms" bitfld.long 0x00 18.--19. " DEBOUNCE ,Amount of debounce time for the BTN input signal" "50 ms,100 ms,500 ms,0 ms" newline bitfld.long 0x00 16.--17. " BTN_PRESS_TIME ,Button press time out values for PMIC logic" "5 s,10 s,15 s,Disabled" bitfld.long 0x00 10.--14. " LPCALB_VAL ,LP calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x00 7. " PWR_GLITCH_EN ,Power glitch enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " DP_EN ,Decides whether dumb or smart PMIC is enabled" "Disabled,Enabled" bitfld.long 0x00 2. " MC_ENV ,Monotonic counter enable and valid" "Disabled/invalid,Enabled/valid" endif group.long 0x4C++0x03 line.long 0x00 "LPSR,LP Status Register" eventfld.long 0x00 18. " SPO ,Set power off" "No effect,Clear" eventfld.long 0x00 17. " EO ,Power off request" "Not requested,Requested" eventfld.long 0x00 2. " MCR ,Monotonic counter rollover" "No rollover,Rollover" rgroup.long 0x5C++0x07 line.long 0x00 "LPSMCMR,LP Secure Monotonic Counter MSB Register" hexmask.long.word 0x00 16.--31. 1. " MC_ERA_BITS ,Monotonic counter era bits" hexmask.long.word 0x00 0.--15. 1. " MON_COUNTER ,Monotonic counter most-significant 16 bits" line.long 0x04 "LPSMCLR,LP Secure Monotonic Counter LSB Register" if (((per.l(ad:0x020CC000)&0x20)==0x00)&&((per.l(ad:0x020CC000+0x34)&0x20)==0x00)) group.long 0x68++0x03 line.long 0x00 "LPGPR,LP General Purpose Register 0 Alias" else rgroup.long 0x68++0x03 line.long 0x00 "LPGPR,LP General Purpose Register 0 Alias" endif rgroup.long 0xBF8++0x07 line.long 0x00 "HPVIDR1,HP Version ID Register 1" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,SNVS block ID" hexmask.long.byte 0x00 8.--15. 1. " MAJOR_REV ,SNVS block major version number" hexmask.long.byte 0x00 0.--7. 1. " MINOR_REV ,SNVS block minor version number" line.long 0x04 "HPVIDR2,HP Version ID Register 2" hexmask.long.byte 0x04 24.--31. 1. " IP_ERA ,Era of the IP design" hexmask.long.byte 0x04 16.--23. 1. " INTG_OPT ,SNVS integration option" hexmask.long.byte 0x04 8.--15. 1. " ECO_REV ,SNVS ECO revision" hexmask.long.byte 0x04 0.--7. 1. " CONFIG_OPT ,SNVS configuration option" width 0x0B tree.end tree "SPBA (Shared Peripheral Bus Arbiter)" base ad:0x0203C000 width 7. group.long 0x0++0x27 line.long 0x00 "PRR0,Peripheral Right Register 0" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x4++0x27 line.long 0x00 "PRR1,Peripheral Right Register 1" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x8++0x27 line.long 0x00 "PRR2,Peripheral Right Register 2" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0xC++0x27 line.long 0x00 "PRR3,Peripheral Right Register 3" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x10++0x27 line.long 0x00 "PRR4,Peripheral Right Register 4" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x14++0x27 line.long 0x00 "PRR5,Peripheral Right Register 5" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x18++0x27 line.long 0x00 "PRR6,Peripheral Right Register 6" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x1C++0x27 line.long 0x00 "PRR7,Peripheral Right Register 7" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x20++0x27 line.long 0x00 "PRR8,Peripheral Right Register 8" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x24++0x27 line.long 0x00 "PRR9,Peripheral Right Register 9" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x28++0x57 line.long 0x00 "PRR10,Peripheral Right Register 10" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x2C++0x57 line.long 0x00 "PRR11,Peripheral Right Register 11" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x30++0x57 line.long 0x00 "PRR12,Peripheral Right Register 12" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x34++0x57 line.long 0x00 "PRR13,Peripheral Right Register 13" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x38++0x57 line.long 0x00 "PRR14,Peripheral Right Register 14" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x3C++0x57 line.long 0x00 "PRR15,Peripheral Right Register 15" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x40++0x57 line.long 0x00 "PRR16,Peripheral Right Register 16" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x44++0x57 line.long 0x00 "PRR17,Peripheral Right Register 17" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x48++0x57 line.long 0x00 "PRR18,Peripheral Right Register 18" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x4C++0x57 line.long 0x00 "PRR19,Peripheral Right Register 19" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x50++0x57 line.long 0x00 "PRR20,Peripheral Right Register 20" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x54++0x57 line.long 0x00 "PRR21,Peripheral Right Register 21" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x58++0x57 line.long 0x00 "PRR22,Peripheral Right Register 22" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x5C++0x57 line.long 0x00 "PRR23,Peripheral Right Register 23" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x60++0x57 line.long 0x00 "PRR24,Peripheral Right Register 24" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x64++0x57 line.long 0x00 "PRR25,Peripheral Right Register 25" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x68++0x57 line.long 0x00 "PRR26,Peripheral Right Register 26" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x6C++0x57 line.long 0x00 "PRR27,Peripheral Right Register 27" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x70++0x57 line.long 0x00 "PRR28,Peripheral Right Register 28" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x74++0x57 line.long 0x00 "PRR29,Peripheral Right Register 29" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x78++0x57 line.long 0x00 "PRR30,Peripheral Right Register 30" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" group.long 0x7C++0x57 line.long 0x00 "PRR31,Peripheral Right Register 31" rbitfld.long 0x00 30.--31. " RMO ,Requesting Master Owner" "Unowned,,Another,Requesting" rbitfld.long 0x00 16.--17. " ROI ,Resource Owner ID" "Unowned,A,B,C" newline bitfld.long 0x00 2. " RARC ,Resource Access Right for Master C" "Not allowed,Allowed" bitfld.long 0x00 1. " RARB ,Resource Access Right for Master B" "Not allowed,Allowed" newline bitfld.long 0x00 0. " RARA ,Resource Access Right for Master A" "Not allowed,Allowed" width 0x0B tree.end tree "SPDIF (Sony/Philips Digital Interface)" base ad:0x02004000 width 9. group.long 0x00++0x07 line.long 0x00 "SCR,Configuration Register" bitfld.long 0x00 23. " RXFIFO_CTRL ,Receive FIFO operation mode" "Normal,Read zero" bitfld.long 0x00 22. " RXFIFO_OFF/ON ,SPDIF Receive FIFO enable" "Enabled,Disabled" bitfld.long 0x00 21. " RXFIFO_RST ,Receive FIFO reset" "No reset,Reset" newline bitfld.long 0x00 19.--20. " RXFIFOFULL_SEL ,Receive FIFO full interrupt select" "1,4,8,16" bitfld.long 0x00 18. " RXAUTOSYNC ,Receive FIFO auto sync enable" "Disabled,Enabled" bitfld.long 0x00 17. " TXAUTOSYNC ,Transmit FIFO Auto Sync Enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " TXFIFOEMPTY_SEL ,Transmit FIFO Empty interrupt select" "0,4,8,12" bitfld.long 0x00 13. " LOW_POWER ,SPDIF low-power mode" "Disabled,Enabled" bitfld.long 0x00 12. " SOFT_RESET ,SPDIF software reset" "No reset,Reset" newline bitfld.long 0x00 10.--11. " TXFIFO_CTRL ,Transmit FIFO Control" "Tx Digital 0,Normal,Reset to 1 samp,?..." bitfld.long 0x00 9. " DMA_RX_EN ,DMA Receive Request enable" "Disabled,Enabled" bitfld.long 0x00 8. " DMA_TX_EN ,DMA Transmit Request enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " VALCTRL ,Outgoing Validity" "Set,Clear" bitfld.long 0x00 2.--4. " TXSEL ,Transmit Select" "0ff and output 0,SPDIFIN,,,,Normal,," bitfld.long 0x00 0.--1. " USRC_SEL ,Receive channel U select" "No embedded,SPDIF receive block,,On chip transmitter" line.long 0x04 "SRCD,CDText Control Register" bitfld.long 0x04 1. " USYNCMODE , U sync mode" "Non-CD data,CD user channel subcode" sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6QUADLITE")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")||(cpu()=="IMX6SLL") if (((per.l(ad:0x02004000+0x08))&0x40)==0x40) group.long 0x08++0x03 line.long 0x00 "SRPC,PhaseConfig Register" sif (cpu()=="IMX6SOLOLITE")||(cpu()=="IMX6SLL") bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "SPDIF_RxClk,SPDIF_RxClk,,SPDIF_RxClk,,REF_CLK_32K,TX_CLK,,SPDIF_EXT_CLK,?..." else bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "SPDIF_RxClk,SPDIF_RxClk,SPDIF_RxClk,SPDIF_RxClk,SPDIF_Rxclk,Extal_clk,Spdif_clk,Asrc_clk,Spdif_extclk,Esai_hckt,SPDIF_RxClk,SPDIF_RxClk,Mkb_clk,Mlb_phy_clk,?..." endif newline rbitfld.long 0x00 6. " LOCK ,Internal DPLL lock" "Not locked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." else group.long 0x08++0x03 line.long 0x00 "SRPC,PhaseConfig Register" sif (cpu()=="IMX6SOLOLITE")||(cpu()=="IMX6SLL") bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "REF_CLK_32K,TX_CLK,,SPDIF_EXT_CLK,,REF_CLK_32K,TX_CLK,,SPDIF_EXT_CLK,?..." else bitfld.long 0x00 7.--10. " CLKSRC_SEL ,Clock source selection" "Extal,Spdif_clk,Asrc_clk,Spdif_extclk,Esai_hckt,Extal_clk,Spdif_clk,Asrc_clk,Spdif_extclk,Esai_hckt,Mlb_clk,Mlb_phy_clk,Mkb_clk,Mlb_phy_clk,?..." endif newline rbitfld.long 0x00 6. " LOCK ,Internal DPLL lock" "Not locked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." endif else group.long 0x08++0x03 line.long 0x00 "SRPC,PhaseConfig Register" rbitfld.long 0x00 6. " LOCK ,Internal DPLL lock" "Not locked,Locked" bitfld.long 0x00 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." endif group.long 0x0C++0x03 line.long 0x00 "SIE,Interrupt Enable Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " TXUNOV ,SPDIF transmit FIFO under/overrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " TXRESYN ,SPDIF transmit FIFO resync interrupt" "Disabled,Enabled" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel" "Disabled,Enabled" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " URXFUL ,U channel receive register full interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RXFIFOUNOV ,RX FIFO underrun/overrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " RXFIFORESYN ,RX FIFO resync interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0 1. " TXEM ,SPDIF transmit FIFO empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF receive FIFO full interrupt enable" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "SIS/SIC,Interrupt Status Register" sif (cpu()=="IMX6SOLOLITE")||(cpu()=="IMX6SLL") setclrfld.long 0x00 20. 0x00 20. 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt enable" "No interrupt,Interrupt" setclrfld.long 0x00 19. 0x00 19. 0x00 19. " TXUNOV ,SPDIF transmit FIFO under/overrun interrupt enable" "No interrupt,Interrupt" newline setclrfld.long 0x00 18. 0x00 18. 0x00 18. " TXRESYN ,SPDIF transmit FIFO resync interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 17. 0x00 17. 0x00 17. " CNEW ,SPDIF receive change in value of control channel" "No interrupt,Interrupt" newline setclrfld.long 0x00 16. 0x00 16. 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt enable" "No interrupt,Interrupt" setclrfld.long 0x00 15. 0x00 15. 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt enable" "No interrupt,Interrupt" newline setclrfld.long 0x00 14. 0x00 14. 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt enable" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x00 10. 0x00 10. " URXFUL ,U channel receive register full interrupt enable" "No interrupt,Interrupt" newline setclrfld.long 0x00 9. 0x00 9. 0x00 9. " URXOV ,U channel receive register overrun interrupt enable" "No interrupt,Interrupt" rbitfld.long 0x00 8. " QRXFUL ,Q channel receive register full interrupt enable" "No interrupt,Interrupt" newline setclrfld.long 0x00 7. 0x00 7. 0x00 7. " QRXOV ,Q channel receive register overrun interrupt enable" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x00 6. 0x00 6. " UQSYNC ,U/Q channel sync found interrupt enable" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x00 5. 0x00 5. " UQERR ,U/Q channel framing error interrupt enable" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x00 4. 0x00 4. " RXFIFOUNOV ,RX FIFO underrun/overrun interrupt enable" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x00 3. 0x00 3. " RXFIFORESYN ,RX FIFO resync interrupt enable" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x00 2. 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt enable" "No interrupt,Interrupt" newline rbitfld.long 0x00 1. " TXEM ,SPDIF transmit FIFO empty interrupt enable" "No interrupt,Interrupt" rbitfld.long 0x00 0. " RXFIFOFUL ,SPDIF RX FIFO full interrupt enable" "No interrupt,Interrupt" else bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt enable" "No interrupt,Interrupt" bitfld.long 0x00 19. " TXUNOV ,SPDIF transmit FIFO under/overrun interrupt enable" "No interrupt,Interrupt" newline bitfld.long 0x00 18. " TXRESYN ,SPDIF transmit FIFO resync interrupt" "No interrupt,Interrupt" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt enable" "No interrupt,Interrupt" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt enable" "No interrupt,Interrupt" newline bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt enable" "No interrupt,Interrupt" bitfld.long 0x00 10. " URXFUL ,U channel receive register full interrupt enable" "No interrupt,Interrupt" newline bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt enable" "No interrupt,Interrupt" rbitfld.long 0x00 8. " QRXFUL ,Q channel receive register full interrupt enable" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt enable" "No interrupt,Interrupt" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt enable" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt enable" "No interrupt,Interrupt" bitfld.long 0x00 4. " RXFIFOUNOV ,RX FIFO underrun/overrun interrupt enable" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " RXFIFORESYN ,RX FIFO resync interrupt enable" "No interrupt,Interrupt" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt enable" "No interrupt,Interrupt" newline rbitfld.long 0x00 1. " TXEM ,SPDIF transmit FIFO empty interrupt enable" "No interrupt,Interrupt" rbitfld.long 0x00 0. " RXFIFOFUL ,SPDIF RX FIFO full interrupt enable" "No interrupt,Interrupt" endif rgroup.long 0x14++0x0F line.long 0x00 "SRL,SPDIF Rx Left Register" hexmask.long.tbyte 0x00 0.--23. 1. " RXDATA_L ,Processor receive SPDIF data left" line.long 0x04 "SRR,SPDIF Rx Right Register" hexmask.long.tbyte 0x04 0.--23. 1. " RXDATA_R ,Processor receive SPDIF data right" line.long 0x08 "SRCSH,SPDIF RxC Channel_h Register" hexmask.long.tbyte 0x08 0.--23. 1. " RXCCH_H ,SPDIF receive C channel register (high bits)" line.long 0x0C "SRCSL,SPDIF RxC Channel_l Register" hexmask.long.tbyte 0x0C 0.--23. 1. " RXCCH_L ,SPDIF receive C channel register (low bits)" sif (cpu()=="IMX6SLL") rgroup.long 0x24++0x07 line.long 0x00 "SRU,U Channel Rx Register" hexmask.long.tbyte 0x00 0.--23. 0x01 " RXUCHANNEL ,Contains next 3 U channel bytes" line.long 0x04 "SRU,U Channel Rx Register" hexmask.long.tbyte 0x04 0.--23. 0x01 " RXQCHANNEL ,Contains next 3 Q channel bytes" else hgroup.long 0x24++0x03 hide.long 0x00 "SRU,U Channel Rx Register" in hgroup.long 0x28++0x03 hide.long 0x00 "SRQ,Q Channel Rx Register" in endif wgroup.long 0x2C++0x07 line.long 0x00 "STL,SPDIF Left Channel Data Transmitter" hexmask.long.tbyte 0x00 0.--23. 1. " TXDATALEFT ,SPDIF transmit left channel data" line.long 0x04 "STR,SPDIF Right Channel Data Transmitter" hexmask.long.tbyte 0x04 0.--23. 1. " TXDATARIGHT ,SPDIF transmit right channel data" group.long 0x34++0x07 line.long 0x0 "STCSCH,SPDIF Tx Consumer Channel Status High Register" hexmask.long.tbyte 0x00 0.--23. 1. " TXCCHANNELCONS_H ,SPDIF transmit Cons. C channel data" line.long 0x04 "STCSCL,SPDIF Tx Consumer Channel Status Low Register" hexmask.long.tbyte 0x04 0.--23. 1. " TXCCHANNELCONS_L ,SPDIF transmit Cons. C channel data" rgroup.long 0x44++0x03 line.long 0x00 "SRFM,Frequency Measurement Data Register" hexmask.long.tbyte 0x00 0.--23. 1. " FREQ_MEAS ,Frequency measurement data" group.long 0x50++0x03 line.long 0x00 "STC,Transmit Clock Control Register" hexmask.long.word 0x00 11.--19. 1. " SYSCLK_DF ,System clock divider factor 2-512" newline sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE") sif (cpu()=="IMX6SOLOLITE")||(cpu()=="IMX6SLL") bitfld.long 0x00 8.--10. " TXCLK_SOURCE ,Tx clock source" "REF_CLK_32K,TX_CLK,,SPDIF_EXT_CLK,,IPG_CLK,?..." newline else bitfld.long 0x00 8.--10. " TXCLK_SOURCE ,Tx clock source" "XTAL clk,CCM spidf0_clk_root,Asrc_clk,Spdif_extclk,Esai_hckt,Frequency divider ipg_clk,Mlb_clk,Mlb phy clk" newline endif bitfld.long 0x00 7. " TX_ALL_CLK_EN ,Spdif transfer clock enable" "Disabled,Enabled" newline endif hexmask.long.byte 0x00 0.--6. 1. " TXCLK_DF ,Divider factor (1-128)" width 0x0B tree.end tree "SRC (System Reset Controller)" base ad:0x020D80000 width 7. group.long 0x00++0x03 line.long 0x00 "SCR,System Reset Controller" bitfld.long 0x00 28.--31. " MASK_WDOG3_RST ,Mask wdog3_rst_b source" ",,,,,Masked,,,,,Not masked,?..." bitfld.long 0x00 26.--27. " MIX_RST_STRCH ,SoC mix reset width" "88 ipg_cycle,2 * 88 ipg_cycle,3 * 88 ipg_cycle,4 * 88 ipg_cycle" newline bitfld.long 0x00 25. " DBG_RST_MSK_PG ,Debug reset mask" "Not masked,Masked" bitfld.long 0x00 24. " WDOG3_RST_OPTN ,Wdog3_rst_b option" "M4,Global" newline bitfld.long 0x00 21. " CORES_DBG_RST ,Software reset for debug of arm platform only" "Not asserted,Asserted" bitfld.long 0x00 17. " CORE0_DBG_RST ,Software reset for core0 debug only" "Not asserted,Asserted" newline bitfld.long 0x00 13. " CORE0_RST ,Software reset for core0 only" "Not asserted,Asserted" bitfld.long 0x00 11. " EIM_RST ,EIM Reset" "No reset,Reset" newline bitfld.long 0x00 7.--10. " MASK_WDOG_RST ,Mask wdog_rst_b source" ",,,,,Masked,,,,,Not masked,?..." bitfld.long 0x00 5.--6. " WARM_RST_BYPASS_COUNT ,XTALI cycles to count before bypassing the MMDC ack for warm reset" "Disabled,16 XTALI,32 XTALI,64 XTALI" newline bitfld.long 0x00 0. " WARM_RESET_ENABLE ,Warm reset enable bit" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SBMR,SRC Boot Mode Register" hexmask.long.byte 0x00 24.--31. 1. " BOOT_CFG4 ,Boot configuration4" hexmask.long.byte 0x00 16.--23. 1. " BOOT_CFG3 ,Boot configuration3" newline hexmask.long.byte 0x00 8.--15. 1. " BOOT_CFG2 ,Boot configuration2" hexmask.long.byte 0x00 0.--7. 1. " BOOT_CFG1 ,Boot configuration1" group.long 0x08++0x03 line.long 0x00 "SRSR,SRC Reset Status Register" bitfld.long 0x00 16. " WARM_BOOT ,Warm boot indication" "Not initiated,Initiated" bitfld.long 0x00 8. " TEMPENSE_RST_B ,Temper Sensor software reset" "Not software,Software" newline eventfld.long 0x00 7. " WDOG3_RST_B ,IC Watchdog3 Time-out reset" "Not WD time-out,WD time-out" eventfld.long 0x00 6. " JTAG_SW_RST ,Reset via JTAG SW" "Not software,Software" newline eventfld.long 0x00 5. " JTAG_RST_B ,Reset via HIGH-Z JTAG" "Not HIGH-Z,HIGH-Z" eventfld.long 0x00 4. " WDOG_RST_B ,IC Watchdog Time-out reset" "Not WD time-out,WD time-out" newline eventfld.long 0x00 3. " IPP_USER_RESET_B ,Reset via ipp_user_reset_b qualified" "Not ipp_user_reset_b,Ipp_user_reset_b" eventfld.long 0x00 2. " CSU_RESET_B ,Reset via csu_reset_b qualified" "Not csu_reset_b,csu_reset_b" newline eventfld.long 0x00 0. " IPP_RESET_B ,Reset via ipp_reset_b pin" "Not ipp_reset_b,Ipp_reset_b" rgroup.long 0x014++0x03 line.long 0x00 "SISR,SRC Interrupt Status Register" bitfld.long 0x00 5. " CORE0_WDOG_RST_REQ ,Watchdog reset request from CPU core0" "Not requested,Requested" rgroup.long 0x1C++0x03 line.long 0x00 "SBMR2,SRC Boot Mode Register 2" bitfld.long 0x00 24.--25. " BMOD ,Boot mode" "0,1,2,3" bitfld.long 0x00 4. " BT_FUSE_SEL ,Boot fuse selection" "0,1" newline bitfld.long 0x00 3. " DIR_BT_DIS ,DIR_BT_DIS fuse state" "0,1" bitfld.long 0x00 1. " SEC_CONFIG[1] ,SEC_CONFIG[1] fuse state" "0,1" newline bitfld.long 0x00 0. " SEC_CONFIG[0] ,SEC_CONFIG[0] fuse state" "0,1" group.long 0x20++0x1F line.long 0x00 "GPR1,SRC General Purpose Register 1" group.long 0x24++0x1F line.long 0x00 "GPR2,SRC General Purpose Register 2" group.long 0x28++0x1F line.long 0x00 "GPR3,SRC General Purpose Register 3" group.long 0x2C++0x1F line.long 0x00 "GPR4,SRC General Purpose Register 4" group.long 0x30++0x1F line.long 0x00 "GPR5,SRC General Purpose Register 5" group.long 0x34++0x1F line.long 0x00 "GPR6,SRC General Purpose Register 6" group.long 0x38++0x1F line.long 0x00 "GPR7,SRC General Purpose Register 7" group.long 0x3C++0x1F line.long 0x00 "GPR8,SRC General Purpose Register 8" group.long 0x44++0x03 line.long 0x00 "GPR10,SRC General Purpose Register 10" hexmask.long.byte 0x00 26.--31. 1. " GPR10[26:31] ,Read/write bits for general purpose" hexmask.long 0x00 0.--24. 1. " GPR10[0:24] ,Read/write bits for general purpose" width 0x0B tree.end tree "SSI (Synchronous Serial Interface)" tree "SSI 1" base ad:0x02028000 width 8. group.long 0x00++0x07 line.long 0x00 "STX0,Transmit Data Register 0" line.long 0x04 "STX1,Transmit Data Register 1" rgroup.long 0x08++0x07 line.long 0x00 "SRX0,Receive Data Register 0" line.long 0x04 "SRX1,Receive Data Register 1" group.long 0x10++0x13 line.long 0x00 "SCR,SSI Control Register" bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched" bitfld.long 0x00 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes" bitfld.long 0x00 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes" bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "0,1" newline bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal" bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected" bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled" line.long 0x04 "SISR,SSI Interrupt Status Register" bitfld.long 0x04 24. " RFRC ,Receive Frame Complete" "Not reached,Reached" bitfld.long 0x04 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached" bitfld.long 0x04 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated" bitfld.long 0x04 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated" newline bitfld.long 0x04 16. " RXT ,Receive Tag Updated" "Not updated,Updated" bitfld.long 0x04 15. " RDR1 ,Receive Data Ready 1" "No new data,New data" bitfld.long 0x04 14. " RDR0 ,Receive Data Ready 0" "No new data,New data" bitfld.long 0x04 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty" newline bitfld.long 0x04 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty" eventfld.long 0x04 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error" eventfld.long 0x04 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error" eventfld.long 0x04 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error" newline eventfld.long 0x04 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error" bitfld.long 0x04 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 5. " TLS ,Transmit Last Time Slot" "No,Yes" newline bitfld.long 0x04 4. " RLS ,Receive Last Time Slot" "No,Yes" bitfld.long 0x04 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full" bitfld.long 0x04 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full" bitfld.long 0x04 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty" newline bitfld.long 0x04 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty" line.long 0x08 "SIER,SSI Interrupt Enable Register" bitfld.long 0x08 24. " RFRCIE ,Receive Frame Complete" "Disabled,Enabled" bitfld.long 0x08 23. " TFRCIE ,Transmit Frame Complete" "Disabled,Enabled" bitfld.long 0x08 22. " RDMAE ,SSI Receiver DMA requests" "Disabled,Enabled" bitfld.long 0x08 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x08 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " CMDAUIE ,Command Address Register Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 17. " CMDDUIE ,Command Data Register Updated Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RXTIE ,Receive Tag Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 15. " RDR1IE ,Receive Data Ready 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 14. " RDR0IE ,Receive Data Ready 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 13. " TDE1IE ,Transmit Data Register Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " TDE0IE ,Transmit Data Register Empty 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 11. " ROE1IE ,Receiver Overrun Error 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ROE0IE ,Receiver Overrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 9. " TUE1IE ,Transmitter Underrun Error 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " TUE0IE ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " TFSIE ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 6. " RFSIE ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x08 5. " TLSIE ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " RLSIE ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 3. " RFF1IE ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " RFF0IE ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " TFE1IE ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled" line.long 0x0C "STCR,SSI Transmit Configuration Register" bitfld.long 0x0C 9. " TXBIT0 ,Transmit Bit 0" "MSB,LSB" bitfld.long 0x0C 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x0C 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled" bitfld.long 0x0C 6. " TFDIR ,Transmit Frame Direction" "External,Internal" newline bitfld.long 0x0C 5. " TXDIR ,Transmit Clock Direction" "External,Internal" bitfld.long 0x0C 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first" bitfld.long 0x0C 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x0C 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low" newline bitfld.long 0x0C 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x0C 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before" line.long 0x10 "SRCR,SSI Receive Configuration Register" bitfld.long 0x10 10. " RXEXT ,Receive Data Extension" "Not extended,Extended" bitfld.long 0x10 9. " RXBIT0 ,Receive Bit 0" "MSB,LSB" bitfld.long 0x10 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x10 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled" newline bitfld.long 0x10 6. " RFDIR ,Receive Frame Direction" "External,Internal" bitfld.long 0x10 5. " RXDIR ,Receive Clock Direction" "External,Internal" bitfld.long 0x10 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first" bitfld.long 0x10 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge" newline bitfld.long 0x10 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low" bitfld.long 0x10 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x10 0. " REFS ,Receive Early Frame Sync" "First bit,One before" if (((per.l(ad:0x02028000+0x10))&0x08)==0x08) group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" else group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" endif group.long 0x2C++0x03 line.long 0x00 "SFCSR,SSI FIFO Control/Status Register" bitfld.long 0x00 28.--31. " RFCNT1 ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TFCNT1 ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RFWM1 ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 16.--19. " TFWM1 ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" newline bitfld.long 0x00 12.--15. " RFCNT0 ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFCNT0 ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RFWM0 ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 0.--3. " TFWM0 ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" group.long 0x38++0x17 line.long 0x00 "SACNT,SSI AC97 Control Register" hexmask.long.byte 0x00 5.--10. 1. " FRDIV ,Frame Rate Divider" bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached" bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached" bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0" newline bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable" bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled" line.long 0x04 "SACADD,SSI AC97 Command Address Register" hexmask.long.tbyte 0x04 0.--18. 0x01 " SACADD ,AC97 Command Address" line.long 0x08 "SACDAT,SSI AC97 Command Data Register" hexmask.long.tbyte 0x08 0.--19. 1. " SACDAT ,AC97 Command Data" line.long 0x0C "SATAG,SSI AC97 Tag Register" hexmask.long.word 0x0C 0.--15. 1. " SATAG ,AC97 Tag Value" line.long 0x10 "STMSK,SSI Transmit Time Slot Mask Register" bitfld.long 0x10 31. " STMSK ,Transmit Mask Bit 31" "0,1" bitfld.long 0x10 30. ",Transmit Mask Bit 30" "0,1" bitfld.long 0x10 29. ",Transmit Mask Bit 29" "0,1" bitfld.long 0x10 28. ",Transmit Mask Bit 28" "0,1" bitfld.long 0x10 27. ",Transmit Mask Bit 27" "0,1" bitfld.long 0x10 26. ",Transmit Mask Bit 26" "0,1" bitfld.long 0x10 25. ",Transmit Mask Bit 25" "0,1" bitfld.long 0x10 24. ",Transmit Mask Bit 24" "0,1" bitfld.long 0x10 23. ",Transmit Mask Bit 23" "0,1" bitfld.long 0x10 22. ",Transmit Mask Bit 22" "0,1" bitfld.long 0x10 21. ",Transmit Mask Bit 21" "0,1" bitfld.long 0x10 20. ",Transmit Mask Bit 20" "0,1" bitfld.long 0x10 19. ",Transmit Mask Bit 19" "0,1" bitfld.long 0x10 18. ",Transmit Mask Bit 18" "0,1" bitfld.long 0x10 17. ",Transmit Mask Bit 17" "0,1" bitfld.long 0x10 16. ",Transmit Mask Bit 16" "0,1" bitfld.long 0x10 15. ",Transmit Mask Bit 15" "0,1" bitfld.long 0x10 14. ",Transmit Mask Bit 14" "0,1" bitfld.long 0x10 13. ",Transmit Mask Bit 13" "0,1" bitfld.long 0x10 12. ",Transmit Mask Bit 12" "0,1" bitfld.long 0x10 11. ",Transmit Mask Bit 11" "0,1" bitfld.long 0x10 10. ",Transmit Mask Bit 10" "0,1" bitfld.long 0x10 9. ",Transmit Mask Bit 9" "0,1" bitfld.long 0x10 8. ",Transmit Mask Bit 8" "0,1" bitfld.long 0x10 7. ",Transmit Mask Bit 7" "0,1" bitfld.long 0x10 6. ",Transmit Mask Bit 6" "0,1" bitfld.long 0x10 5. ",Transmit Mask Bit 5" "0,1" bitfld.long 0x10 4. ",Transmit Mask Bit 4" "0,1" bitfld.long 0x10 3. ",Transmit Mask Bit 3" "0,1" bitfld.long 0x10 2. ",Transmit Mask Bit 2" "0,1" bitfld.long 0x10 1. ",Transmit Mask Bit 1" "0,1" bitfld.long 0x10 0. ",Transmit Mask Bit 0" "0,1" line.long 0x14 "SRMSK,SSI Receive Time Slot Mask Register" bitfld.long 0x14 31. " SRMSK ,Receive Mask Bit 31" "0,1" bitfld.long 0x14 30. ",Receive Mask Bit 30" "0,1" bitfld.long 0x14 29. ",Receive Mask Bit 29" "0,1" bitfld.long 0x14 28. ",Receive Mask Bit 28" "0,1" bitfld.long 0x14 27. ",Receive Mask Bit 27" "0,1" bitfld.long 0x14 26. ",Receive Mask Bit 26" "0,1" bitfld.long 0x14 25. ",Receive Mask Bit 25" "0,1" bitfld.long 0x14 24. ",Receive Mask Bit 24" "0,1" bitfld.long 0x14 23. ",Receive Mask Bit 23" "0,1" bitfld.long 0x14 22. ",Receive Mask Bit 22" "0,1" bitfld.long 0x14 21. ",Receive Mask Bit 21" "0,1" bitfld.long 0x14 20. ",Receive Mask Bit 20" "0,1" bitfld.long 0x14 19. ",Receive Mask Bit 19" "0,1" bitfld.long 0x14 18. ",Receive Mask Bit 18" "0,1" bitfld.long 0x14 17. ",Receive Mask Bit 17" "0,1" bitfld.long 0x14 16. ",Receive Mask Bit 16" "0,1" bitfld.long 0x14 15. ",Receive Mask Bit 15" "0,1" bitfld.long 0x14 14. ",Receive Mask Bit 14" "0,1" bitfld.long 0x14 13. ",Receive Mask Bit 13" "0,1" bitfld.long 0x14 12. ",Receive Mask Bit 12" "0,1" bitfld.long 0x14 11. ",Receive Mask Bit 11" "0,1" bitfld.long 0x14 10. ",Receive Mask Bit 10" "0,1" bitfld.long 0x14 9. ",Receive Mask Bit 9" "0,1" bitfld.long 0x14 8. ",Receive Mask Bit 8" "0,1" bitfld.long 0x14 7. ",Receive Mask Bit 7" "0,1" bitfld.long 0x14 6. ",Receive Mask Bit 6" "0,1" bitfld.long 0x14 5. ",Receive Mask Bit 5" "0,1" bitfld.long 0x14 4. ",Receive Mask Bit 4" "0,1" bitfld.long 0x14 3. ",Receive Mask Bit 3" "0,1" bitfld.long 0x14 2. ",Receive Mask Bit 2" "0,1" bitfld.long 0x14 1. ",Receive Mask Bit 1" "0,1" bitfld.long 0x14 0. ",Receive Mask Bit 0" "0,1" newline width 16. group.long 0x50++0x03 line.long 0x00 "SACCST_SET/CLR,SSI AC97 Channel SET/CLR Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SACCST9_SET/CLR ,AC97 Channel Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SACCST8_SET/CLR ,AC97 Channel Status 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SACCST7_SET/CLR ,AC97 Channel Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SACCST6_SET/CLR ,AC97 Channel Status 6" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SACCST5_SET/CLR ,AC97 Channel Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SACCST4_SET/CLR ,AC97 Channel Status 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SACCST3_SET/CLR ,AC97 Channel Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SACCST2_SET/CLR ,AC97 Channel Status 2" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SACCST1_SET/CLR ,AC97 Channel Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SACCST0_SET/CLR ,AC97 Channel Status 0" "Disabled,Enabled" width 0x0B tree.end tree "SSI 2" base ad:0x0202C000 width 8. group.long 0x00++0x07 line.long 0x00 "STX0,Transmit Data Register 0" line.long 0x04 "STX1,Transmit Data Register 1" rgroup.long 0x08++0x07 line.long 0x00 "SRX0,Receive Data Register 0" line.long 0x04 "SRX1,Receive Data Register 1" group.long 0x10++0x13 line.long 0x00 "SCR,SSI Control Register" bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched" bitfld.long 0x00 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes" bitfld.long 0x00 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes" bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "0,1" newline bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal" bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected" bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled" line.long 0x04 "SISR,SSI Interrupt Status Register" bitfld.long 0x04 24. " RFRC ,Receive Frame Complete" "Not reached,Reached" bitfld.long 0x04 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached" bitfld.long 0x04 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated" bitfld.long 0x04 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated" newline bitfld.long 0x04 16. " RXT ,Receive Tag Updated" "Not updated,Updated" bitfld.long 0x04 15. " RDR1 ,Receive Data Ready 1" "No new data,New data" bitfld.long 0x04 14. " RDR0 ,Receive Data Ready 0" "No new data,New data" bitfld.long 0x04 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty" newline bitfld.long 0x04 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty" eventfld.long 0x04 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error" eventfld.long 0x04 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error" eventfld.long 0x04 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error" newline eventfld.long 0x04 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error" bitfld.long 0x04 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 5. " TLS ,Transmit Last Time Slot" "No,Yes" newline bitfld.long 0x04 4. " RLS ,Receive Last Time Slot" "No,Yes" bitfld.long 0x04 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full" bitfld.long 0x04 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full" bitfld.long 0x04 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty" newline bitfld.long 0x04 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty" line.long 0x08 "SIER,SSI Interrupt Enable Register" bitfld.long 0x08 24. " RFRCIE ,Receive Frame Complete" "Disabled,Enabled" bitfld.long 0x08 23. " TFRCIE ,Transmit Frame Complete" "Disabled,Enabled" bitfld.long 0x08 22. " RDMAE ,SSI Receiver DMA requests" "Disabled,Enabled" bitfld.long 0x08 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x08 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " CMDAUIE ,Command Address Register Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 17. " CMDDUIE ,Command Data Register Updated Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RXTIE ,Receive Tag Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 15. " RDR1IE ,Receive Data Ready 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 14. " RDR0IE ,Receive Data Ready 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 13. " TDE1IE ,Transmit Data Register Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " TDE0IE ,Transmit Data Register Empty 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 11. " ROE1IE ,Receiver Overrun Error 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ROE0IE ,Receiver Overrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 9. " TUE1IE ,Transmitter Underrun Error 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " TUE0IE ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " TFSIE ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 6. " RFSIE ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x08 5. " TLSIE ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " RLSIE ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 3. " RFF1IE ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " RFF0IE ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " TFE1IE ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled" line.long 0x0C "STCR,SSI Transmit Configuration Register" bitfld.long 0x0C 9. " TXBIT0 ,Transmit Bit 0" "MSB,LSB" bitfld.long 0x0C 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x0C 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled" bitfld.long 0x0C 6. " TFDIR ,Transmit Frame Direction" "External,Internal" newline bitfld.long 0x0C 5. " TXDIR ,Transmit Clock Direction" "External,Internal" bitfld.long 0x0C 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first" bitfld.long 0x0C 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x0C 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low" newline bitfld.long 0x0C 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x0C 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before" line.long 0x10 "SRCR,SSI Receive Configuration Register" bitfld.long 0x10 10. " RXEXT ,Receive Data Extension" "Not extended,Extended" bitfld.long 0x10 9. " RXBIT0 ,Receive Bit 0" "MSB,LSB" bitfld.long 0x10 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x10 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled" newline bitfld.long 0x10 6. " RFDIR ,Receive Frame Direction" "External,Internal" bitfld.long 0x10 5. " RXDIR ,Receive Clock Direction" "External,Internal" bitfld.long 0x10 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first" bitfld.long 0x10 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge" newline bitfld.long 0x10 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low" bitfld.long 0x10 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x10 0. " REFS ,Receive Early Frame Sync" "First bit,One before" if (((per.l(ad:0x0202C000+0x10))&0x08)==0x08) group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" else group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" endif group.long 0x2C++0x03 line.long 0x00 "SFCSR,SSI FIFO Control/Status Register" bitfld.long 0x00 28.--31. " RFCNT1 ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TFCNT1 ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RFWM1 ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 16.--19. " TFWM1 ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" newline bitfld.long 0x00 12.--15. " RFCNT0 ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFCNT0 ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RFWM0 ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 0.--3. " TFWM0 ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" group.long 0x38++0x17 line.long 0x00 "SACNT,SSI AC97 Control Register" hexmask.long.byte 0x00 5.--10. 1. " FRDIV ,Frame Rate Divider" bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached" bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached" bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0" newline bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable" bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled" line.long 0x04 "SACADD,SSI AC97 Command Address Register" hexmask.long.tbyte 0x04 0.--18. 0x01 " SACADD ,AC97 Command Address" line.long 0x08 "SACDAT,SSI AC97 Command Data Register" hexmask.long.tbyte 0x08 0.--19. 1. " SACDAT ,AC97 Command Data" line.long 0x0C "SATAG,SSI AC97 Tag Register" hexmask.long.word 0x0C 0.--15. 1. " SATAG ,AC97 Tag Value" line.long 0x10 "STMSK,SSI Transmit Time Slot Mask Register" bitfld.long 0x10 31. " STMSK ,Transmit Mask Bit 31" "0,1" bitfld.long 0x10 30. ",Transmit Mask Bit 30" "0,1" bitfld.long 0x10 29. ",Transmit Mask Bit 29" "0,1" bitfld.long 0x10 28. ",Transmit Mask Bit 28" "0,1" bitfld.long 0x10 27. ",Transmit Mask Bit 27" "0,1" bitfld.long 0x10 26. ",Transmit Mask Bit 26" "0,1" bitfld.long 0x10 25. ",Transmit Mask Bit 25" "0,1" bitfld.long 0x10 24. ",Transmit Mask Bit 24" "0,1" bitfld.long 0x10 23. ",Transmit Mask Bit 23" "0,1" bitfld.long 0x10 22. ",Transmit Mask Bit 22" "0,1" bitfld.long 0x10 21. ",Transmit Mask Bit 21" "0,1" bitfld.long 0x10 20. ",Transmit Mask Bit 20" "0,1" bitfld.long 0x10 19. ",Transmit Mask Bit 19" "0,1" bitfld.long 0x10 18. ",Transmit Mask Bit 18" "0,1" bitfld.long 0x10 17. ",Transmit Mask Bit 17" "0,1" bitfld.long 0x10 16. ",Transmit Mask Bit 16" "0,1" bitfld.long 0x10 15. ",Transmit Mask Bit 15" "0,1" bitfld.long 0x10 14. ",Transmit Mask Bit 14" "0,1" bitfld.long 0x10 13. ",Transmit Mask Bit 13" "0,1" bitfld.long 0x10 12. ",Transmit Mask Bit 12" "0,1" bitfld.long 0x10 11. ",Transmit Mask Bit 11" "0,1" bitfld.long 0x10 10. ",Transmit Mask Bit 10" "0,1" bitfld.long 0x10 9. ",Transmit Mask Bit 9" "0,1" bitfld.long 0x10 8. ",Transmit Mask Bit 8" "0,1" bitfld.long 0x10 7. ",Transmit Mask Bit 7" "0,1" bitfld.long 0x10 6. ",Transmit Mask Bit 6" "0,1" bitfld.long 0x10 5. ",Transmit Mask Bit 5" "0,1" bitfld.long 0x10 4. ",Transmit Mask Bit 4" "0,1" bitfld.long 0x10 3. ",Transmit Mask Bit 3" "0,1" bitfld.long 0x10 2. ",Transmit Mask Bit 2" "0,1" bitfld.long 0x10 1. ",Transmit Mask Bit 1" "0,1" bitfld.long 0x10 0. ",Transmit Mask Bit 0" "0,1" line.long 0x14 "SRMSK,SSI Receive Time Slot Mask Register" bitfld.long 0x14 31. " SRMSK ,Receive Mask Bit 31" "0,1" bitfld.long 0x14 30. ",Receive Mask Bit 30" "0,1" bitfld.long 0x14 29. ",Receive Mask Bit 29" "0,1" bitfld.long 0x14 28. ",Receive Mask Bit 28" "0,1" bitfld.long 0x14 27. ",Receive Mask Bit 27" "0,1" bitfld.long 0x14 26. ",Receive Mask Bit 26" "0,1" bitfld.long 0x14 25. ",Receive Mask Bit 25" "0,1" bitfld.long 0x14 24. ",Receive Mask Bit 24" "0,1" bitfld.long 0x14 23. ",Receive Mask Bit 23" "0,1" bitfld.long 0x14 22. ",Receive Mask Bit 22" "0,1" bitfld.long 0x14 21. ",Receive Mask Bit 21" "0,1" bitfld.long 0x14 20. ",Receive Mask Bit 20" "0,1" bitfld.long 0x14 19. ",Receive Mask Bit 19" "0,1" bitfld.long 0x14 18. ",Receive Mask Bit 18" "0,1" bitfld.long 0x14 17. ",Receive Mask Bit 17" "0,1" bitfld.long 0x14 16. ",Receive Mask Bit 16" "0,1" bitfld.long 0x14 15. ",Receive Mask Bit 15" "0,1" bitfld.long 0x14 14. ",Receive Mask Bit 14" "0,1" bitfld.long 0x14 13. ",Receive Mask Bit 13" "0,1" bitfld.long 0x14 12. ",Receive Mask Bit 12" "0,1" bitfld.long 0x14 11. ",Receive Mask Bit 11" "0,1" bitfld.long 0x14 10. ",Receive Mask Bit 10" "0,1" bitfld.long 0x14 9. ",Receive Mask Bit 9" "0,1" bitfld.long 0x14 8. ",Receive Mask Bit 8" "0,1" bitfld.long 0x14 7. ",Receive Mask Bit 7" "0,1" bitfld.long 0x14 6. ",Receive Mask Bit 6" "0,1" bitfld.long 0x14 5. ",Receive Mask Bit 5" "0,1" bitfld.long 0x14 4. ",Receive Mask Bit 4" "0,1" bitfld.long 0x14 3. ",Receive Mask Bit 3" "0,1" bitfld.long 0x14 2. ",Receive Mask Bit 2" "0,1" bitfld.long 0x14 1. ",Receive Mask Bit 1" "0,1" bitfld.long 0x14 0. ",Receive Mask Bit 0" "0,1" newline width 16. group.long 0x50++0x03 line.long 0x00 "SACCST_SET/CLR,SSI AC97 Channel SET/CLR Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SACCST9_SET/CLR ,AC97 Channel Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SACCST8_SET/CLR ,AC97 Channel Status 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SACCST7_SET/CLR ,AC97 Channel Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SACCST6_SET/CLR ,AC97 Channel Status 6" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SACCST5_SET/CLR ,AC97 Channel Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SACCST4_SET/CLR ,AC97 Channel Status 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SACCST3_SET/CLR ,AC97 Channel Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SACCST2_SET/CLR ,AC97 Channel Status 2" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SACCST1_SET/CLR ,AC97 Channel Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SACCST0_SET/CLR ,AC97 Channel Status 0" "Disabled,Enabled" width 0x0B tree.end tree "SSI 3" base ad:0x02030000 width 8. group.long 0x00++0x07 line.long 0x00 "STX0,Transmit Data Register 0" line.long 0x04 "STX1,Transmit Data Register 1" rgroup.long 0x08++0x07 line.long 0x00 "SRX0,Receive Data Register 0" line.long 0x04 "SRX1,Receive Data Register 1" group.long 0x10++0x13 line.long 0x00 "SCR,SSI Control Register" bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched" bitfld.long 0x00 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes" bitfld.long 0x00 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes" bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "0,1" newline bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled" bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal" bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected" bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled" line.long 0x04 "SISR,SSI Interrupt Status Register" bitfld.long 0x04 24. " RFRC ,Receive Frame Complete" "Not reached,Reached" bitfld.long 0x04 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached" bitfld.long 0x04 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated" bitfld.long 0x04 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated" newline bitfld.long 0x04 16. " RXT ,Receive Tag Updated" "Not updated,Updated" bitfld.long 0x04 15. " RDR1 ,Receive Data Ready 1" "No new data,New data" bitfld.long 0x04 14. " RDR0 ,Receive Data Ready 0" "No new data,New data" bitfld.long 0x04 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty" newline bitfld.long 0x04 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty" eventfld.long 0x04 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error" eventfld.long 0x04 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error" eventfld.long 0x04 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error" newline eventfld.long 0x04 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error" bitfld.long 0x04 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred" bitfld.long 0x04 5. " TLS ,Transmit Last Time Slot" "No,Yes" newline bitfld.long 0x04 4. " RLS ,Receive Last Time Slot" "No,Yes" bitfld.long 0x04 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full" bitfld.long 0x04 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full" bitfld.long 0x04 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty" newline bitfld.long 0x04 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty" line.long 0x08 "SIER,SSI Interrupt Enable Register" bitfld.long 0x08 24. " RFRCIE ,Receive Frame Complete" "Disabled,Enabled" bitfld.long 0x08 23. " TFRCIE ,Transmit Frame Complete" "Disabled,Enabled" bitfld.long 0x08 22. " RDMAE ,SSI Receiver DMA requests" "Disabled,Enabled" bitfld.long 0x08 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x08 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " CMDAUIE ,Command Address Register Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 17. " CMDDUIE ,Command Data Register Updated Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RXTIE ,Receive Tag Updated Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 15. " RDR1IE ,Receive Data Ready 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 14. " RDR0IE ,Receive Data Ready 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 13. " TDE1IE ,Transmit Data Register Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " TDE0IE ,Transmit Data Register Empty 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 11. " ROE1IE ,Receiver Overrun Error 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 10. " ROE0IE ,Receiver Overrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 9. " TUE1IE ,Transmitter Underrun Error 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " TUE0IE ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " TFSIE ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 6. " RFSIE ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x08 5. " TLSIE ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " RLSIE ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 3. " RFF1IE ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " RFF0IE ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 1. " TFE1IE ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled" line.long 0x0C "STCR,SSI Transmit Configuration Register" bitfld.long 0x0C 9. " TXBIT0 ,Transmit Bit 0" "MSB,LSB" bitfld.long 0x0C 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x0C 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled" bitfld.long 0x0C 6. " TFDIR ,Transmit Frame Direction" "External,Internal" newline bitfld.long 0x0C 5. " TXDIR ,Transmit Clock Direction" "External,Internal" bitfld.long 0x0C 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first" bitfld.long 0x0C 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x0C 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low" newline bitfld.long 0x0C 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x0C 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before" line.long 0x10 "SRCR,SSI Receive Configuration Register" bitfld.long 0x10 10. " RXEXT ,Receive Data Extension" "Not extended,Extended" bitfld.long 0x10 9. " RXBIT0 ,Receive Bit 0" "MSB,LSB" bitfld.long 0x10 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled" bitfld.long 0x10 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled" newline bitfld.long 0x10 6. " RFDIR ,Receive Frame Direction" "External,Internal" bitfld.long 0x10 5. " RXDIR ,Receive Clock Direction" "External,Internal" bitfld.long 0x10 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first" bitfld.long 0x10 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge" newline bitfld.long 0x10 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low" bitfld.long 0x10 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit" bitfld.long 0x10 0. " REFS ,Receive Early Frame Sync" "First bit,One before" if (((per.l(ad:0x02030000+0x10))&0x08)==0x08) group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" else group.long 0x24++0x07 line.long 0x00 "STCCR,SSI Transmit Clock Control Register" bitfld.long 0x00 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x00 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x00 13.--16. " WL3_WL0 ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32" bitfld.long 0x00 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x00 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" line.long 0x04 "SRCCR,SSI Receive Clock Control Register" bitfld.long 0x04 18. " DIV2 ,Divide By 2" "Bypassed,/2" bitfld.long 0x04 17. " PSR ,Prescaler Range" "Bypassed,/8" bitfld.long 0x04 13.--16. " WL3_WL0 ,Word Length Control" ",,,8,10,12,,16,18,20,22,24,,,," bitfld.long 0x04 8.--12. " DC4_DC0 ,Frame Rate Divider Control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline hexmask.long.byte 0x04 0.--7. 1. " PM7_PM0 ,Prescaler Modulus Select" endif group.long 0x2C++0x03 line.long 0x00 "SFCSR,SSI FIFO Control/Status Register" bitfld.long 0x00 28.--31. " RFCNT1 ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " TFCNT1 ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RFWM1 ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 16.--19. " TFWM1 ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" newline bitfld.long 0x00 12.--15. " RFCNT0 ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFCNT0 ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RFWM0 ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" bitfld.long 0x00 0.--3. " TFWM0 ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15" group.long 0x38++0x17 line.long 0x00 "SACNT,SSI AC97 Control Register" hexmask.long.byte 0x00 5.--10. 1. " FRDIV ,Frame Rate Divider" bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached" bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached" bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0" newline bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable" bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled" line.long 0x04 "SACADD,SSI AC97 Command Address Register" hexmask.long.tbyte 0x04 0.--18. 0x01 " SACADD ,AC97 Command Address" line.long 0x08 "SACDAT,SSI AC97 Command Data Register" hexmask.long.tbyte 0x08 0.--19. 1. " SACDAT ,AC97 Command Data" line.long 0x0C "SATAG,SSI AC97 Tag Register" hexmask.long.word 0x0C 0.--15. 1. " SATAG ,AC97 Tag Value" line.long 0x10 "STMSK,SSI Transmit Time Slot Mask Register" bitfld.long 0x10 31. " STMSK ,Transmit Mask Bit 31" "0,1" bitfld.long 0x10 30. ",Transmit Mask Bit 30" "0,1" bitfld.long 0x10 29. ",Transmit Mask Bit 29" "0,1" bitfld.long 0x10 28. ",Transmit Mask Bit 28" "0,1" bitfld.long 0x10 27. ",Transmit Mask Bit 27" "0,1" bitfld.long 0x10 26. ",Transmit Mask Bit 26" "0,1" bitfld.long 0x10 25. ",Transmit Mask Bit 25" "0,1" bitfld.long 0x10 24. ",Transmit Mask Bit 24" "0,1" bitfld.long 0x10 23. ",Transmit Mask Bit 23" "0,1" bitfld.long 0x10 22. ",Transmit Mask Bit 22" "0,1" bitfld.long 0x10 21. ",Transmit Mask Bit 21" "0,1" bitfld.long 0x10 20. ",Transmit Mask Bit 20" "0,1" bitfld.long 0x10 19. ",Transmit Mask Bit 19" "0,1" bitfld.long 0x10 18. ",Transmit Mask Bit 18" "0,1" bitfld.long 0x10 17. ",Transmit Mask Bit 17" "0,1" bitfld.long 0x10 16. ",Transmit Mask Bit 16" "0,1" bitfld.long 0x10 15. ",Transmit Mask Bit 15" "0,1" bitfld.long 0x10 14. ",Transmit Mask Bit 14" "0,1" bitfld.long 0x10 13. ",Transmit Mask Bit 13" "0,1" bitfld.long 0x10 12. ",Transmit Mask Bit 12" "0,1" bitfld.long 0x10 11. ",Transmit Mask Bit 11" "0,1" bitfld.long 0x10 10. ",Transmit Mask Bit 10" "0,1" bitfld.long 0x10 9. ",Transmit Mask Bit 9" "0,1" bitfld.long 0x10 8. ",Transmit Mask Bit 8" "0,1" bitfld.long 0x10 7. ",Transmit Mask Bit 7" "0,1" bitfld.long 0x10 6. ",Transmit Mask Bit 6" "0,1" bitfld.long 0x10 5. ",Transmit Mask Bit 5" "0,1" bitfld.long 0x10 4. ",Transmit Mask Bit 4" "0,1" bitfld.long 0x10 3. ",Transmit Mask Bit 3" "0,1" bitfld.long 0x10 2. ",Transmit Mask Bit 2" "0,1" bitfld.long 0x10 1. ",Transmit Mask Bit 1" "0,1" bitfld.long 0x10 0. ",Transmit Mask Bit 0" "0,1" line.long 0x14 "SRMSK,SSI Receive Time Slot Mask Register" bitfld.long 0x14 31. " SRMSK ,Receive Mask Bit 31" "0,1" bitfld.long 0x14 30. ",Receive Mask Bit 30" "0,1" bitfld.long 0x14 29. ",Receive Mask Bit 29" "0,1" bitfld.long 0x14 28. ",Receive Mask Bit 28" "0,1" bitfld.long 0x14 27. ",Receive Mask Bit 27" "0,1" bitfld.long 0x14 26. ",Receive Mask Bit 26" "0,1" bitfld.long 0x14 25. ",Receive Mask Bit 25" "0,1" bitfld.long 0x14 24. ",Receive Mask Bit 24" "0,1" bitfld.long 0x14 23. ",Receive Mask Bit 23" "0,1" bitfld.long 0x14 22. ",Receive Mask Bit 22" "0,1" bitfld.long 0x14 21. ",Receive Mask Bit 21" "0,1" bitfld.long 0x14 20. ",Receive Mask Bit 20" "0,1" bitfld.long 0x14 19. ",Receive Mask Bit 19" "0,1" bitfld.long 0x14 18. ",Receive Mask Bit 18" "0,1" bitfld.long 0x14 17. ",Receive Mask Bit 17" "0,1" bitfld.long 0x14 16. ",Receive Mask Bit 16" "0,1" bitfld.long 0x14 15. ",Receive Mask Bit 15" "0,1" bitfld.long 0x14 14. ",Receive Mask Bit 14" "0,1" bitfld.long 0x14 13. ",Receive Mask Bit 13" "0,1" bitfld.long 0x14 12. ",Receive Mask Bit 12" "0,1" bitfld.long 0x14 11. ",Receive Mask Bit 11" "0,1" bitfld.long 0x14 10. ",Receive Mask Bit 10" "0,1" bitfld.long 0x14 9. ",Receive Mask Bit 9" "0,1" bitfld.long 0x14 8. ",Receive Mask Bit 8" "0,1" bitfld.long 0x14 7. ",Receive Mask Bit 7" "0,1" bitfld.long 0x14 6. ",Receive Mask Bit 6" "0,1" bitfld.long 0x14 5. ",Receive Mask Bit 5" "0,1" bitfld.long 0x14 4. ",Receive Mask Bit 4" "0,1" bitfld.long 0x14 3. ",Receive Mask Bit 3" "0,1" bitfld.long 0x14 2. ",Receive Mask Bit 2" "0,1" bitfld.long 0x14 1. ",Receive Mask Bit 1" "0,1" bitfld.long 0x14 0. ",Receive Mask Bit 0" "0,1" newline width 16. group.long 0x50++0x03 line.long 0x00 "SACCST_SET/CLR,SSI AC97 Channel SET/CLR Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SACCST9_SET/CLR ,AC97 Channel Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SACCST8_SET/CLR ,AC97 Channel Status 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SACCST7_SET/CLR ,AC97 Channel Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SACCST6_SET/CLR ,AC97 Channel Status 6" "Disabled,Enabled" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SACCST5_SET/CLR ,AC97 Channel Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SACCST4_SET/CLR ,AC97 Channel Status 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SACCST3_SET/CLR ,AC97 Channel Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SACCST2_SET/CLR ,AC97 Channel Status 2" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SACCST1_SET/CLR ,AC97 Channel Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SACCST0_SET/CLR ,AC97 Channel Status 0" "Disabled,Enabled" width 0x0B tree.end tree.end tree "TEMPMON (Temperature Monitor)" base ad:0x020C8180 width 16. group.long 0x00++0x1F line.long 0x00 "TEMPSENSE0,Tempsensor Control Register 0" hexmask.long.word 0x00 20.--31. 1. " ALARM_VALUE ,Temperature count" hexmask.long.word 0x00 8.--19. 1. " TEMP_CNT ,Last measured temperature" rbitfld.long 0x00 2. " FINISHED ,Latest temp valid" "Invalid,Valid" newline bitfld.long 0x00 1. " MEASURE_TEMP ,Starts the measurement process" "Stop,Start" bitfld.long 0x00 0. " POWER_DOWN ,Power down the temperature sensor" "Power up,Power down" line.long 0x04 "TEMPSENSE0_SET, Tempsensor Control Set Register 0" hexmask.long.word 0x04 20.--31. 1. " ALARM_VALUE ,Temperature count set" hexmask.long.word 0x04 8.--19. 1. " TEMP_CNT ,Last measured temperature set" rbitfld.long 0x04 2. " FINISHED ,Latest temp valid set" "No effect,Set" newline bitfld.long 0x04 1. " MEASURE_TEMP ,Starts the measurement process set" "No effect,Set" bitfld.long 0x04 0. " POWER_DOWN ,Power down the temperature sensor set" "No effect,Set" line.long 0x08 "TEMPSENSE0_CLR, Tempsensor Control Clear Register 0" hexmask.long.word 0x08 20.--31. 1. " ALARM_VALUE ,Temperature count clear" hexmask.long.word 0x08 8.--19. 1. " TEMP_CNT ,Last measured temperature clear" rbitfld.long 0x08 2. " FINISHED ,Latest temp valid clear" "No effect,Cleared" newline bitfld.long 0x08 1. " MEASURE_TEMP ,Starts the measurement process clear" "No effect,Cleared" bitfld.long 0x08 0. " POWER_DOWN ,Power down the temperature sensor clear" "No effect,Cleared" line.long 0x0C "TEMPSENSE0_TOG, Tempsensor Control Toggle Register 0" hexmask.long.word 0x0C 20.--31. 1. " ALARM_VALUE ,Temperature count toggle" hexmask.long.word 0x0C 8.--19. 1. " TEMP_CNT ,Last measured temperature toggle" rbitfld.long 0x0C 2. " FINISHED ,Latest temp valid toggle" "Not toggled,Toggled" newline bitfld.long 0x0C 1. " MEASURE_TEMP ,Starts the measurement process toggle" "Not toggled,Toggled" bitfld.long 0x0C 0. " POWER_DOWN ,Power down the temperature sensor toggle" "Not toggled,Toggled" line.long 0x10 "TEMPSENSE1,Tempsensor Control Register 1" hexmask.long.word 0x10 0.--15. 1. " MEASURE_FREQ ,Numbers of RTC clocks to wait before automatically repeating" line.long 0x14 "TEMPSENSE1_SET,Tempsensor Control Register 1" hexmask.long.word 0x14 0.--15. 1. " MEASURE_FREQ ,Numbers of RTC clocks to wait before automatically repeating set" line.long 0x18 "TEMPSENSE1_CLR,Tempsensor Control Register 1" hexmask.long.word 0x18 0.--15. 1. " MEASURE_FREQ ,Numbers of RTC clocks to wait before automatically repeating clear" line.long 0x1C "TEMPSENSE1_TOG,Tempsensor Control Register 1" hexmask.long.word 0x1C 0.--15. 1. " MEASURE_FREQ ,Numbers of RTC clocks to wait before automatically repeating toggle" width 0x0B tree.end tree "TZASC (TrustZone Address Space Controller)" base ad:0x021D0000 width 18. tree "Configuration, Lockdown and Interrupt Registers" rgroup.long 0x00++0x03 line.long 0x00 "CONFIGURATION,TZC-380 Configuration Register" bitfld.long 0x00 8.--13. " ADDRESS_WIDTH ,Address Width of the AXI address bus" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 0.--3. " NO_OF_REGIONS ,Number of Regions" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x04++0x0B line.long 0x00 "ACTION,TZC-380 Action Register" bitfld.long 0x00 0.--1. " REACTION_VALUE ,bresps[1:0]/rresps[1:0]/tzasc_int signals usage on region permission failure" "tzasc_int LOW/OKAY,tzasc_int LOW/DECERR,tzasc_int HIGH/OKAY,tzasc_int HIGH/DECERR" line.long 0x04 "LOCKDOWN_RANGE,TZC-380 Lockdown Range Register" bitfld.long 0x04 31. " ENABLE ,Lockdown_regions field regions lock enable" "Disabled,Enabled" bitfld.long 0x04 0.--3. " LOCKDOWN_REGIONS ,Controls the number of regions to lockdown" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x08 "LOCKDOWN_SELECT,TZC-380 Lockdown Select Register" bitfld.long 0x08 2. " ACC_SPECULATION_CNTL ,SPECULATION_CONTROL register access type" "Read/Write,Read-only" bitfld.long 0x08 1. " SECURITY_INV ,SECURITY_INVERSION_EN register access type" "Read/Write,Read-only" newline bitfld.long 0x08 0. " REGION_REGISTER ,LOCKDOWN_RANGE register access type" "Read/Write,Read-only" rgroup.long 0x10++0x03 line.long 0x00 "INTERRUPT_STATUS,TZC-380 Interrupt Status Register" bitfld.long 0x00 1. " OVERRUN ,Two or more region permission failures occurrence interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " STATUS ,Status of the interrupt" "Inactive,Active" wgroup.long 0x14++0x03 line.long 0x00 "INTERRUPT_CLEAR,TZC-380 Interrupt Clear Register" bitfld.long 0x00 1. " CLR_OVERRUN ,Overrun interrupt clear" "No effect,Clear" bitfld.long 0x00 0. " CLR_STATUS ,Interrupt status clear" "No effect,Clear" tree.end width 19. tree "Fail Status Registers" rgroup.long 0x20++0x0F line.long 0x00 "FAIL_ADDRESS_LOW,TZC-380 fail_address_low Register" line.long 0x04 "FAIL_ADDRESS_HIGH,TZC-380 fail_address_high Register" hexmask.long.byte 0x04 0.--7. 0x01 " ADDR_STAT_HIGH ,Address bits [axi_address_msb:32] of the first access to fail a region permission check after the interrupt was cleared" line.long 0x08 "FAIL_CONTROL,TZC-380 fail_control Register" bitfld.long 0x08 24. " WRITE ,Failed access type" "Read,Write" bitfld.long 0x08 21. " NONSECURE ,Permission check failed region first access secure state" "Secure,Non-secure" bitfld.long 0x08 20. " PRIVILEGED ,Permission check failed region first access privileged state" "Unprivileged,Privileged" line.long 0x0C "FAIL_ID,TZC-380 fail_id Register" hexmask.long.word 0x0C 0.--15. 0x01 " ID ,Permission check failed region first access master AXI ID" tree.end width 27. tree "Control Registers" group.long 0x30++0x07 line.long 0x00 "SPECULATION_CONTROL,TZC-380 speculation_control Register" bitfld.long 0x00 1. " WRITE_SPECULATION ,Write access speculation enable" "Enabled,Disabled" bitfld.long 0x00 0. " READ_SPECULATION ,Read access speculation enable" "Enabled,Disabled" line.long 0x04 "SECURITY_INVERSION_ENABLE,TZC-380 security_inversion_enable Register" bitfld.long 0x04 1. " SECURITY_INV_EN ,Security inversion enable" "Disabled,Enabled" tree.end width 22. tree "Region Control Registers" tree "Region 0 " group.long 0x100++0x07 line.long 0x00 "REGION_SETUP_LOW_0 ,TZC-380 The region_setup_low_0 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_0 ,Region 0 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_0 ,TZC-380 The region_setup_high_0 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x100+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_0 ,TZS-380 Region Attributes 0 Register" bitfld.long 0x00 28.--31. " SP0 ,Region 0 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" else group.long (0x100+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_0 ,TZS-380 Region Attributes 0 Register" bitfld.long 0x00 28.--31. " SP0 ,Region 0 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" endif tree.end tree "Region 1 " group.long 0x110++0x07 line.long 0x00 "REGION_SETUP_LOW_1 ,TZC-380 The region_setup_low_1 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_1 ,Region 1 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_1 ,TZC-380 The region_setup_high_1 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x110+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_1 ,TZS-380 Region Attributes 1 Register" bitfld.long 0x00 28.--31. " SP1 ,Region 1 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 1 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 1 Enable" "Disabled,Enabled" else group.long (0x110+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_1 ,TZS-380 Region Attributes 1 Register" bitfld.long 0x00 28.--31. " SP1 ,Region 1 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 1 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 1 Enable" "Disabled,Enabled" endif tree.end tree "Region 2 " group.long 0x120++0x07 line.long 0x00 "REGION_SETUP_LOW_2 ,TZC-380 The region_setup_low_2 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_2 ,Region 2 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_2 ,TZC-380 The region_setup_high_2 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x120+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_2 ,TZS-380 Region Attributes 2 Register" bitfld.long 0x00 28.--31. " SP2 ,Region 2 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 2 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 2 Enable" "Disabled,Enabled" else group.long (0x120+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_2 ,TZS-380 Region Attributes 2 Register" bitfld.long 0x00 28.--31. " SP2 ,Region 2 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 2 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 2 Enable" "Disabled,Enabled" endif tree.end tree "Region 3 " group.long 0x130++0x07 line.long 0x00 "REGION_SETUP_LOW_3 ,TZC-380 The region_setup_low_3 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_3 ,Region 3 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_3 ,TZC-380 The region_setup_high_3 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x130+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_3 ,TZS-380 Region Attributes 3 Register" bitfld.long 0x00 28.--31. " SP3 ,Region 3 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 3 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 3 Enable" "Disabled,Enabled" else group.long (0x130+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_3 ,TZS-380 Region Attributes 3 Register" bitfld.long 0x00 28.--31. " SP3 ,Region 3 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 3 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 3 Enable" "Disabled,Enabled" endif tree.end tree "Region 4 " group.long 0x140++0x07 line.long 0x00 "REGION_SETUP_LOW_4 ,TZC-380 The region_setup_low_4 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_4 ,Region 4 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_4 ,TZC-380 The region_setup_high_4 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x140+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_4 ,TZS-380 Region Attributes 4 Register" bitfld.long 0x00 28.--31. " SP4 ,Region 4 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 4 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 4 Enable" "Disabled,Enabled" else group.long (0x140+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_4 ,TZS-380 Region Attributes 4 Register" bitfld.long 0x00 28.--31. " SP4 ,Region 4 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 4 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 4 Enable" "Disabled,Enabled" endif tree.end tree "Region 5 " group.long 0x150++0x07 line.long 0x00 "REGION_SETUP_LOW_5 ,TZC-380 The region_setup_low_5 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_5 ,Region 5 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_5 ,TZC-380 The region_setup_high_5 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x150+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_5 ,TZS-380 Region Attributes 5 Register" bitfld.long 0x00 28.--31. " SP5 ,Region 5 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 5 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 5 Enable" "Disabled,Enabled" else group.long (0x150+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_5 ,TZS-380 Region Attributes 5 Register" bitfld.long 0x00 28.--31. " SP5 ,Region 5 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 5 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 5 Enable" "Disabled,Enabled" endif tree.end tree "Region 6 " group.long 0x160++0x07 line.long 0x00 "REGION_SETUP_LOW_6 ,TZC-380 The region_setup_low_6 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_6 ,Region 6 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_6 ,TZC-380 The region_setup_high_6 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x160+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_6 ,TZS-380 Region Attributes 6 Register" bitfld.long 0x00 28.--31. " SP6 ,Region 6 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 6 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 6 Enable" "Disabled,Enabled" else group.long (0x160+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_6 ,TZS-380 Region Attributes 6 Register" bitfld.long 0x00 28.--31. " SP6 ,Region 6 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 6 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 6 Enable" "Disabled,Enabled" endif tree.end tree "Region 7 " group.long 0x170++0x07 line.long 0x00 "REGION_SETUP_LOW_7 ,TZC-380 The region_setup_low_7 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_7 ,Region 7 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_7 ,TZC-380 The region_setup_high_7 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x170+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_7 ,TZS-380 Region Attributes 7 Register" bitfld.long 0x00 28.--31. " SP7 ,Region 7 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 7 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 7 Enable" "Disabled,Enabled" else group.long (0x170+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_7 ,TZS-380 Region Attributes 7 Register" bitfld.long 0x00 28.--31. " SP7 ,Region 7 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 7 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 7 Enable" "Disabled,Enabled" endif tree.end tree "Region 8 " group.long 0x180++0x07 line.long 0x00 "REGION_SETUP_LOW_8 ,TZC-380 The region_setup_low_8 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_8 ,Region 8 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_8 ,TZC-380 The region_setup_high_8 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x180+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_8 ,TZS-380 Region Attributes 8 Register" bitfld.long 0x00 28.--31. " SP8 ,Region 8 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 8 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 8 Enable" "Disabled,Enabled" else group.long (0x180+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_8 ,TZS-380 Region Attributes 8 Register" bitfld.long 0x00 28.--31. " SP8 ,Region 8 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 8 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 8 Enable" "Disabled,Enabled" endif tree.end tree "Region 9 " group.long 0x190++0x07 line.long 0x00 "REGION_SETUP_LOW_9 ,TZC-380 The region_setup_low_9 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_9 ,Region 9 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_9 ,TZC-380 The region_setup_high_9 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x190+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_9 ,TZS-380 Region Attributes 9 Register" bitfld.long 0x00 28.--31. " SP9 ,Region 9 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 9 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 9 Enable" "Disabled,Enabled" else group.long (0x190+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_9 ,TZS-380 Region Attributes 9 Register" bitfld.long 0x00 28.--31. " SP9 ,Region 9 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 9 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 9 Enable" "Disabled,Enabled" endif tree.end tree "Region 10" group.long 0x1A0++0x07 line.long 0x00 "REGION_SETUP_LOW_10,TZC-380 The region_setup_low_10 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_10 ,Region 10 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_10,TZC-380 The region_setup_high_10 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x1A0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_10,TZS-380 Region Attributes 10 Register" bitfld.long 0x00 28.--31. " SP10 ,Region 10 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 10 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 10 Enable" "Disabled,Enabled" else group.long (0x1A0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_10,TZS-380 Region Attributes 10 Register" bitfld.long 0x00 28.--31. " SP10 ,Region 10 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 10 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 10 Enable" "Disabled,Enabled" endif tree.end tree "Region 11" group.long 0x1B0++0x07 line.long 0x00 "REGION_SETUP_LOW_11,TZC-380 The region_setup_low_11 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_11 ,Region 11 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_11,TZC-380 The region_setup_high_11 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x1B0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_11,TZS-380 Region Attributes 11 Register" bitfld.long 0x00 28.--31. " SP11 ,Region 11 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 11 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 11 Enable" "Disabled,Enabled" else group.long (0x1B0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_11,TZS-380 Region Attributes 11 Register" bitfld.long 0x00 28.--31. " SP11 ,Region 11 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 11 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 11 Enable" "Disabled,Enabled" endif tree.end tree "Region 12" group.long 0x1C0++0x07 line.long 0x00 "REGION_SETUP_LOW_12,TZC-380 The region_setup_low_12 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_12 ,Region 12 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_12,TZC-380 The region_setup_high_12 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x1C0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_12,TZS-380 Region Attributes 12 Register" bitfld.long 0x00 28.--31. " SP12 ,Region 12 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 12 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 12 Enable" "Disabled,Enabled" else group.long (0x1C0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_12,TZS-380 Region Attributes 12 Register" bitfld.long 0x00 28.--31. " SP12 ,Region 12 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 12 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 12 Enable" "Disabled,Enabled" endif tree.end tree "Region 13" group.long 0x1D0++0x07 line.long 0x00 "REGION_SETUP_LOW_13,TZC-380 The region_setup_low_13 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_13 ,Region 13 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_13,TZC-380 The region_setup_high_13 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x1D0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_13,TZS-380 Region Attributes 13 Register" bitfld.long 0x00 28.--31. " SP13 ,Region 13 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 13 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 13 Enable" "Disabled,Enabled" else group.long (0x1D0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_13,TZS-380 Region Attributes 13 Register" bitfld.long 0x00 28.--31. " SP13 ,Region 13 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 13 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 13 Enable" "Disabled,Enabled" endif tree.end tree "Region 14" group.long 0x1E0++0x07 line.long 0x00 "REGION_SETUP_LOW_14,TZC-380 The region_setup_low_14 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_14 ,Region 14 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_14,TZC-380 The region_setup_high_14 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x1E0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_14,TZS-380 Region Attributes 14 Register" bitfld.long 0x00 28.--31. " SP14 ,Region 14 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 14 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 14 Enable" "Disabled,Enabled" else group.long (0x1E0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_14,TZS-380 Region Attributes 14 Register" bitfld.long 0x00 28.--31. " SP14 ,Region 14 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 14 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 14 Enable" "Disabled,Enabled" endif tree.end tree "Region 15" group.long 0x1F0++0x07 line.long 0x00 "REGION_SETUP_LOW_15,TZC-380 The region_setup_low_15 Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW_15 ,Region 15 base address bits [31:15]" line.long 0x04 "REGION_SETUP_HIGH_15,TZC-380 The region_setup_high_15 Register" if (((per.l(ad:0x021D0000+0x34))&0x01)==0x01) group.long (0x1F0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_15,TZS-380 Region Attributes 15 Register" bitfld.long 0x00 28.--31. " SP15 ,Region 15 permission setting (Secure/Non-secure)" "None/None,None/Write,None/Read,None/Read-Write,Write/None,Write/Write,Write/Read,Write/Read-Write,Read/None,Read/Write,Read/Read,Read/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 15 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 15 Enable" "Disabled,Enabled" else group.long (0x1F0+0x08)++0x03 line.long 0x00 "REGION_ATTRIBUTES_15,TZS-380 Region Attributes 15 Register" bitfld.long 0x00 28.--31. " SP15 ,Region 15 permission setting (Secure/Non-secure)" "None/None,Write/Write,Read/Read,Read-Write/Read-Write,Write/None,Write/Write,Read-Write/Read,Read-Write/Read-Write,Read/None,Read-Write/Write,Read/Read,Read-Write/Read-Write,Read-Write/None,Read-Write/Write,Read-Write/Read,Read-Write/Read-Write" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "No,Yes" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "No,Yes" newline bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "No,Yes" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "No,Yes" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "No,Yes" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "No,Yes" newline bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "No,Yes" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "No,Yes" newline bitfld.long 0x00 1.--6. " SIZE ,Region 15 size" ",,,,,,,,,,,,,,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,16GB,32GB,64GB,128GB,256GB,512GB,1TB,2TB,4TB,8TB,16TB,32TB,64TB,128TB,256TB,512TB,1PB,2PB,4PB,8PB,16PB,32PB,64PB,128PB,256PB,512PB,1EB,2EB,4EB,8EB,16EB" bitfld.long 0x00 0. " EN ,Region 15 Enable" "Disabled,Enabled" endif tree.end tree.end width 28. tree "Integration Test Registers" group.long 0xE00++0x03 line.long 0x00 "INTEGRATION_TEST_CONTROL,TZS-380 Integration Test Control Register" bitfld.long 0x00 0. " INT_TEST_EN ,Integration test logic enable" "Disabled,Enabled" rgroup.long 0xE04++0x03 line.long 0x00 "INTEGRATION_INPUT_CONTROL,TZS-380 Integration Test Input Register" bitfld.long 0x00 0. " ITIP_SECURE_BOOT_LOCK ,secure_boot_lock status" "Low,High" group.long 0xE08++0x03 line.long 0x00 "INTEGRATION_OUTPUT_CONTROL,TZS-380 Integration Test Output Register" bitfld.long 0x00 0. " ITOP_INT ,tzasc_int port value" "Low,High" tree.end width 16. tree "Component Configuration Registers" rgroup.long 0xFD0++0x03 line.long 0x00 "PERIPH_ID_4,TZS-380 Peripheral Identification 4 Register" bitfld.long 0x00 4.--7. " COUNT_4KB ,The number of 4KB address blocks you require to access the registers" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 0.--3. " JEP106_C_CODE ,The JEP106 continuation code value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFE0++0x0F line.long 0x00 "PERIPH_ID_0,TZS-380 Peripheral Identification 0 Register" hexmask.long.byte 0x00 0.--7. 0x1 " PART_NUM_0 ,part_number_0" line.long 0x04 "PERIPH_ID_1,TZS-380 Peripheral Identification 1 Register" bitfld.long 0x04 4.--7. " JEP106_ID_3_0 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PART_NUM_1 ,part_number_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPH_ID_2,TZS-380 Peripheral Identification 2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision of the TZASC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3. " JEDEC_USED ,A JEDEC manufacturer identity code by JEP106 is used" "Not used,Used" bitfld.long 0x08 0.--2. " JEP106_ID_6_4 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" line.long 0x0C "PERIPH_ID_3,TZS-380 Peripheral Identification 3 Register" bitfld.long 0x0C 4.--7. " REVAND ,Silicon revision occurrence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " MOD_NUMBER ,mod_number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFF0++0x03 line.long 0x00 "COMPONENT_ID_0,TZS-380 The Component ID 0 Register" hexmask.long.byte 0x00 0.--7. 0x1 " COMPONENT_ID_0 ,component_id_0" rgroup.long 0xFF4++0x03 line.long 0x00 "COMPONENT_ID_1,TZS-380 The Component ID 1 Register" hexmask.long.byte 0x00 0.--7. 0x1 " COMPONENT_ID_1 ,component_id_1" rgroup.long 0xFF8++0x03 line.long 0x00 "COMPONENT_ID_2,TZS-380 The Component ID 2 Register" hexmask.long.byte 0x00 0.--7. 0x1 " COMPONENT_ID_2 ,component_id_2" rgroup.long 0xFFC++0x03 line.long 0x00 "COMPONENT_ID_3,TZS-380 The Component ID 3 Register" hexmask.long.byte 0x00 0.--7. 0x1 " COMPONENT_ID_3 ,component_id_3" tree.end width 0x0B tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" tree "UART 4" base ad:0x02018000 width 7. sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x02018000+0x80)&0x01)==0x00)||((per.l(ad:0x02018000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x02018000+0xB4)&0xA00)==0xA00) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in elif ((per.l(ad:0x02018000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x02018000+0x80)&0x01)==0x00)||((per.l(ad:0x02018000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x02018000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif else hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in endif sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x02018000+0x80)&0x01)==0x00)||((per.l(ad:0x02018000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x02018000+0x80)&0x01)==0x00)||((per.l(ad:0x02018000+0x84)&0x04)==0x00)) wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" else hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in endif endif if ((per.l(ad:0x02018000+0xB8)&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,?..." bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" newline bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" newline bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" newline bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x02018000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02018000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02018000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02018000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02018000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02018000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02018000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02018000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02018000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02018000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02018000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02018000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02018000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02018000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x02018000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02018000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02018000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02018000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02018000+0x80))&0x80)==0x00))) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x1B line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7,?..." newline bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." line.long 0x04 "USR1,UART Status Register 1" eventfld.long 0x04 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x04 14. " RTSS ,RTS Pin Status" "High,Low" rbitfld.long 0x04 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x04 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x04 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x04 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x04 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x04 7. " DTRD ,DTR Delta" "Not changed,Changed" newline rbitfld.long 0x04 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x04 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x04 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" newline eventfld.long 0x04 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" line.long 0x08 "USR2,UART Status Register 2" eventfld.long 0x08 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x08 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x08 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" newline eventfld.long 0x08 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x08 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x08 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" newline rbitfld.long 0x08 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x08 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x08 7. " WAKE ,Wake" "Not detected,Detected" newline eventfld.long 0x08 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x08 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x08 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x08 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x08 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x08 1. " ORE ,Overrun Error" "No error,Error" newline rbitfld.long 0x08 0. " RDR ,Receive Data Ready" "Not ready,Ready" line.long 0x0C "UESC,UART Escape Character Register" hexmask.long.byte 0x0C 0.--7. 1. " ESC_CHAR ,UART Escape Character" line.long 0x10 "UTIM,UART Escape Timer Register" hexmask.long.word 0x10 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x14 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x14 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x18 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x18 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,Debug Enable" "Enabled,Disabled" newline bitfld.long 0x04 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x04 9. " RXDBG ,RX FIFO Read Counter Control in Debug Mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" newline bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x04 3. " RXFULL ,Rx FIFO Full" "Not full,Full" newline bitfld.long 0x04 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" newline bitfld.long 0x08 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" newline bitfld.long 0x08 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x08 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART 1" base ad:0x02020000 width 7. sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x02020000+0x80)&0x01)==0x00)||((per.l(ad:0x02020000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x02020000+0xB4)&0xA00)==0xA00) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in elif ((per.l(ad:0x02020000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x02020000+0x80)&0x01)==0x00)||((per.l(ad:0x02020000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x02020000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif else hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in endif sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x02020000+0x80)&0x01)==0x00)||((per.l(ad:0x02020000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x02020000+0x80)&0x01)==0x00)||((per.l(ad:0x02020000+0x84)&0x04)==0x00)) wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" else hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in endif endif if ((per.l(ad:0x02020000+0xB8)&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,?..." bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" newline bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" newline bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" newline bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x02020000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02020000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02020000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02020000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02020000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02020000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02020000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02020000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02020000+0x80))&0x80)==0x00))) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x1B line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7,?..." newline bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." line.long 0x04 "USR1,UART Status Register 1" eventfld.long 0x04 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x04 14. " RTSS ,RTS Pin Status" "High,Low" rbitfld.long 0x04 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x04 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x04 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x04 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x04 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x04 7. " DTRD ,DTR Delta" "Not changed,Changed" newline rbitfld.long 0x04 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x04 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x04 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" newline eventfld.long 0x04 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" line.long 0x08 "USR2,UART Status Register 2" eventfld.long 0x08 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x08 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x08 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" newline eventfld.long 0x08 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x08 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x08 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" newline rbitfld.long 0x08 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x08 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x08 7. " WAKE ,Wake" "Not detected,Detected" newline eventfld.long 0x08 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x08 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x08 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x08 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x08 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x08 1. " ORE ,Overrun Error" "No error,Error" newline rbitfld.long 0x08 0. " RDR ,Receive Data Ready" "Not ready,Ready" line.long 0x0C "UESC,UART Escape Character Register" hexmask.long.byte 0x0C 0.--7. 1. " ESC_CHAR ,UART Escape Character" line.long 0x10 "UTIM,UART Escape Timer Register" hexmask.long.word 0x10 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x14 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x14 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x18 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x18 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,Debug Enable" "Enabled,Disabled" newline bitfld.long 0x04 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x04 9. " RXDBG ,RX FIFO Read Counter Control in Debug Mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" newline bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x04 3. " RXFULL ,Rx FIFO Full" "Not full,Full" newline bitfld.long 0x04 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" newline bitfld.long 0x08 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" newline bitfld.long 0x08 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x08 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART 2" base ad:0x02024000 width 7. sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x02024000+0x80)&0x01)==0x00)||((per.l(ad:0x02024000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x02024000+0xB4)&0xA00)==0xA00) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in elif ((per.l(ad:0x02024000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x02024000+0x80)&0x01)==0x00)||((per.l(ad:0x02024000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x02024000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif else hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in endif sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x02024000+0x80)&0x01)==0x00)||((per.l(ad:0x02024000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x02024000+0x80)&0x01)==0x00)||((per.l(ad:0x02024000+0x84)&0x04)==0x00)) wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" else hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in endif endif if ((per.l(ad:0x02024000+0xB8)&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,?..." bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" newline bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" newline bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" newline bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x02024000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02024000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02024000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02024000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02024000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02024000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02024000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02024000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02024000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02024000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02024000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02024000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02024000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02024000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x02024000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02024000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02024000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02024000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02024000+0x80))&0x80)==0x00))) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x1B line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7,?..." newline bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." line.long 0x04 "USR1,UART Status Register 1" eventfld.long 0x04 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x04 14. " RTSS ,RTS Pin Status" "High,Low" rbitfld.long 0x04 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x04 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x04 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x04 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x04 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x04 7. " DTRD ,DTR Delta" "Not changed,Changed" newline rbitfld.long 0x04 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x04 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x04 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" newline eventfld.long 0x04 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" line.long 0x08 "USR2,UART Status Register 2" eventfld.long 0x08 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x08 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x08 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" newline eventfld.long 0x08 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x08 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x08 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" newline rbitfld.long 0x08 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x08 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x08 7. " WAKE ,Wake" "Not detected,Detected" newline eventfld.long 0x08 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x08 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x08 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x08 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x08 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x08 1. " ORE ,Overrun Error" "No error,Error" newline rbitfld.long 0x08 0. " RDR ,Receive Data Ready" "Not ready,Ready" line.long 0x0C "UESC,UART Escape Character Register" hexmask.long.byte 0x0C 0.--7. 1. " ESC_CHAR ,UART Escape Character" line.long 0x10 "UTIM,UART Escape Timer Register" hexmask.long.word 0x10 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x14 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x14 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x18 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x18 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,Debug Enable" "Enabled,Disabled" newline bitfld.long 0x04 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x04 9. " RXDBG ,RX FIFO Read Counter Control in Debug Mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" newline bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x04 3. " RXFULL ,Rx FIFO Full" "Not full,Full" newline bitfld.long 0x04 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" newline bitfld.long 0x08 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" newline bitfld.long 0x08 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x08 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART 3" base ad:0x02034000 width 7. sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x02034000+0x80)&0x01)==0x00)||((per.l(ad:0x02034000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x02034000+0xB4)&0xA00)==0xA00) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in elif ((per.l(ad:0x02034000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x02034000+0x80)&0x01)==0x00)||((per.l(ad:0x02034000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x02034000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif else hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in endif sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x02034000+0x80)&0x01)==0x00)||((per.l(ad:0x02034000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x02034000+0x80)&0x01)==0x00)||((per.l(ad:0x02034000+0x84)&0x04)==0x00)) wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" else hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in endif endif if ((per.l(ad:0x02034000+0xB8)&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,?..." bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" newline bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" newline bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" newline bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x02034000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02034000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02034000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02034000+0x90))&0x40)==0x40)&&((((per.l(ad:0x02034000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02034000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02034000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02034000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02034000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02034000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02034000+0x90))&0x40)==0x00)&&((((per.l(ad:0x02034000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02034000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02034000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x02034000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02034000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x02034000+0xB8))&0x01)==0x01)||((((per.l(ad:0x02034000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x02034000+0x80))&0x80)==0x00))) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x1B line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7,?..." newline bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." line.long 0x04 "USR1,UART Status Register 1" eventfld.long 0x04 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x04 14. " RTSS ,RTS Pin Status" "High,Low" rbitfld.long 0x04 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x04 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x04 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x04 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x04 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x04 7. " DTRD ,DTR Delta" "Not changed,Changed" newline rbitfld.long 0x04 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x04 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x04 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" newline eventfld.long 0x04 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" line.long 0x08 "USR2,UART Status Register 2" eventfld.long 0x08 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x08 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x08 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" newline eventfld.long 0x08 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x08 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x08 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" newline rbitfld.long 0x08 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x08 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x08 7. " WAKE ,Wake" "Not detected,Detected" newline eventfld.long 0x08 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x08 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x08 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x08 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x08 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x08 1. " ORE ,Overrun Error" "No error,Error" newline rbitfld.long 0x08 0. " RDR ,Receive Data Ready" "Not ready,Ready" line.long 0x0C "UESC,UART Escape Character Register" hexmask.long.byte 0x0C 0.--7. 1. " ESC_CHAR ,UART Escape Character" line.long 0x10 "UTIM,UART Escape Timer Register" hexmask.long.word 0x10 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x14 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x14 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x18 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x18 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,Debug Enable" "Enabled,Disabled" newline bitfld.long 0x04 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x04 9. " RXDBG ,RX FIFO Read Counter Control in Debug Mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" newline bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x04 3. " RXFULL ,Rx FIFO Full" "Not full,Full" newline bitfld.long 0x04 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" newline bitfld.long 0x08 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" newline bitfld.long 0x08 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x08 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree "UART 5" base ad:0x021F4000 width 7. sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x021F4000+0x80)&0x01)==0x00)||((per.l(ad:0x021F4000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x021F4000+0xB4)&0xA00)==0xA00) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in elif ((per.l(ad:0x021F4000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x021F4000+0x80)&0x01)==0x00)||((per.l(ad:0x021F4000+0x84)&0x02)==0x00)) hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" elif ((per.l(ad:0x021F4000+0xB8)&0x01)==0x00) rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Parity Error flag" "No error,Error" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" else rgroup.long 0x00++0x03 line.long 0x00 "URXD,UART Receiver Register" bitfld.long 0x00 15. " CHARRDY ,Character Ready" "Invalid,Valid and ready" bitfld.long 0x00 14. " ERR ,Error Detect" "No error,Error" bitfld.long 0x00 13. " OVRRUN ,Receiver Overrun" "No overrun,Overrun" newline bitfld.long 0x00 12. " FRMERR ,Frame Error" "No error,Error" bitfld.long 0x00 11. " BRK ,BREAK Detect" "Not detected,Detected" bitfld.long 0x00 10. " PRERR ,Holds the ninth data bit (bit [8]) of received 9-bit RS-485 data" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " RX_DATA ,Received Data" endif else hgroup.long 0x00++0x03 hide.long 0x00 "URXD,UART Receiver Register" in endif sif (cpu()=="IMX6ULTRALITE"||cpu()=="IMX6ULL") if (((per.l(ad:0x021F4000+0x80)&0x01)==0x00)||((per.l(ad:0x021F4000+0x84)&0x04)==0x00)) hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in else wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" endif elif (cpu()=="IMX6QUAD"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6DUAL"||cpu()=="IMX6DUALLITE"||cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6SLL") if (((per.l(ad:0x021F4000+0x80)&0x01)==0x00)||((per.l(ad:0x021F4000+0x84)&0x04)==0x00)) wgroup.long 0x40++0x03 line.long 0x00 "UTXD,UART Transmitter Register" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data" else hgroup.long 0x40++0x03 hide.long 0x00 "UTXD,UART Transmitter Register" in endif endif if ((per.l(ad:0x021F4000+0xB8)&0x01)==0x00) group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "UCR1,UART Control Register 1" bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled" bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames" bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled" bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,?..." bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent" bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled" bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled" bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "UCR2,UART Control Register 2" bitfld.long 0x00 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored" bitfld.long 0x00 13. " CTSC ,CTS Pin Control" "CTS,Receiver" newline bitfld.long 0x00 12. " CTS ,Clear to Send" "High,Low" bitfld.long 0x00 11. " ESCEN ,Escape Enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any" newline bitfld.long 0x00 8. " PREN ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 7. " PROE ,Parity Odd/Even" "Even,Odd" bitfld.long 0x00 6. " STPB ,Number of stop bits" "1 bit,2 bits" newline bitfld.long 0x00 5. " WS ,Word Size" "7-bit,8-bit" bitfld.long 0x00 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXEN ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXEN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRST ,Software Reset" "Reset,No reset" if ((((per.l(ad:0x021F4000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F4000+0x90))&0x40)==0x40)&&((((per.l(ad:0x021F4000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DSR Interrupt Edge Control" "Rising,Falling,Both,Both" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect - DCDDELT enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RI ,Ring Indicator - RIDELT enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F4000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x80))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Set TXD active level in IrDA mode" "Active low,Active high" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F4000+0x90))&0x40)==0x00)&&((((per.l(ad:0x021F4000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x00)))) group.long 0x88++0x03 line.long 0x00 "UCR3,UART Control Register 3" bitfld.long 0x00 14.--15. " DPEC ,DTR Interrupt Edge Control" "Rising,Falling,Any,Any" bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1" bitfld.long 0x00 9. " DCD ,Data Carrier Detect (DCD logic state)" "0,1" newline bitfld.long 0x00 8. " RI ,Ring Indicator (RI logic state)" "0,1" bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old" newline bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed" bitfld.long 0x00 1. " INVT ,Invert TXD output in RS-232/RS-485 mode" "Not inverted,Inverted" newline bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x88++0x03 hide.long 0x00 "UCR3,UART Control Register 3" endif if ((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x80)) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,RXD input logic level in IrDA mode" "Active low,Active high" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" elif ((((per.l(ad:0x021F4000+0xB8))&0x01)==0x01)||((((per.l(ad:0x021F4000+0xB8))&0x01)==0x00)&&(((per.l(ad:0x021F4000+0x80))&0x80)==0x00))) group.long 0x8C++0x03 line.long 0x00 "UCR4,UART Control Register 4" bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 9. " INVR ,Invert RXD input in RS-232/RS-485 Mode" "Not inverted,Inverted" bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock" newline bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled" bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "UCR4,UART Control Register 4" endif group.long 0x90++0x1B line.long 0x00 "UFCR,UART FIFO Control Register" bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "/6,/5,/4,/3,/2,/1,/7,?..." newline bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE" bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." line.long 0x04 "USR1,UART Status Register 1" eventfld.long 0x04 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected" rbitfld.long 0x04 14. " RTSS ,RTS Pin Status" "High,Low" rbitfld.long 0x04 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt" newline eventfld.long 0x04 12. " RTSD ,RTS Delta" "Not changed,Changed" eventfld.long 0x04 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected" eventfld.long 0x04 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x04 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready" eventfld.long 0x04 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active" eventfld.long 0x04 7. " DTRD ,DTR Delta" "Not changed,Changed" newline rbitfld.long 0x04 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle" eventfld.long 0x04 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected" eventfld.long 0x04 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected" newline eventfld.long 0x04 3. " SAD ,RS-485 Slave Address Detected Interrupt Flag" "Not detected,Detected" line.long 0x08 "USR2,UART Status Register 2" eventfld.long 0x08 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received" rbitfld.long 0x08 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty" eventfld.long 0x08 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected" newline eventfld.long 0x08 12. " IDLE ,Idle Condition" "Not detected,Detected" eventfld.long 0x08 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished" eventfld.long 0x08 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed" newline rbitfld.long 0x08 9. " RIIN ,Ring Indicator Input" "Detected,Not detected" eventfld.long 0x08 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected" eventfld.long 0x08 7. " WAKE ,Wake" "Not detected,Detected" newline eventfld.long 0x08 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed" rbitfld.long 0x08 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected" eventfld.long 0x08 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected" newline rbitfld.long 0x08 3. " TXDC ,Transmitter Complete" "Not completed,Completed" eventfld.long 0x08 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected" eventfld.long 0x08 1. " ORE ,Overrun Error" "No error,Error" newline rbitfld.long 0x08 0. " RDR ,Receive Data Ready" "Not ready,Ready" line.long 0x0C "UESC,UART Escape Character Register" hexmask.long.byte 0x0C 0.--7. 1. " ESC_CHAR ,UART Escape Character" line.long 0x10 "UTIM,UART Escape Timer Register" hexmask.long.word 0x10 0.--11. 1. " TIM ,UART Escape Timer" line.long 0x14 "UBIR,UART BRM Incremental Register" hexmask.long.word 0x14 0.--15. 1. " INC ,UART BRM Incremental Numerator" line.long 0x18 "UBMR,UART BRM Modulator Register" hexmask.long.word 0x18 0.--15. 1. " MOD ,Modulator Dominator" rgroup.long 0xAC++0x03 line.long 0x00 "UBRC,UART Baud Rate Count Register" hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register" group.long 0xB0++0x0B line.long 0x00 "ONEMS,UART One Millisecond Register" hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register" line.long 0x04 "UTS,UART Test Register" bitfld.long 0x04 13. " FRCPERR ,Force Parity Error" "Normal,Inverted" bitfld.long 0x04 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop" bitfld.long 0x04 11. " DBGEN ,Debug Enable" "Enabled,Disabled" newline bitfld.long 0x04 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop" bitfld.long 0x04 9. " RXDBG ,RX FIFO Read Counter Control in Debug Mode" "Not incremented,Incremented" bitfld.long 0x04 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty" newline bitfld.long 0x04 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty" bitfld.long 0x04 4. " TXFULL ,Tx FIFO Full" "Not full,Full" bitfld.long 0x04 3. " RXFULL ,Rx FIFO Full" "Not full,Full" newline bitfld.long 0x04 0. " SOFTRST ,Software Reset" "No reset,Reset" line.long 0x08 "UMCR,RS-485 Mode Control Register" hexmask.long.byte 0x08 8.--15. 1. " SLADDR ,RS-485 Slave Address Character" newline bitfld.long 0x08 3. " SADEN ,RS-485 Slave Address Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 2. " TXB8 ,Transmit RS-485 bit 8" "0,1" newline bitfld.long 0x08 1. " SLAM ,RS-485 Slave Address Detect Mode Selection" "Normal,Automatic" bitfld.long 0x08 0. " MDEN ,9-bit data or Multidrop Mode (RS-485) Enable" "RS-232/IrDA mode,RS-485 mode" width 0x0B tree.end tree.end tree "USB Controller (Universal Serial Bus Controller)" tree "USBNC (USB Non-Core)" base ad:0x02184800 width 21. group.long 0x00++0x07 line.long 0x00 "USB_OTG1_CTRL,USB OTG1 Control Register" rbitfld.long 0x00 31. " WIR ,OTG wake-up interrupt request" "Not requested,Requested" bitfld.long 0x00 17. " WKUP_VBUS_EN ,OTG wake-up on VBUS change enable" "Disabled,Enabled" bitfld.long 0x00 16. " WKUP_ID_EN ,OTG wake-up on ID change enable" "Disabled,Enabled" bitfld.long 0x00 15. " WKUP_SW ,OTG software wake-up" "Inactive,Wake-up" newline bitfld.long 0x00 14. " WKUP_SW_EN ,OTG software wake-up enable" "Disabled,Enabled" bitfld.long 0x00 10. " WIE ,OTG wake-up interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " PWR_POL ,OTG power polarity" "Low,High" bitfld.long 0x00 8. " OVER_CUR_POL ,OTG polarity of over current" "High,Low" newline bitfld.long 0x00 7. " OVER_CUR_DIS ,Disable OTG over current detection" "No,Yes" line.long 0x04 "USB_OTG2_CTRL,USB OTG2 Control Register" rbitfld.long 0x04 31. " WIR ,OTG wake-up interrupt request" "Not requested,Requested" bitfld.long 0x04 17. " WKUP_VBUS_EN ,OTG wake-up on VBUS change enable" "Disabled,Enabled" bitfld.long 0x04 16. " WKUP_ID_EN ,OTG wake-up on ID change enable" "Disabled,Enabled" bitfld.long 0x04 15. " WKUP_SW ,OTG software wake-up" "Inactive,Wake-up" newline bitfld.long 0x04 14. " WKUP_SW_EN ,OTG software wake-up enable" "Disabled,Enabled" bitfld.long 0x04 10. " WIE ,OTG wake-up interrupt enable" "Disabled,Enabled" bitfld.long 0x04 9. " PWR_POL ,OTG power polarity" "Low,High" bitfld.long 0x04 8. " OVER_CUR_POL ,OTG polarity of over current" "High,Low" newline bitfld.long 0x04 7. " OVER_CUR_DIS ,Disable OTG over current detection" "No,Yes" group.long 0x18++0x07 line.long 0x00 "USB_OTG1_PHY_CTRL_0,OTG1 UTMI PHY Control 0 Register" bitfld.long 0x00 31. " UTMI_CLK_VLD ,UTMI PHY clock valid" "Invalid,Valid" line.long 0x04 "USB_OTG2_PHY_CTRL_0,OTG2 UTMI PHY Control 0 Register" bitfld.long 0x04 31. " UTMI_CLK_VLD ,UTMI PHY clock valid" "Invalid,Valid" width 0x0B tree.end tree "USBC (USB Core)" tree "UOG 1" base ad:0x02184000 width 11. rgroup.long 0x00++0x0B line.long 0x00 "ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision Number of the Core" hexmask.long.byte 0x00 8.--13. 1. " NID ,Ones Complement Version of ID" newline hexmask.long.byte 0x00 0.--5. 1. " ID ,Configuration Number" line.long 0x04 "HWGENERAL,General Hardware Register" bitfld.long 0x04 9.--10. " SM ,Serial interface mode capability" "No engine/parallel signaling,Engine present/serial signaling,Soft programmable/Reset to parallel,Soft programmable/Reset to serial" newline bitfld.long 0x04 6.--8. " PHYM ,Transceiver type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Soft programmable reset to UTMI/UMTI+,Soft programmable reset to ULPI DDR,Soft programmable reset to ULPI,Soft programmable reset to Serial" newline bitfld.long 0x04 4.--5. " PHYW ,Data width of the transceiver connected to the controller core" "8 bit non programmable,16 bit non programmable,8 bit programmable,16 bit programmable" line.long 0x08 "HWHOST,Host Hardware Parameters Register" bitfld.long 0x08 1.--3. " NPORT ,Number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x08 0. " HC ,Host operation mode support for device" "Not supported,Supported" rgroup.long 0x0C++0x03 line.long 0x00 "HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x00 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device operation mode support" "Not supported,Supported" rgroup.long 0x10++0x07 line.long 0x00 "HWTXBUF,TX Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" width 16. group.long 0x80++0x0F "Device/Host Timer Registers" line.long 0x00 "GPTIMER0LD,General Purpose Timer #0 Load Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x04 "GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x04 30. " GPTRST ,General purpose timer reset" "No effect,Reset" newline bitfld.long 0x04 24. " GPTMODE ,General purpose timer mode" "One Shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x08 "GPTIMER1LD,General Purpose Timer #1 Load Register" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x0C "GPTIMER1CTRL,General purpose timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General purpose timer Run" "Stopped,Running" bitfld.long 0x0C 30. " GPTRST ,General purpose timer Reset" "No effect,Reset" newline bitfld.long 0x0C 24. " GPTMODE ,General purpose timer mode" "One Shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General purpose timer counter" group.long 0x90++0x03 line.long 0x00 "SBUSCFG,System Bus Config" bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte 0x100++0x00 line.byte 0x00 "CAPLENGTH,Address offset to the Operational registers" rgroup.word 0x102++0x01 line.word 0x00 "HCIVERSION,EHCI revision number supported by this host controller" rgroup.long 0x104++0x07 line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT ,Number of transaction translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT ,Number of ports per transaction translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16. " PI ,Port Indicators" "Low,High" bitfld.long 0x00 12.--15. " N_CC ,Number of companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " N_PCC ,Number of ports per companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port power control" "Not included,Included" newline bitfld.long 0x00 0.--3. " N_PORTS ,Number of downstream ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI extended capabilities pointer" bitfld.long 0x04 4.--7. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported" bitfld.long 0x04 1. " PFL ,Programmable frame list flag" "Disabled,Enabled" newline bitfld.long 0x04 0. " ADC ,64-bit addressing capability" "Not supported,Supported" rgroup.word 0x120++0x01 line.word 0x00 "DCIVERSION,Device Interface Version Number Register" rgroup.long 0x124++0x03 line.long 0x00 "DCCPARAMS,Device Control Capability Parameters Register" bitfld.long 0x00 8. " HC ,Host capable" "Not supported,Supported" bitfld.long 0x00 7. " DC ,Device capable" "Not supported,Supported" newline bitfld.long 0x00 0.--4. " DEN ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." group.long 0x140++0x03 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD tripwire" "Not added,Added" newline bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Hazard,No hazard" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" "0,1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame list size 1" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset" newline bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" if (((per.l(ad:0x02184000+0x1A8))&0x03)==0x03) group.long 0x144++0x03 line.long 0x00 "USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" newline rbitfld.long 0x00 16. " NAKI ,NAK interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous schedule status" "Disabled,Enabled" newline rbitfld.long 0x00 14. " PS ,Periodic schedule status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" newline rbitfld.long 0x00 12. " HCH ,HC halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " SRI ,SOF received" "Not detected,Detected" bitfld.long 0x00 5. " AAI ,Interrupt on async advance" "Not requested,Requested" newline bitfld.long 0x00 4. " SEI ,System error" "No error,Error" bitfld.long 0x00 3. " FRI ,Frame list rollover" "Not rollover,Rollover" newline bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed" bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error" newline bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt" else group.long 0x144++0x03 line.long 0x00 "USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" newline rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" newline bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" newline bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" endif group.long 0x148++0x07 line.long 0x00 "USBINTR,USB Interrupt Enable" bitfld.long 0x00 25. " TIE1 ,GPT interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,GPT interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " ULPIE ,ULPI enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,SOF received enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " URE ,USB reset enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on async Advance Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame list rollover enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x04 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index" if (((per.l(ad:0x02184000+0x1A8))&0x03)==0x03) group.long 0x154++0x07 line.long 0x00 "PERIODICLISTBASE,Host Controller Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base address (Low)" line.long 0x04 "ASYNCLISTADDR,Host Controller Next Asynch Address Register" hexmask.long 0x04 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low" elif (((per.l(ad:0x02184000+0x1A8))&0x03)==0x02) group.long 0x154++0x07 line.long 0x00 "DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x02 " BASEADR ,USB device address" newline bitfld.long 0x00 24. " USBADRA ,Write method to USBADR" "Instantaneous,Staged/hidden register" line.long 0x04 "ENDPTLISTADDR,Device Controller Endpoint List Address Register" hexmask.long.tbyte 0x04 11.--31. 0x08 " EPBASE[31:11] ,Device controller endpoint list address" endif group.long 0x160++0x07 line.long 0x00 "BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX burst length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX burst length" line.long 0x04 "TXFILLTUNING,TX FIFO Fill Tuning Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO burst threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler health counter" newline hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler overhead" group.long 0x178++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK register" bitfld.long 0x00 23. " EPTN[7] ,TX Endpoint NAK 7" "Low,High" bitfld.long 0x00 22. " [6] ,TX endpoint NAK 6" "Low,High" newline bitfld.long 0x00 21. " [5] ,TX endpoint NAK 5" "Low,High" bitfld.long 0x00 20. " [4] ,TX endpoint NAK 4" "Low,High" newline bitfld.long 0x00 19. " [3] ,TX endpoint NAK 3" "Low,High" bitfld.long 0x00 18. " [2] ,TX endpoint NAK 2" "Low,High" newline bitfld.long 0x00 17. " [1] ,TX endpoint NAK 1" "Low,High" bitfld.long 0x00 16. " [0] ,TX endpoint NAK 0" "Low,High" newline bitfld.long 0x00 7. " EPRN[7] ,RX endpoint NAK 7" "Low,High" bitfld.long 0x00 6. " [6] ,RX endpoint NAK 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,RX endpoint NAK 5" "Low,High" bitfld.long 0x00 4. " [4] ,RX endpoint NAK 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,RX endpoint NAK 3" "Low,High" bitfld.long 0x00 2. " [2] ,RX endpoint NAK 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,RX endpoint NAK 1" "Low,High" bitfld.long 0x00 0. " [0] ,RX endpoint NAK 0" "Low,High" line.long 0x04 "ENDPTNAKEN,Endpoint NAK register enable" bitfld.long 0x04 23. " EPTN[7] ,TX endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 22. " [6] ,TX endpoint NAK 6" "Disabled,Enabled" newline bitfld.long 0x04 21. " [5] ,TX endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,TX endpoint NAK 4" "Disabled,Enabled" newline bitfld.long 0x04 19. " [3] ,TX endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,TX endpoint NAK 2" "Disabled,Enabled" newline bitfld.long 0x04 17. " [1] ,TX endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,TX endpoint NAK 0" "Disabled,Enabled" newline bitfld.long 0x04 7. " EPRN[7] ,RX endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,RX endpoint NAK 6" "Disabled,Enabled" newline bitfld.long 0x04 5. " [5] ,RX endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,RX endpoint NAK 4" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,RX endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,RX endpoint NAK 2" "Disabled,Enabled" newline bitfld.long 0x04 1. " [1] ,RX endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,RX endpoint NAK 0" "Disabled,Enabled" rgroup.long 0x180++0x03 line.long 0x00 "CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Configure flag" "Classic host,This host" if (((per.l(ad:0x02184000+0x1A8))&0x03)==0x03) group.long 0x184++0x03 line.long 0x00 "PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel transceiver select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." newline bitfld.long 0x00 29. " STS ,Serial transceiver select" "Not selected,Selected" newline bitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full,Low,High,?..." newline bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "Not suspended,Suspended" newline bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " PTC[3:0] ,Port test control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." newline bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Disabled,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Port owner" "Cleared,Set" newline bitfld.long 0x00 12. " PP ,Port power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." newline rbitfld.long 0x00 9. " HSP ,High-speed port" "Not high-speed,High-speed" bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" newline bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" newline eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" newline eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" newline eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current connect status" "No device,Device" else group.long 0x184++0x03 line.long 0x00 "PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel transceiver select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." newline bitfld.long 0x00 29. " STS ,Serial transceiver select" "Not selected,Selected" newline bitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full,Low,High,?..." newline bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "Not suspended,Suspended" newline bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " PTC[3:0] ,Port test control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." newline bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Disabled,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Port owner" "Cleared,Set" newline bitfld.long 0x00 12. " PP ,Port power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." newline rbitfld.long 0x00 9. " HSP ,High-speed port" "Not high-speed,High-speed" rbitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" newline rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" newline eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" newline eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" newline eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current connect status" "No device,Device" endif group.long 0x1A4++0x03 line.long 0x00 "OTGSC,OTG Status Control Register" bitfld.long 0x00 30. " DPIE ,Data pulse interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1MSE ,1 milisecond timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " BSEIE ,B session end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B session valid interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " ASVIE ,A session valid interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus valid interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IDIE ,USB ID interrupt enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data pulse interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x00 21. " STATUS_1MS ,1 milisecond timer interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 20. " BSEIS ,B session end interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " BSVIS ,B Session valid interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 18. " ASVIS ,A session valid interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x00 17. " AVVIS ,A VBus valid interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 16. " IDIS ,USB ID interrupt status" "No interrupt,Interrupt" newline rbitfld.long 0x00 14. " DPS ,Data bus pulsing status" "Not detected,Detected" rbitfld.long 0x00 13. " OG_1MS ,1 millisecond timer toggle" "Not toggled,Toggled" newline rbitfld.long 0x00 12. " BSE ,B session end" "Not ended,Ended" rbitfld.long 0x00 11. " BSV ,B session valid" "Not valid,Valid" newline rbitfld.long 0x00 10. " ASV ,A Session valid" "Not valid,Valid" rbitfld.long 0x00 9. " AVV ,A VBus valid" "Not valid,Valid" newline rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 5. " IDPU ,ID pullup" "Disabled,Enabled" newline bitfld.long 0x00 4. " DP ,Data pulsing" "Disabled,Enabled" bitfld.long 0x00 3. " OT ,OTG termination" "Disabled,Enabled" newline bitfld.long 0x00 1. " VC ,VBUS charge" "Not charged,Charged" bitfld.long 0x00 0. " VD ,VBUS discharge" "Not discharged,Discharged" group.long 0x1A8++0x03 line.long 0x00 "USBMODE,USB Device Mode Register" bitfld.long 0x00 4. " SDIS ,Stream disable mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup lockout mode" "On,Off" newline bitfld.long 0x00 2. " ES ,Endian select" "Little,Big" bitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device,Host" newline if (((per.l(ad:0x02184000+0x1A8))&0x03)==0x02) group.long 0x1AC++0x0B line.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" bitfld.long 0x00 15. " ENDPTSETUPSTAT[15] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 14. " ENDPTSETUPSTAT[14] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 13. " ENDPTSETUPSTAT[13] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 12. " ENDPTSETUPSTAT[12] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 11. " ENDPTSETUPSTAT[11] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 10. " ENDPTSETUPSTAT[10] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 9. " ENDPTSETUPSTAT[09] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 8. " ENDPTSETUPSTAT[08] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 7. " ENDPTSETUPSTAT[07] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 6. " ENDPTSETUPSTAT[06] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 5. " ENDPTSETUPSTAT[05] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 4. " ENDPTSETUPSTAT[04] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 3. " ENDPTSETUPSTAT[03] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 2. " ENDPTSETUPSTAT[02] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 1. " ENDPTSETUPSTAT[01] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 0. " ENDPTSETUPSTAT[00] ,Setup endpoint status" "Not received,Received" newline line.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" bitfld.long 0x04 23. " PETB7 ,Prime endpoint transmit buffer" "Not prime,Prime" bitfld.long 0x04 22. " PETB6 ,Prime endpoint transmit buffer" "Not prime,Prime" newline bitfld.long 0x04 21. " PETB5 ,Prime endpoint transmit buffer" "Not prime,Prime" bitfld.long 0x04 20. " PETB4 ,Prime endpoint transmit buffer" "Not prime,Prime" newline bitfld.long 0x04 19. " PETB3 ,Prime endpoint transmit buffer" "Not prime,Prime" bitfld.long 0x04 18. " PETB2 ,Prime endpoint transmit buffer" "Not prime,Prime" newline bitfld.long 0x04 17. " PETB1 ,Prime endpoint transmit buffer" "Not prime,Prime" bitfld.long 0x04 16. " PETB0 ,Prime endpoint transmit buffer" "Not prime,Prime" newline bitfld.long 0x04 7. " PERB7 ,Prime endpoint receive buffer" "Not prime,Prime" bitfld.long 0x04 6. " PERB6 ,Prime endpoint receive buffer" "Not prime,Prime" newline bitfld.long 0x04 5. " PERB5 ,Prime endpoint receive buffer" "Not prime,Prime" bitfld.long 0x04 4. " PERB4 ,Prime endpoint receive buffer" "Not prime,Prime" newline bitfld.long 0x04 3. " PERB3 ,Prime endpoint receive buffer" "Not prime,Prime" bitfld.long 0x04 2. " PERB2 ,Prime endpoint receive buffer" "Not prime,Prime" newline bitfld.long 0x04 1. " PERB1 ,Prime endpoint receive buffer" "Not prime,Prime" bitfld.long 0x04 0. " PERB0 ,Prime endpoint receive buffer" "Not prime,Prime" line.long 0x08 "ENDPTFLUSH,Endpoint De-Initialize Register" bitfld.long 0x08 23. " FETB7 ,Flush endpoint transmit buffer" "Not flushed,Flushed" bitfld.long 0x08 22. " FETB6 ,Flush endpoint transmit buffer" "Not flushed,Flushed" newline bitfld.long 0x08 21. " FETB5 ,Flush endpoint transmit buffer" "Not flushed,Flushed" bitfld.long 0x08 20. " FETB4 ,Flush endpoint transmit buffer" "Not flushed,Flushed" newline bitfld.long 0x08 19. " FETB3 ,Flush endpoint transmit buffer" "Not flushed,Flushed" bitfld.long 0x08 18. " FETB2 ,Flush endpoint transmit buffer" "Not flushed,Flushed" newline bitfld.long 0x08 17. " FETB1 ,Flush endpoint transmit buffer" "Not flushed,Flushed" bitfld.long 0x08 16. " FETB0 ,Flush endpoint transmit buffer" "Not flushed,Flushed" newline bitfld.long 0x08 7. " FERB7 ,Flush endpoint receive buffer" "Not flushed,Flushed" bitfld.long 0x08 6. " FERB6 ,Flush endpoint receive buffer" "Not flushed,Flushed" newline bitfld.long 0x08 5. " FERB5 ,Flush endpoint receive buffer" "Not flushed,Flushed" bitfld.long 0x08 4. " FERB4 ,Flush endpoint receive buffer" "Not flushed,Flushed" newline bitfld.long 0x08 3. " FERB3 ,Flush endpoint receive buffer" "Not flushed,Flushed" bitfld.long 0x08 2. " FERB2 ,Flush endpoint receive buffer" "Not flushed,Flushed" newline bitfld.long 0x08 1. " FERB1 ,Flush endpoint receive buffer" "Not flushed,Flushed" bitfld.long 0x08 0. " FERB0 ,Flush endpoint receive buffer" "Not flushed,Flushed" rgroup.long 0x1B8++0x03 line.long 0x00 "ENDPTSTAT,Endpoint Status Register" bitfld.long 0x00 23. " ETBR7 ,Endpoint transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 22. " ETBR6 ,Endpoint transmit buffer ready" "Not ready,Ready" newline bitfld.long 0x00 21. " ETBR5 ,Endpoint transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 20. " ETBR4 ,Endpoint transmit buffer ready" "Not ready,Ready" newline bitfld.long 0x00 19. " ETBR3 ,Endpoint transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR2 ,Endpoint transmit buffer ready" "Not ready,Ready" newline bitfld.long 0x00 17. " ETBR1 ,Endpoint transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR0 ,Endpoint transmit buffer ready" "Not ready,Ready" newline bitfld.long 0x00 7. " ERBR7 ,Endpoint receive buffer ready" "Not ready,Ready" bitfld.long 0x00 6. " ERBR6 ,Endpoint receive buffer ready" "Not ready,Ready" newline bitfld.long 0x00 5. " ERBR5 ,Endpoint receive buffer ready" "Not ready,Ready" bitfld.long 0x00 4. " ERBR4 ,Endpoint receive buffer ready" "Not ready,Ready" newline bitfld.long 0x00 3. " ERBR3 ,Endpoint receive buffer ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR2 ,Endpoint receive buffer ready" "Not ready,Ready" newline bitfld.long 0x00 1. " ERBR1 ,Endpoint receive buffer ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR0 ,Endpoint receive buffer ready" "Not ready,Ready" group.long 0x1BC++0x03 line.long 0x00 "ENDPTCOMPLETE,Endpoint Compete Register" eventfld.long 0x00 23. " ETCE7 ,Endpoint transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 22. " ETCE6 ,Endpoint transmit complete event" "Not occurred,Occurred" newline eventfld.long 0x00 21. " ETCE5 ,Endpoint transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 20. " ETCE4 ,Endpoint transmit complete event" "Not occurred,Occurred" newline eventfld.long 0x00 19. " ETCE3 ,Endpoint transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE2 ,Endpoint transmit complete event" "Not occurred,Occurred" newline eventfld.long 0x00 17. " ETCE1 ,Endpoint transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE0 ,Endpoint transmit complete event" "Not occurred,Occurred" newline eventfld.long 0x00 7. " ERCE7 ,Endpoint receive complete event" "Not occurred,Occurred" eventfld.long 0x00 6. " ERCE6 ,Endpoint receive complete event" "Not occurred,Occurred" newline eventfld.long 0x00 5. " ERCE5 ,Endpoint receive complete event" "Not occurred,Occurred" eventfld.long 0x00 4. " ERCE4 ,Endpoint receive complete event" "Not occurred,Occurred" newline eventfld.long 0x00 3. " ERCE3 ,Endpoint receive complete event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE2 ,Endpoint receive complete event" "Not occurred,Occurred" newline eventfld.long 0x00 1. " ERCE1 ,Endpoint receive complete event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE0 ,Endpoint receive complete event" "Not occurred,Occurred" else hgroup.long 0x1AC++0x03 hide.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" hgroup.long 0x1B0++0x03 hide.long 0x00 "ENDPTPRIME,Endpoint Initialization Register" hgroup.long 0x1B4++0x03 hide.long 0x00 "ENDPTFLUSH,Endpoint De-Initialize Register" hgroup.long 0x1B8++0x03 hide.long 0x00 "ENDPTSTAT,Endpoint Status Register" hgroup.long 0x1BC++0x03 hide.long 0x00 "ENDPTCOMPLETE,Endpoint Compete Register" endif group.long 0x1C0++0x03 line.long 0x00 "ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,?..." newline bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" if (((per.l(ad:0x02184000+0x1A8))&0x03)==0x02) group.long 0x1C0++0x03 line.long 0x00 "ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1C4++0x03 line.long 0x00 "ENDPTCTRL1,Endpoint Control 1 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1C8++0x03 line.long 0x00 "ENDPTCTRL2,Endpoint Control 2 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1CC++0x03 line.long 0x00 "ENDPTCTRL3,Endpoint Control 3 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1D0++0x03 line.long 0x00 "ENDPTCTRL4,Endpoint Control 4 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1D4++0x03 line.long 0x00 "ENDPTCTRL5,Endpoint Control 5 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1D8++0x03 line.long 0x00 "ENDPTCTRL6,Endpoint Control 6 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1DC++0x03 line.long 0x00 "ENDPTCTRL7,Endpoint Control 7 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1C0++0x03 hide.long 0x00 "ENDPTCTRL0,Endpoint Control 0 Register" hgroup.long 0x1C4++0x03 hide.long 0x00 "ENDPTCTRL1,Endpoint Control 1 Register" hgroup.long 0x1C8++0x03 hide.long 0x00 "ENDPTCTRL2,Endpoint Control 2 Register" hgroup.long 0x1CC++0x03 hide.long 0x00 "ENDPTCTRL3,Endpoint Control 3 Register" hgroup.long 0x1D0++0x03 hide.long 0x00 "ENDPTCTRL4,Endpoint Control 4 Register" hgroup.long 0x1D4++0x03 hide.long 0x00 "ENDPTCTRL5,Endpoint Control 5 Register" hgroup.long 0x1D8++0x03 hide.long 0x00 "ENDPTCTRL6,Endpoint Control 6 Register" hgroup.long 0x1DC++0x03 hide.long 0x00 "ENDPTCTRL7,Endpoint Control 7 Register" endif width 0x0B tree.end tree "UOG 2" base ad:0x02184200 width 11. rgroup.long 0x00++0x0B line.long 0x00 "ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision Number of the Core" hexmask.long.byte 0x00 8.--13. 1. " NID ,Ones Complement Version of ID" newline hexmask.long.byte 0x00 0.--5. 1. " ID ,Configuration Number" line.long 0x04 "HWGENERAL,General Hardware Register" bitfld.long 0x04 9.--10. " SM ,Serial interface mode capability" "No engine/parallel signaling,Engine present/serial signaling,Soft programmable/Reset to parallel,Soft programmable/Reset to serial" newline bitfld.long 0x04 6.--8. " PHYM ,Transceiver type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Soft programmable reset to UTMI/UMTI+,Soft programmable reset to ULPI DDR,Soft programmable reset to ULPI,Soft programmable reset to Serial" newline bitfld.long 0x04 4.--5. " PHYW ,Data width of the transceiver connected to the controller core" "8 bit non programmable,16 bit non programmable,8 bit programmable,16 bit programmable" line.long 0x08 "HWHOST,Host Hardware Parameters Register" bitfld.long 0x08 1.--3. " NPORT ,Number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x08 0. " HC ,Host operation mode support for device" "Not supported,Supported" rgroup.long 0x0C++0x03 line.long 0x00 "HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x00 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " DC ,Device operation mode support" "Not supported,Supported" rgroup.long 0x10++0x07 line.long 0x00 "HWTXBUF,TX Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" width 16. group.long 0x80++0x0F "Device/Host Timer Registers" line.long 0x00 "GPTIMER0LD,General Purpose Timer #0 Load Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x04 "GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x04 30. " GPTRST ,General purpose timer reset" "No effect,Reset" newline bitfld.long 0x04 24. " GPTMODE ,General purpose timer mode" "One Shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x08 "GPTIMER1LD,General Purpose Timer #1 Load Register" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x0C "GPTIMER1CTRL,General purpose timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General purpose timer Run" "Stopped,Running" bitfld.long 0x0C 30. " GPTRST ,General purpose timer Reset" "No effect,Reset" newline bitfld.long 0x0C 24. " GPTMODE ,General purpose timer mode" "One Shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General purpose timer counter" group.long 0x90++0x03 line.long 0x00 "SBUSCFG,System Bus Config" bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte 0x100++0x00 line.byte 0x00 "CAPLENGTH,Address offset to the Operational registers" rgroup.word 0x102++0x01 line.word 0x00 "HCIVERSION,EHCI revision number supported by this host controller" rgroup.long 0x104++0x07 line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT ,Number of transaction translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT ,Number of ports per transaction translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16. " PI ,Port Indicators" "Low,High" bitfld.long 0x00 12.--15. " N_CC ,Number of companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " N_PCC ,Number of ports per companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port power control" "Not included,Included" newline bitfld.long 0x00 0.--3. " N_PORTS ,Number of downstream ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI extended capabilities pointer" bitfld.long 0x04 4.--7. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported" bitfld.long 0x04 1. " PFL ,Programmable frame list flag" "Disabled,Enabled" newline bitfld.long 0x04 0. " ADC ,64-bit addressing capability" "Not supported,Supported" rgroup.word 0x120++0x01 line.word 0x00 "DCIVERSION,Device Interface Version Number Register" rgroup.long 0x124++0x03 line.long 0x00 "DCCPARAMS,Device Control Capability Parameters Register" bitfld.long 0x00 8. " HC ,Host capable" "Not supported,Supported" bitfld.long 0x00 7. " DC ,Device capable" "Not supported,Supported" newline bitfld.long 0x00 0.--4. " DEN ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." group.long 0x140++0x03 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD tripwire" "Not added,Added" newline bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Hazard,No hazard" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" "0,1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame list size 1" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset" newline bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" if (((per.l(ad:0x02184200+0x1A8))&0x03)==0x03) group.long 0x144++0x03 line.long 0x00 "USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" newline rbitfld.long 0x00 16. " NAKI ,NAK interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous schedule status" "Disabled,Enabled" newline rbitfld.long 0x00 14. " PS ,Periodic schedule status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty" newline rbitfld.long 0x00 12. " HCH ,HC halted" "Not halted,Halted" bitfld.long 0x00 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " SRI ,SOF received" "Not detected,Detected" bitfld.long 0x00 5. " AAI ,Interrupt on async advance" "Not requested,Requested" newline bitfld.long 0x00 4. " SEI ,System error" "No error,Error" bitfld.long 0x00 3. " FRI ,Frame list rollover" "Not rollover,Rollover" newline bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed" bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error" newline bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt" else group.long 0x144++0x03 line.long 0x00 "USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt" newline rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset" newline bitfld.long 0x00 4. " SEI ,System Error" "No error,Error" bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed" newline bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error" bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" endif group.long 0x148++0x07 line.long 0x00 "USBINTR,USB Interrupt Enable" bitfld.long 0x00 25. " TIE1 ,GPT interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,GPT interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " ULPIE ,ULPI enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,SOF received enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " URE ,USB reset enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on async Advance Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame list rollover enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x04 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index" if (((per.l(ad:0x02184200+0x1A8))&0x03)==0x03) group.long 0x154++0x07 line.long 0x00 "PERIODICLISTBASE,Host Controller Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base address (Low)" line.long 0x04 "ASYNCLISTADDR,Host Controller Next Asynch Address Register" hexmask.long 0x04 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low" elif (((per.l(ad:0x02184200+0x1A8))&0x03)==0x02) group.long 0x154++0x07 line.long 0x00 "DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x02 " BASEADR ,USB device address" newline bitfld.long 0x00 24. " USBADRA ,Write method to USBADR" "Instantaneous,Staged/hidden register" line.long 0x04 "ENDPTLISTADDR,Device Controller Endpoint List Address Register" hexmask.long.tbyte 0x04 11.--31. 0x08 " EPBASE[31:11] ,Device controller endpoint list address" endif group.long 0x160++0x07 line.long 0x00 "BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX burst length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX burst length" line.long 0x04 "TXFILLTUNING,TX FIFO Fill Tuning Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO burst threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler health counter" newline hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler overhead" group.long 0x178++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK register" bitfld.long 0x00 23. " EPTN[7] ,TX Endpoint NAK 7" "Low,High" bitfld.long 0x00 22. " [6] ,TX endpoint NAK 6" "Low,High" newline bitfld.long 0x00 21. " [5] ,TX endpoint NAK 5" "Low,High" bitfld.long 0x00 20. " [4] ,TX endpoint NAK 4" "Low,High" newline bitfld.long 0x00 19. " [3] ,TX endpoint NAK 3" "Low,High" bitfld.long 0x00 18. " [2] ,TX endpoint NAK 2" "Low,High" newline bitfld.long 0x00 17. " [1] ,TX endpoint NAK 1" "Low,High" bitfld.long 0x00 16. " [0] ,TX endpoint NAK 0" "Low,High" newline bitfld.long 0x00 7. " EPRN[7] ,RX endpoint NAK 7" "Low,High" bitfld.long 0x00 6. " [6] ,RX endpoint NAK 6" "Low,High" newline bitfld.long 0x00 5. " [5] ,RX endpoint NAK 5" "Low,High" bitfld.long 0x00 4. " [4] ,RX endpoint NAK 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,RX endpoint NAK 3" "Low,High" bitfld.long 0x00 2. " [2] ,RX endpoint NAK 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,RX endpoint NAK 1" "Low,High" bitfld.long 0x00 0. " [0] ,RX endpoint NAK 0" "Low,High" line.long 0x04 "ENDPTNAKEN,Endpoint NAK register enable" bitfld.long 0x04 23. " EPTN[7] ,TX endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 22. " [6] ,TX endpoint NAK 6" "Disabled,Enabled" newline bitfld.long 0x04 21. " [5] ,TX endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,TX endpoint NAK 4" "Disabled,Enabled" newline bitfld.long 0x04 19. " [3] ,TX endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,TX endpoint NAK 2" "Disabled,Enabled" newline bitfld.long 0x04 17. " [1] ,TX endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,TX endpoint NAK 0" "Disabled,Enabled" newline bitfld.long 0x04 7. " EPRN[7] ,RX endpoint NAK 7" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,RX endpoint NAK 6" "Disabled,Enabled" newline bitfld.long 0x04 5. " [5] ,RX endpoint NAK 5" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,RX endpoint NAK 4" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,RX endpoint NAK 3" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,RX endpoint NAK 2" "Disabled,Enabled" newline bitfld.long 0x04 1. " [1] ,RX endpoint NAK 1" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,RX endpoint NAK 0" "Disabled,Enabled" rgroup.long 0x180++0x03 line.long 0x00 "CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Configure flag" "Classic host,This host" if (((per.l(ad:0x02184200+0x1A8))&0x03)==0x03) group.long 0x184++0x03 line.long 0x00 "PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel transceiver select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." newline bitfld.long 0x00 29. " STS ,Serial transceiver select" "Not selected,Selected" newline bitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full,Low,High,?..." newline bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "Not suspended,Suspended" newline bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " PTC[3:0] ,Port test control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." newline bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Disabled,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Port owner" "Cleared,Set" newline bitfld.long 0x00 12. " PP ,Port power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." newline rbitfld.long 0x00 9. " HSP ,High-speed port" "Not high-speed,High-speed" bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" newline bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" newline eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" newline eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" newline eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current connect status" "No device,Device" else group.long 0x184++0x03 line.long 0x00 "PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel transceiver select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." newline bitfld.long 0x00 29. " STS ,Serial transceiver select" "Not selected,Selected" newline bitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full,Low,High,?..." newline bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "Not suspended,Suspended" newline bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " PTC[3:0] ,Port test control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." newline bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Disabled,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Port owner" "Cleared,Set" newline bitfld.long 0x00 12. " PP ,Port power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." newline rbitfld.long 0x00 9. " HSP ,High-speed port" "Not high-speed,High-speed" rbitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" newline rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" newline eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" newline eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" newline eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current connect status" "No device,Device" endif group.long 0x1A4++0x03 line.long 0x00 "OTGSC,OTG Status Control Register" bitfld.long 0x00 30. " DPIE ,Data pulse interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " 1MSE ,1 milisecond timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " BSEIE ,B session end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B session valid interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " ASVIE ,A session valid interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus valid interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IDIE ,USB ID interrupt enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data pulse interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x00 21. " STATUS_1MS ,1 milisecond timer interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 20. " BSEIS ,B session end interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " BSVIS ,B Session valid interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 18. " ASVIS ,A session valid interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x00 17. " AVVIS ,A VBus valid interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 16. " IDIS ,USB ID interrupt status" "No interrupt,Interrupt" newline rbitfld.long 0x00 14. " DPS ,Data bus pulsing status" "Not detected,Detected" rbitfld.long 0x00 13. " OG_1MS ,1 millisecond timer toggle" "Not toggled,Toggled" newline rbitfld.long 0x00 12. " BSE ,B session end" "Not ended,Ended" rbitfld.long 0x00 11. " BSV ,B session valid" "Not valid,Valid" newline rbitfld.long 0x00 10. " ASV ,A Session valid" "Not valid,Valid" rbitfld.long 0x00 9. " AVV ,A VBus valid" "Not valid,Valid" newline rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 5. " IDPU ,ID pullup" "Disabled,Enabled" newline bitfld.long 0x00 4. " DP ,Data pulsing" "Disabled,Enabled" bitfld.long 0x00 3. " OT ,OTG termination" "Disabled,Enabled" newline bitfld.long 0x00 1. " VC ,VBUS charge" "Not charged,Charged" bitfld.long 0x00 0. " VD ,VBUS discharge" "Not discharged,Discharged" group.long 0x1A8++0x03 line.long 0x00 "USBMODE,USB Device Mode Register" bitfld.long 0x00 4. " SDIS ,Stream disable mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup lockout mode" "On,Off" newline bitfld.long 0x00 2. " ES ,Endian select" "Little,Big" bitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device,Host" newline if (((per.l(ad:0x02184200+0x1A8))&0x03)==0x02) group.long 0x1AC++0x0B line.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" bitfld.long 0x00 15. " ENDPTSETUPSTAT[15] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 14. " ENDPTSETUPSTAT[14] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 13. " ENDPTSETUPSTAT[13] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 12. " ENDPTSETUPSTAT[12] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 11. " ENDPTSETUPSTAT[11] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 10. " ENDPTSETUPSTAT[10] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 9. " ENDPTSETUPSTAT[09] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 8. " ENDPTSETUPSTAT[08] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 7. " ENDPTSETUPSTAT[07] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 6. " ENDPTSETUPSTAT[06] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 5. " ENDPTSETUPSTAT[05] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 4. " ENDPTSETUPSTAT[04] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 3. " ENDPTSETUPSTAT[03] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 2. " ENDPTSETUPSTAT[02] ,Setup endpoint status" "Not received,Received" newline bitfld.long 0x00 1. " ENDPTSETUPSTAT[01] ,Setup endpoint status" "Not received,Received" bitfld.long 0x00 0. " ENDPTSETUPSTAT[00] ,Setup endpoint status" "Not received,Received" newline line.long 0x04 "ENDPTPRIME,Endpoint Initialization Register" bitfld.long 0x04 23. " PETB7 ,Prime endpoint transmit buffer" "Not prime,Prime" bitfld.long 0x04 22. " PETB6 ,Prime endpoint transmit buffer" "Not prime,Prime" newline bitfld.long 0x04 21. " PETB5 ,Prime endpoint transmit buffer" "Not prime,Prime" bitfld.long 0x04 20. " PETB4 ,Prime endpoint transmit buffer" "Not prime,Prime" newline bitfld.long 0x04 19. " PETB3 ,Prime endpoint transmit buffer" "Not prime,Prime" bitfld.long 0x04 18. " PETB2 ,Prime endpoint transmit buffer" "Not prime,Prime" newline bitfld.long 0x04 17. " PETB1 ,Prime endpoint transmit buffer" "Not prime,Prime" bitfld.long 0x04 16. " PETB0 ,Prime endpoint transmit buffer" "Not prime,Prime" newline bitfld.long 0x04 7. " PERB7 ,Prime endpoint receive buffer" "Not prime,Prime" bitfld.long 0x04 6. " PERB6 ,Prime endpoint receive buffer" "Not prime,Prime" newline bitfld.long 0x04 5. " PERB5 ,Prime endpoint receive buffer" "Not prime,Prime" bitfld.long 0x04 4. " PERB4 ,Prime endpoint receive buffer" "Not prime,Prime" newline bitfld.long 0x04 3. " PERB3 ,Prime endpoint receive buffer" "Not prime,Prime" bitfld.long 0x04 2. " PERB2 ,Prime endpoint receive buffer" "Not prime,Prime" newline bitfld.long 0x04 1. " PERB1 ,Prime endpoint receive buffer" "Not prime,Prime" bitfld.long 0x04 0. " PERB0 ,Prime endpoint receive buffer" "Not prime,Prime" line.long 0x08 "ENDPTFLUSH,Endpoint De-Initialize Register" bitfld.long 0x08 23. " FETB7 ,Flush endpoint transmit buffer" "Not flushed,Flushed" bitfld.long 0x08 22. " FETB6 ,Flush endpoint transmit buffer" "Not flushed,Flushed" newline bitfld.long 0x08 21. " FETB5 ,Flush endpoint transmit buffer" "Not flushed,Flushed" bitfld.long 0x08 20. " FETB4 ,Flush endpoint transmit buffer" "Not flushed,Flushed" newline bitfld.long 0x08 19. " FETB3 ,Flush endpoint transmit buffer" "Not flushed,Flushed" bitfld.long 0x08 18. " FETB2 ,Flush endpoint transmit buffer" "Not flushed,Flushed" newline bitfld.long 0x08 17. " FETB1 ,Flush endpoint transmit buffer" "Not flushed,Flushed" bitfld.long 0x08 16. " FETB0 ,Flush endpoint transmit buffer" "Not flushed,Flushed" newline bitfld.long 0x08 7. " FERB7 ,Flush endpoint receive buffer" "Not flushed,Flushed" bitfld.long 0x08 6. " FERB6 ,Flush endpoint receive buffer" "Not flushed,Flushed" newline bitfld.long 0x08 5. " FERB5 ,Flush endpoint receive buffer" "Not flushed,Flushed" bitfld.long 0x08 4. " FERB4 ,Flush endpoint receive buffer" "Not flushed,Flushed" newline bitfld.long 0x08 3. " FERB3 ,Flush endpoint receive buffer" "Not flushed,Flushed" bitfld.long 0x08 2. " FERB2 ,Flush endpoint receive buffer" "Not flushed,Flushed" newline bitfld.long 0x08 1. " FERB1 ,Flush endpoint receive buffer" "Not flushed,Flushed" bitfld.long 0x08 0. " FERB0 ,Flush endpoint receive buffer" "Not flushed,Flushed" rgroup.long 0x1B8++0x03 line.long 0x00 "ENDPTSTAT,Endpoint Status Register" bitfld.long 0x00 23. " ETBR7 ,Endpoint transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 22. " ETBR6 ,Endpoint transmit buffer ready" "Not ready,Ready" newline bitfld.long 0x00 21. " ETBR5 ,Endpoint transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 20. " ETBR4 ,Endpoint transmit buffer ready" "Not ready,Ready" newline bitfld.long 0x00 19. " ETBR3 ,Endpoint transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 18. " ETBR2 ,Endpoint transmit buffer ready" "Not ready,Ready" newline bitfld.long 0x00 17. " ETBR1 ,Endpoint transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 16. " ETBR0 ,Endpoint transmit buffer ready" "Not ready,Ready" newline bitfld.long 0x00 7. " ERBR7 ,Endpoint receive buffer ready" "Not ready,Ready" bitfld.long 0x00 6. " ERBR6 ,Endpoint receive buffer ready" "Not ready,Ready" newline bitfld.long 0x00 5. " ERBR5 ,Endpoint receive buffer ready" "Not ready,Ready" bitfld.long 0x00 4. " ERBR4 ,Endpoint receive buffer ready" "Not ready,Ready" newline bitfld.long 0x00 3. " ERBR3 ,Endpoint receive buffer ready" "Not ready,Ready" bitfld.long 0x00 2. " ERBR2 ,Endpoint receive buffer ready" "Not ready,Ready" newline bitfld.long 0x00 1. " ERBR1 ,Endpoint receive buffer ready" "Not ready,Ready" bitfld.long 0x00 0. " ERBR0 ,Endpoint receive buffer ready" "Not ready,Ready" group.long 0x1BC++0x03 line.long 0x00 "ENDPTCOMPLETE,Endpoint Compete Register" eventfld.long 0x00 23. " ETCE7 ,Endpoint transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 22. " ETCE6 ,Endpoint transmit complete event" "Not occurred,Occurred" newline eventfld.long 0x00 21. " ETCE5 ,Endpoint transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 20. " ETCE4 ,Endpoint transmit complete event" "Not occurred,Occurred" newline eventfld.long 0x00 19. " ETCE3 ,Endpoint transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 18. " ETCE2 ,Endpoint transmit complete event" "Not occurred,Occurred" newline eventfld.long 0x00 17. " ETCE1 ,Endpoint transmit complete event" "Not occurred,Occurred" eventfld.long 0x00 16. " ETCE0 ,Endpoint transmit complete event" "Not occurred,Occurred" newline eventfld.long 0x00 7. " ERCE7 ,Endpoint receive complete event" "Not occurred,Occurred" eventfld.long 0x00 6. " ERCE6 ,Endpoint receive complete event" "Not occurred,Occurred" newline eventfld.long 0x00 5. " ERCE5 ,Endpoint receive complete event" "Not occurred,Occurred" eventfld.long 0x00 4. " ERCE4 ,Endpoint receive complete event" "Not occurred,Occurred" newline eventfld.long 0x00 3. " ERCE3 ,Endpoint receive complete event" "Not occurred,Occurred" eventfld.long 0x00 2. " ERCE2 ,Endpoint receive complete event" "Not occurred,Occurred" newline eventfld.long 0x00 1. " ERCE1 ,Endpoint receive complete event" "Not occurred,Occurred" eventfld.long 0x00 0. " ERCE0 ,Endpoint receive complete event" "Not occurred,Occurred" else hgroup.long 0x1AC++0x03 hide.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status Register" hgroup.long 0x1B0++0x03 hide.long 0x00 "ENDPTPRIME,Endpoint Initialization Register" hgroup.long 0x1B4++0x03 hide.long 0x00 "ENDPTFLUSH,Endpoint De-Initialize Register" hgroup.long 0x1B8++0x03 hide.long 0x00 "ENDPTSTAT,Endpoint Status Register" hgroup.long 0x1BC++0x03 hide.long 0x00 "ENDPTCOMPLETE,Endpoint Compete Register" endif group.long 0x1C0++0x03 line.long 0x00 "ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,?..." newline bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled" if (((per.l(ad:0x02184200+0x1A8))&0x03)==0x02) group.long 0x1C0++0x03 line.long 0x00 "ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1C4++0x03 line.long 0x00 "ENDPTCTRL1,Endpoint Control 1 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1C8++0x03 line.long 0x00 "ENDPTCTRL2,Endpoint Control 2 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1CC++0x03 line.long 0x00 "ENDPTCTRL3,Endpoint Control 3 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1D0++0x03 line.long 0x00 "ENDPTCTRL4,Endpoint Control 4 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1D4++0x03 line.long 0x00 "ENDPTCTRL5,Endpoint Control 5 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1D8++0x03 line.long 0x00 "ENDPTCTRL6,Endpoint Control 6 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1DC++0x03 line.long 0x00 "ENDPTCTRL7,Endpoint Control 7 Register" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,RX data toggle reset" "No effect,Reset" newline bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,?..." newline bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Dual port memory buffer/DMA Engine,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else hgroup.long 0x1C0++0x03 hide.long 0x00 "ENDPTCTRL0,Endpoint Control 0 Register" hgroup.long 0x1C4++0x03 hide.long 0x00 "ENDPTCTRL1,Endpoint Control 1 Register" hgroup.long 0x1C8++0x03 hide.long 0x00 "ENDPTCTRL2,Endpoint Control 2 Register" hgroup.long 0x1CC++0x03 hide.long 0x00 "ENDPTCTRL3,Endpoint Control 3 Register" hgroup.long 0x1D0++0x03 hide.long 0x00 "ENDPTCTRL4,Endpoint Control 4 Register" hgroup.long 0x1D4++0x03 hide.long 0x00 "ENDPTCTRL5,Endpoint Control 5 Register" hgroup.long 0x1D8++0x03 hide.long 0x00 "ENDPTCTRL6,Endpoint Control 6 Register" hgroup.long 0x1DC++0x03 hide.long 0x00 "ENDPTCTRL7,Endpoint Control 7 Register" endif width 0x0B tree.end tree "UH 1" base ad:0x02184400 width 11. rgroup.long 0x00++0x0B line.long 0x00 "ID,Identification Register" hexmask.long.byte 0x00 16.--23. 1. " REVISION ,Revision Number of the Core" hexmask.long.byte 0x00 8.--13. 1. " NID ,Ones Complement Version of ID" newline hexmask.long.byte 0x00 0.--5. 1. " ID ,Configuration Number" line.long 0x04 "HWGENERAL,General Hardware Register" bitfld.long 0x04 9.--10. " SM ,Serial interface mode capability" "No engine/parallel signaling,Engine present/serial signaling,Soft programmable/Reset to parallel,Soft programmable/Reset to serial" newline bitfld.long 0x04 6.--8. " PHYM ,Transceiver type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Soft programmable reset to UTMI/UMTI+,Soft programmable reset to ULPI DDR,Soft programmable reset to ULPI,Soft programmable reset to Serial" newline bitfld.long 0x04 4.--5. " PHYW ,Data width of the transceiver connected to the controller core" "8 bit non programmable,16 bit non programmable,8 bit programmable,16 bit programmable" line.long 0x08 "HWHOST,Host Hardware Parameters Register" bitfld.long 0x08 1.--3. " NPORT ,Number of downstream ports supported by the host controller" "1,2,3,4,5,6,7,8" bitfld.long 0x08 0. " HC ,Host operation mode support for device" "Not supported,Supported" rgroup.long 0x10++0x07 line.long 0x00 "HWTXBUF,TX Buffer Hardware Parameters Register" hexmask.long.byte 0x00 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint" hexmask.long.byte 0x00 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer" line.long 0x04 "HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints" hexmask.long.byte 0x04 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer" width 16. group.long 0x80++0x0F "Device/Host Timer Registers" line.long 0x00 "GPTIMER0LD,General Purpose Timer #0 Load Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x04 "GPTIMER0CTRL,General Purpose Timer #0 Controller" bitfld.long 0x04 31. " GPTRUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x04 30. " GPTRST ,General purpose timer reset" "No effect,Reset" newline bitfld.long 0x04 24. " GPTMODE ,General purpose timer mode" "One Shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x08 "GPTIMER1LD,General Purpose Timer #1 Load Register" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x0C "GPTIMER1CTRL,General purpose timer #1 Controller" bitfld.long 0x0C 31. " GPTRUN ,General purpose timer Run" "Stopped,Running" bitfld.long 0x0C 30. " GPTRST ,General purpose timer Reset" "No effect,Reset" newline bitfld.long 0x0C 24. " GPTMODE ,General purpose timer mode" "One Shot,Repeat" hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General purpose timer counter" group.long 0x90++0x03 line.long 0x00 "SBUSCFG,System Bus Config" bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface burst configuration" "Incremental/Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified" rgroup.byte 0x100++0x00 line.byte 0x00 "CAPLENGTH,Address offset to the Operational registers" rgroup.word 0x102++0x01 line.word 0x00 "HCIVERSION,EHCI revision number supported by this host controller" rgroup.long 0x104++0x07 line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 24.--27. " N_TT ,Number of transaction translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT ,Number of ports per transaction translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16. " PI ,Port Indicators" "Low,High" bitfld.long 0x00 12.--15. " N_CC ,Number of companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " N_PCC ,Number of ports per companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port power control" "Not included,Included" newline bitfld.long 0x00 0.--3. " N_PORTS ,Number of downstream ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI extended capabilities pointer" bitfld.long 0x04 4.--7. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported" bitfld.long 0x04 1. " PFL ,Programmable frame list flag" "Disabled,Enabled" newline bitfld.long 0x04 0. " ADC ,64-bit addressing capability" "Not supported,Supported" group.long 0x140++0x03 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD tripwire" "Not added,Added" newline bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Hazard,No hazard" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" "0,1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame list size 1" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset" newline bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" group.long 0x148++0x07 line.long 0x00 "USBINTR,USB Interrupt Enable" bitfld.long 0x00 25. " TIE1 ,GPT interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,GPT interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " ULPIE ,ULPI enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,SOF received enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " URE ,USB reset enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on async Advance Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame list rollover enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x04 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index" if (((per.l(ad:0x02184400+0x1A8))&0x03)==0x03) group.long 0x154++0x07 line.long 0x00 "PERIODICLISTBASE,Host Controller Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base address (Low)" line.long 0x04 "ASYNCLISTADDR,Host Controller Next Asynch Address Register" hexmask.long 0x04 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low" endif group.long 0x160++0x07 line.long 0x00 "BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register" hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX burst length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX burst length" line.long 0x04 "TXFILLTUNING,TX FIFO Fill Tuning Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO burst threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler health counter" newline hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler overhead" rgroup.long 0x180++0x03 line.long 0x00 "CONFIGFLAG,Configure Flag Register" bitfld.long 0x00 0. " CF ,Configure flag" "Classic host,This host" if (((per.l(ad:0x02184400+0x1A8))&0x03)==0x03) group.long 0x184++0x03 line.long 0x00 "PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel transceiver select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." newline bitfld.long 0x00 29. " STS ,Serial transceiver select" "Not selected,Selected" newline bitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full,Low,High,?..." newline bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "Not suspended,Suspended" newline bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " PTC[3:0] ,Port test control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." newline bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Disabled,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Port owner" "Cleared,Set" newline bitfld.long 0x00 12. " PP ,Port power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." newline rbitfld.long 0x00 9. " HSP ,High-speed port" "Not high-speed,High-speed" bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" newline bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" newline eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" newline eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" newline eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current connect status" "No device,Device" else group.long 0x184++0x03 line.long 0x00 "PORTSC1,Port 1 Status and Control Register" bitfld.long 0x00 30.--31. 25. " PTS ,Parallel transceiver select" "HSIC,HSIC,UTMI/UTMI+,,ULPI,Serial/USB 1.1 PHY/IC-USB,HSIC,?..." newline bitfld.long 0x00 29. " STS ,Serial transceiver select" "Not selected,Selected" newline bitfld.long 0x00 28. " PTW ,Parallel transceiver width" "8-bit,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full,Low,High,?..." newline bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "Not suspended,Suspended" newline bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDC ,Wake on disconnect enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " PTC[3:0] ,Port test control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." newline bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "Disabled,Amber,Green,?..." bitfld.long 0x00 13. " PO ,Port owner" "Cleared,Set" newline bitfld.long 0x00 12. " PP ,Port power" "Not available,Available" bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." newline rbitfld.long 0x00 9. " HSP ,High-speed port" "Not high-speed,High-speed" rbitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" newline rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" newline eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" newline eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" newline eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current connect status" "No device,Device" endif group.long 0x1A8++0x03 line.long 0x00 "USBMODE,USB Device Mode Register" bitfld.long 0x00 4. " SDIS ,Stream disable mode" "Inactive,Active" bitfld.long 0x00 3. " SLOM ,Setup lockout mode" "On,Off" newline bitfld.long 0x00 2. " ES ,Endian select" "Little,Big" bitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device,Host" newline width 0x0B tree.end tree.end tree.end tree "USB_PHY (Universal Serial Bus 2.0 Integrated PHY)" tree.open "USB_PHY" tree "USBPHY 1" base ad:0x020C9000 width 14. group.long 0x00++0x03 line.long 0x00 "PWD_SET/CLR,USB PHY Power-Down Register" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " RXPWDRX ,Power-down the entire USB PHY receiver block except for the full-speed differential receiver" "Powered up,Powered down" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " RXPWDDIFF ,Power-down the USB high-speed differential receiver" "Powered up,Powered down" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " RXPWD1PT1 ,Power-down the USB full-speed differential receiver" "Powered up,Powered down" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " RXPWDENV ,Power-down the USB high-speed receiver envelope detector (squelch signal)" "Powered up,Powered down" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " TXPWDV2I ,Power-down the USB PHY transmit V-to-I converter and the current mirror" "Powered up,Powered down" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " TXPWDIBIAS ,Power-down the USB PHY current bias block for the transmitter" "Powered up,Powered down" newline setclrfld.long 0x00 10. 0x04 10. 0x08 10. " TXPWDFS ,Power-down the USB full-speed drivers" "Powered up,Powered down" group.long 0x0C++0x27 line.long 0x00 "PWD_TOG,USB PHY Power-Down Register" bitfld.long 0x00 20. " RXPWDRX ,Power-down the entire USB PHY receiver block except for the full-speed differential receiver" "Powered up,Powered down" bitfld.long 0x00 19. " RXPWDDIFF ,Power-down the USB high-speed differential receiver" "Powered up,Powered down" bitfld.long 0x00 18. " RXPWD1PT1 ,Power-down the USB full-speed differential receiver" "Powered up,Powered down" newline bitfld.long 0x00 17. " RXPWDENV ,Power-down the USB high-speed receiver envelope detector (squelch signal)" "Powered up,Powered down" bitfld.long 0x00 12. " TXPWDV2I ,Power-down the USB PHY transmit V-to-I converter and the current mirror" "Powered up,Powered down" bitfld.long 0x00 11. " TXPWDIBIAS ,Power-down the USB PHY current bias block for the transmitter" "Powered up,Powered down" newline bitfld.long 0x00 10. " TXPWDFS ,Power-down the USB full-speed drivers" "Powered up,Powered down" line.long 0x04 "TX,USB PHY Transmitter Control Register" bitfld.long 0x04 26.--28. " USBPHY_TX_EDGECTRL ,Edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--19. " TXCAL45DP ,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " TXCAL45DN ,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " D_CAL ,Resistor trimming code" "0.16%,,,,,,,,,,,,,,Nominal,+25%" line.long 0x08 "TX_SET,USB PHY Transmitter Control Register" bitfld.long 0x08 26.--28. " USBPHY_TX_EDGECTRL ,Edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--19. " TXCAL45DP ,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " TXCAL45DN ,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " D_CAL ,Resistor trimming code" "0.16%,,,,,,,,,,,,,,Nominal,+25%" line.long 0x0C "TX_CLR,USB PHY Transmitter Control Register" bitfld.long 0x0C 26.--28. " USBPHY_TX_EDGECTRL ,Edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--19. " TXCAL45DP ,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. " TXCAL45DN ,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. " D_CAL ,Resistor trimming code" "0.16%,,,,,,,,,,,,,,Nominal,+25%" line.long 0x10 "TX_TOG,USB PHY Transmitter Control Register" bitfld.long 0x10 26.--28. " USBPHY_TX_EDGECTRL ,Edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--19. " TXCAL45DP ,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. " TXCAL45DN ,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. " D_CAL ,Resistor trimming code" "0.16%,,,,,,,,,,,,,,Nominal,+25%" line.long 0x14 "RX,USB PHY Receiver Control Register" setclrfld.long 0x14 22. 0x18 22. 0x1C 22. " RXDBYPASS_SET/CLR ,Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver" "Not used,Used" bitfld.long 0x14 4.--6. " DISCONADJ ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." bitfld.long 0x14 0.--2. " ENVADJ ,The ENVADJ field adjusts the trip point for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x18 "RX_SET,USB PHY Receiver Control Register" bitfld.long 0x18 4.--6. " DISCONADJ ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." bitfld.long 0x18 0.--2. " ENVADJ ,The ENVADJ field adjusts the trip point for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x1C "RX_CLR,USB PHY Receiver Control Register" bitfld.long 0x1C 4.--6. " DISCONADJ ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." bitfld.long 0x1C 0.--2. " ENVADJ ,The ENVADJ field adjusts the trip point for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x20 "RX_TOG,USB PHY Receiver Control Register" bitfld.long 0x20 22. " RXDBYPASS ,Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver" "Not used,Used" bitfld.long 0x20 4.--6. " DISCONADJ ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." bitfld.long 0x20 0.--2. " ENVADJ ,The ENVADJ field adjusts the trip point for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x24 "CTRL,USB PHY General Control Register" setclrfld.long 0x24 31. 0x28 31. 0x2C 31. " SFTRST_SET/CLR ,Soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers" "No reset,Reset" setclrfld.long 0x24 30. 0x28 30. 0x2C 30. " CLKGATE_SET/CLR ,Gate UTMI clocks" "Not gated,Gated" rbitfld.long 0x24 29. " UTMI_SUSPENDM ,Indicate a powered-down state" "Powered up,Powered down" newline setclrfld.long 0x24 28. 0x28 28. 0x2C 28. " HOST_FORCE_LS_SE0_SET/CLR ,Forces the next FS packet that is transmitted to have a EOP with LS timing" "Not forced,Forced" rbitfld.long 0x24 27. " OTG_ID_VALUE ,Results of ID pin on MiniAB plug" "False,True" setclrfld.long 0x24 24. 0x28 24. 0x2C 24. " FSDLL_RST_EN_SET/CLR ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "Disabled,Enabled" newline setclrfld.long 0x24 23. 0x28 23. 0x2C 23. " ENVBUSCHG_WKUP_SET/CLR ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "Disabled,Enabled" setclrfld.long 0x24 22. 0x28 22. 0x2C 22. " ENIDCHG_WKUP_SET/CLR ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "Disabled,Enabled" setclrfld.long 0x24 21. 0x28 21. 0x2C 21. " ENDPDMCHG_WKUP_SET/CLR ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "Disabled,Enabled" newline setclrfld.long 0x24 20. 0x28 20. 0x2C 20. " ENAUTOCLR_PHY_PWD_SET/CLR ,Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended" "Disabled,Enabled" setclrfld.long 0x24 19. 0x28 19. 0x2C 19. " ENAUTOCLR_CLKGATE_SET/CLR ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "Disabled,Enabled" setclrfld.long 0x24 18. 0x28 18. 0x2C 18. " ENAUTO_PWRON_PLL_SET/CLR ,Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended" "Disabled,Enabled" newline setclrfld.long 0x24 17. 0x28 17. 0x2C 17. " WAKEUP_IRQ_SET/CLR ,Indicates that there is a wakeup event" "Not occurred,Occurred" setclrfld.long 0x24 16. 0x28 16. 0x2C 16. " ENIRQWAKEUP_SET/CLR ,Enables interrupt for the wakeup events" "No interrupt,Interrupt" setclrfld.long 0x24 15. 0x28 15. 0x2C 15. " ENUTMILEVEL3_SET/CLR ,Enables UTMI+ Level3" "Disabled,Enabled" newline setclrfld.long 0x24 14. 0x28 14. 0x2C 14. " ENUTMILEVEL2_SET/CLR ,Enables UTMI+ Level2" "Disabled,Enabled" setclrfld.long 0x24 13. 0x28 13. 0x2C 13. " DATA_ON_LRADC_SET/CLR ,Enables the LRADC to monitor USB_DP and USB_DM" "Disabled,Enabled" setclrfld.long 0x24 12. 0x28 12. 0x2C 12. " DEVPLUGIN_IRQ_SET/CLR ,Indicates that the device is connected" "Not connected,Connected" newline setclrfld.long 0x24 11. 0x28 11. 0x2C 11. " ENIRQDEVPLUGIN_SET/CLR ,Enables interrupt for the detection of connectivity to the USB line" "No interrupt,Interrupt" setclrfld.long 0x24 10. 0x28 10. 0x2C 10. " RESUME_IRQ_SET/CLR ,Indicates that the host is sending a wake-up after suspend" "No wake-up,Wake-up" setclrfld.long 0x24 9. 0x28 9. 0x2C 9. " ENIRQRESUMEDETECT_SET/CLR ,Enables interrupt for detection of a non-J state on the USB line" "No interrupt,Interrupt" newline setclrfld.long 0x24 8. 0x28 8. 0x2C 8. " RESUMEIRQSTICKY_SET/CLR ,RESUME_IRQ bit a sticky bit until software clear it" "Not set,Set" setclrfld.long 0x24 7. 0x28 7. 0x2C 7. " ENOTGIDDETECT_SET/CLR ,Enables circuit to detect resistance of MiniAB ID pin" "Disabled,Enabled" setclrfld.long 0x24 6. 0x28 6. 0x2C 6. " OTG_ID_CHG_IRQ_SET/CLR ,OTG ID change interrupt" "Disabled,Enabled" newline setclrfld.long 0x24 5. 0x28 5. 0x2C 5. " DEVPLUGIN_POLARITY_SET/CLR ,Device plug in/unplugged interrupt polarity" "Plugged in,Unplugged" setclrfld.long 0x24 4. 0x28 4. 0x2C 4. " ENDEVPLUGINDETECT_SET/CLR ,Enables 200-KOhm pullups for detecting connectivity to the host" "Disabled,Enabled" setclrfld.long 0x24 3. 0x28 3. 0x2C 3. " HOSTDISCONDETECT_IRQ_SET/CLR ,Indicates that the device has disconnected in high-speed mode" "Connected,Disconnected" newline setclrfld.long 0x24 2. 0x28 2. 0x2C 2. " ENIRQHOSTDISCON_SET/CLR ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No interrupt,Interrupt" setclrfld.long 0x24 1. 0x28 1. 0x2C 1. " ENHOSTDISCONDETECT_SET/CLR ,Enables high-speed disconnect detector" "Disabled,Enabled" setclrfld.long 0x24 0. 0x28 0. 0x2C 0. " ENOTG_ID_CHG_IRQ_SET/CLR ,Enable OTG_ID_CHG_IRQ" "Disabled,Enabled" group.long 0x3C++0x07 line.long 0x00 "CTRL_TOG,USB PHY General Control Register" bitfld.long 0x00 31. " SFTRST ,Soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate UTMI clocks" "Not gated,Gated" rbitfld.long 0x00 29. " UTMI_SUSPENDM ,Indicate a powered-down state" "Powered up,Powered down" newline bitfld.long 0x00 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with LS timing" "Not forced,Forced" rbitfld.long 0x00 27. " OTG_ID_VALUE ,Results of ID pin on MiniAB plug" "False,True" bitfld.long 0x00 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "Disabled,Enabled" newline bitfld.long 0x00 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "Disabled,Enabled" bitfld.long 0x00 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "Disabled,Enabled" bitfld.long 0x00 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "Disabled,Enabled" newline bitfld.long 0x00 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended" "Disabled,Enabled" bitfld.long 0x00 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "Disabled,Enabled" bitfld.long 0x00 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended" "Disabled,Enabled" newline bitfld.long 0x00 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "Not occurred,Occurred" bitfld.long 0x00 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "No interrupt,Interrupt" bitfld.long 0x00 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "Disabled,Enabled" newline bitfld.long 0x00 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "Disabled,Enabled" bitfld.long 0x00 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "Disabled,Enabled" bitfld.long 0x00 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "Not connected,Connected" newline bitfld.long 0x00 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "No interrupt,Interrupt" bitfld.long 0x00 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "No wake-up,Wake-up" bitfld.long 0x00 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No interrupt,Interrupt" newline bitfld.long 0x00 8. " RESUMEIRQSTICKY ,RESUME_IRQ bit a sticky bit until software clear it" "Not set,Set" bitfld.long 0x00 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Disabled,Enabled" bitfld.long 0x00 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt" "Disabled,Enabled" newline bitfld.long 0x00 5. " DEVPLUGIN_POLARITY ,Device plug in/unplugged interrupt polarity" "Plugged in,Unplugged" bitfld.long 0x00 4. " ENDEVPLUGINDETECT ,Enables 200-KOhm pullups for detecting connectivity to the host" "Disabled,Enabled" bitfld.long 0x00 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "Connected,Disconnected" newline bitfld.long 0x00 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No interrupt,Interrupt" bitfld.long 0x00 1. " ENHOSTDISCONDETECT ,Enables high-speed disconnect detector" "Disabled,Enabled" bitfld.long 0x00 0. " ENOTG_ID_CHG_IRQ ,Enable OTG_ID_CHG_IRQ" "Disabled,Enabled" line.long 0x04 "STATUS,USB PHY Status Register" rbitfld.long 0x04 10. " RESUME_STATUS ,Indicates that the host is sending a wake-up after suspend and has triggered an interrupt" "No interrupt,Interrupt" bitfld.long 0x04 8. " OTGID_STATUS ,Indicates the results of ID pin on MiniAB plug" "False,True" rbitfld.long 0x04 6. " DEVPLUGIN_STATUS ,Indicates that the device has been connected on the USB_DP and USB_DM lines" "Disconnected,Connected" newline rbitfld.long 0x04 3. " HOSTDISCONDETECT_STATUS ,Indicates that the device has disconnected while in high-speed host mode" "Connected,Disconnected" group.long 0x50++0x03 line.long 0x00 "DEBUG,USB PHY Debug Register" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Gate test clocks" "Not gated,Gated" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " HOST_RESUME_DEBUG_SET/CLR ,Host resume trigger SE0" "HOST_FORCE_LS_SE0,UTMI_SUSPEND" bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline setclrfld.long 0x00 24. 0x04 24. 0x08 24. " ENSQUELCHRESET_SET/CLR ,Allow squelch to reset high-speed receive" "Not allowed,Allowed" bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " ENTX2RXCOUNT_SET/CLR ,Allow a countdown to transition in between TX and RX" "Not allowed,Allowed" newline bitfld.long 0x00 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ENHSTPULLDOWN ,Enable host pulldown" "Disabled,USB_DM 15-KOhm,USB_DP 15-KOhm,?..." bitfld.long 0x00 2.--3. " HSTPULLDOWN ,Host pulldown" "Disabled,15-KOhm on USB_DM,15-KOhm on USB_DP,?..." newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " DEBUG_INTERFACE_HOLD_SET/CLR ,Use holding registers to assist in timing for external UTMI interface" "Not used,Used" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OTGIDPIOLOCK_SET/CLR ,Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value" "Not held,Held" group.long 0x5C++0x07 line.long 0x00 "DEBUG_TOG,USB PHY Debug Register" bitfld.long 0x00 30. " CLKGATE ,Gate test clocks" "Not gated,Gated" bitfld.long 0x00 29. " HOST_RESUME_DEBUG ,Host resume trigger SE0" "HOST_FORCE_LS_SE0,UTMI_SUSPEND" bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24. " ENSQUELCHRESET ,Allow squelch to reset high-speed receive" "Not allowed,Allowed" bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12. " ENTX2RXCOUNT ,Allow a countdown to transition in between TX and RX" "Not allowed,Allowed" newline bitfld.long 0x00 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ENHSTPULLDOWN ,Enable host pulldown" "Disabled,USB_DM 15-KOhm,USB_DP 15-KOhm,?..." bitfld.long 0x00 2.--3. " HSTPULLDOWN ,Host pulldown" "Disabled,15-KOhm on USB_DM,15-KOhm on USB_DP,?..." newline bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "Not used,Used" bitfld.long 0x00 0. " OTGIDPIOLOCK ,Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value" "Not held,Held" line.long 0x04 "DEBUG0_STATUS,UTMI Debug Status Register 0" bitfld.long 0x04 26.--31. " SQUELCH_COUNT ,Running count of the squelch reset instead of normal end for HS RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 16.--25. 1. " UTMI_RXERROR_FAIL_COUNT ,Running count of the UTMI_RXERROR" hexmask.long.word 0x04 0.--15. 1. " LOOP_BACK_FAIL_COUNT ,Running count of the failed pseudo-random generator loopback" group.long 0x70++0x0F line.long 0x00 "DEBUG1,UTMI Debug Status Register 1" bitfld.long 0x00 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x04 "DEBUG1_SET,UTMI Debug Status Register 1" bitfld.long 0x04 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x08 "DEBUG1_CLR,UTMI Debug Status Register 1" bitfld.long 0x08 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x0C "DEBUG1_TOG,UTMI Debug Status Register 1" bitfld.long 0x0C 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" rgroup.long 0x80++0x03 line.long 0x00 "VERSION,UTMI RTL Version" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed value reflecting the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed value reflecting the stepping of the RTL version" width 0x0B tree.end tree "USBPHY 2" base ad:0x020CA000 width 14. group.long 0x00++0x03 line.long 0x00 "PWD_SET/CLR,USB PHY Power-Down Register" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " RXPWDRX ,Power-down the entire USB PHY receiver block except for the full-speed differential receiver" "Powered up,Powered down" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " RXPWDDIFF ,Power-down the USB high-speed differential receiver" "Powered up,Powered down" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " RXPWD1PT1 ,Power-down the USB full-speed differential receiver" "Powered up,Powered down" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " RXPWDENV ,Power-down the USB high-speed receiver envelope detector (squelch signal)" "Powered up,Powered down" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " TXPWDV2I ,Power-down the USB PHY transmit V-to-I converter and the current mirror" "Powered up,Powered down" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " TXPWDIBIAS ,Power-down the USB PHY current bias block for the transmitter" "Powered up,Powered down" newline setclrfld.long 0x00 10. 0x04 10. 0x08 10. " TXPWDFS ,Power-down the USB full-speed drivers" "Powered up,Powered down" group.long 0x0C++0x27 line.long 0x00 "PWD_TOG,USB PHY Power-Down Register" bitfld.long 0x00 20. " RXPWDRX ,Power-down the entire USB PHY receiver block except for the full-speed differential receiver" "Powered up,Powered down" bitfld.long 0x00 19. " RXPWDDIFF ,Power-down the USB high-speed differential receiver" "Powered up,Powered down" bitfld.long 0x00 18. " RXPWD1PT1 ,Power-down the USB full-speed differential receiver" "Powered up,Powered down" newline bitfld.long 0x00 17. " RXPWDENV ,Power-down the USB high-speed receiver envelope detector (squelch signal)" "Powered up,Powered down" bitfld.long 0x00 12. " TXPWDV2I ,Power-down the USB PHY transmit V-to-I converter and the current mirror" "Powered up,Powered down" bitfld.long 0x00 11. " TXPWDIBIAS ,Power-down the USB PHY current bias block for the transmitter" "Powered up,Powered down" newline bitfld.long 0x00 10. " TXPWDFS ,Power-down the USB full-speed drivers" "Powered up,Powered down" line.long 0x04 "TX,USB PHY Transmitter Control Register" bitfld.long 0x04 26.--28. " USBPHY_TX_EDGECTRL ,Edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--19. " TXCAL45DP ,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " TXCAL45DN ,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " D_CAL ,Resistor trimming code" "0.16%,,,,,,,,,,,,,,Nominal,+25%" line.long 0x08 "TX_SET,USB PHY Transmitter Control Register" bitfld.long 0x08 26.--28. " USBPHY_TX_EDGECTRL ,Edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--19. " TXCAL45DP ,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " TXCAL45DN ,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " D_CAL ,Resistor trimming code" "0.16%,,,,,,,,,,,,,,Nominal,+25%" line.long 0x0C "TX_CLR,USB PHY Transmitter Control Register" bitfld.long 0x0C 26.--28. " USBPHY_TX_EDGECTRL ,Edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--19. " TXCAL45DP ,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. " TXCAL45DN ,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. " D_CAL ,Resistor trimming code" "0.16%,,,,,,,,,,,,,,Nominal,+25%" line.long 0x10 "TX_TOG,USB PHY Transmitter Control Register" bitfld.long 0x10 26.--28. " USBPHY_TX_EDGECTRL ,Edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--19. " TXCAL45DP ,Decode to select a 45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. " TXCAL45DN ,Decode to select a 45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. " D_CAL ,Resistor trimming code" "0.16%,,,,,,,,,,,,,,Nominal,+25%" line.long 0x14 "RX,USB PHY Receiver Control Register" setclrfld.long 0x14 22. 0x18 22. 0x1C 22. " RXDBYPASS_SET/CLR ,Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver" "Not used,Used" bitfld.long 0x14 4.--6. " DISCONADJ ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." bitfld.long 0x14 0.--2. " ENVADJ ,The ENVADJ field adjusts the trip point for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x18 "RX_SET,USB PHY Receiver Control Register" bitfld.long 0x18 4.--6. " DISCONADJ ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." bitfld.long 0x18 0.--2. " ENVADJ ,The ENVADJ field adjusts the trip point for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x1C "RX_CLR,USB PHY Receiver Control Register" bitfld.long 0x1C 4.--6. " DISCONADJ ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." bitfld.long 0x1C 0.--2. " ENVADJ ,The ENVADJ field adjusts the trip point for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x20 "RX_TOG,USB PHY Receiver Control Register" bitfld.long 0x20 22. " RXDBYPASS ,Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver" "Not used,Used" bitfld.long 0x20 4.--6. " DISCONADJ ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." bitfld.long 0x20 0.--2. " ENVADJ ,The ENVADJ field adjusts the trip point for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x24 "CTRL,USB PHY General Control Register" setclrfld.long 0x24 31. 0x28 31. 0x2C 31. " SFTRST_SET/CLR ,Soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers" "No reset,Reset" setclrfld.long 0x24 30. 0x28 30. 0x2C 30. " CLKGATE_SET/CLR ,Gate UTMI clocks" "Not gated,Gated" rbitfld.long 0x24 29. " UTMI_SUSPENDM ,Indicate a powered-down state" "Powered up,Powered down" newline setclrfld.long 0x24 28. 0x28 28. 0x2C 28. " HOST_FORCE_LS_SE0_SET/CLR ,Forces the next FS packet that is transmitted to have a EOP with LS timing" "Not forced,Forced" rbitfld.long 0x24 27. " OTG_ID_VALUE ,Results of ID pin on MiniAB plug" "False,True" setclrfld.long 0x24 24. 0x28 24. 0x2C 24. " FSDLL_RST_EN_SET/CLR ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "Disabled,Enabled" newline setclrfld.long 0x24 23. 0x28 23. 0x2C 23. " ENVBUSCHG_WKUP_SET/CLR ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "Disabled,Enabled" setclrfld.long 0x24 22. 0x28 22. 0x2C 22. " ENIDCHG_WKUP_SET/CLR ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "Disabled,Enabled" setclrfld.long 0x24 21. 0x28 21. 0x2C 21. " ENDPDMCHG_WKUP_SET/CLR ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "Disabled,Enabled" newline setclrfld.long 0x24 20. 0x28 20. 0x2C 20. " ENAUTOCLR_PHY_PWD_SET/CLR ,Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended" "Disabled,Enabled" setclrfld.long 0x24 19. 0x28 19. 0x2C 19. " ENAUTOCLR_CLKGATE_SET/CLR ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "Disabled,Enabled" setclrfld.long 0x24 18. 0x28 18. 0x2C 18. " ENAUTO_PWRON_PLL_SET/CLR ,Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended" "Disabled,Enabled" newline setclrfld.long 0x24 17. 0x28 17. 0x2C 17. " WAKEUP_IRQ_SET/CLR ,Indicates that there is a wakeup event" "Not occurred,Occurred" setclrfld.long 0x24 16. 0x28 16. 0x2C 16. " ENIRQWAKEUP_SET/CLR ,Enables interrupt for the wakeup events" "No interrupt,Interrupt" setclrfld.long 0x24 15. 0x28 15. 0x2C 15. " ENUTMILEVEL3_SET/CLR ,Enables UTMI+ Level3" "Disabled,Enabled" newline setclrfld.long 0x24 14. 0x28 14. 0x2C 14. " ENUTMILEVEL2_SET/CLR ,Enables UTMI+ Level2" "Disabled,Enabled" setclrfld.long 0x24 13. 0x28 13. 0x2C 13. " DATA_ON_LRADC_SET/CLR ,Enables the LRADC to monitor USB_DP and USB_DM" "Disabled,Enabled" setclrfld.long 0x24 12. 0x28 12. 0x2C 12. " DEVPLUGIN_IRQ_SET/CLR ,Indicates that the device is connected" "Not connected,Connected" newline setclrfld.long 0x24 11. 0x28 11. 0x2C 11. " ENIRQDEVPLUGIN_SET/CLR ,Enables interrupt for the detection of connectivity to the USB line" "No interrupt,Interrupt" setclrfld.long 0x24 10. 0x28 10. 0x2C 10. " RESUME_IRQ_SET/CLR ,Indicates that the host is sending a wake-up after suspend" "No wake-up,Wake-up" setclrfld.long 0x24 9. 0x28 9. 0x2C 9. " ENIRQRESUMEDETECT_SET/CLR ,Enables interrupt for detection of a non-J state on the USB line" "No interrupt,Interrupt" newline setclrfld.long 0x24 8. 0x28 8. 0x2C 8. " RESUMEIRQSTICKY_SET/CLR ,RESUME_IRQ bit a sticky bit until software clear it" "Not set,Set" setclrfld.long 0x24 7. 0x28 7. 0x2C 7. " ENOTGIDDETECT_SET/CLR ,Enables circuit to detect resistance of MiniAB ID pin" "Disabled,Enabled" setclrfld.long 0x24 6. 0x28 6. 0x2C 6. " OTG_ID_CHG_IRQ_SET/CLR ,OTG ID change interrupt" "Disabled,Enabled" newline setclrfld.long 0x24 5. 0x28 5. 0x2C 5. " DEVPLUGIN_POLARITY_SET/CLR ,Device plug in/unplugged interrupt polarity" "Plugged in,Unplugged" setclrfld.long 0x24 4. 0x28 4. 0x2C 4. " ENDEVPLUGINDETECT_SET/CLR ,Enables 200-KOhm pullups for detecting connectivity to the host" "Disabled,Enabled" setclrfld.long 0x24 3. 0x28 3. 0x2C 3. " HOSTDISCONDETECT_IRQ_SET/CLR ,Indicates that the device has disconnected in high-speed mode" "Connected,Disconnected" newline setclrfld.long 0x24 2. 0x28 2. 0x2C 2. " ENIRQHOSTDISCON_SET/CLR ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No interrupt,Interrupt" setclrfld.long 0x24 1. 0x28 1. 0x2C 1. " ENHOSTDISCONDETECT_SET/CLR ,Enables high-speed disconnect detector" "Disabled,Enabled" setclrfld.long 0x24 0. 0x28 0. 0x2C 0. " ENOTG_ID_CHG_IRQ_SET/CLR ,Enable OTG_ID_CHG_IRQ" "Disabled,Enabled" group.long 0x3C++0x07 line.long 0x00 "CTRL_TOG,USB PHY General Control Register" bitfld.long 0x00 31. " SFTRST ,Soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate UTMI clocks" "Not gated,Gated" rbitfld.long 0x00 29. " UTMI_SUSPENDM ,Indicate a powered-down state" "Powered up,Powered down" newline bitfld.long 0x00 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with LS timing" "Not forced,Forced" rbitfld.long 0x00 27. " OTG_ID_VALUE ,Results of ID pin on MiniAB plug" "False,True" bitfld.long 0x00 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "Disabled,Enabled" newline bitfld.long 0x00 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "Disabled,Enabled" bitfld.long 0x00 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "Disabled,Enabled" bitfld.long 0x00 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "Disabled,Enabled" newline bitfld.long 0x00 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended" "Disabled,Enabled" bitfld.long 0x00 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "Disabled,Enabled" bitfld.long 0x00 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended" "Disabled,Enabled" newline bitfld.long 0x00 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "Not occurred,Occurred" bitfld.long 0x00 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "No interrupt,Interrupt" bitfld.long 0x00 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "Disabled,Enabled" newline bitfld.long 0x00 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "Disabled,Enabled" bitfld.long 0x00 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "Disabled,Enabled" bitfld.long 0x00 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "Not connected,Connected" newline bitfld.long 0x00 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "No interrupt,Interrupt" bitfld.long 0x00 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "No wake-up,Wake-up" bitfld.long 0x00 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No interrupt,Interrupt" newline bitfld.long 0x00 8. " RESUMEIRQSTICKY ,RESUME_IRQ bit a sticky bit until software clear it" "Not set,Set" bitfld.long 0x00 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Disabled,Enabled" bitfld.long 0x00 6. " OTG_ID_CHG_IRQ ,OTG ID change interrupt" "Disabled,Enabled" newline bitfld.long 0x00 5. " DEVPLUGIN_POLARITY ,Device plug in/unplugged interrupt polarity" "Plugged in,Unplugged" bitfld.long 0x00 4. " ENDEVPLUGINDETECT ,Enables 200-KOhm pullups for detecting connectivity to the host" "Disabled,Enabled" bitfld.long 0x00 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "Connected,Disconnected" newline bitfld.long 0x00 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No interrupt,Interrupt" bitfld.long 0x00 1. " ENHOSTDISCONDETECT ,Enables high-speed disconnect detector" "Disabled,Enabled" bitfld.long 0x00 0. " ENOTG_ID_CHG_IRQ ,Enable OTG_ID_CHG_IRQ" "Disabled,Enabled" line.long 0x04 "STATUS,USB PHY Status Register" rbitfld.long 0x04 10. " RESUME_STATUS ,Indicates that the host is sending a wake-up after suspend and has triggered an interrupt" "No interrupt,Interrupt" bitfld.long 0x04 8. " OTGID_STATUS ,Indicates the results of ID pin on MiniAB plug" "False,True" rbitfld.long 0x04 6. " DEVPLUGIN_STATUS ,Indicates that the device has been connected on the USB_DP and USB_DM lines" "Disconnected,Connected" newline rbitfld.long 0x04 3. " HOSTDISCONDETECT_STATUS ,Indicates that the device has disconnected while in high-speed host mode" "Connected,Disconnected" group.long 0x50++0x03 line.long 0x00 "DEBUG,USB PHY Debug Register" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE_SET/CLR ,Gate test clocks" "Not gated,Gated" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " HOST_RESUME_DEBUG_SET/CLR ,Host resume trigger SE0" "HOST_FORCE_LS_SE0,UTMI_SUSPEND" bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline setclrfld.long 0x00 24. 0x04 24. 0x08 24. " ENSQUELCHRESET_SET/CLR ,Allow squelch to reset high-speed receive" "Not allowed,Allowed" bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " ENTX2RXCOUNT_SET/CLR ,Allow a countdown to transition in between TX and RX" "Not allowed,Allowed" newline bitfld.long 0x00 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ENHSTPULLDOWN ,Enable host pulldown" "Disabled,USB_DM 15-KOhm,USB_DP 15-KOhm,?..." bitfld.long 0x00 2.--3. " HSTPULLDOWN ,Host pulldown" "Disabled,15-KOhm on USB_DM,15-KOhm on USB_DP,?..." newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " DEBUG_INTERFACE_HOLD_SET/CLR ,Use holding registers to assist in timing for external UTMI interface" "Not used,Used" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OTGIDPIOLOCK_SET/CLR ,Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value" "Not held,Held" group.long 0x5C++0x07 line.long 0x00 "DEBUG_TOG,USB PHY Debug Register" bitfld.long 0x00 30. " CLKGATE ,Gate test clocks" "Not gated,Gated" bitfld.long 0x00 29. " HOST_RESUME_DEBUG ,Host resume trigger SE0" "HOST_FORCE_LS_SE0,UTMI_SUSPEND" bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24. " ENSQUELCHRESET ,Allow squelch to reset high-speed receive" "Not allowed,Allowed" bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12. " ENTX2RXCOUNT ,Allow a countdown to transition in between TX and RX" "Not allowed,Allowed" newline bitfld.long 0x00 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ENHSTPULLDOWN ,Enable host pulldown" "Disabled,USB_DM 15-KOhm,USB_DP 15-KOhm,?..." bitfld.long 0x00 2.--3. " HSTPULLDOWN ,Host pulldown" "Disabled,15-KOhm on USB_DM,15-KOhm on USB_DP,?..." newline bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "Not used,Used" bitfld.long 0x00 0. " OTGIDPIOLOCK ,Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value" "Not held,Held" line.long 0x04 "DEBUG0_STATUS,UTMI Debug Status Register 0" bitfld.long 0x04 26.--31. " SQUELCH_COUNT ,Running count of the squelch reset instead of normal end for HS RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 16.--25. 1. " UTMI_RXERROR_FAIL_COUNT ,Running count of the UTMI_RXERROR" hexmask.long.word 0x04 0.--15. 1. " LOOP_BACK_FAIL_COUNT ,Running count of the failed pseudo-random generator loopback" group.long 0x70++0x0F line.long 0x00 "DEBUG1,UTMI Debug Status Register 1" bitfld.long 0x00 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x04 "DEBUG1_SET,UTMI Debug Status Register 1" bitfld.long 0x04 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x08 "DEBUG1_CLR,UTMI Debug Status Register 1" bitfld.long 0x08 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" line.long 0x0C "DEBUG1_TOG,UTMI Debug Status Register 1" bitfld.long 0x0C 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" rgroup.long 0x80++0x03 line.long 0x00 "VERSION,UTMI RTL Version" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed value reflecting the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed value reflecting the stepping of the RTL version" width 0x0B tree.end tree.end tree "USB_ANALOG" base ad:0x020C81A0 width 26. group.long 0x1A0++0x13 line.long 0x00 "USB1_VBUS_DETECT,USB VBUS Detect Register" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " CHARGE_VBUS_SET/CLR ,USB OTG charge VBUS" "Discharged,Charged" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " DISCHARGE_VBUS_SET/CLR ,USB OTG discharge VBUS" "Charged,Discharged" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " VBUSVALID_PWRUP_CMPS_SET/CLR ,Powers up comparators for vbus_valid detector" "Powered down,Powered up" newline bitfld.long 0x00 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" group.long 0x1AC++0x07 line.long 0x00 "USB1_VBUS_DETECT_TOG,USB VBUS Detect Register" bitfld.long 0x00 27. " CHARGE_VBUS ,USB OTG charge VBUS" "Discharged,Charged" bitfld.long 0x00 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS" "Charged,Discharged" bitfld.long 0x00 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector" "Powered down,Powered up" newline bitfld.long 0x00 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x04 "USB1_CHRG_DETECT_SET/CLR,USB Charger Detect Register" setclrfld.long 0x04 20. 0x04 20. 0x08 20. " EN_B ,Control the charger detector (disable)" "No,Yes" setclrfld.long 0x04 19. 0x04 19. 0x08 19. " CHK_CHRG_B ,Check the charger connection" "Checked,Not checked" setclrfld.long 0x04 18. 0x04 18. 0x08 18. " CHK_CONTACT ,Check the contact of USB plug" "Not checked,Checked" group.long 0x1BC++0x3 line.long 0x00 "USB1_CHRG_DETECT_TOG,USB Charger Detect Register" bitfld.long 0x00 20. " EN_B ,Control the charger detector (disable)" "No,Yes" bitfld.long 0x00 19. " CHK_CHRG_B ,Check the charger connection" "Checked,Not checked" bitfld.long 0x00 18. " CHK_CONTACT ,Check the contact of USB plug" "Not checked,Checked" rgroup.long 0x1C0++0x3 line.long 0x00 "USB1_VBUS_DETECT_STAT,USB VBUS Detect Status Register" bitfld.long 0x00 3. " VBUS_VALID ,VBus valid for USB OTG" "Not valid,Valid" bitfld.long 0x00 2. " AVALID ,Indicates VBus is valid for a A-peripheral" "Not valid,Valid" bitfld.long 0x00 1. " BVALID ,Indicates VBus is valid for a B-peripheral" "Not valid,Valid" newline bitfld.long 0x00 0. " SESSEND ,Session end for USB OTG" "Not ended,Ended" rgroup.long 0x1D0++0x3 line.long 0x00 "USB1_CHRG_DETECT_STAT,USB Charger Detect Status Register" bitfld.long 0x00 3. " DP_STATE ,DP line state output of the charger detector" "0,1" bitfld.long 0x00 2. " DM_STATE ,DM line state output of the charger detector" "0,1" bitfld.long 0x00 1. " CHRG_DETECTED ,State of charger detection" "Charger not present,Charger present" newline bitfld.long 0x00 0. " PLUG_CONTACT ,State of the USB plug contact detector" "No contact,Good contact" group.long 0x1F0++0x3 line.long 0x00 "USB1_MISC_SET/CLR,USB Misc Register" setclrfld.long 0x00 30. 0x00 30. 0x00 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x00 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x00 0. " HS_USE_EXTERNAL_R ,Use external resistor to generate the current bias for the high speed transmitter" "Not used,Used" group.long 0x1FC++0x3 line.long 0x00 "USB1_MISC_TOG,USB Misc Register" bitfld.long 0x00 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block" "Disabled,Enabled" bitfld.long 0x00 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output" "Disabled,Enabled" bitfld.long 0x00 0. " HS_USE_EXTERNAL_R ,Use external resistor to generate the current bias for the high speed transmitter" "Not used,Used" group.long 0x200++0x13 line.long 0x00 "USB2_VBUS_DETECT,USB VBUS Detect Register" setclrfld.long 0x00 27. 0x00 27. 0x00 27. " CHARGE_VBUS_SET/CLR ,USB OTG charge VBUS." "Discharged,Charged" setclrfld.long 0x00 26. 0x00 26. 0x00 26. " DISCHARGE_VBUS_SET/CLR ,USB OTG discharge VBUS" "Charged,Discharged" setclrfld.long 0x00 20. 0x00 20. 0x00 20. " VBUSVALID_PWRUP_CMPS_SET/CLR ,Powers up comparators for vbus_valid detector" "Powered down,Powered up" newline bitfld.long 0x00 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" group.long 0x20C++0x07 line.long 0x00 "USB2_VBUS_DETECT_TOG,USB VBUS Detect Register" bitfld.long 0x00 27. " CHARGE_VBUS ,USB OTG charge VBUS." "Discharged,Charged" bitfld.long 0x00 26. " DISCHARGE_VBUS ,USB OTG discharge VBUS" "Charged,Discharged" bitfld.long 0x00 20. " VBUSVALID_PWRUP_CMPS ,Powers up comparators for vbus_valid detector" "Powered down,Powered up" newline bitfld.long 0x00 0.--2. " VBUSVALID_THRESH ,Threshold for the VBUSVALID comparator" "4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V,4.7V" line.long 0x04 "USB2_CHRG_DETECT_SET/CLR,USB Charger Detect Register" setclrfld.long 0x04 20. 0x04 20. 0x08 20. " EN_B ,Control the charger detector (disable)" "No,Yes" setclrfld.long 0x04 19. 0x04 19. 0x08 19. " CHK_CHRG_B ,Check the charger connection" "Checked,Not checked" setclrfld.long 0x04 18. 0x04 18. 0x08 18. " CHK_CONTACT ,Check the contact of USB plug" "Not checked,Checked" group.long 0x21C++0x3 line.long 0x00 "USB2_CHRG_DETECT_TOG,USB Charger Detect Register" bitfld.long 0x00 20. " EN_B ,Control the charger detector (disable)" "No,Yes" bitfld.long 0x00 19. " CHK_CHRG_B ,Check the charger connection" "Checked,Not checked" bitfld.long 0x00 18. " CHK_CONTACT ,Check the contact of USB plug" "Not checked,Checked" rgroup.long 0x220++0x3 line.long 0x00 "USB2_VBUS_DETECT_STAT,USB VBUS Detect Status Register" bitfld.long 0x00 3. " VBUS_VALID ,VBus valid for USB OTG" "Not valid,Valid" bitfld.long 0x00 2. " AVALID ,Indicates VBus is valid for a A-peripheral" "Not valid,Valid" bitfld.long 0x00 1. " BVALID ,Indicates VBus is valid for a B-peripheral" "Not valid,Valid" newline bitfld.long 0x00 0. " SESSEND ,Session End for USB OTG" "0,1" rgroup.long 0x230++0x3 line.long 0x00 "USB2_CHRG_DETECT_STAT,USB Charger Detect Status Register" bitfld.long 0x00 3. " DP_STATE ,DP line state output of the charger detector" "0,1" bitfld.long 0x00 2. " DM_STATE ,DM line state output of the charger detector" "0,1" bitfld.long 0x00 1. " CHRG_DETECTED ,State of charger detection" "Not present,Present" newline bitfld.long 0x00 0. " PLUG_CONTACT ,State of the USB plug contact detector" "No contact,Good contact" group.long 0x250++0x3 line.long 0x00 "USB2_MISC_SET/CLR,USB Misc Register" setclrfld.long 0x00 30. 0x00 30. 0x00 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x00 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x00 0. " HS_USE_EXTERNAL_R ,Use external resistor to generate the current bias for the high speed transmitter" "Not used,Used" group.long 0x25C++0x3 line.long 0x00 "USB2_MISC_TOG,USB Misc Register" bitfld.long 0x00 30. " EN_CLK_UTMI ,Enables the clk to the UTMI block" "Disabled,Enabled" bitfld.long 0x00 1. " EN_DEGLITCH ,Enable the deglitching circuit of the USB PLL output" "Disabled,Enabled" bitfld.long 0x00 0. " HS_USE_EXTERNAL_R ,Use external resistor to generate the current bias for the high speed transmitter" "No external,External" rgroup.long 0x260++0x3 line.long 0x00 "DIGPROG,Chip Silicon Version" hexmask.long.byte 0x00 16.--23. 1. " MAJOR_UPPER ,MAJOR upper byte value representing the chip type" hexmask.long.byte 0x00 8.--15. 1. " MAJOR_LOWER ,MAJOR lower byte value representing a major silicon revision" hexmask.long.byte 0x00 0.--7. 1. " MINOR ,MINOR lower byte value representing a minor silicon revision" width 0x0B tree.end tree.end tree "USDHC (Ultra Secured Digital Host Controller)" tree "USDHC 1" base ad:0x02190000 width 22. sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) if ((((per.l(ad:0x02190000+0x24))&0x04)==0x04)||(((per.l(ad:0x02190000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA System Address" else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA System Address" endif else if ((((per.l(ad:0x02190000+0x24))&0x04)==0x04)||(((per.l(ad:0x02190000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" endif endif sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) if (((per.l(ad:0x02190000+0x48))&0x02)==0x02) group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" else group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" endif if (((per.l(ad:0x02190000+0x24))&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" else rgroup.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" endif else group.long 0x04++0x07 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x04 "CMD_ARG,Command Argument Register" endif if (((per.l(ad:0x02190000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT line 7 signal level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT line 6 signal level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT line 5 signal level" "Low,High" newline bitfld.long 0x00 28. " DLSL[4] ,DAT line 4 signal level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT line 3 signal level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT line 2 signal level" "Low,High" newline bitfld.long 0x00 25. " DLSL[1] ,DAT line 1 signal level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT line 0 signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" newline bitfld.long 0x00 15. " TSCD ,Tape select change done" "Not finished,Finished" bitfld.long 0x00 12. " RTR ,Re-Tuning request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x02190000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" newline bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." newline bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." newline bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 28. " RSTT ,Reset tuning" "No reset,Reset" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" newline bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "Low,High" newline bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 26. " TNE ,Tuning error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" newline eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" newline eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" newline eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" eventfld.long 0x04 14. " TP ,Tuning pass" "Not transferred,Transferred" eventfld.long 0x04 12. " RTE ,Re-tuning event" "Not requested,Requested" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" newline bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 14. " TPSEN ,Tuning pass status enable" "Disabled,Enabled" bitfld.long 0x08 12. " RTESEN ,Re-tuning event status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " TPIEN ,Tuning pass interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 12. " RTEIEN ,Re-Tuning event interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x02190000+0xCC)&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample clock select" "Fixed clock,Tuned clock" bitfld.long 0x00 22. " EXECUTE_TUNING ,Execute tuning" "Not started,Started" rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" newline rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" newline rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3,?..." newline bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use tuning for SDR50" "Not required,Required" bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time counter for retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" newline rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" line.long 0x04 "WTMK_LVL,Watermark Level Register" bitfld.long 0x04 24.--28. " WR_BRST_LEN ,Write burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--12. " RD_BRST_LEN ,Read burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." newline hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x08 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" newline bitfld.long 0x08 23. " SMP_CLK_SEL ,Sample clock selection" "Tuned,Fixed" bitfld.long 0x08 22. " EXE_TUNE ,Execute tuning" "Not executed,Executed" bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Disabled,Enabled" bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" newline bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 26. " FEVTTNE ,Force tuning error" "No error,Error" newline bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" newline bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" newline bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" newline bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" newline bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x02190000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x60++0x03 line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Slave delay line update interval" bitfld.long 0x00 16.--18. " SLV_DLY_TARGET1 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 9.--15. 1. " SLV_OVERRIDE_VAL ,Slave override value" bitfld.long 0x00 8. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " GATE_UPDATE ,The DLL update" "Automatically,No update" newline bitfld.long 0x00 3.--6. " SLV_DLY_TARGET0 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " SLV_FORCE_UPD ,DLL slave update" "No update,Updated" bitfld.long 0x00 1. " RESET ,DLL reset" "No reset,Reset" newline bitfld.long 0x00 0. " ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLL_STATUS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" newline bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if ((per.l(ad:0x02190000+0x48)&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" newline hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" newline bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" newline bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0F line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal state value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" newline bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending abort command" "Active,Inactive" newline bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of dat3 pin when its used as card detection" "High,Low" newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (Around: 3.0V,1.8V)" "High,Low" newline bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA request enable" "Disabled,Enabled" line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the card interrupt status bit" "No,Yes" newline bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0],Invalid" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" newline bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Disable drive CMD_OE/DAT_OE at once after driving the end bit" "No,Yes" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for ncr changes/ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0C 24. " STD_TUNING_EN ,Standard tuning circuit and procedure enable" "Disabled,Enabled" bitfld.long 0x0C 20.--22. " TUNING_WINDOW ,Select data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " TUNING_STEP ,The increasing delay cell steps in tuning procedure" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,The MAX repeat CMD19 times in tuning procedure" hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 0x0B tree.end tree "USDHC 2" base ad:0x02194000 width 22. sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) if ((((per.l(ad:0x02194000+0x24))&0x04)==0x04)||(((per.l(ad:0x02194000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA System Address" else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA System Address" endif else if ((((per.l(ad:0x02194000+0x24))&0x04)==0x04)||(((per.l(ad:0x02194000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" endif endif sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) if (((per.l(ad:0x02194000+0x48))&0x02)==0x02) group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" else group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" endif if (((per.l(ad:0x02194000+0x24))&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" else rgroup.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" endif else group.long 0x04++0x07 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x04 "CMD_ARG,Command Argument Register" endif if (((per.l(ad:0x02194000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT line 7 signal level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT line 6 signal level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT line 5 signal level" "Low,High" newline bitfld.long 0x00 28. " DLSL[4] ,DAT line 4 signal level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT line 3 signal level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT line 2 signal level" "Low,High" newline bitfld.long 0x00 25. " DLSL[1] ,DAT line 1 signal level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT line 0 signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" newline bitfld.long 0x00 15. " TSCD ,Tape select change done" "Not finished,Finished" bitfld.long 0x00 12. " RTR ,Re-Tuning request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x02194000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" newline bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." newline bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." newline bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 28. " RSTT ,Reset tuning" "No reset,Reset" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" newline bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "Low,High" newline bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 26. " TNE ,Tuning error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" newline eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" newline eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" newline eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" eventfld.long 0x04 14. " TP ,Tuning pass" "Not transferred,Transferred" eventfld.long 0x04 12. " RTE ,Re-tuning event" "Not requested,Requested" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" newline bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 14. " TPSEN ,Tuning pass status enable" "Disabled,Enabled" bitfld.long 0x08 12. " RTESEN ,Re-tuning event status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " TPIEN ,Tuning pass interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 12. " RTEIEN ,Re-Tuning event interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x02194000+0xCC)&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample clock select" "Fixed clock,Tuned clock" bitfld.long 0x00 22. " EXECUTE_TUNING ,Execute tuning" "Not started,Started" rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" newline rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" newline rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3,?..." newline bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use tuning for SDR50" "Not required,Required" bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time counter for retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" newline rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" line.long 0x04 "WTMK_LVL,Watermark Level Register" bitfld.long 0x04 24.--28. " WR_BRST_LEN ,Write burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--12. " RD_BRST_LEN ,Read burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." newline hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x08 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" newline bitfld.long 0x08 23. " SMP_CLK_SEL ,Sample clock selection" "Tuned,Fixed" bitfld.long 0x08 22. " EXE_TUNE ,Execute tuning" "Not executed,Executed" bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Disabled,Enabled" bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" newline bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 26. " FEVTTNE ,Force tuning error" "No error,Error" newline bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" newline bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" newline bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" newline bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" newline bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x02194000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x60++0x03 line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Slave delay line update interval" bitfld.long 0x00 16.--18. " SLV_DLY_TARGET1 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 9.--15. 1. " SLV_OVERRIDE_VAL ,Slave override value" bitfld.long 0x00 8. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " GATE_UPDATE ,The DLL update" "Automatically,No update" newline bitfld.long 0x00 3.--6. " SLV_DLY_TARGET0 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " SLV_FORCE_UPD ,DLL slave update" "No update,Updated" bitfld.long 0x00 1. " RESET ,DLL reset" "No reset,Reset" newline bitfld.long 0x00 0. " ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLL_STATUS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" newline bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if ((per.l(ad:0x02194000+0x48)&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" newline hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" newline bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" newline bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0F line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal state value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" newline bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending abort command" "Active,Inactive" newline bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of dat3 pin when its used as card detection" "High,Low" newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (Around: 3.0V,1.8V)" "High,Low" newline bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA request enable" "Disabled,Enabled" line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the card interrupt status bit" "No,Yes" newline bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0],Invalid" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" newline bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Disable drive CMD_OE/DAT_OE at once after driving the end bit" "No,Yes" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for ncr changes/ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0C 24. " STD_TUNING_EN ,Standard tuning circuit and procedure enable" "Disabled,Enabled" bitfld.long 0x0C 20.--22. " TUNING_WINDOW ,Select data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " TUNING_STEP ,The increasing delay cell steps in tuning procedure" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,The MAX repeat CMD19 times in tuning procedure" hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 0x0B tree.end tree "USDHC 3" base ad:0x02198000 width 22. sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) if ((((per.l(ad:0x02198000+0x24))&0x04)==0x04)||(((per.l(ad:0x02198000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA System Address" else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA System Address" endif else if ((((per.l(ad:0x02198000+0x24))&0x04)==0x04)||(((per.l(ad:0x02198000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" endif endif sif (cpuis("IMX8DX*")||cpuis("IMX8QXP*")) if (((per.l(ad:0x02198000+0x48))&0x02)==0x02) group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" else group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" endif if (((per.l(ad:0x02198000+0x24))&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" else rgroup.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" endif else group.long 0x04++0x07 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x04 "CMD_ARG,Command Argument Register" endif if (((per.l(ad:0x02198000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,DAT line 7 signal level" "Low,High" bitfld.long 0x00 30. " DLSL[6] ,DAT line 6 signal level" "Low,High" bitfld.long 0x00 29. " DLSL[5] ,DAT line 5 signal level" "Low,High" newline bitfld.long 0x00 28. " DLSL[4] ,DAT line 4 signal level" "Low,High" bitfld.long 0x00 27. " DLSL[3] ,DAT line 3 signal level" "Low,High" bitfld.long 0x00 26. " DLSL[2] ,DAT line 2 signal level" "Low,High" newline bitfld.long 0x00 25. " DLSL[1] ,DAT line 1 signal level" "Low,High" bitfld.long 0x00 24. " DLSL[0] ,DAT line 0 signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" newline bitfld.long 0x00 15. " TSCD ,Tape select change done" "Not finished,Finished" bitfld.long 0x00 12. " RTR ,Re-Tuning request" "Not requested,Requested" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x02198000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 29. " BURST_LEN_EN[2] ,BURST length enable for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN[1] ,BURST length enable for INCR4/INCR8/INCR16" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST_LEN_EN[0] ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" newline bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." newline bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." newline bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 28. " RSTT ,Reset tuning" "No reset,Reset" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" newline bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "Low,High" newline bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28" hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS[3:0] ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 26. " TNE ,Tuning error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" newline eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" newline eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" newline eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" eventfld.long 0x04 14. " TP ,Tuning pass" "Not transferred,Transferred" eventfld.long 0x04 12. " RTE ,Re-tuning event" "Not requested,Requested" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" newline bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 14. " TPSEN ,Tuning pass status enable" "Disabled,Enabled" bitfld.long 0x08 12. " RTESEN ,Re-tuning event status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " TPIEN ,Tuning pass interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 12. " RTEIEN ,Re-Tuning event interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x02198000+0xCC)&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 23. " SMP_CLK_SEL ,Sample clock select" "Fixed clock,Tuned clock" bitfld.long 0x00 22. " EXECUTE_TUNING ,Execute tuning" "Not started,Started" rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" newline rbitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" rbitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" rbitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" newline rbitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." rbitfld.long 0x00 14.--15. " RETUNING_MODE ,Retuning Mode" "Mode 1,Mode 2,Mode 3,?..." newline bitfld.long 0x00 13. " USE_TUNING_SDR50 ,Use tuning for SDR50" "Not required,Required" bitfld.long 0x00 8.--11. " TIME_COUNT_RETUNING ,Time counter for retuning" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " DDR50_SUPPORT ,DDR50 support" "Not supported,Supported" newline rbitfld.long 0x00 1. " SDR104_SUPPORT ,SDR104 support" "Not supported,Supported" rbitfld.long 0x00 0. " SDR50_SUPPORT ,SDR50 support" "Not supported,Supported" line.long 0x04 "WTMK_LVL,Watermark Level Register" bitfld.long 0x04 24.--28. " WR_BRST_LEN ,Write burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--12. " RD_BRST_LEN ,Read burst length" "8,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." newline hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 25. " FBCLK_SEL ,Feedback clock source selection" "Loopback CLK,Ipp_card_clk_out" bitfld.long 0x08 24. " AUTO_TUNE_EN ,Auto tuning enable" "Disabled,Enabled" newline bitfld.long 0x08 23. " SMP_CLK_SEL ,Sample clock selection" "Tuned,Fixed" bitfld.long 0x08 22. " EXE_TUNE ,Execute tuning" "Not executed,Executed" bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Disabled,Enabled" bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" newline bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 26. " FEVTTNE ,Force tuning error" "No error,Error" newline bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" newline bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" newline bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" newline bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" newline bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x02198000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x60++0x03 line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Slave delay line update interval" bitfld.long 0x00 16.--18. " SLV_DLY_TARGET1 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 9.--15. 1. " SLV_OVERRIDE_VAL ,Slave override value" bitfld.long 0x00 8. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled" bitfld.long 0x00 7. " GATE_UPDATE ,The DLL update" "Automatically,No update" newline bitfld.long 0x00 3.--6. " SLV_DLY_TARGET0 ,The delay target for the USDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " SLV_FORCE_UPD ,DLL slave update" "No update,Updated" bitfld.long 0x00 1. " RESET ,DLL reset" "No reset,Reset" newline bitfld.long 0x00 0. " ENABLE ,DLL enable" "Disabled,Enabled" rgroup.long 0x64++0x03 line.long 0x00 "DLL_STATUS,DLL Status Register" hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference delay line select taps" hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave delay line select status" newline bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Invalid,Valid" if ((per.l(ad:0x02198000+0x48)&0x800000)==0x800000) group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" rbitfld.long 0x00 31. " PRE_ERR ,PRE error" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " NXT_ERR ,NXT error" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x68++0x03 line.long 0x00 "CLK_TUNE_CTRL_STATUS,Clock Tuning Control And Status Register" hexmask.long.byte 0x00 24.--30. 1. " TAP_SEL_PRE ,Number of delay cells added on the feedback clock between the feedback clock and CLK_PRE" rbitfld.long 0x00 20.--23. " TAP_SEL_OUT ,Number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. " TAP_SEL_POST ,Number of delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--14. 1. " DLY_CELL_SET_PRE ,Number of delay cells on the feedback clock between the feedback clock and CLK_PRE" newline bitfld.long 0x00 4.--7. " DLY_CELL_SET_OUT ,Number of delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DLY_CELL_SET_POST ,Number of delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" newline hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" newline bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.byte 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" newline bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0F line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal state value" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" newline bitfld.long 0x00 14. " CARD_CLK_SOFT_EN ,Card clock software enable" "Disabled,Enabled" bitfld.long 0x00 13. " IPG_PERCLK_SOFT_EN ,IPG_PERCLK software enable" "Disabled,Enabled" bitfld.long 0x00 12. " HCLK_SOFT_EN ,AHB clock software enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " IPG_CLK_SOFT_EN ,IPG_CLK software enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" bitfld.long 0x00 7. " CLKONJ_IN_ABORT ,Force CLK output active when sending abort command" "Active,Inactive" newline bitfld.long 0x00 6. " WP_POL ,Polarity of the WP pin" "High,Low" bitfld.long 0x00 5. " CD_POL ,Polarity of the CD pin" "Low,High" bitfld.long 0x00 4. " DAT3_CD_POL ,Polarity of dat3 pin when its used as card detection" "High,Low" newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (Around: 3.0V,1.8V)" "High,Low" newline bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA request enable" "Disabled,Enabled" line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,SDCLK x 2^28" line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 7. " CARD_INT_AUTO_CLR_DIS ,Disable clearing of the card interrupt status bit" "No,Yes" newline bitfld.long 0x08 6. " TUNING_CMD_EN ,Enable the auto tuning circuit to check the CMD line" "Disabled,Enabled" bitfld.long 0x08 4.--5. " TUNING_EN ,Enable the auto tuning circuit to check the DAT[7:0]" "DAT[3:0],DAT[0],DAT[7:0],Invalid" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" newline bitfld.long 0x08 2. " SDR104_NSD_DIS ,Interrupt window after abort command is sent" "9 cycles,5 cycles" bitfld.long 0x08 1. " SDR104_OE_DIS ,Disable drive CMD_OE/DAT_OE at once after driving the end bit" "No,Yes" bitfld.long 0x08 0. " SDR104_TIMING_DIS ,The timeout counter for ncr changes/ncrc changes" "80/21,72/15" line.long 0x0C "TUNING_CTRL,Tuning Control Register" bitfld.long 0x0C 24. " STD_TUNING_EN ,Standard tuning circuit and procedure enable" "Disabled,Enabled" bitfld.long 0x0C 20.--22. " TUNING_WINDOW ,Select data window value for auto tuning" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. " TUNING_STEP ,The increasing delay cell steps in tuning procedure" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0C 8.--15. 1. " TUNING_COUNTER ,The MAX repeat CMD19 times in tuning procedure" hexmask.long.byte 0x0C 0.--7. 1. " TUNING_START_TAP ,The start delay cell point when send first CMD19 in tuning procedure" width 0x0B tree.end tree.end tree "WDOG (Watchdog)" tree "WDOG 1" base ad:0x020BC000 width 6. group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog 1 Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Time-out Field" bitfld.word 0x00 7. " WDW ,Watchdog Disable for Wait" "Continues,Suspended" bitfld.word 0x00 6. " SRE ,Software reset extension" "Original,Extended" newline bitfld.word 0x00 5. " WDA ,WDOG assertion" "Asserted,No effect" bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect" bitfld.word 0x00 3. " WDT ,WDOG Time-out assertion" "No effect,Asserted" newline bitfld.word 0x00 2. " WDE ,Watchdog Enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG Enable" "Continues,Suspended" bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Continues,Suspended" line.word 0x02 "WSR,Watchdog 1 Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog 1 Reset Status Register" bitfld.word 0x00 4. " POR ,Power On Reset" "No reset,Reset" bitfld.word 0x00 1. " TOUT ,Time-out" "No reset,Reset" bitfld.word 0x00 0. " SFTW ,Software Reset" "No reset,Reset" group.word 0x06++0x03 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog Timer Interrupt Enable" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog Timer Interrupt Status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog Interrupt Count Time-out " line.word 0x02 "WMCR,Watchdog 1 Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power Down Enable" "Disabled,Enabled" width 0x0B tree.end tree "WDOG 2" base ad:0x020C0000 width 6. group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog 2 Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Time-out Field" bitfld.word 0x00 7. " WDW ,Watchdog Disable for Wait" "Continues,Suspended" bitfld.word 0x00 6. " SRE ,Software reset extension" "Original,Extended" newline bitfld.word 0x00 5. " WDA ,WDOG assertion" "Asserted,No effect" bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect" bitfld.word 0x00 3. " WDT ,WDOG Time-out assertion" "No effect,Asserted" newline bitfld.word 0x00 2. " WDE ,Watchdog Enable" "Disabled,Enabled" bitfld.word 0x00 1. " WDBG ,Watchdog DEBUG Enable" "Continues,Suspended" bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Continues,Suspended" line.word 0x02 "WSR,Watchdog 2 Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog 2 Reset Status Register" bitfld.word 0x00 4. " POR ,Power On Reset" "No reset,Reset" bitfld.word 0x00 1. " TOUT ,Time-out" "No reset,Reset" bitfld.word 0x00 0. " SFTW ,Software Reset" "No reset,Reset" group.word 0x06++0x03 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog Timer Interrupt Enable" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog Timer Interrupt Status" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog Interrupt Count Time-out " line.word 0x02 "WMCR,Watchdog 2 Miscellaneous Control Register" bitfld.word 0x02 0. " PDE ,Power Down Enable" "Disabled,Enabled" width 0x0B tree.end tree.end tree "XTALOSC (Crystal Oscillator)" base ad:0x20C8150 width 17. group.long 0x00++0x0F line.long 0x00 "MISC0,Miscellaneous Register 0" bitfld.long 0x00 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x00 30. " XTAL_24M_PWD ,24M crystal oscillator power down" "No,Yes" bitfld.long 0x00 29. " RTC_XTAL_SOURCE ,This field indicates which chip source is being used for the rtc clock" "Internal,RTX_XTAL" newline bitfld.long 0x00 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and release the clock to the digital logic inside the analog block" "0.5ms,1.0ms,2.0ms,3.0ms,4.0ms,5.0ms,6.0ms,7.0ms" bitfld.long 0x00 25. " CLKGATE_CTRL ,Disabling the clock gate" "No,Yes" newline bitfld.long 0x00 16. " OSC_XTALOK_EN ,Enable bit for the xtal_ok module (24 MHz)" "Disabled,Enabled" rbitfld.long 0x00 15. " OSC_XTALOK ,Status of output of the 24MHz crystal oscillator" "Not stable,Stable" bitfld.long 0x00 13.--14. " OSC_I ,Determines the bias current in the 24MHz oscillator" "Nominal,-12.5%,-25.0%,-37.5%" newline bitfld.long 0x00 12. " DISCON_HIGH_SNVS ,Switch from VDD_HIGH_IN to VDD_SNVS_IN" "On,Off" newline bitfld.long 0x00 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode" "All powered down (except RTC) | XtalOsc=on | RCOsc=off,Certain powered-up | XtalOsc=on | RCOsc=off,XtalOsc=off | RCOsc=on | Old BG=on | New BG=off,XtalOsc=off | RCOsc=on | Old BG=off | New BG=on" newline bitfld.long 0x00 7. " REFTOP_VBGUP ,Status of the analog bandgap voltage" "Not stable,Stable" newline bitfld.long 0x00 4.--6. " REFTOP_VBGADJ ,Analog bandgap voltage adjustment" "Nominal,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" bitfld.long 0x00 3. " REFTOP_SELFBIASOFF ,Disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x00 0. " REFTOP_PWD ,Power-down the analog bandgap reference circuitry" "Not set,Set" line.long 0x04 "MISC0_SET,Miscellaneous Set Register 0" bitfld.long 0x04 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x04 30. " XTAL_24M_PWD ,24M crystal oscillator power down" "No,Yes" bitfld.long 0x04 29. " RTC_XTAL_SOURCE ,This field indicates which chip source is being used for the rtc clock" "Internal,RTX_XTAL" newline bitfld.long 0x04 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and release the clock to the digital logic inside the analog block" "0.5ms,1.0ms,2.0ms,3.0ms,4.0ms,5.0ms,6.0ms,7.0ms" bitfld.long 0x04 25. " CLKGATE_CTRL ,Disabling the clock gate" "No,Yes" newline bitfld.long 0x04 16. " OSC_XTALOK_EN ,Enable bit for the xtal_ok module (24 MHz)" "Disabled,Enabled" rbitfld.long 0x04 15. " OSC_XTALOK ,Status of output of the 24MHz crystal oscillator" "Not stable,Stable" bitfld.long 0x04 13.--14. " OSC_I ,Determines the bias current in the 24MHz oscillator" "Nominal,-12.5%,-25.0%,-37.5%" newline bitfld.long 0x04 12. " DISCON_HIGH_SNVS ,Switch from VDD_HIGH_IN to VDD_SNVS_IN" "On,Off" newline bitfld.long 0x04 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode" "All powered down (except RTC) | XtalOsc=on | RCOsc=off,Certain powered-up | XtalOsc=on | RCOsc=off,XtalOsc=off | RCOsc=on | Old BG=on | New BG=off,XtalOsc=off | RCOsc=on | Old BG=off | New BG=on" newline bitfld.long 0x04 7. " REFTOP_VBGUP ,Status of the analog bandgap voltage" "Not stable,Stable" newline bitfld.long 0x04 4.--6. " REFTOP_VBGADJ ,Analog bandgap voltage adjustment" "Nominal,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" bitfld.long 0x04 3. " REFTOP_SELFBIASOFF ,Disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x04 0. " REFTOP_PWD ,Power-down the analog bandgap reference circuitry" "Not set,Set" line.long 0x08 "MISC0_CLR,Miscellaneous Clear Register 0" bitfld.long 0x08 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x08 30. " XTAL_24M_PWD ,24M crystal oscillator power down" "No,Yes" bitfld.long 0x08 29. " RTC_XTAL_SOURCE ,This field indicates which chip source is being used for the rtc clock" "Internal,RTX_XTAL" newline bitfld.long 0x08 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and release the clock to the digital logic inside the analog block" "0.5ms,1.0ms,2.0ms,3.0ms,4.0ms,5.0ms,6.0ms,7.0ms" bitfld.long 0x08 25. " CLKGATE_CTRL ,Disabling the clock gate" "No,Yes" newline bitfld.long 0x08 16. " OSC_XTALOK_EN ,Enable bit for the xtal_ok module (24 MHz)" "Disabled,Enabled" rbitfld.long 0x08 15. " OSC_XTALOK ,Status of output of the 24MHz crystal oscillator" "Not stable,Stable" bitfld.long 0x08 13.--14. " OSC_I ,Determines the bias current in the 24MHz oscillator" "Nominal,-12.5%,-25.0%,-37.5%" newline bitfld.long 0x08 12. " DISCON_HIGH_SNVS ,Switch from VDD_HIGH_IN to VDD_SNVS_IN" "On,Off" newline bitfld.long 0x08 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode" "All powered down (except RTC) | XtalOsc=on | RCOsc=off,Certain powered-up | XtalOsc=on | RCOsc=off,XtalOsc=off | RCOsc=on | Old BG=on | New BG=off,XtalOsc=off | RCOsc=on | Old BG=off | New BG=on" newline bitfld.long 0x08 7. " REFTOP_VBGUP ,Status of the analog bandgap voltage" "Not stable,Stable" newline bitfld.long 0x08 4.--6. " REFTOP_VBGADJ ,Analog bandgap voltage adjustment" "Nominal,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" bitfld.long 0x08 3. " REFTOP_SELFBIASOFF ,Disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x08 0. " REFTOP_PWD ,Power-down the analog bandgap reference circuitry" "Not set,Set" line.long 0x0C "MISC0_TOG,Miscellaneous Toggle Register 0" bitfld.long 0x0C 31. " VID_PLL_PREDIV ,Predivider for the source clock of the PLL's" "/1,/2" bitfld.long 0x0C 30. " XTAL_24M_PWD ,24M crystal oscillator power down" "No,Yes" bitfld.long 0x0C 29. " RTC_XTAL_SOURCE ,This field indicates which chip source is being used for the rtc clock" "Internal,RTX_XTAL" newline bitfld.long 0x0C 26.--28. " CLKGATE_DELAY ,Delay between powering up the XTAL 24MHz clock and release the clock to the digital logic inside the analog block" "0.5ms,1.0ms,2.0ms,3.0ms,4.0ms,5.0ms,6.0ms,7.0ms" bitfld.long 0x0C 25. " CLKGATE_CTRL ,Disabling the clock gate" "No,Yes" newline bitfld.long 0x0C 16. " OSC_XTALOK_EN ,Enable bit for the xtal_ok module (24 MHz)" "Disabled,Enabled" rbitfld.long 0x0C 15. " OSC_XTALOK ,Status of output of the 24MHz crystal oscillator" "Not stable,Stable" bitfld.long 0x0C 13.--14. " OSC_I ,Determines the bias current in the 24MHz oscillator" "Nominal,-12.5%,-25.0%,-37.5%" newline bitfld.long 0x0C 12. " DISCON_HIGH_SNVS ,Switch from VDD_HIGH_IN to VDD_SNVS_IN" "On,Off" newline bitfld.long 0x0C 10.--11. " STOP_MODE_CONFIG ,Configure the analog behavior in stop mode" "All powered down (except RTC) | XtalOsc=on | RCOsc=off,Certain powered-up | XtalOsc=on | RCOsc=off,XtalOsc=off | RCOsc=on | Old BG=on | New BG=off,XtalOsc=off | RCOsc=on | Old BG=off | New BG=on" newline bitfld.long 0x0C 7. " REFTOP_VBGUP ,Status of the analog bandgap voltage" "Not stable,Stable" newline bitfld.long 0x0C 4.--6. " REFTOP_VBGADJ ,Analog bandgap voltage adjustment" "Nominal,VBG+0.78%,VBG+1.56%,VBG+2.34%,VBG-0.78%,VBG-1.56%,VBG-2.34%,VBG-3.12%" bitfld.long 0x0C 3. " REFTOP_SELFBIASOFF ,Disable the self-bias circuit in the analog bandgap" "No,Yes" bitfld.long 0x0C 0. " REFTOP_PWD ,Power-down the analog bandgap reference circuitry" "Not set,Set" newline width 13. group.long 0x120++0x03 line.long 0x00 "LOWPWR_CTRL,LP Control Register" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " MIX_PWRGATE_SET/CLR ,Display power gate control" "Not gated,Gated" rbitfld.long 0x00 16. " XTALOSC_PWRUP_STAT ,Display power gate control" "Not stable,Stable" bitfld.long 0x00 14.--15. " XTALOSC_PWRUP_DELAY_SET/CLR ,Specifies delay between when 24MHz xtal is powered up until it is stable" "0.25ms,0.5ms,1ms,2ms" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " RCOSC_CG_OVERRIDE_SET/CLR ,For debug purposes only" "Low,High" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " DISPLAY_PWRGATE_SET/CLR ,Display logic power gate control" "Not gated,Gated" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " CPU_PWRGATE_SET/CLR ,CPU power gate control" "Not gated,Gated" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " L2_PWRGATE_SET/CLR ,L2 power gate control" "Not gated,Gated" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " L1_PWRGATE_SET/CLR ,L1 power gate control" "Not gated,Gated" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " REFTOP_IBIAS_OFF_SET/CLR ,Low power reftop ibias disable" "No,Yes" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " LPBG_TEST_SET/CLR ,Low power bandgap test bit" "Low,High" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " LPBG_SEL_SET/CLR ,Bandgap select" "Normal,Low power" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " OSC_SEL_SET/CLR ,Select the source for the 24MHz clock" "XTAL,RC" newline bitfld.long 0x00 1.--3. " RC_OSC_PROG_SET/CLR ,RC osc tuning values" "0,1,2,3,4,5,6,7" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RC_OSC_EN_SET/CLR ,RC osc enable control" "Disabled,Enabled" group.long 0x150++0x2F line.long 0x00 "CONFIG0,Configuration 0 Register" hexmask.long.byte 0x00 24.--31. 1. " RC_OSC_PROG_CUR ,The current tuning value in use" bitfld.long 0x00 16.--19. " HYST_MINUS ,Negative hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " HYST_PLUS ,Positive hysteresis value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 4.--11. 1. " RC_OSC_PROG ,RC osc tuning values" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " INVERT ,Invert the stepping of the calculated RC tuning value" "Not inverted,Inverted" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " BYPASS ,Bypasses any calculated RC tuning value and uses the programmed register value" "Not bypassed,Bypassed" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ENABLE ,Enables the tuning logic to calculate new RC tuning values" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " START ,Start/stop bit for the RC tuning calculation logic" "Not started,Started" line.long 0x10 "CONFIG1,Configuration 1 Register" hexmask.long.word 0x10 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x10 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x14 "CONFIG1_SET,Configuration 1 Register Set" hexmask.long.word 0x14 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x14 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x18 "CONFIG1_CLR,Configuration 1 Register Clear" hexmask.long.word 0x18 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x18 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x1C "CONFIG1_TOG,Configuration 1 Register Toggle" hexmask.long.word 0x1C 20.--31. 1. " COUNT_RC_CUR ,The current tuning value in use" hexmask.long.word 0x1C 0.--11. 1. " COUNT_RC_TRG ,The target count used to tune the RC OSC frequency" line.long 0x20 "CONFIG2,Configuration 2 Register" bitfld.long 0x20 31. " CLK_1M_ERR_FL ,Flag indicates that the count_1m count wasn't reached within 1 32KHz period" "No error,Error" bitfld.long 0x20 17. " MUX_1M ,Mux the corrected or uncorrected 1MHz clock to the output" "Low,High" bitfld.long 0x20 16. " ENABLE_1M ,Enable the 1MHz clock output" "Disabled,Enabled" hexmask.long.word 0x20 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" line.long 0x24 "CONFIG2_SET,Configuration 2 Register Set" bitfld.long 0x24 31. " CLK_1M_ERR_FL ,Flag indicates that the count_1m count wasn't reached within 1 32KHz period" "No error,Error" bitfld.long 0x24 17. " MUX_1M ,Mux the corrected or uncorrected 1MHz clock to the output" "Low,High" bitfld.long 0x24 16. " ENABLE_1M ,Enable the 1MHz clock output" "Disabled,Enabled" hexmask.long.word 0x24 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" line.long 0x28 "CONFIG2_CLR,Configuration 2 Register Clear" bitfld.long 0x28 31. " CLK_1M_ERR_FL ,Flag indicates that the count_1m count wasn't reached within 1 32KHz period" "No error,Error" bitfld.long 0x28 17. " MUX_1M ,Mux the corrected or uncorrected 1MHz clock to the output" "Low,High" bitfld.long 0x28 16. " ENABLE_1M ,Enable the 1MHz clock output" "Disabled,Enabled" hexmask.long.word 0x28 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" line.long 0x2C "CONFIG2_TOG,Configuration 2 Register Toggle" bitfld.long 0x2C 31. " CLK_1M_ERR_FL ,Flag indicates that the count_1m count wasn't reached within 1 32KHz period" "No error,Error" bitfld.long 0x2C 17. " MUX_1M ,Mux the corrected or uncorrected 1MHz clock to the output" "Low,High" bitfld.long 0x2C 16. " ENABLE_1M ,Enable the 1MHz clock output" "Disabled,Enabled" hexmask.long.word 0x2C 0.--11. 1. " COUNT_1M_TRG ,The target count used to tune the RC OSC frequency" width 0x0B tree.end newline